Display substrate and manufacturing method therefor, and display device

Abstract

A display substrate and a manufacturing method therefor, and a display device. The display substrate comprises a pixel definition layer (PDL), a second electrode adapter layer (13), a partition structure layer (30), a light-emitting structure layer (40), and a second electrode layer (42) which are sequentially arranged on one side of a substrate (101); a plurality of first openings (K21) are formed in the second electrode adapter layer (13) and the partition structure layer (30); first grooves (W1) are formed in the side walls of the first openings (K21); the light-emitting structure layer (40) and the second electrode layer (42) are disconnected at the first grooves (W1); the areas, not covered by the partition structure layer (30), of the surface of the side of the second electrode adapter layer (13) away from the substrate (101) serve as the bottom walls (C1) of the first grooves (W1); the second electrode layer (42) is connected to the bottom walls (C1) of the first grooves (W1) at the disconnection position; and the distance between each bottom wall (C1) of the corresponding first groove (W1) and the substrate is gradually reduced in the direction from the first groove (W1) to the corresponding first opening (K21).

Description

Display substrate and its preparation method, display device Technical Field

[0001] This article relates to, but is not limited to, the field of display technology, specifically to a display substrate and its preparation method, and a display device. Background Technology

[0002] Micro-OLEDs (Micro-Organic Light-Emitting Diodes) are microdisplays that have emerged in recent years, with silicon-based OLEDs being one type. Silicon-based OLEDs not only enable active pixel addressing but also allow for the fabrication of pixel driving circuits and other structures on silicon substrates, which helps reduce system size and achieve lightweight design. Silicon-based OLEDs are fabricated using mature Complementary Metal Oxide Semiconductor (CMOS) integrated circuit technology, offering advantages such as small size, high resolution (Pixels Per Inch, PPI), and high refresh rate. They are widely used in near-eye displays for Virtual Reality (VR) and Augmented Reality (AR).

[0003] Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] In a first aspect, embodiments of the present disclosure provide a display substrate, including a substrate and a pixel definition layer, a second electrode transition layer, a barrier structure layer, a light-emitting structure layer, and a second electrode layer sequentially disposed on one side of the substrate; the pixel definition layer is provided with a plurality of pixel openings, the light-emitting structure layer includes a plurality of light-emitting structures, the plurality of light-emitting structures correspond one-to-one with the plurality of pixel openings, and at least a portion of the light-emitting structure is located in the corresponding pixel opening.

[0006] The second electrode transition layer and the isolation structure layer are provided with a plurality of first openings, each of which corresponds to a plurality of pixel openings. The orthographic projection of the first opening on the substrate at least partially overlaps with the orthographic projection of the corresponding pixel opening on the substrate. The sidewall of the first opening is provided with a first groove, and the light-emitting structure layer and the second electrode layer are disconnected at the first groove position.

[0007] In the surface of the second electrode transition layer on the side away from the substrate, at least a portion of the area not covered by the partition structure layer serves as the bottom wall of the first groove. The second electrode layer is connected to the bottom wall of the first groove in the disconnected position. In the direction from the first groove to the corresponding first opening, the distance between the bottom wall of the first groove and the substrate gradually decreases.

[0008] In an exemplary embodiment, the second electrode layer overlaps with the bottom wall of the first groove at the disconnected position.

[0009] In an exemplary embodiment, in the direction from the first groove to the corresponding first opening, the bottom wall of the first groove includes a first region and a second region arranged sequentially, and the second region is located between the corresponding first opening and the first region;

[0010] The second electrode layer overlaps with the first region at the disconnected position, and the light-emitting structure layer covers the second region at the disconnected position.

[0011] In an exemplary embodiment, a second groove is provided on the sidewall of the pixel opening, and the minimum distance between the second electrode layer and the second groove is less than the average thickness of the light-emitting structure layer corresponding to the second region, wherein the light-emitting structure layer corresponding to the second region covers the corresponding second region.

[0012] In an exemplary embodiment, on a plane parallel to the substrate, in the direction from the first groove to the corresponding first opening, the ratio of the size of the first groove to the size of the second groove is greater than or equal to 5:1.

[0013] In an exemplary embodiment, in a direction perpendicular to the substrate, the ratio of the size of the first groove to the size of the second groove is greater than or equal to 5:1.

[0014] In an exemplary embodiment, in the direction from the first groove to the corresponding first opening, the difference between the maximum and minimum distances between the bottom wall of the first groove and the substrate is greater than the minimum distance between the second electrode layer and the second groove, but less than the thickness of the second electrode layer.

[0015] In an exemplary embodiment, on a plane parallel to the substrate, in the direction from the first groove to the corresponding first opening, the second electrode layer includes a first structural portion, a second structural portion, and a third structural portion arranged sequentially, the first structural portion, the second structural portion, and the third structural portion being connected sequentially;

[0016] In the direction from the first groove to the corresponding first opening, the distance between the surface of the first structural part and the third structural part away from the substrate and the substrate gradually increases, while the distance between the surface of the second structural part away from the substrate and the substrate gradually decreases.

[0017] In an exemplary embodiment, there is a first difference between the maximum and minimum distance between the surface of the first structural portion away from the substrate and the substrate, a second difference between the maximum and minimum distance between the surface of the second structural portion away from the substrate and the substrate, and a third difference between the maximum and minimum distance between the surface of the third structural portion away from the substrate and the substrate.

[0018] In the direction from the first groove to the corresponding first opening, the length dimension of the first structural part is the first length dimension, the length dimension of the second structural part is the second length dimension, and the length dimension of the third structural part is the third length dimension;

[0019] The ratio of the third difference to the third length dimension is greater than the ratio of the first difference to the first length dimension; the ratio of the second difference to the second length dimension is greater than the ratio of the third difference to the third length dimension.

[0020] In an exemplary embodiment, the display substrate further includes a first electrode layer, which is located between the substrate and the pixel definition layer in a direction perpendicular to the plane of the substrate; the second electrode layer further includes a fourth structural portion in a direction from the first groove to the corresponding first opening; the fourth structural portion is located on the side of the third structural portion away from the second structural portion;

[0021] The distance between the surface of the fourth structural portion near the substrate and the surface of the first electrode layer away from the substrate is greater than the distance between the surface of the third structural portion near the substrate and the surface of the first electrode layer away from the substrate.

[0022] In an exemplary embodiment, the distance between the surface of the third structural portion near the substrate and the surface of the first electrode layer away from the substrate is greater than the minimum distance between the second structural portion and the pixel definition layer.

[0023] In an exemplary embodiment, the minimum distance between the second structural portion and the pixel definition layer is greater than the size of the second groove in the direction perpendicular to the substrate.

[0024] In an exemplary embodiment, the second electrode layer further includes a fourth structural portion in the direction from the first groove to the corresponding first opening. The fourth structural portion is located on the side of the third structural portion away from the second structural portion, and the fourth structural portion is connected to the third structural portion. At least a portion of the fourth structural portion is located in the pixel opening.

[0025] The first structural part is at least partially located within the first groove, with one end connected to the bottom wall of the first groove and the other end connected to the second structural part. The surface of the first structural part away from the base forms a first angle with the base.

[0026] One end of the second structural part is close to the first groove and connected to the first structural part, and the other end is close to the second groove and connected to the third structural part. A second included angle is formed between the surface of the second structural part away from the base and the base.

[0027] One end of the third structural part is close to the second groove and connected to the second structural part, and the other end is close to the corresponding pixel opening and connected to the fourth structural part. The surface of the third structural part away from the substrate forms a third included angle with the substrate.

[0028] The first included angle and the third included angle are both acute angles, the second included angle is an obtuse angle, and the angles of the supplementary angle of the second included angle, the third included angle, and the first included angle decrease sequentially.

[0029] In an exemplary embodiment, the fourth structural portion is parallel to the substrate.

[0030] In an exemplary embodiment, in a direction perpendicular to the plane of the substrate, the light-emitting structure layer includes at least a first light-emitting structure sublayer, a light-emitting layer, and a second light-emitting structure sublayer sequentially stacked on one side of the substrate, wherein the first light-emitting structure sublayer is broken at the second groove position.

[0031] In an exemplary embodiment, in a direction perpendicular to the plane of the substrate, the pixel definition layer includes a first pixel definition layer, a second pixel definition layer, and a third pixel definition layer stacked sequentially on one side of the substrate. The surface of the second pixel definition layer near any of the light-emitting structures is recessed into the surfaces of the first pixel definition layer and the third pixel definition layer near the same light-emitting structure, forming the second groove.

[0032] In an exemplary embodiment, in a direction perpendicular to the plane of the substrate, the thickness of the second pixel definition layer is greater than half the thickness of the first light-emitting structure sublayer.

[0033] In an exemplary embodiment, the first pixel definition layer and the third pixel definition layer are silicon oxide layers, and the second pixel definition layer is a silicon nitride layer.

[0034] In an exemplary embodiment, the partition structure layer includes a first partition structure layer and a second partition structure layer stacked sequentially on the side of the pixel definition layer away from the substrate. The surface of the first partition structure layer near any of the light-emitting structures is recessed into the surface of the second partition structure layer near the same light-emitting structure, forming the first groove.

[0035] In an exemplary embodiment, the pixel definition layer has a first recess on the side away from the substrate, and the first partition structure layer has a second recess on the side away from the substrate.

[0036] The first recess includes a first intermediate region and two first sub-recesses located on both sides of the first intermediate region. The height of the surface of the first intermediate region away from the substrate relative to the substrate is greater than the height of the surface of the first sub-recesses away from the substrate relative to the substrate, and less than the height of the surface of the pixel definition layer located outside the first recess relative to the substrate relative to the substrate.

[0037] The second recess includes a second intermediate region and two second sub-recesses located on both sides of the second intermediate region. The height of the surface of the second intermediate region away from the substrate relative to the substrate is greater than the height of the surface of the second sub-recesses away from the substrate relative to the substrate, but less than the height of the surface of the first partition structure layer outside the second recess relative to the substrate relative to the substrate.

[0038] In an exemplary embodiment, in a direction perpendicular to the substrate, among a first connecting line and a second connecting line located in the same plane, the orthographic projection of the second connecting line on the substrate is within the range of the orthographic projection of the corresponding first connecting line on the substrate, wherein the first connecting line is a connecting line between two first sub-recesses located in the same first recess, and the second connecting line is a connecting line between two second sub-recesses located in the same second recess.

[0039] In an exemplary embodiment, the first connecting line is a line connecting two first sub-recesses located in the same first recess, and the second connecting line is a line connecting two second sub-recesses located in the same second recess, the first position being the position where the height of the surface of the first sub-recess near the base is the smallest relative to the base, and the second position being the position where the height of the surface of the second sub-recess near the base is the smallest relative to the base.

[0040] In an exemplary embodiment, the second partition structure layer has a third recess on the side away from the substrate. The third recess includes a third intermediate region and two third sub-recesses located on both sides of the third intermediate region. The height of the surface of the third intermediate region away from the substrate relative to the substrate is greater than the height of the surface of the third sub-recesses away from the substrate relative to the substrate, and less than the height of the surface of the second partition structure layer outside the third recess relative to the substrate.

[0041] The distance between two first sub-recesses located in the same first recess is the first distance, the distance between two second sub-recesses located in the same second recess is the second distance, and the distance between two third sub-recesses located in the same third recess is the third distance. The difference between the first distance and the corresponding second distance is less than the difference between the second distance and the corresponding third distance.

[0042] In an exemplary embodiment, in a direction perpendicular to the plane of the substrate, the thickness of the first partition structure layer is 1.5 to 3 times the thickness of the second partition structure layer, and the thickness of the first partition structure layer is 1.5 to 3 times the thickness of the pixel definition layer.

[0043] In an exemplary embodiment, the cross-sectional structure of the first partition structure layer between two adjacent first openings is a "T" shaped structure.

[0044] In an exemplary embodiment, the cross-sectional structure of the first partition structure layer and the second electrode transition layer between two adjacent first openings is an "I" shaped structure.

[0045] In an exemplary embodiment, the first partition structure layer is a silicon nitride layer, and the second partition structure layer is a silicon oxide layer.

[0046] In an exemplary embodiment, on a plane parallel to the substrate, the second electrode transition layer includes a first groove region and an intermediate region surrounded by the first groove region, the bottom wall of the first groove being located in the first groove region, and the intermediate region being covered by the partition structure layer; in a direction perpendicular to the substrate, the thickness of the intermediate region is greater than the thickness of the first groove region.

[0047] In an exemplary embodiment, the thickness of the first groove region gradually decreases in the direction perpendicular to the substrate, from the first groove to the corresponding first opening.

[0048] Secondly, embodiments of this disclosure provide a display device including any of the display substrates described above.

[0049] Thirdly, embodiments of this disclosure provide a method for preparing a display substrate, comprising:

[0050] A pixel definition layer is formed on one side of the substrate, and the pixel definition layer has multiple pixel openings;

[0051] A second electrode transition layer and a barrier structure layer are sequentially formed on the side of the pixel definition layer away from the substrate. The second electrode transition layer and the barrier structure layer have multiple first openings, each corresponding to a pixel opening. The orthographic projection of the first opening onto the substrate at least partially overlaps with the orthographic projection of the corresponding pixel opening onto the substrate. The sidewall of the first opening has a first groove. At least a portion of the surface of the second electrode transition layer on the side away from the substrate, not covered by the barrier structure layer, serves as the bottom wall of the first groove. The distance between the bottom wall of the first groove and the substrate gradually decreases in the direction from the first groove to the corresponding first opening.

[0052] A light-emitting structure layer is formed on the side of the partition structure layer away from the substrate. The light-emitting structure layer includes a plurality of light-emitting structures, each of which corresponds to a plurality of pixel openings. At least a portion of each light-emitting structure is located in the corresponding pixel opening. The light-emitting structure layer is broken at the first groove position.

[0053] A second electrode layer is formed on the side of the light-emitting structure layer away from the substrate. The second electrode layer is disconnected at the first groove position and connected to the bottom wall of the first groove at the disconnected position.

[0054] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0055] The accompanying drawings are provided to illustrate the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure. The shape and size of each component in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure.

[0056] Figure 1 is a schematic diagram of a display device;

[0057] Figure 2 is a schematic diagram of the planar structure of a display device;

[0058] Figure 3a is a cross-sectional structural diagram of a display substrate provided in an embodiment of this disclosure;

[0059] Figure 3b is a cross-sectional structural diagram of a display substrate provided in an exemplary embodiment of the present disclosure;

[0060] Figure 3c is a cross-sectional structural diagram of a display substrate provided in an exemplary embodiment of the present disclosure;

[0061] Figure 3d is a cross-sectional structural diagram of a display substrate provided in an exemplary embodiment of the present disclosure;

[0062] Figure 4a is a schematic diagram of a display substrate after the formation of a first electrode layer according to an exemplary embodiment of the present disclosure;

[0063] Figure 4b is a schematic diagram of a display substrate after a filler structural layer film has been formed, according to an exemplary embodiment of the present disclosure.

[0064] Figure 4c is a schematic diagram of a display substrate after a filling structure has been formed, according to an exemplary embodiment of the present disclosure;

[0065] Figure 4d is a schematic diagram of a display substrate after forming a third pixel definition film according to an exemplary embodiment of the present disclosure;

[0066] Figure 4e is a schematic diagram of a display substrate after forming a pixel definition layer according to an exemplary embodiment of the present disclosure;

[0067] Figure 4f is a schematic diagram of a display substrate after a trench is formed on the side of the pixel definition layer away from the substrate, according to an exemplary embodiment of the present disclosure.

[0068] Figure 4g is a schematic diagram of a display substrate after a trench is formed on the side of the pixel definition layer away from the substrate, according to an exemplary embodiment of the present disclosure.

[0069] Figure 4h is a schematic diagram of a display substrate after a trench is formed on the side of the pixel definition layer away from the substrate, according to an exemplary embodiment of the present disclosure.

[0070] Figure 4i is a schematic diagram of a display substrate after the formation of a second electrode transition layer according to an exemplary embodiment of the present disclosure;

[0071] Figure 4j is a schematic diagram of a display substrate after forming a second barrier structure thin film according to an exemplary embodiment of the present disclosure;

[0072] Figure 4k is a schematic diagram of a display substrate after forming an isolation structure layer according to an exemplary embodiment of the present disclosure;

[0073] Figure 41 is a schematic diagram of a display substrate after forming an encapsulation layer according to an exemplary embodiment of the present disclosure;

[0074] Figure 4m is a schematic diagram of a display substrate after forming a microlens structure according to an exemplary embodiment of the present disclosure;

[0075] Figure 4n is a schematic diagram of a display substrate after a filler layer has been formed, according to an exemplary embodiment of the present disclosure.

[0076] Figure 5 is a schematic diagram of a driving circuit layer in a display substrate provided by an exemplary embodiment of the present disclosure;

[0077] Figure 6a is an external structural diagram of a pixel definition layer provided by an exemplary embodiment of the present disclosure;

[0078] Figure 6b is a cross-sectional structural diagram of an encapsulation layer after being formed, provided by an exemplary embodiment of the present disclosure;

[0079] Figure 6c is a cross-sectional structural diagram of an encapsulation layer after being formed, provided by an exemplary embodiment of the present disclosure;

[0080] Figure 7 is a schematic diagram of a display device provided in an embodiment of this disclosure. Detailed Implementation

[0081] To make the objectives, technical solutions, and advantages of this disclosure clearer, embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be varied in various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0082] The scale of the figures in this disclosure can be used as a reference in actual manufacturing processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The figures described in this disclosure are only schematic diagrams of the structure, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0083] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0084] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0085] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0086] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0087] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged, and the "source terminal" and "drain terminal" can be interchanged.

[0088] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0089] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0090] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0091] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.

[0092] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0093] Figure 1 is a schematic diagram of a display device. As shown in Figure 1, the display device may include a timing controller, a data signal driver, a scan signal driver, and a pixel array. The pixel array may include multiple scan signal lines (S1 to Sm), multiple data signal lines (D1 to Dn), and multiple sub-pixels Pxij.

[0094] In an exemplary embodiment, the timing controller can provide grayscale values ​​and control signals of specifications suitable for the data signal driver to the data signal driver, and can provide clock signals, scan start signals, etc., of specifications suitable for the scan signal driver to the scan signal driver. The data signal driver can use the grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to the data signal lines D1, D2, D3, ..., Dn. For example, the data signal driver can sample the grayscale values ​​using a clock signal and apply the data voltage corresponding to the grayscale values ​​to the data signal lines D1 to Dn on a sub-pixel row basis, where n can be a natural number. The scan signal driver can generate scan signals to be provided to the scan signal lines S1, S2, S3, ..., Sm by receiving clock signals, scan start signals, etc., from the timing controller. For example, the scan signal driver can sequentially provide scan signals with on-level pulses to the scan signal lines S1 to Sm. For example, a scan signal driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals, provided in the form of on-level pulses, to the next stage circuit under the control of a clock signal, where m can be a natural number. A sub-pixel array can include multiple sub-pixels PXij. Each sub-pixel PXij can be connected to a corresponding data signal line and a corresponding scan signal line, where i and j can be natural numbers. A sub-pixel PXij can refer to a sub-pixel whose transistor is connected to the i-th scan signal line and to the j-th data signal line.

[0095] Figure 2 is a schematic diagram of a planar structure of a display device. As shown in Figure 2, the display area of ​​the display device may include multiple pixel units P arranged in a matrix. At least one of the multiple pixel units P includes a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light. Each of the first sub-pixel P1, second sub-pixel P2, and third sub-pixel P3 includes a pixel driving circuit and a light-emitting device. The pixel driving circuit in the sub-pixel is connected to a scan signal line and a data signal line, respectively. The pixel driving circuit is configured to receive the data voltage transmitted by the data signal line under the control of the scan signal line and output a corresponding current to the light-emitting device. The light-emitting device in the sub-pixel is connected to the pixel driving circuit of its respective sub-pixel. The light-emitting device is configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of its respective sub-pixel.

[0096] In an exemplary embodiment, the first sub-pixel P1 can be a red sub-pixel emitting red (R) light, the second sub-pixel P2 can be a blue sub-pixel emitting blue (B) light, and the third sub-pixel P3 can be a green sub-pixel emitting green (G) light. In an exemplary embodiment, the shape of the sub-pixels can be any one or more of triangles, squares, rectangles, rhombuses, trapezoids, parallelograms, pentagons, hexagons, and other polygons, and they can be arranged in horizontal parallel, vertical parallel, X-shaped, cross-shaped, triangular, square, diamond-shaped, or delta-shaped arrangements, etc., without limitation herein.

[0097] In an exemplary embodiment, the number of sub-pixels included in a pixel unit is not limited to three. For example, a pixel unit may include four sub-pixels, and this disclosure does not limit it.

[0098] In display products, some film layers (such as hole injection layer and hole transport layer) in the light-emitting structure layer of the light-emitting device climb up the sidewall of the pixel opening, causing the distance between some film layers in the light-emitting structure layer and the second electrode layer (which can be used as a cathode layer) to be too close, resulting in leakage current, which in turn leads to display abnormalities (for example, display abnormalities include color crosstalk between adjacent sub-pixels).

[0099] This disclosure provides a display substrate, which may include a substrate and a pixel definition layer, a second electrode transition layer, a partition structure layer, a light-emitting structure layer and a second electrode layer sequentially disposed on one side of the substrate; the pixel definition layer is provided with a plurality of pixel openings, and the light-emitting structure layer includes a plurality of light-emitting structures, the plurality of light-emitting structures corresponding one-to-one with the plurality of pixel openings, and at least a portion of the light-emitting structures being located in the corresponding pixel openings.

[0100] The second electrode transition layer and the isolation structure layer are provided with a plurality of first openings, each of which corresponds to a plurality of pixel openings. The orthographic projection of the first opening on the substrate at least partially overlaps with the orthographic projection of the corresponding pixel opening on the substrate. The sidewall of the first opening is provided with a first groove, and the light-emitting structure layer and the second electrode layer are disconnected at the first groove position.

[0101] In the surface of the second electrode transfer layer on the side away from the substrate, at least a portion of the area not covered by the partition structure layer serves as the bottom wall of the first groove. The second electrode layer is connected to the bottom wall of the first groove in the disconnected position. In the direction from the first groove to the corresponding first opening, the distance between the bottom wall of the first groove and the substrate gradually decreases.

[0102] The display substrate provided in this disclosure includes a substrate and a pixel definition layer, a second electrode transition layer, a barrier structure layer, a light-emitting structure layer, and a second electrode layer sequentially disposed on one side of the substrate. The pixel definition layer has multiple pixel openings, and the second electrode transition layer and the barrier structure layer have multiple first openings, each corresponding to one of the pixel openings. A first groove is provided on the sidewall of each first opening. The light-emitting structure layer and the second electrode layer are disconnected at the first groove location. The second electrode layer is connected to the bottom wall of the first groove at the disconnected location. The distance between the bottom wall of the first groove and the substrate gradually decreases from the first groove towards the corresponding first opening. The technical solution provided in this disclosure, where the light-emitting structure layer and the second electrode layer are disconnected at the first groove location, can prevent leakage caused by excessively close proximity between the portion of the film layer near the substrate in the light-emitting structure layer and the second electrode layer, effectively reducing the risk of display abnormalities.

[0103] In an exemplary embodiment, the second electrode layer is connected to the bottom wall of the first groove at the disconnected position. The bottom wall of the first groove is a portion of the surface of the second electrode adapter layer away from the substrate. The second electrode layer disconnected at the first groove position can be connected through the second electrode adapter layer. That is, the second electrode layer is connected through the second electrode adapter layer at multiple disconnected positions of the first groove.

[0104] In an exemplary embodiment, the distance between the bottom wall of the first groove and the substrate gradually decreases in the direction from the first groove to the corresponding first opening. Under the premise of avoiding leakage between the light-emitting structure layer and the second electrode, the contact area between the second electrode layer and the second electrode transition layer can be increased, thus avoiding poor contact between the second electrode layer and the second electrode transition layer.

[0105] Figure 3a is a cross-sectional structural diagram of a display substrate according to an embodiment of the present disclosure. As shown in Figure 3a, the display substrate may include a substrate 101 and a pixel definition layer PDL, a second electrode transition layer 13, a partition structure layer 30, a light-emitting structure layer 40, and a second electrode layer 42 sequentially disposed on one side of the substrate 101; the pixel definition layer PDL is provided with a plurality of pixel openings K11, and the light-emitting structure layer 40 includes a plurality of light-emitting structures 41, the plurality of light-emitting structures 41 corresponding one-to-one with the plurality of pixel openings K11, and at least a portion of the light-emitting structure 41 is located in the corresponding pixel opening K11;

[0106] The second electrode transition layer 13 and the partition structure layer 30 are provided with a plurality of first openings K21, and the plurality of first openings K21 correspond one-to-one with a plurality of pixel openings K11. The orthographic projection of the first opening K21 on the substrate 101 at least partially overlaps with the orthographic projection of the corresponding pixel opening K11 on the substrate. The sidewall of the first opening K21 is provided with a first groove W1, and the light-emitting structure layer 40 and the second electrode layer 42 are disconnected at the first groove W1.

[0107] In the surface of the second electrode transition layer 13 away from the substrate, at least a portion of the area not covered by the partition structure layer 30 serves as the bottom wall C1 of the first groove W1. The second electrode layer 42 is connected to the bottom wall C1 of the first groove W1 in the disconnected position. In the direction from the first groove W1 to the corresponding first opening K21, the distance M1 between the bottom wall C1 of the first groove W1 and the substrate gradually decreases.

[0108] In some possible implementations, the display device may include other film layers, such as, as shown in Figures 3b to 3d, an encapsulation layer 43 disposed on the side of the second electrode layer 42 away from the substrate, a color filter structure layer and a touch structure layer disposed on the encapsulation structure layer 43 away from the substrate, a driving circuit layer 102 located between the pixel definition layer PDL and the substrate 101, and a first electrode 11 located between the driving circuit layer 102 and the light-emitting structure layer 40. This disclosure is not limited herein. In an exemplary embodiment, the first electrode 11 (which may serve as an anode), the second electrode 42, and the light-emitting structure 41 located between the first electrode 11 and the second electrode 42 constitute a light-emitting device. There are multiple first electrodes 11, and each of the multiple first electrodes 11 corresponds one-to-one with a multiple light-emitting structure 41. At least a portion of the first electrode 11 is located in the pixel opening K11, and the orthogonal projections of the first electrode 11 and the corresponding light-emitting structure 41 on the substrate 101 at least partially overlap. As shown in Figure 3b, the first groove W1 can be filled by the encapsulation layer 43, or as shown in Figures 3c and 3d, at least a portion of the space in the first groove W1 is not filled by the encapsulation layer 43, and the space not filled by the encapsulation layer 43 forms a closed space R1.

[0109] In an exemplary embodiment, the substrate 101 may be a flexible substrate, such as polyimide (PI). The driving circuit layer 102 may be fabricated on the substrate 101 using silicon semiconductor processes (e.g., CMOS processes). The driving circuit layer 102 may include multiple pixel driving circuits, and a sub-pixel may include a light-emitting device and a pixel driving circuit that drives the light-emitting device to emit light.

[0110] In an exemplary embodiment, the second electrode layer 42 can overlap with the bottom wall C1 of the first groove W1 in the disconnected position. The second electrode layer 42 can be connected via the second electrode transition layer 13. In an exemplary embodiment, in the direction from the first groove W1 to the corresponding first opening K21, the bottom wall C1 of the first groove W1 may include a first region d1 and a second region d2 arranged sequentially, with the second region d2 located between the corresponding first opening K21 and the first region d1; the second electrode layer 42 overlaps with the first region d1 in the disconnected position, and the light-emitting structure layer 40 covers the second region d2 in the disconnected position. In the direction from the first groove W1 to the corresponding first opening K21, the distance M1 between the bottom wall C1 of the first groove W1 and the substrate 101 gradually decreases. Under the premise of avoiding leakage between the light-emitting structure layer 40 and the second electrode, the contact area between the second electrode layer 42 and the second electrode transition layer 13 can be increased, avoiding poor contact between the second electrode layer 42 and the second electrode transition layer 13, and improving the stability of the connection between the second electrode layer 42 and the second electrode transition layer 13.

[0111] In an exemplary embodiment, the distance M1 between the bottom wall C1 of the first groove W1 and the substrate gradually decreases in the direction from the first groove W1 to the corresponding first opening K21, which can increase the area of ​​the first region d1 and improve the contact area between the second electrode layer 42 and the second electrode transition layer 13.

[0112] In an exemplary embodiment, the light-emitting structure layer 40 may include multiple stacked film layers. A second groove W2 is provided on the sidewall of the pixel opening K11. The minimum distance r1 between the second electrode layer 42 and the second groove W2 is less than the average thickness of the light-emitting structure layer 40 corresponding to the second region d2. This allows at least a portion of the film layer structure on the side of the light-emitting structure layer 40 closest to the substrate 101 to be disconnected at the second groove W2 position, and the light-emitting structure layer 40 corresponding to the second region d2 to cover the corresponding second region d2. The second groove W2 forms an undercut structure, disconnecting at least a portion of the film layer structure (e.g., hole injection layer and hole transport layer) on the side of the light-emitting structure layer 40 closest to the substrate 101. This avoids leakage caused by the distance between the portion of the film layer on the side of the light-emitting structure layer 40 closest to the substrate 101 and the second electrode layer 42 being too close, thus improving the defect of crosstalk between adjacent sub-pixels caused by leakage current.

[0113] In an exemplary embodiment, the first groove W1 forms an undercut structure, disconnecting the light-emitting structure layer 40 and the second electrode layer 42. This prevents leakage caused by the light-emitting structure layer 40 and the second electrode layer 42 being too close, thus mitigating the crosstalk between adjacent sub-pixels caused by leakage current. The first groove W1 prevents the second electrode layer 42 and the light-emitting structure layer 40 from climbing onto the surface of the isolation structure layer 30 away from the substrate, and the second groove W2 prevents at least a portion of the film layer in the light-emitting structure layer 40 from climbing onto the surface of the second electrode transition layer 13 away from the substrate, further reducing color crosstalk between adjacent sub-pixels.

[0114] In an exemplary embodiment, on a plane parallel to the substrate, in the direction from the first groove W1 to the corresponding first opening K21, the ratio of the size L1 of the first groove W1 to the size L2 of the second groove W2 is greater than or equal to 5:1.

[0115] In an exemplary embodiment, in the direction Z perpendicular to the substrate, the ratio of the size H1 of the first groove W1 to the size H2 of the second groove W2 is greater than or equal to 5:1.

[0116] In an exemplary embodiment, L1:L2 is greater than or equal to 5:1 and H1:H2 is greater than or equal to 5:1. During the fabrication of the display substrate, the second electrode layer 42 and the light-emitting structure layer 41 can be disconnected by the first groove W1, and at least a portion of the film layer structure in the light-emitting structure layer 41 can be disconnected by the second groove 42. However, this disclosure is not limited to this. The dimensions of L1, L2, H1, and H2 and their corresponding proportional relationships can be set according to the thickness of multiple film layers in the light-emitting structure layer 41 (such as the thickness of the hole injection layer and the hole transport layer) and the thickness of the second electrode layer 42. This can achieve the goal of disconnecting the second electrode layer 42 and the light-emitting structure layer 41 by the first groove W1 and disconnecting at least a portion of the film layer structure in the light-emitting structure layer 41 by the second groove 42.

[0117] In an exemplary embodiment, as shown in FIG3d, in the direction from the first groove W1 to the corresponding first opening K21, the difference between the maximum distance M11 and the minimum distance M12 between the bottom wall C1 of the first groove W1 and the substrate 101 is greater than the minimum distance r1 between the second electrode layer 42 and the second groove W2, but less than the thickness of the second electrode layer 42.

[0118] In an exemplary embodiment, on a plane parallel to the substrate 101, in the direction from the first groove W1 to the corresponding first opening K21, the second electrode layer 42 may include a first structural part 421, a second structural part 422 and a third structural part 423 arranged sequentially, with the first structural part 421, the second structural part 422 and the third structural part 423 connected in sequence.

[0119] In the direction from the first groove W1 to the corresponding first opening K21, the distance between the surface of the first structural part 421 and the third structural part 423 away from the substrate and the substrate gradually increases, while the distance between the surface of the second structural part 422 away from the substrate and the substrate gradually decreases.

[0120] In an exemplary embodiment, as shown in FIG3d, there is a first difference between the maximum distance b11 and the minimum distance b12 between the surface of the first structural part 421 on the side away from the base 101 and the base 101; there is a second difference between the maximum distance b21 and the minimum distance b22 between the surface of the second structural part 422 on the side away from the base 101 and the base 101; and there is a third difference between the maximum distance b31 and the minimum distance b32 between the surface of the third structural part 423 on the side away from the base 101 and the base 101.

[0121] In the direction from the first groove W1 to the corresponding first opening K21, the length dimension of the first structural part 421 is the first length dimension V1, the length dimension of the second structural part 422 is the second length dimension V2, and the length dimension of the third structural part 423 is the third length dimension V3.

[0122] The ratio of the third difference to the third length dimension V3 is greater than the ratio of the first difference to the first length dimension V1; the ratio of the second difference to the second length dimension V2 is greater than the ratio of the third difference to the third length dimension V3.

[0123] In an exemplary embodiment, the display substrate may further include a first electrode layer 103, which may be located between the substrate 101 and the pixel definition layer PDL in a direction perpendicular to the plane of the substrate 101; the second electrode layer 42 may further include a fourth structural portion 424, which is located in the direction from the first groove W1 to the corresponding first opening K21; the fourth structural portion 424 is located on the side of the third structural portion 423 away from the second structural portion 422;

[0124] The distance d41 between the surface of the fourth structural part 424 near the substrate 101 and the surface of the first electrode layer 103 away from the substrate 101 is greater than the distance d33 between the surface of the third structural part 423 near the substrate 101 and the surface of the first electrode layer 103 away from the substrate 101.

[0125] In an exemplary embodiment, as shown in FIG3d, the distance d33 between the surface of the third structural portion 423 near the substrate 101 and the surface of the first electrode layer 103 away from the substrate 101 is greater than the minimum distance r2 between the second structural portion 422 and the pixel definition layer PDL.

[0126] In an exemplary embodiment, the minimum distance r2 between the second structural portion 422 and the pixel definition layer PDL is greater than the size H2 of the second groove W2 in the direction Z perpendicular to the substrate 101.

[0127] In an exemplary embodiment, the second electrode layer 42 may further include a fourth structural portion 424 in the direction from the first groove W1 to the corresponding first opening K21. The fourth structural portion 424 is located on the side of the third structural portion 423 away from the second structural portion 422. The fourth structural portion 424 is connected to the third structural portion 423. At least a portion of the fourth structural portion 424 is located in the pixel opening K11.

[0128] The first structural part 421 is at least partially located in the first groove W1, with one end connected to the bottom wall C1 of the first groove W1 and the other end connected to the second structural part 422. The surface of the first structural part 421 away from the base 101 forms a first included angle f1 with the base. In an exemplary embodiment, one end of the first structural part 421 is connected to a first region d1 in the bottom wall C1 of the first groove W1.

[0129] The second structural part 422 is connected to the first structural part 421 and the third structural part 423. One end is close to the first groove W1 and connected to the first structural part 421, and the other end is close to the second groove W2 and connected to the third structural part 423. The surface of the second structural part 422 away from the base 101 forms a second included angle f2 with the base.

[0130] The third structural part 423 is connected to the second structural part 422 and the fourth structural part 424. One end is close to the second groove W2 and connected to the second structural part 422, and the other end is close to the corresponding pixel opening K11 and connected to the fourth structural part 424. A third included angle f3 is formed between the surface of the third structural part 423 away from the substrate 101 and the substrate.

[0131] The first included angle f1 and the third included angle f3 are both acute angles, the second included angle f2 is an obtuse angle, and the angles of the supplementary angle f0 of the second included angle f2, the third included angle f3, and the first included angle f1 decrease sequentially.

[0132] In an exemplary embodiment, the slope of the surface of the first structural part 421 away from the substrate relative to the substrate, the slope of the surface of the third structural part 423 away from the substrate relative to the substrate, and the slope of the surface of the second structural part 422 away from the substrate relative to the substrate increase sequentially.

[0133] In an exemplary embodiment, the fourth structural portion 424 may be parallel to the substrate 101.

[0134] In an exemplary embodiment, in the direction Z perpendicular to the plane of the substrate, the light-emitting structure layer 40 includes at least a first light-emitting structure sublayer 411, a light-emitting layer 412, and a second light-emitting structure sublayer 413 sequentially stacked on one side of the substrate. The first light-emitting structure sublayer 411 is interrupted at the location of the second groove W2. In an exemplary embodiment, the first light-emitting structure sublayer 411 may include a hole injection layer and a hole transport layer sequentially stacked, and the second light-emitting structure sublayer 413 may include one or more of the following: a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), an electron injection layer (EIL), and a charge production layer (CGL). In the direction perpendicular to the substrate, the light-emitting structure 41 located between the first electrode 11 and the second electrode 42 can emit light under the drive of the first electrode 11 and the second electrode 42.

[0135] In an exemplary embodiment, in the direction Z perpendicular to the plane of the substrate, the pixel definition layer PDL may include a first pixel definition layer PDL1, a second pixel definition layer PDL2 and a third pixel definition layer PDL3 stacked sequentially on one side of the substrate. The surface of the second pixel definition layer PDL2 near any of the light-emitting structures 41 is recessed into the surfaces of the first pixel definition layer PDL1 and the third pixel definition layer PDL3 near the same light-emitting structure 41, forming a second groove W2.

[0136] In an exemplary embodiment, the thickness of the third pixel definition layer PDL3 is greater than half the thickness of the light-emitting structure layer 41 in the direction Z perpendicular to the plane of the substrate.

[0137] In an exemplary embodiment, in the direction Z perpendicular to the plane of the substrate, the thickness of the second pixel definition layer PDL2 is greater than half the thickness of the first light-emitting structure sublayer 411.

[0138] In an exemplary embodiment, the first pixel definition layer PDL1 and the third pixel definition layer PDL3 can be silicon oxide layers, and the second pixel definition layer PDL2 can be a silicon nitride layer.

[0139] In an exemplary embodiment, the minimum distance r2 between the second structural portion 422 and the pixel definition layer PDL is less than or equal to the minimum distance r3 between the second structural portion 422 and the third pixel definition layer PDL3. In an exemplary embodiment, the minimum distance r3 between the second structural portion 422 and the third pixel definition layer PDL3 is greater than the dimension H2 of the second groove W2 in the direction Z perpendicular to the substrate 101, and less than the distance d33 between the surface of the third structural portion 423 on the side closer to the substrate 101 and the surface of the first electrode layer 103 on the side farther from the substrate 101.

[0140] In an exemplary embodiment, the partition structure layer 30 may include a first partition structure layer 31 and a second partition structure layer 32 sequentially stacked on the side of the pixel definition layer PDL away from the substrate. The surface of the first partition structure layer 31 near any light-emitting structure 41 is recessed into the surface of the second partition structure layer 32 near the same light-emitting structure 41, forming a first groove W1.

[0141] In an exemplary embodiment, as shown in Figures 6b and 6c, a first recess 81 is provided on the side of the pixel definition layer (PDL) away from the substrate 101, and a second recess 82 is provided on the side of the first partition structure layer (31) away from the substrate 101.

[0142] The first recess 81 may include a first intermediate region 811 and two first sub-recesses 812 located on both sides of the first intermediate region 811. The height H11 of the surface of the first intermediate region 811 away from the substrate relative to the substrate 101 is greater than the height H12 of the surface of the first sub-recesses 812 away from the substrate relative to the substrate 101, and less than the height H13 of the surface of the pixel definition layer PDL located outside the first recess 81 away from the substrate 101 relative to the substrate 101.

[0143] The second recess 82 may include a second intermediate region 821 and two second sub-recesses 822 located on both sides of the second intermediate region 821. The height H21 of the surface of the second intermediate region 821 away from the substrate relative to the substrate 101 is greater than the height H22 of the surface of the second sub-recesses 822 away from the substrate relative to the substrate 101, and less than the height H23 of the surface of the first partition structure layer 31 located outside the second recess 82 away from the substrate relative to the substrate 101.

[0144] In an exemplary embodiment, in the direction Z perpendicular to the substrate, among the first and second connecting lines located in the same plane, the orthographic projection of the second connecting line on the substrate is within the range of the orthographic projection of the corresponding first connecting line on the substrate. The first connecting line is the connecting line between two first sub-recesses 812 located in the same first recess 81, and the second connecting line is the connecting line between two second sub-recesses 822 located in the same second recess 82.

[0145] In an exemplary embodiment, the first connecting line is the line connecting the first positions 810 of two first sub-recesses 812 located in the same first recess 81, and the second connecting line is the line connecting the second positions 820 of two second sub-recesses 822 located in the same second recess 82. The first position 810 is the position where the surface of the first sub-recess 812 near the substrate has the smallest height relative to the substrate, and the second position 820 is the position where the surface of the second sub-recess 822 near the substrate has the smallest height relative to the substrate. In an exemplary embodiment, the third position 830 is the position where the surface of the third sub-recess 832 near the substrate has the smallest height relative to the substrate.

[0146] In an exemplary embodiment, a third recess 83 is provided on the side of the second partition structure layer 32 away from the substrate. The third recess includes a third intermediate region 831 and two third sub-recesses 832 located on both sides of the third intermediate region 831. The height H31 of the surface of the third intermediate region 831 away from the substrate relative to the substrate is greater than the height H32 of the surface of the third sub-recesses 832 away from the substrate relative to the substrate, and less than the height H33 of the surface of the second partition structure layer 32 outside the third recess relative to the substrate relative to the substrate.

[0147] The distance between two first sub-recesses 812 located in the same first recess 81 is the first distance L11, the distance between two second sub-recesses 822 located in the same second recess 82 is the second distance L12, and the distance between two third sub-recesses 832 located in the same third recess 83 is the third distance L13. The difference between the first distance L11 and the corresponding second distance L12 is less than the difference between the second distance L12 and the corresponding third distance L13.

[0148] In an exemplary embodiment, the first distance L11 can be the distance between the first positions 810 of two first sub-recesses 812 located in the same first recess 81, the second distance L12 can be the distance between the second positions 820 of two second sub-recesses 822 located in the same second recess 82, and the third distance L13 can be the distance between the third positions 830 of two third sub-recesses 832 located in the same third recess 83.

[0149] In an exemplary embodiment, the minimum distance between the edge of the orthographic projection of the first recess 81 on the substrate and the edge of the orthographic projection of the corresponding second recess 82 on the substrate is greater than the minimum distance between the edge of the orthographic projection of the second recess 82 on the substrate and the edge of the orthographic projection of the corresponding third recess 83 on the substrate.

[0150] In an exemplary embodiment, the orthographic projection of the second recess 82 on the substrate is within the range of the orthographic projection of the corresponding first recess 81 on the substrate.

[0151] In an exemplary embodiment, in the direction Z perpendicular to the plane where the substrate is located, the thickness of the first partition structure layer 31 is 1.5 to 3 times the thickness of the second partition structure layer 32, and the thickness of the first partition structure layer 31 is 1.5 to 3 times the thickness of the pixel definition layer.

[0152] In an exemplary embodiment, the cross-sectional structure of the first partition structure layer 31 between two adjacent first openings K21 is a "T" shaped structure.

[0153] In an exemplary embodiment, the cross-sectional structure of the first partition structure layer 31 and the second electrode transition layer 13 between two adjacent first openings K21 is an "I" shaped structure.

[0154] In an exemplary embodiment, the first partition structure layer 31 may be a silicon nitride layer, and the second partition structure layer 32 may be a silicon oxide layer.

[0155] In an exemplary embodiment, the size H1 of the first groove W1 in the direction Z perpendicular to the substrate can be controlled by the thickness of the first partition structure layer 31, and the size H2 of the second groove W2 can be controlled by the thickness of the second pixel definition layer PDL2.

[0156] In an exemplary embodiment, on a plane parallel to the substrate, the size L1 of the first groove W1 can be controlled by the etching speed of the first partition structure layer 31 and the second partition structure layer 32 during the fabrication of the partition structure layer 30, and the size L2 of the second groove W2 can be controlled by the etching speed of the first pixel definition layer PDL1 to the third pixel definition layer PDL3 during the fabrication of the pixel definition layer PDL.

[0157] In an exemplary embodiment, on a plane parallel to the substrate, the second electrode transition layer 13 may include a first groove region q1 and an intermediate region q2 surrounded by the first groove region q1. The bottom wall C1 of the first groove W1 is located in the first groove region q1, and the intermediate region q2 is covered by the partition structure layer 30. In the direction Z perpendicular to the substrate, the thickness of the intermediate region q2 is greater than the thickness of the first groove region q1. Specifically, in the direction from the first groove W1 to the corresponding first opening W2, the first groove region q1 may include a first region d1 and a second region d2. The second region d2 is located between the first region d1 and the corresponding first opening W2, and the thickness of the first region d1 may be greater than the thickness of the second region d2.

[0158] In an exemplary embodiment, the thickness of the first groove region q1 in the direction perpendicular to the base direction Z gradually decreases from the direction of the first groove W1 to the corresponding first opening K21.

[0159] The following description uses the fabrication process of a display substrate as an example. The terms "patterning process" and "photolithography process" used in this disclosure, for metallic, inorganic, or transparent conductive materials, include processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, they include processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. "Thin film" refers to a thin film made of a certain material on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0160] In an exemplary embodiment, the fabrication process of the display substrate may include the following operations.

[0161] (101) Form a driving circuit layer and a first electrode layer.

[0162] In an exemplary embodiment, forming the driving circuit layer and the first electrode layer may include: forming a driving circuit layer 102 on a substrate 101; depositing a first conductive film on the side of the driving circuit layer 102 away from the substrate 101; patterning the first conductive film using a photolithography process to form a first electrode layer 103 disposed on the side of the driving circuit layer 102 away from the substrate 101; the first electrode layer 103 may include a plurality of first electrodes 11 (which may serve as anodes), as shown in FIG4a, the plurality of first electrodes 11 are spaced apart; and forming a filling structure between the plurality of first electrodes 11.

[0163] In an exemplary embodiment, the filling structure formed between the plurality of first electrodes 11 can be achieved using a Lateral Height Coverage (LHC) process to reduce the gap between the surface of the first electrode 11 away from the substrate 101 and the surface of the adjacent filling structure away from the substrate 101. As shown in FIG4b, a filling structure layer film 1031 covering the plurality of first electrodes 11 and the driving circuit layer 102 is deposited on the side of the first electrode layer 103 away from the substrate 101. The thickness of the filling structure layer film 1031 can be greater than the thickness of the first electrode 11. As shown in FIG4c, the filling structure layer film 1031 is thinned to be flush with the first electrode 11 by etching to obtain the filling structure 12. In the third direction Z, the surface of the filling structure 12 away from the substrate 101 is flush with the surface of the first electrode 11 away from the substrate 101. The cross-sectional structure diagram after the filling structure 12 is formed can be shown in Figure 4c. The filling structure 12 can be located between two adjacent first electrodes 11, so that the height of the first electrode 11 and the adjacent filling structure 12 on the side away from the substrate 101 is the same, thereby reducing the discontinuity between the first electrode 11 and the adjacent filling structure 12 on the side away from the substrate 101.

[0164] In an exemplary embodiment, the shape of the cross section of the filling structure 12 in the direction Z perpendicular to the substrate 101 may be an inverted trapezoid, and the shape of the cross section of the first electrode 11 in the direction Z perpendicular to the substrate 101 may be a regular trapezoid.

[0165] In an exemplary embodiment, the first electrode 11 may be a multilayer structure of titanium (Ti), titanium nitride (TiN), aluminum (Al), titanium nitride, and indium tin oxide (ITO) stacked sequentially on the driving circuit layer 102, or the first electrode 11 may be a double-layer structure of aluminum (Al) and indium tin oxide (ITO), and the material of the filling structure 12 may be silicon oxide (SiOx, for example, SiO).

[0166] (102) Form a pixel definition layer.

[0167] In an exemplary embodiment, forming a pixel definition layer may include: as shown in Figures 4d and 4e, on the substrate on which the aforementioned pattern is formed, a first pixel definition film 104 covering the first electrode 11 and the filling structure 12, a second pixel definition film 105 covering the first pixel definition film 104, and a third pixel definition film 106 covering the second pixel definition film 105 are sequentially deposited on the side away from the substrate 101. The first pixel definition film 104, the second pixel definition film 105, and the third pixel definition film 106 are patterned using a photolithography process, so that the first pixel definition film 104 is shaped... A first pixel definition layer PDL1 is formed on the side of the first electrode 11 and the filling structure 12 away from the substrate 101. A second pixel definition film 105 is formed on the side of the first pixel definition layer PDL1 away from the substrate 101, creating a second pixel definition layer PDL2. A third pixel definition film 106 is formed on the side of the second pixel definition layer PDL2 away from the substrate 101, creating a third pixel definition layer PDL3. As shown in FIG4e, the pixel definition layer PDL may include the first pixel definition layer PDL1, the second pixel definition layer PDL2, and the third pixel definition layer PDL3 sequentially stacked on the side of the first electrode 11 away from the substrate 101. In an exemplary embodiment, the pixel definition layer PDL has a plurality of pixel openings K11.

[0168] In an exemplary embodiment, the pixel definition layer PDL can also be etched (either by dry etching or by photolithography) on the side of the pixel definition layer PDL away from the substrate 101 to form a trench 21 (which can serve as the first recess 81 mentioned above). In the third direction Z, the depth of the trench 21 can be less than the thickness of the third pixel definition layer PDL3 (as shown in FIG. 4f), or greater than the thickness of the third definition layer PDL3 and less than the total thickness of the pixel definition layer PDL (as shown in FIG. 4g), or equal to the thickness of the third pixel definition layer PDL3 (as shown in FIG. 4h). The trench 21 can be etched based on the one shown in FIG. 4d (i.e., first etch the trench 21, and then form the pixel definition layer PDL by photolithography), or the trench 21 can be formed based on the one shown in FIG. 4e (i.e., first form the pixel definition layer PDL by photolithography, and then etch the trench 21).

[0169] In an exemplary embodiment, the contact area between the subsequently formed second electrode transition layer 13 and the pixel definition layer PDL can be increased by the trench 21, thereby enhancing the adhesion of the second electrode transition layer 13 and reducing the risk of the second electrode transition layer 13 peeling off.

[0170] In an exemplary embodiment, as shown in Figures 4f to 4h, the orthographic projection of the trench 21 onto the substrate 103 can lie within the range of the orthographic projection of the pixel definition layer PDL onto the substrate 101. The orthographic projections of the first pixel definition layer PDL1 to the third pixel definition layer PDL3 onto the substrate 101 can cover the orthographic projection of the trench 21 onto the substrate 103.

[0171] As shown in Figure 4e, the orthographic projection of the first pixel definition layer PDL1 on the substrate 101 does not overlap with the orthographic projection of the first electrode 11 on the substrate 101 at least partially, and at least the middle region of the first electrode 11 is not covered by the first pixel definition layer PDL1; the orthographic projection of the second pixel definition layer PDL2 on the substrate 101 is within the range of the orthographic projection of the first pixel definition layer PDL1 on the substrate 101, and the orthographic projection of the second pixel definition layer PDL2 on the substrate 101 is within the range of the orthographic projection of the third pixel definition layer PDL3 on the substrate 101.

[0172] In an exemplary embodiment, the first pixel definition layer PDL1 to the third pixel definition layer PDL3 constitute a pixel definition layer PDL. The cross-sections of the first pixel definition layer PDL1 and the third pixel definition layer PDL3 in the direction Z perpendicular to the substrate 101 can be regular trapezoids. The cross-section of the second pixel definition layer PDL2 in the direction Z perpendicular to the substrate 101 can be an inverted trapezoid. The orthogonal projection of the second pixel definition layer PDL2 on the substrate 101 is within the range of the orthogonal projection positions of the first pixel definition layer PDL1 and the third pixel definition layer PDL3 on the substrate 101.

[0173] In an exemplary embodiment, the pixel definition layer (PDL) may include inorganic materials, such as an oxide-nitride-oxide (ONO) stack structure. The materials of the first pixel definition layer (PDL1) and the third pixel definition layer (PDL3) may include silicon oxide (SiOx), and the material of the second pixel definition layer (PDL2) may include silicon nitride (SiNx), forming an ONO-structured pixel definition layer (PDL). In an exemplary embodiment, the etching rates of the first pixel definition film 104, the second pixel definition film 105, and the third pixel definition film 106 may be different. In an exemplary embodiment, different gases may be used to etch the first pixel definition film 104, the second pixel definition film 105, and the third pixel definition film 106; alternatively, the same gas may be used to etch the first pixel definition film 104, the second pixel definition film 105, and the third pixel definition film 106. In an exemplary embodiment, under the same etching conditions, the etching rate for silicon nitride (SiNx) is faster than that for silicon oxide (SiOx). This allows for the formation of a second pixel definition layer (PDL2) as shown in Figures 4e to 4h, where the second PDL2 is etched more extensively than the first and third pixel definition layers (PDL1 and PDL3). This results in a slightly inward-curving structure in the PDL in the direction perpendicular to the substrate 101, forming a second groove W2. The second groove W2 constitutes a first undercut structure 22, which can isolate at least a portion of the light-emitting structure layer near the substrate, preventing at least a portion of the light-emitting structure layer from climbing upwards along the PDL. During the etching process, because the second pixel definition film 105 is shielded by the first pixel definition film 104 on the side away from the substrate 101, the second pixel definition layer (PDL2) formed after etching is approximately an inverted trapezoidal structure.

[0174] (103) Form a second electrode transition layer.

[0175] In an exemplary embodiment, forming the second electrode transition layer may include: as shown in FIG4i, depositing a second conductive film on the side of the pixel definition layer PDL away from the substrate 101 on the substrate on which the aforementioned pattern is formed, and patterning the second conductive film by photolithography to form the second electrode transition layer 13 disposed on the side of the pixel definition layer PDL away from the substrate 101.

[0176] In an exemplary embodiment, the orthographic projection of the second electrode transition layer 13 on the substrate is within the orthographic projection range of the pixel definition layer PDL on the substrate, and the orthographic projection of the second electrode transition layer 13 on the substrate overlaps with the orthographic projections of the first pixel definition layer PDL1 to the third pixel definition layer PDL3 on the substrate.

[0177] In an exemplary embodiment, at least a portion of the second electrode transition layer 13 covers the third pixel definition layer PDL3 and the surface of the trench 21 away from the substrate 101.

[0178] In an exemplary embodiment, the orthographic projection of the second electrode transition layer 13 on the substrate covers the orthographic projection of the trench 21 on the substrate. At least a portion of the second electrode transition layer 13 fills the trench 21. The second electrode transition layer 13 forms a first recessed region 23 at the trench 21. The first recessed region 23 is recessed along the direction close to the substrate. The first recessed region 23 overlaps with the orthographic projection of the trench 21 on the substrate. For example, the orthographic projection of the first recessed region 23 on the substrate is located within the range of the orthographic projection of the trench 21 on the substrate.

[0179] In an exemplary embodiment, the second electrode transition layer 13 can be a single-layer structure or a multi-layer structure. For example, the second electrode transition layer 13 can be a single-layer structure, comprising a metal, alloy, or semiconductor, such as a highly conductive metal like aluminum, titanium, molybdenum, aluminum-neodymium alloy, or copper, or a semiconductor like indium tin oxide (ITO). The second electrode transition layer 13 can also be a multi-layer structure, for example, comprising a first thin film, a second thin film, and a third thin film sequentially disposed therefrom. The first and third thin films can both comprise titanium, and the second thin film can comprise one of aluminum, copper, or molybdenum; or at least one of the first to third thin films is an indium tin oxide (ITO) semiconductor, and the other two layers are metals or alloys.

[0180] (104) Forming a partition structure layer.

[0181] In an exemplary embodiment, forming the isolation structure layer may include: as shown in Figures 4j and 4k, on the substrate on which the aforementioned pattern is formed, a first isolation structure film 107 and a second isolation structure film 108 are sequentially deposited on the side of the second electrode transition layer away from the substrate 101; the first isolation structure film 107 and the second isolation structure film 108 are patterned by photolithography, so that the first isolation structure film 107 forms a first isolation structure layer disposed on the side of the second electrode transition layer away from the substrate 101, and the second isolation structure film 108 forms a second isolation structure layer disposed on the side of the first isolation structure layer away from the substrate 101; the isolation structure layer 30 includes a first isolation structure layer 31 and a second isolation structure layer 32; as shown in Figure 4k, the isolation structure layer 30 may include a first isolation structure layer 31 and a second isolation structure layer 32 sequentially stacked on the side of the second electrode transition layer 13 away from the substrate 101. In an exemplary embodiment, the isolation structure layer 30 is provided with a plurality of first openings K21. Multiple first openings K21 can correspond one-to-one with multiple pixel openings K11, and the orthographic projections of the first openings K21 and the corresponding pixel openings K11 on the substrate 101 at least partially overlap.

[0182] In an exemplary embodiment, the orthographic projection of the partition structure layer 30 on the substrate overlaps with the orthographic projection of the second electrode transition layer 13 on the substrate. For example, the orthographic projection of the partition structure layer 30 on the substrate may be within the range of the orthographic projection of the second electrode transition layer 13 on the substrate.

[0183] In an exemplary embodiment, the orthographic projection of the first partition structure layer 31 on the substrate overlaps with the orthographic projection of the second partition structure layer 32 on the substrate. For example, the orthographic projection of the first partition structure layer 31 on the substrate may be within the range of the orthographic projection of the second partition structure layer 32 on the substrate.

[0184] In an exemplary embodiment, the orthographic projection of the partition structure layer 30 onto the substrate covers the orthographic projection of the trench 21 onto the substrate, and at least part of the partition structure 31 covers the first recessed region 23 of the second electrode transition layer 13. The first partition structure layer 31 forms a second recessed region 24 (which can be the aforementioned second recessed portion 82) at the first recessed region 23, and the second partition structure layer 32 forms a third recessed region 25 (which can be the aforementioned third recessed portion 83) at the second recessed region 24, with the second recessed region 24 and the third recessed region 25 recessed along a direction close to the substrate 101. In the direction Z perpendicular to the substrate, the outline of the inner wall of the second recessed region 24 extends along the outline of the inner wall of the first recessed region 23. The orthographic projection of the second recessed region 24 on the substrate is within the range of the orthographic projection of the first recessed region 23 on the substrate. The orthographic projection of the second recessed region 24 and the orthographic projection of the groove 21 on the substrate overlap. The outline of the inner wall of the third recessed region 25 extends along the outline of the inner wall of the second recessed region 24. The orthographic projection of the third recessed region 25 on the substrate is within the range of the orthographic projection of the second recessed region 24 on the substrate. The orthographic projection of the third recessed region 25 and the orthographic projection of the groove 21 on the substrate overlap. In an exemplary embodiment, the first recessed region 23 can increase the contact area between the second electrode transition layer 13 and the first isolation structure layer 31, enhance the adhesion between the first isolation structure layer 31 and the second electrode transition layer 13, and reduce the risk of the first isolation structure layer 31 peeling off; the second recessed region 24 can increase the contact area between the first isolation structure layer 31 and the second isolation structure layer 32, enhance the adhesion between the second isolation structure layer 32 and the first isolation structure layer 31, and reduce the risk of the second isolation structure layer 32 peeling off; the third recessed region 25 can increase the contact area between the second isolation structure layer 32 and the subsequently formed encapsulation layer, enhance the adhesion between the second isolation structure layer 32 and the encapsulation layer, and reduce the risk of the encapsulation layer peeling off.

[0185] In an exemplary embodiment, the first isolation structure layer 31 and the second isolation structure layer 32 may include inorganic materials, such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiOxNy). In an exemplary embodiment, the material of the first isolation structure layer 31 may be silicon nitride (SiNx), and the material of the second isolation structure layer 32 may be (SiOx). In an exemplary embodiment, different gases may be used to etch the first isolation structure film 107 and the second isolation structure film 108; alternatively, the same gas may be used to etch the first isolation structure film 107 and the second isolation structure film 108. In an exemplary embodiment, under the same etching conditions, the etching rate of silicon nitride (SiNx) is faster than that of silicon oxide (SiOx), which allows the first isolation structure film 107, as shown in FIG4k, to be etched more than the second isolation structure film 108. This causes the first isolation structure layer 31 to shrink inward relative to the second isolation structure layer 32. The second isolation structure layer 32, the first isolation structure layer 31, and the second electrode transition layer 13 form an I-shaped structure. A first groove W1 is formed between the second isolation structure layer 32, the first isolation structure layer 31, and the second electrode transition layer 13. The first groove W1 constitutes a second undercut structure 26, which can isolate the subsequently formed light-emitting structure layer material and the second electrode material. During the etching process, the first partition structure film 107 is blocked by the second partition structure film 108 on the side away from the substrate 101. The first partition structure 32 formed after etching is roughly a "T" shaped structure. The first partition structure layer 31 with the "T" shaped structure can provide good support for the second partition structure layer 32.

[0186] In an exemplary embodiment, as shown in FIG4k, during the etching of the isolation structure layer 30, a portion of the peripheral area of ​​the second electrode transition layer 13 is etched, resulting in the thickness of the edge region of the second electrode transition layer 13 being less than the thickness of the middle region. That is, the thickness of the overlapping region between the second electrode transition layer 13 and the first electrode 11 on the substrate is less than the thickness of the overlapping region between the second electrode transition layer 13 and the first isolation structure layer 31 on the substrate. This avoids short circuits caused by the overlap between the second electrode transition layer 13 and the first electrode 11. In an exemplary embodiment, for each second electrode transition layer 13, on a plane parallel to the substrate 101, from the region overlapping with the first isolation structure layer 31 to the direction away from the region overlapping with the first isolation structure layer 31, the thickness of the region of the second electrode transition layer 13 not covered by the first isolation structure layer 31 gradually decreases in the third direction Z.

[0187] (105) Forming a light-emitting structure layer, a second electrode and an encapsulation layer.

[0188] In an exemplary embodiment, forming the light-emitting structure layer, the second electrode, and the encapsulation layer may include: on the substrate on which the aforementioned pattern is formed, by a coating process, such as a thermal evaporation coating process, sequentially depositing a light-emitting structure layer material, a second electrode material, and an encapsulation layer material on the side of the partition structure layer 30 and the first electrode 11 away from the substrate 101, with at least a portion of the light-emitting structure layer material disposed on the surface of the first electrode 11 away from the substrate to form a light-emitting structure layer 40, with at least a portion of the second electrode material disposed on the surface of the light-emitting structure layer 40 away from the substrate to form a second electrode 42 (which can serve as a second electrode), and the encapsulation layer material disposed on the surface of the second electrode away from the substrate to form an encapsulation layer 43, as shown in FIG41. The first electrode 11, the light-emitting structure layer 40, and the second electrode 42 form a light-emitting device for a sub-pixel, and the light-emitting structure layer 40 includes a plurality of spaced-apart light-emitting structures 41, which may be located in the pixel opening K11.

[0189] In an exemplary embodiment, the orthographic projections of the light-emitting structure layer 40 and the first electrode 11 on the substrate overlap, and the light-emitting structure layer 40 and the first electrode 11 can be in direct contact. Similarly, the orthographic projections of the second electrode 42 and the light-emitting structure layer 40 on the substrate overlap, and the light-emitting structure layer 40 and the second electrode 42 can be in direct contact.

[0190] In an exemplary embodiment, the light-emitting structure layer 40 may include at least one light-emitting layer (EML), and any one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), an electron injection layer (EIL), and a charge generation layer (CGL).

[0191] In an exemplary embodiment, the second electrode 42 can be a single-layer structure or a multi-layer structure. For example, the second electrode 42 is a single-layer structure and may include a metal or alloy, such as aluminum, titanium, molybdenum, aluminum-neodymium alloy, copper, or other highly conductive metals. Alternatively, the second electrode 42 can be a multi-layer structure; for example, the second electrode 42 may include a first thin film, a second thin film, and a third thin film sequentially disposed therefrom. The first and third thin films may each include titanium, and the second thin film may include one of aluminum, copper, or molybdenum.

[0192] In an exemplary embodiment, as shown in FIG41, the light-emitting structure layer 40 and the second electrode 42 are separated by the first undercut structure 22 and the second undercut structure 26, effectively blocking leakage current and solving the problem of crosstalk between adjacent sub-pixels to a certain extent.

[0193] In an exemplary embodiment, the second electrode 42 can be electrically connected to the second electrode transition layer 13 at the location of the second undercut structure 26. In an exemplary embodiment, the first undercut structure 22 can isolate at least a portion of the film layer structure in the light-emitting structure layer 40, effectively preventing the light-emitting structure layer from being connected to the second electrode 42 and avoiding crosstalk between adjacent sub-pixels.

[0194] In an exemplary embodiment, from the region overlapping with the first partition structure layer 31 to the region away from the overlap with the first partition structure layer 31, the thickness of the area of ​​the second electrode transition layer 13 not covered by the first partition structure layer 31 gradually decreases in the third direction Z. That is, the distance between the surface of the bottom wall C1 of the first groove W1 away from the substrate and the substrate gradually decreases, which can increase the contact area between the second electrode layer 42 and the second electrode transition layer 13 and provide stability to the connection between the second electrode layer 42 and the second electrode transition layer 13. During the formation of the light-emitting structure layer 40, the evaporation angle can be adjusted to reduce the area of ​​the light-emitting structure layer 40 covering the second electrode transition layer 13, thereby increasing the contact area between the second electrode layer 42 and the second electrode transition layer 13. On the other hand, during the formation of the second electrode layer 42, the evaporation angle can be adjusted to maximize the contact area between the second electrode layer 42 and the second electrode transition layer 13.

[0195] In an exemplary embodiment, the method for fabricating a display substrate according to this disclosure can simultaneously form a light-emitting structure layer and a second electrode for emitting multiple sub-pixels of the same color through the same fabrication process. For example, the method for fabricating a display substrate according to this disclosure can first form a light-emitting structure layer and a second electrode for multiple first sub-pixels through a first thermal evaporation coating process; then, form a light-emitting structure layer and a second electrode for multiple second sub-pixels through a second thermal evaporation coating process; then, form a light-emitting structure layer and a second electrode for multiple third sub-pixels through a third thermal evaporation coating process; finally, form an encapsulation layer 43 by vapor deposition or deposition.

[0196] In an exemplary embodiment, the encapsulation layer 43 can be a single-layer or multi-layer structure. A single-layer encapsulation layer 43 may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer sequentially disposed along a direction away from the substrate. The first, second, and third encapsulation layers may employ thin-film encapsulation (TFE) to prevent external moisture from entering the light-emitting structure layer. In an exemplary embodiment, the first and third encapsulation layers may include inorganic materials, such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiOxNy). The second encapsulation layer may include organic materials, such as resin. In an exemplary embodiment, the first encapsulation layer may be a multi-layer structure. For example, the first encapsulation layer 15 may include a first inorganic dielectric layer and a second inorganic dielectric layer. The first inorganic dielectric layer is located on the side of the second inorganic dielectric layer closer to the substrate. The first inorganic dielectric layer may be silicon oxide, and the second inorganic dielectric layer may be silicon nitride.

[0197] In an exemplary embodiment, the structure after forming the encapsulation layer 43 can be as shown in FIG41, but is not limited to the structure shown in FIG41. The thickness and proportional relationship of the multiple film layer structures located on one side of the substrate 101 in the display substrate can be set according to the actual product, for example, as shown in FIG3b and FIG3c.

[0198] In another exemplary embodiment, the method for fabricating the display substrate can simultaneously form a light-emitting structure layer, a second electrode, and an encapsulation layer for multiple sub-pixels emitting the same color through the same fabrication process. For example, the method for fabricating the display substrate in this embodiment can first form a light-emitting structure layer film, a second electrode film, and an encapsulation layer film for multiple first sub-pixels through a first thermal evaporation coating process, and then form a light-emitting structure layer, a second electrode film, and an encapsulation layer for multiple first sub-pixels through a photolithography process (etching away the light-emitting structure layer film, second electrode film, and encapsulation layer film located outside the first sub-pixel region); subsequently, a second thermal evaporation coating process is used to simultaneously form a light-emitting structure layer film, a second electrode film, and an encapsulation layer film for multiple second sub-pixels, and then form a light-emitting structure layer, a second electrode film, and an encapsulation layer for multiple second sub-pixels through a photolithography process (etching away the light-emitting structure layer film, second electrode film, and encapsulation layer film located outside the first sub-pixel region). Multiple light-emitting structure layers, second electrodes, and encapsulation layers for second sub-pixels are formed by a light-emitting structure layer film, a second electrode film, and an encapsulation layer film located outside the second sub-pixel region. Subsequently, multiple light-emitting structure layer films, second electrode films, and encapsulation layer films for third sub-pixels are formed simultaneously by a third thermal evaporation deposition process. Multiple light-emitting structure layers, second electrodes, and encapsulation layers for third sub-pixels are formed by a photolithography process (etching away the light-emitting structure layer film, second electrode film, and encapsulation layer film located outside the third sub-pixel region). Finally, an encapsulation layer 43 is formed on the side of the isolation structure layer 30 away from the substrate 101 by, for example, deposition. The encapsulation layer 43 from the first sub-pixel to the third sub-pixel is connected to the encapsulation layer 43 on the side of the isolation structure layer 30 away from the substrate to form an integral unit.

[0199] In an exemplary embodiment, the light-emitting device of a sub-pixel can be a multilayer light-emitting device. For example, the light-emitting device may include a first electrode 11, a second electrode 42, and a light-emitting structure layer 40 disposed between the first electrode 11 and the second electrode 42. The light-emitting structure layer 40 may include a hole injection layer disposed on the side of the first electrode 11 away from the substrate 101, a first hole transport layer disposed on the side of the hole injection layer away from the substrate 101, a first light-emitting layer disposed on the side of the first hole transport layer away from the substrate 101, a first electron transport layer disposed on the side of the first light-emitting layer away from the substrate 101, a charge production layer disposed on the side of the first electron transport layer away from the substrate 101, a second hole transport layer disposed on the side of the charge production layer away from the substrate 101, a second light-emitting layer disposed on the side of the second hole transport layer away from the substrate 101, a second electron transport layer disposed on the side of the second light-emitting layer away from the substrate 101, and an electron injection layer disposed on the side of the second electron transport layer away from the substrate 101.

[0200] In an exemplary embodiment, the light-emitting device of a sub-pixel can be a single-layer light-emitting device. For example, the light-emitting device includes a first electrode 11, a second electrode 42, and a light-emitting structure layer 40 disposed between the first electrode 11 and the second electrode 42. The light-emitting structure layer 40 may include a hole injection layer disposed on the first electrode 11, a hole transport layer disposed on the side of the hole injection layer away from the substrate 101, a light-emitting layer disposed on the side of the hole transport layer away from the substrate 101, an electron transport layer disposed on the side of the light-emitting layer away from the substrate 101, and an electron injection layer disposed on the side of the electron transport layer away from the substrate 101.

[0201] (106) Forming a microlens structure.

[0202] In an exemplary embodiment, forming a microlens structure may include: as shown in FIG4m, forming an adhesive layer 51 on the side of the encapsulation layer 43 away from the substrate on the substrate on which the aforementioned pattern is formed, and fabricating a plurality of microlens structures 61 on the side of the adhesive layer 51 away from the substrate. In an exemplary embodiment, the adhesive layer 51 can be formed on the side of the encapsulation layer 43 away from the substrate by coating, and a microlens structure material layer can be formed on the side of the adhesive layer 51 away from the substrate by coating. The microlens structure material layer is patterned by photolithography to form a plurality of dot-like structures distributed in an array, and then baked to make the upper surface of the microlens structure material layer bulge, forming a plurality of microlens structures 61 distributed in an array.

[0203] (107) Form a filling layer.

[0204] In an exemplary embodiment, forming a filler layer may include, as shown in FIG4n, forming a filler layer 71 on the side of the microlens structure 61 and the adhesive layer 51 away from the substrate on the substrate on which the aforementioned pattern is formed, by means of, for example, coating.

[0205] In an exemplary embodiment, the driving circuit layer 102 and the substrate 101 constitute a driving backplane of the display substrate, and the driving backplane can be a silicon-based driving backplane.

[0206] The structure of a silicon-based driving backplane is described below by way of example. Figure 5 shows a schematic cross-sectional structure of a silicon-based driving backplane provided in an exemplary embodiment of this disclosure. As shown in Figure 5, the silicon-based driving backplane may include multiple transistors, which may be metal oxide semiconductor (MOS) field-effect transistors.

[0207] In an exemplary embodiment, as shown in FIG5, the driving circuit layer 102 may include multiple circuit units, each of which may include at least a pixel driving circuit. The pixel driving circuit is connected to the scan signal line and the data signal line, respectively. The pixel driving circuit may include multiple transistors and a storage capacitor. FIG5 uses only one transistor as an example. The transistor may include a gate electrode G, a first electrode S, and a second electrode D. The gate electrode G, the first electrode S, and the second electrode D may be connected to the corresponding connection electrode through a first via (i.e., a tungsten via, W-via) V1 filled with tungsten metal, and may be connected to other electrical structures (such as traces) through the connection electrode.

[0208] As shown in Figure 5, the silicon-based driving backplane may include a substrate 101, a source / drain layer 1021, a gate insulating layer 1022, a gate layer 1023, a first insulating layer 1024, a first wiring layer 1025, a second insulating layer 1026, a second wiring layer 1027, and a planarization layer 1028 stacked sequentially. The wiring 10 may be located in the second wiring layer 1021 and is used to electrically connect the first electrode 11 and the transistor in the driving backplane. In an exemplary embodiment, the planarization layer 1028 has multiple second vias V2 to facilitate electrical connection between the wiring in the second wiring layer 1027 and the first electrode 11.

[0209] In an exemplary embodiment, the gate layer 1023 may include a gate electrode G, and the source-drain layer 1021 may include a first electrode S and a second electrode D. The gate electrode G, the first electrode S, and the second electrode D form a MOS transistor.

[0210] In an exemplary embodiment, at least one or more of the gate electrode G, the first electrode S, and the second electrode D in a portion of the transistor can be electrically connected to the traces in the second trace layer 1027 via traces in the first trace layer 1025.

[0211] In an exemplary embodiment, the transistor can be an N-type MOS transistor or a P-type MOS transistor. For an N-type MOS transistor, the substrate 101 located below the N-type MOS transistor can be a P-type semiconductor, and the first electrode S and the second electrode D can be N-type semiconductors; for a P-type MOS transistor, the substrate 101 located below the P-type MOS transistor can be an N-type semiconductor, and the first electrode S and the second electrode D can be P-type semiconductors.

[0212] In an exemplary embodiment, the gate insulating layer 1022 is provided with a plurality of first vias V1 to facilitate the connection of the traces in the second wiring layer 1027 to the transistor. The first vias V1 can penetrate the gate insulating layer 1022, the first insulating layer 1024, and the second insulating layer 1026.

[0213] In an exemplary embodiment, the material used to fabricate the gate layer 1023 can be one or more of the following metals: aluminum, molybdenum, copper, titanium, etc.

[0214] In an exemplary embodiment, the material used to fabricate the gate insulating layer 1022 may be silicon oxide or silicon nitride, such as silicon nitride.

[0215] In an exemplary embodiment, the material used to fabricate the first insulating layer 1024 may be silicon oxide or silicon nitride, such as silicon nitride.

[0216] In an exemplary embodiment, the material used to fabricate the second insulating layer 1026 may be silicon oxide or silicon nitride, such as silicon nitride.

[0217] In an exemplary embodiment, the planarization layer 109 may be made of an organic insulating material, such as resin.

[0218] This disclosure provides a method for preparing a display substrate, including:

[0219] A first electrode is formed on the substrate;

[0220] A pixel definition layer is formed on a substrate, the pixel definition layer being located on at least one side of the first electrode;

[0221] A partition structure layer is formed on the side of the pixel definition layer away from the substrate, and a trench is formed in the pixel definition layer. The partition structure layer is provided with an undercut structure near the first electrode. The trench extends from the surface of the pixel definition layer away from the substrate along the direction close to the substrate. The partition structure layer includes at least a first auxiliary second electrode, and at least a portion of the first auxiliary second electrode covers the inner wall of the trench.

[0222] A light-emitting structure layer and a second electrode are sequentially formed on the side of the first electrode away from the substrate. At least one of the light-emitting structure layer and the second electrode is separated at the undercut structure. The second electrode is connected to the first auxiliary second electrode.

[0223] In an exemplary embodiment, FIG6a shows an external structural diagram of a pixel definition layer (PDL) after formation, taken by scanning electron microscopy (SEM), and FIG6b and FIG6c show cross-sectional structural diagrams of a package layer (43) after formation, taken by scanning electron microscopy (STEM). In FIG6a, on the side of the pixel definition layer (PDL) near the corresponding pixel opening K11, the surface of the second pixel definition layer (PDL2) is recessed relative to the surfaces of the first pixel definition layer (PDL1) and the third pixel definition layer (PDL3) to form a second groove W2.

[0224] This disclosure provides a method for preparing a display substrate, including:

[0225] A pixel definition layer is formed on one side of the substrate, and the pixel definition layer has multiple pixel openings;

[0226] A second electrode transition layer and a barrier structure layer are sequentially formed on the side of the pixel definition layer away from the substrate. The second electrode transition layer and the barrier structure layer have multiple first openings, each corresponding to a pixel opening. The orthographic projection of the first opening onto the substrate at least partially overlaps with the orthographic projection of the corresponding pixel opening onto the substrate. The sidewall of the first opening has a first groove. At least a portion of the surface of the second electrode transition layer on the side away from the substrate, not covered by the barrier structure layer, serves as the bottom wall of the first groove. The distance between the bottom wall of the first groove and the substrate gradually decreases in the direction from the first groove to the corresponding first opening.

[0227] A light-emitting structure layer is formed on the side of the partition structure layer away from the substrate. The light-emitting structure layer includes a plurality of light-emitting structures, each of which corresponds to a plurality of pixel openings. At least a portion of each light-emitting structure is located in the corresponding pixel opening. The light-emitting structure layer is broken at the first groove position.

[0228] A second electrode layer is formed on the side of the light-emitting structure layer away from the substrate. The second electrode layer is disconnected at the first groove position and connected to the bottom wall of the first groove at the disconnected position.

[0229] This disclosure provides a display device, as shown in FIG7. The display device may include the aforementioned display substrate. The display device may be any product or component with display function, such as a mobile phone, wearable device, AR or VR display device, in-vehicle display device, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. The embodiments of this invention are not limited thereto.

[0230] The display substrate and its fabrication method, as well as the display device provided in this disclosure, include a substrate and a pixel definition layer, a second electrode transition layer, a barrier structure layer, a light-emitting structure layer, and a second electrode layer sequentially disposed on one side of the substrate. The pixel definition layer has multiple pixel openings, and the second electrode transition layer and the barrier structure layer have multiple first openings, each corresponding to one of the pixel openings. A first groove is provided on the sidewall of each first opening. The light-emitting structure layer and the second electrode layer are disconnected at the first groove location. The second electrode layer is connected to the bottom wall of the first groove at the disconnected location. The distance between the bottom wall of the first groove and the substrate gradually decreases from the first groove towards the corresponding first opening. The technical solution provided in this disclosure, where the light-emitting structure layer and the second electrode layer are disconnected at the first groove location, can prevent leakage caused by excessively close proximity between the portion of the film layer near the substrate in the light-emitting structure layer and the second electrode layer, effectively reducing the risk of display abnormalities.

[0231] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit the invention. Any person skilled in the art may make any modifications and changes to the form and details of the implementation without departing from the spirit and scope of this disclosure; however, the patent protection scope of this invention shall still be determined by the scope defined in the appended claims.

Claims

1. A display substrate, comprising a substrate and a pixel definition layer, a second electrode transition layer, a barrier structure layer, a light-emitting structure layer, and a second electrode layer sequentially disposed on one side of the substrate; the pixel definition layer is provided with a plurality of pixel openings, the light-emitting structure layer includes a plurality of light-emitting structures, the plurality of light-emitting structures corresponding one-to-one with the plurality of pixel openings, and at least a portion of the light-emitting structures being located in the corresponding pixel openings; The second electrode transition layer and the isolation structure layer are provided with a plurality of first openings, and the plurality of first openings correspond one-to-one with the plurality of pixel openings. The orthographic projection of the first opening on the substrate and the orthographic projection of the corresponding pixel opening on the substrate at least partially overlap. The sidewall of the first opening is provided with a first groove, and the light-emitting structure layer and the second electrode layer are disconnected at the position of the first groove; In the surface of the second electrode transition layer on the side away from the substrate, at least a portion of the area not covered by the partition structure layer serves as the bottom wall of the first groove. The second electrode layer is connected to the bottom wall of the first groove in the disconnected position. In the direction from the first groove to the corresponding first opening, the distance between the bottom wall of the first groove and the substrate gradually decreases.

2. The display substrate according to claim 1, wherein, The second electrode layer overlaps with the bottom wall of the first groove at the disconnected position.

3. The display substrate according to claim 2, wherein, In the direction from the first groove to the corresponding first opening, the bottom wall of the first groove includes a first region and a second region arranged in sequence, and the second region is located between the corresponding first opening and the first region; The second electrode layer overlaps with the first region at the disconnected position, and the light-emitting structure layer covers the second region at the disconnected position.

4. The display substrate according to claim 3, wherein, A second groove is provided on the sidewall of the pixel opening. The minimum distance between the second electrode layer and the second groove is less than the average thickness of the light-emitting structure layer corresponding to the second region. The light-emitting structure layer corresponding to the second region covers the corresponding second region.

5. The display substrate according to claim 4, wherein, On a plane parallel to the base, in the direction from the first groove to the corresponding first opening, the ratio of the size of the first groove to the size of the second groove is greater than or equal to 5:

1.

6. The display substrate according to claim 4, wherein, In the direction perpendicular to the base, the ratio of the size of the first groove to the size of the second groove is greater than or equal to 5:

1.

7. The display substrate according to claim 4, wherein, In the direction from the first groove to the corresponding first opening, the difference between the maximum and minimum distances between the bottom wall of the first groove and the substrate is greater than the minimum distance between the second electrode layer and the second groove, but less than the thickness of the second electrode layer.

8. The display substrate according to any one of claims 4, wherein, On a plane parallel to the substrate, in the direction from the first groove to the corresponding first opening, the second electrode layer includes a first structural part, a second structural part, and a third structural part arranged sequentially, and the first structural part, the second structural part, and the third structural part are connected in sequence. In the direction from the first groove to the corresponding first opening, the distance between the surface of the first structural part and the third structural part away from the substrate and the substrate gradually increases, while the distance between the surface of the second structural part away from the substrate and the substrate gradually decreases.

9. The display substrate according to claim 8, wherein, There is a first difference between the maximum and minimum distance between the surface of the first structural part away from the substrate and the substrate; there is a second difference between the maximum and minimum distance between the surface of the second structural part away from the substrate and the substrate; and there is a third difference between the maximum and minimum distance between the surface of the third structural part away from the substrate and the substrate. In the direction from the first groove to the corresponding first opening, the length dimension of the first structural part is the first length dimension, the length dimension of the second structural part is the second length dimension, and the length dimension of the third structural part is the third length dimension; The ratio of the third difference to the third length dimension is greater than the ratio of the first difference to the first length dimension; The ratio of the second difference to the second length dimension is greater than the ratio of the third difference to the third length dimension.

10. The display substrate according to claim 8, further comprising a first electrode layer, wherein the first electrode layer is located between the substrate and the pixel definition layer in a direction perpendicular to the plane of the substrate; the second electrode layer further comprises a fourth structural portion in a direction from the first groove to the corresponding first opening; the fourth structural portion is located on the side of the third structural portion away from the second structural portion; The distance between the surface of the fourth structural portion near the substrate and the surface of the first electrode layer away from the substrate is greater than the distance between the surface of the third structural portion near the substrate and the surface of the first electrode layer away from the substrate.

11. The display substrate according to claim 10, wherein, The distance between the surface of the third structure near the substrate and the surface of the first electrode layer away from the substrate is greater than the minimum distance between the second structure and the pixel definition layer.

12. The display substrate according to claims 8 to 11, wherein, The minimum distance between the second structural portion and the pixel definition layer is greater than the dimension of the second groove in the direction perpendicular to the substrate.

13. The display substrate according to claim 8, wherein, The second electrode layer further includes a fourth structural portion in the direction from the first groove to the corresponding first opening. The fourth structural portion is located on the side of the third structural portion away from the second structural portion. The fourth structural portion is connected to the third structural portion. At least a portion of the fourth structural portion is located in the pixel opening. The first structural part is at least partially located within the first groove, with one end connected to the bottom wall of the first groove and the other end connected to the second structural part. The surface of the first structural part away from the base forms a first angle with the base. One end of the second structural part is close to the first groove and connected to the first structural part, and the other end is close to the second groove and connected to the third structural part. A second included angle is formed between the surface of the second structural part away from the base and the base. One end of the third structural part is close to the second groove and connected to the second structural part, and the other end is close to the corresponding pixel opening and connected to the fourth structural part. The surface of the third structural part away from the substrate forms a third included angle with the substrate. The first included angle and the third included angle are both acute angles, the second included angle is an obtuse angle, and the angles of the supplementary angle of the second included angle, the third included angle, and the first included angle decrease sequentially.

14. The display substrate according to claim 13, wherein, The fourth structural component is parallel to the base.

15. The display substrate according to claim 4, wherein, In a direction perpendicular to the plane of the substrate, the pixel definition layer includes a first pixel definition layer, a second pixel definition layer and a third pixel definition layer stacked sequentially on one side of the substrate. The surface of the second pixel definition layer near any of the light-emitting structures is recessed into the surfaces of the first pixel definition layer and the third pixel definition layer near the same light-emitting structure, forming the second groove.

16. The display substrate according to claim 15, wherein, In a direction perpendicular to the plane of the substrate, the thickness of the third pixel definition layer is greater than half the thickness of the light-emitting structure layer.

17. The display substrate according to claim 15 or 16, wherein, The first pixel definition layer and the third pixel definition layer are silicon oxide layers, and the second pixel definition layer is a silicon nitride layer.

18. The display substrate according to claim 1, wherein, The isolation structure layer includes a first isolation structure layer and a second isolation structure layer stacked sequentially on the side of the pixel definition layer away from the substrate. The surface of the first isolation structure layer near any of the light-emitting structures is recessed into the surface of the second isolation structure layer near the same light-emitting structure, forming the first groove.

19. The display substrate according to claim 18, wherein, The pixel definition layer has a first recess on the side away from the substrate, and the first partition structure layer has a second recess on the side away from the substrate. The first recess includes a first intermediate region and two first sub-recesses located on both sides of the first intermediate region. The height of the surface of the first intermediate region away from the substrate relative to the substrate is greater than the height of the surface of the first sub-recesses away from the substrate relative to the substrate, and less than the height of the surface of the pixel definition layer located outside the first recess relative to the substrate relative to the substrate. The second recess includes a second intermediate region and two second sub-recesses located on both sides of the second intermediate region. The height of the surface of the second intermediate region away from the substrate relative to the substrate is greater than the height of the surface of the second sub-recesses away from the substrate relative to the substrate, but less than the height of the surface of the first partition structure layer outside the second recess relative to the substrate relative to the substrate.

20. The display substrate according to claim 19, wherein, In a direction perpendicular to the base, among the first and second connecting lines located in the same plane, the orthographic projection of the second connecting line on the base is within the range of the orthographic projection of the corresponding first connecting line on the base, wherein the first connecting line is a connecting line between two first sub-recesses located in the same first recess, and the second connecting line is a connecting line between two second sub-recesses located in the same second recess.

21. The display substrate according to claim 19, wherein, The first connecting line is a line connecting two first sub-recesses located in the same first recess to a first position, and the second connecting line is a line connecting two second sub-recesses located in the same second recess to a second position. The first position is the position where the surface of the first sub-recess near the base has the smallest height relative to the base, and the second position is the position where the surface of the second sub-recess near the base has the smallest height relative to the base.

22. The display substrate according to claim 21, wherein, The second partition structure layer has a third recess on the side away from the substrate. The third recess includes a third intermediate region and two third sub-recesses located on both sides of the third intermediate region. The height of the surface of the third intermediate region away from the substrate relative to the substrate is greater than the height of the surface of the third sub-recesses away from the substrate relative to the substrate, and less than the height of the surface of the second partition structure layer outside the third recess relative to the substrate. The distance between two first sub-recesses located in the same first recess is the first distance, the distance between two second sub-recesses located in the same second recess is the second distance, and the distance between two third sub-recesses located in the same third recess is the third distance. The difference between the first distance and the corresponding second distance is less than the difference between the second distance and the corresponding third distance.

23. The display substrate according to claim 18, wherein, In a direction perpendicular to the plane of the substrate, the thickness of the first partition structure layer is 1.5 to 3 times the thickness of the second partition structure layer, and the thickness of the first partition structure layer is 1.5 to 3 times the thickness of the pixel definition layer.

24. The display substrate according to claim 18, wherein, The cross-sectional structure of the first partition structure layer between two adjacent first openings is a "T" shaped structure.

25. The display substrate according to any one of claims 18 to 21, wherein, The cross-sectional structure of the first partition structure layer and the second electrode transition layer between two adjacent first openings is an "I" shaped structure.

26. The display substrate according to any one of claims 18 to 24, wherein, The first partition structure layer is a silicon nitride layer, and the second partition structure layer is a silicon oxide layer.

27. The display substrate according to any one of claims 1 to 11, 13 to 24, wherein, On a plane parallel to the substrate, the second electrode transition layer includes a first groove region and an intermediate region surrounded by the first groove region, the bottom wall of the first groove being located in the first groove region, and the intermediate region being covered by the partition structure layer; in a direction perpendicular to the substrate, the thickness of the intermediate region is greater than the thickness of the first groove region.

28. The display substrate according to claim 27, wherein, In the direction from the first groove to the corresponding first opening, the thickness of the first groove region gradually decreases in the direction perpendicular to the base.

29. A display device comprising a display substrate as described in any one of claims 1 to 28.

30. A method for preparing a display substrate, comprising: A pixel definition layer is formed on one side of the substrate, and the pixel definition layer has multiple pixel openings; A second electrode transition layer and a barrier structure layer are sequentially formed on the side of the pixel definition layer away from the substrate. The second electrode transition layer and the barrier structure layer have multiple first openings, which are respectively connected to the multiple... Each pixel opening corresponds to a pixel opening. The orthographic projection of the first opening on the substrate at least partially overlaps with the orthographic projection of the corresponding pixel opening on the substrate. The sidewall of the first opening is provided with a first groove. In the surface of the second electrode transition layer away from the substrate, at least a portion of the area not covered by the partition structure layer serves as the bottom wall of the first groove. In the direction from the first groove to the corresponding first opening, the distance between the bottom wall of the first groove and the substrate gradually decreases. A light-emitting structure layer is formed on the side of the partition structure layer away from the substrate. The light-emitting structure layer includes a plurality of light-emitting structures, each of which corresponds to a plurality of pixel openings. At least a portion of each light-emitting structure is located in the corresponding pixel opening. The light-emitting structure layer is broken at the first groove position. A second electrode layer is formed on the side of the light-emitting structure layer away from the substrate. The second electrode layer is disconnected at the first groove position and connected to the bottom wall of the first groove at the disconnected position.

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