Liquid crystal lens substrate and manufacturing method therefor, and liquid crystal lens module and display apparatus

Abstract

A liquid crystal lens substrate and a manufacturing method therefor, and a liquid crystal lens module and a display apparatus. The liquid crystal lens substrate comprises: a base substrate (101), which has a display area and a non-display area; a plurality of traces (102), which are located on the same side of the base substrate (101), wherein the plurality of traces (102) surround the display area; an insulating layer (103), which is located on the side, which is away from the base substrate (101), of a layer where the plurality of traces (102) are located, wherein the insulating layer (103) comprises a plurality of first via holes located in the non-display area, and a plurality of second via holes at least located in the non-display area, the plurality of second via holes having undercut angles, orthographic projections of the plurality of second via holes on the base substrate (101) intersecting with orthographic projections of the plurality of traces (102) on the base substrate (101), and orthographic projections of the plurality of first via holes on the base substrate (101) being located within the orthographic projections of the plurality of traces (102) on the base substrate (101); and a plurality of first electrodes (104), which are located on the side of the insulating layer (103) that is away from the layer where the plurality of traces (102) are located, wherein the plurality of first electrodes (104) are at least located in the non-display area, the plurality of first electrodes (104) are electrically connected to the plurality of traces (102) by means of the plurality of first via holes, and adjacent first electrodes (104) are arranged spaced apart from each other by means of the second via hole.

Description

Liquid crystal lens substrate, its manufacturing method, liquid crystal lens module and display device

[0001] Cross-references to related applications

[0002] This application claims priority to Chinese Patent Application No. 202410504491.7, filed on April 24, 2024, with the invention entitled "Liquid Crystal Lens Substrate, Method for Manufacturing the Same, Liquid Crystal Lens Module and Display Device", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of display technology, and in particular to a liquid crystal lens substrate, its manufacturing method, a liquid crystal lens module, and a display device. Background Technology

[0004] 3D display technology provides stereoscopic images for the human eye. Liquid crystal lenses (LCDs) possess excellent performance and can be electrically focused, making them widely used in focusing devices and human eye magnification devices, especially in 3D displays. The application of LCDs can eliminate the need for 3D glasses, enabling glasses-free 3D displays and allowing for seamless switching between 2D and 3D display modes, showing immense future application potential. Summary of the Invention

[0005] The liquid crystal lens substrate, its manufacturing method, liquid crystal lens module, and display device disclosed herein are specifically as follows:

[0006] In one aspect, embodiments of this disclosure provide a liquid crystal lens substrate, comprising:

[0007] A substrate, the substrate including a display area and a non-display area located on at least one side of the display area;

[0008] Multiple traces are located on the same side of the substrate, and the multiple traces are wound around the display area within the non-display area;

[0009] An insulating layer is located on the side of the layer containing the plurality of traces away from the substrate. The insulating layer includes a plurality of first vias located in the non-display area and a plurality of second vias located at least in the non-display area. The plurality of second vias include undercut corners. The orthographic projections of the plurality of second vias on the substrate intersect the orthographic projections of the plurality of traces on the substrate. The orthographic projections of the plurality of first vias on the substrate are located within the orthographic projections of the plurality of traces on the substrate.

[0010] A plurality of first electrodes are located on the side of the insulating layer away from the layer where the plurality of traces are located, and the plurality of first electrodes are at least located in the non-display area. The plurality of first electrodes are electrically connected to the plurality of traces through the plurality of first vias penetrating the insulating layer, and adjacent first electrodes are spaced apart through second vias.

[0011] In some embodiments, the liquid crystal lens substrate provided in the present disclosure further includes at least a plurality of second electrodes located in the non-display area and disposed on the same layer as the plurality of first electrodes. The orthographic projection of the plurality of second electrodes on the substrate is located within the orthographic projection of the plurality of second vias on the substrate, and the orthographic projection of the plurality of second electrodes on the substrate does not overlap with the orthographic projection of the undercut angle on the substrate.

[0012] In some embodiments, in the liquid crystal lens substrate provided in the present disclosure, the plurality of second vias, the plurality of first electrodes, and the plurality of second electrodes are located in the non-display area;

[0013] The liquid crystal lens substrate also includes a plurality of third electrodes located in the display area, and the plurality of third electrodes are integrally disposed with the plurality of first electrodes.

[0014] In some embodiments, in the liquid crystal lens substrate provided in the present disclosure, the plurality of second vias, the plurality of first electrodes, and the plurality of second electrodes are located in the display area and the non-display area.

[0015] In some embodiments, in the liquid crystal lens substrate provided in the present disclosure, the second via is a blind via, the second electrode is in a floating state, and the second electrode is insulated from the plurality of traces.

[0016] In some embodiments, in the liquid crystal lens substrate provided in the present disclosure, the insulating layer includes a first sub-insulating layer, and a second sub-insulating layer and a third sub-insulating layer located sequentially on the side of the first sub-insulating layer away from the substrate, and the blind hole penetrates the third sub-insulating layer and the second sub-insulating layer.

[0017] In some embodiments, in the liquid crystal lens substrate provided in the present disclosure, the second via is a through hole at the part of the overlap with the trace, and the second electrode is electrically connected to the trace through the through hole.

[0018] In some embodiments, in the liquid crystal lens substrate provided in the present disclosure, the insulating layer includes a first sub-insulating layer, a second sub-insulating layer and a third sub-insulating layer stacked sequentially, the first sub-insulating layer being located between the second sub-insulating layer and the substrate, and the through hole penetrating the third sub-insulating layer, the second sub-insulating layer and the first sub-insulating layer.

[0019] In some embodiments, in the liquid crystal lens substrate provided in the present disclosure, the through hole and the first via hole are located in the non-display area on the same side of the display area, or the through hole and the first via hole are located in the non-display area on the opposite side of the display area.

[0020] In some embodiments, in the liquid crystal lens substrate provided in the present disclosure, the material of the first sub-insulating layer is different from the material of the second sub-insulating layer, and the material of the second sub-insulating layer is the same as the material of the third sub-insulating layer, but the film of the second sub-insulating layer is more porous than that of the third sub-insulating layer.

[0021] In some embodiments, in the liquid crystal lens substrate provided in the present disclosure, the second via includes an inverted trapezoidal structure and a regular trapezoidal structure that are disposed through each other, wherein the inverted trapezoidal structure penetrates the third sub-insulating layer, the regular trapezoidal structure penetrates at least the second sub-insulating layer, and the base angle of the regular trapezoidal structure away from the inverted trapezoidal structure is the bottom chamfer angle.

[0022] In some embodiments, in the liquid crystal lens substrate provided in the present disclosure, the bottom edge dimension of the inverted trapezoidal structure that is far from the regular trapezoidal structure is A, the bottom edge dimension shared by the inverted trapezoidal structure and the regular trapezoidal structure is B, 2μm≤A≤8μm, 1μm≤B≤6μm.

[0023] In some embodiments, in the liquid crystal lens substrate provided in the present disclosure, the undercut angle has a dimension C in the direction of extending the bottom edge of the inverted trapezoidal structure, the undercut angle has a dimension D in the stacking direction, the height of the regular trapezoidal structure in the stacking direction is E, 0.5μm≤C≤2μm, and D≈E.

[0024] In some embodiments, in the liquid crystal lens substrate provided in the present disclosure, the distance between the first electrode and the second electrode in the extending direction of the waist of the inverted trapezoidal structure is F, where 0.8 ≤ F / E ≤ 1.2.

[0025] In some embodiments, in the liquid crystal lens substrate provided in the present disclosure, the material of the first sub-insulating layer includes silicon oxide, the material of the second sub-insulating layer, and the material of the third sub-insulating layer include silicon nitride.

[0026] In some embodiments, in the liquid crystal lens substrate provided in the present disclosure, in the stacking direction: the thickness of the first sub-insulating layer is G, the thickness of the second sub-insulating layer is H, the thickness of the third sub-insulating layer is I, 20nm≤G≤50nm, 100nm≤H≤500nm, and 100nm≤I≤300nm.

[0027] On the other hand, this disclosure provides a method for manufacturing the above-mentioned liquid crystal lens substrate, including:

[0028] A substrate is provided, the substrate including a display area and a non-display area located on at least one side of the display area;

[0029] Multiple traces are patterned on the substrate and wound around the display area;

[0030] An insulating layer comprising multiple first vias and multiple second vias is patterned on the layer containing the multiple traces; wherein, the multiple second vias are at least located in the non-display area, the multiple second vias include undercut corners, and the orthographic projections of the multiple second vias on the substrate intersect with the orthographic projections of the multiple traces on the substrate; the orthographic projections of the multiple first vias on the substrate are located within the orthographic projections of the multiple traces on the substrate;

[0031] A plurality of first electrodes are deposited on the insulating layer to form at least one in the non-display area, such that the plurality of first electrodes are electrically connected to the plurality of traces through the plurality of first vias, and adjacent first electrodes are spaced apart through second vias.

[0032] In some embodiments, in the manufacturing method provided in this disclosure, an insulating layer including a plurality of second vias is patterned on the layer containing the plurality of traces, the plurality of second vias being located at least in the non-display area, and the plurality of second vias including a bottom chamfer; specifically including:

[0033] An insulating layer comprising a first sub-insulating layer, a second sub-insulating layer, and a third sub-insulating layer is formed by depositing a film on the layer containing the multiple traces;

[0034] The process involves photoresist coating, photomask application, exposure, development, etching, and photoresist stripping to form multiple inverted trapezoidal structures penetrating at least the third sub-insulating layer in the non-display area, and multiple upright trapezoidal structures penetrating at least the second sub-insulating layer. The inverted trapezoidal structures and the upright trapezoidal structures are connected to form a second via, and the bottom angle of the upright trapezoidal structure away from the inverted trapezoidal structure is the bottom chamfer angle of the second via.

[0035] In some embodiments, in the fabrication method provided in the present disclosure, the deposition of a second sub-insulating layer and a third sub-insulating layer specifically includes:

[0036] A second sub-insulating layer is formed by depositing silane, ammonia and nitrogen in a gas ratio of 1:2:7 to 1:3:7 on the first sub-insulating layer.

[0037] A third sub-insulating layer is formed by depositing silane, ammonia, and nitrogen in a gas ratio of 1:10:40 to 1:15:40 on the second sub-insulating layer.

[0038] In some embodiments, the fabrication method provided in this disclosure involves forming, specifically, an etching process, a plurality of inverted trapezoidal structures penetrating at least the third sub-insulating layer within the non-display area and a plurality of upright trapezoidal structures penetrating at least the second sub-insulating layer, specifically including:

[0039] Using SF6:O2 with a gas ratio of 1:1 to 1:2 and an etching power of 6KW to 10KW, the third sub-insulating layer and the second sub-insulating layer are etched in a uniform etching mode to form multiple inverted trapezoidal structures penetrating the third sub-insulating layer and multiple upright trapezoidal structures penetrating the second sub-insulating layer, at least within the non-display area.

[0040] In some embodiments, in the fabrication method provided in this disclosure, an SF6:O2 gas ratio of 1:1 to 1:2 and an etching power of 6KW to 10KW are used to etch the third sub-insulating layer and the second sub-insulating layer in a uniform etching mode to form a plurality of inverted trapezoidal structures penetrating the third sub-insulating layer and a plurality of upright trapezoidal structures penetrating the second sub-insulating layer, at least within the non-display area. The method further includes:

[0041] Using a mixture of CF4 and O2, the first sub-insulating layer at the partial overlap between the trapezoidal structure and the trace is etched away, so that the trapezoidal structure is penetrated from the second sub-insulating layer to the first sub-insulating layer at the partial overlap with the trace.

[0042] In some embodiments, in the manufacturing method provided in this disclosure, forming an insulating layer including a plurality of first vias in the non-display area specifically includes:

[0043] Using SF6:O2 with a gas ratio of 1:3 to 1:4 and an etching power of 2KW to 10KW, the third sub-insulating layer and the second sub-insulating layer are etched in reactive particle etching mode to form a plurality of sub-vias that penetrate the third sub-insulating layer and the second sub-insulating layer in the non-display area and have approximately uniform apertures.

[0044] A mixed gas of CF4 and O2 is used to etch away the first sub-insulating layer under the plurality of sub-vias, so that the plurality of sub-vias penetrate into the first sub-insulating layer to form a plurality of first vias.

[0045] In some embodiments, in the fabrication method provided in the present disclosure, a plurality of first electrodes located at least in the non-display area are deposited on the insulating layer, such that adjacent first electrodes are spaced apart by the second vias, specifically including:

[0046] A conductive layer is formed by depositing a film on the insulating layer. The conductive layer is at least separated in the non-display area by the plurality of second vias into a plurality of first electrodes overlapping the edges of the second vias, and a plurality of second electrodes located within the plurality of second vias.

[0047] In some embodiments, in the fabrication method provided in this disclosure, a conductive layer is formed by depositing a film on the insulating layer. After the non-display area is separated by the plurality of second vias into a plurality of first electrodes overlapping the edges of the second vias, and a plurality of second electrodes located within the plurality of second vias, the conductive layer further includes:

[0048] The conductive layer is formed in the display area by a process of photoresist coating, masking, exposure, development, etching, and photoresist stripping, thereby forming multiple third electrodes integrally disposed with the multiple first electrodes.

[0049] On the other hand, embodiments of this disclosure provide a method for manufacturing a liquid crystal lens substrate, including:

[0050] A substrate is provided, the substrate including a display area and a non-display area located on at least one side of the display area;

[0051] Multiple traces are patterned on the substrate and wound around the display area;

[0052] An insulating layer including multiple first vias is patterned on the layer containing the multiple traces, wherein the orthographic projection of the multiple first vias on the substrate is located within the orthographic projection of the multiple traces on the substrate;

[0053] A plurality of partition structures extending from the display area to the non-display area are formed on the insulating layer, wherein the orthogonal projections of the plurality of partition structures on the substrate do not overlap with the orthogonal projections of the plurality of first vias on the substrate.

[0054] A conductive layer is formed by depositing a film on the layer containing the plurality of partition structures;

[0055] The plurality of isolation structures are removed such that the conductive layers at the plurality of isolation structures are simultaneously removed, and the remaining conductive layers form a plurality of first electrodes, and the plurality of first electrodes are electrically connected to the plurality of traces through the plurality of first vias.

[0056] On the other hand, embodiments of this disclosure provide a liquid crystal lens substrate, comprising:

[0057] A substrate, the substrate including a display area and a non-display area located on at least one side of the display area;

[0058] A plurality of first electrodes are located on the same side of the substrate, and the plurality of first electrodes extend from the display area to the non-display area;

[0059] An insulating layer is located on the side of the layer containing the plurality of first electrodes away from the substrate. The insulating layer includes a plurality of first vias located in the non-display area. The orthographic projection of the plurality of first vias on the substrate is located within the orthographic projection of the plurality of traces on the substrate.

[0060] Multiple traces are located on the side of the insulating layer away from the layer containing the multiple first electrodes. The multiple traces are wound around the display area and are electrically connected to the multiple first electrodes through the multiple first vias.

[0061] On the other hand, this disclosure provides a method for manufacturing the above-mentioned liquid crystal lens substrate, including:

[0062] A substrate is provided, the substrate including a display area and a non-display area located on at least one side of the display area;

[0063] A plurality of first electrodes extending from the display area to the non-display area are patterned on the substrate.

[0064] An insulating layer including multiple first vias is patterned on the layer containing the multiple first electrodes, wherein the orthographic projection of the multiple first vias on the substrate is located within the orthographic projection of the multiple first electrodes on the substrate;

[0065] Multiple traces are patterned on the insulating layer and wound around the display area, such that the multiple traces are electrically connected to the multiple first electrodes through the multiple first vias.

[0066] On the other hand, this disclosure provides a liquid crystal lens module, including a first substrate and a second substrate disposed opposite to each other, and a liquid crystal layer located between the first substrate and the second substrate, wherein the first substrate is the liquid crystal lens substrate provided in this disclosure.

[0067] On the other hand, this disclosure provides a display device, including: a display panel, and a liquid crystal lens module located on the display side of the display panel, wherein the liquid crystal lens module is the liquid crystal lens module provided in this disclosure. Attached Figure Description

[0068] Figure 1 shows an image of electrode climbing fracture in a related technology;

[0069] Figure 2 is a schematic diagram of the structure of the liquid crystal lens substrate provided in an embodiment of this disclosure;

[0070] Figure 3 is a magnified structural diagram of region Z1 in Figure 2;

[0071] Figure 4 is a magnified structural diagram of region Z2 in Figure 3;

[0072] Figure 5 is a schematic diagram of another enlarged structure of region Z2 in Figure 3;

[0073] Figure 6 is a magnified structural diagram of region Z3 in Figure 3;

[0074] Figure 7 is a schematic diagram of another enlarged structure of region Z3 in Figure 3;

[0075] Figure 8 is a cross-sectional view along line I-I' in Figures 4 to 6;

[0076] Figure 9 is a cross-sectional view along line II-II' in Figures 6 and 7;

[0077] Figure 10 is a schematic diagram of the wiring dimensions of the liquid crystal lens substrate shown in Figure 4;

[0078] Figure 11 is a flowchart of the fabrication method of the liquid crystal lens substrate shown in Figures 4 to 7;

[0079] Figure 12 is a flowchart of the fabrication process of the liquid crystal lens substrate shown in Figure 4;

[0080] Figure 13 is a schematic diagram of another structure of the liquid crystal lens substrate provided in the embodiments of this disclosure;

[0081] Figure 14 is a flowchart of the fabrication method of the liquid crystal lens substrate shown in Figure 13;

[0082] Figure 15 is a flowchart of the fabrication process of the liquid crystal lens substrate shown in Figure 13.

[0083] Figure 16 is a schematic diagram of another enlarged structure of region Z1 in Figure 2;

[0084] Figure 17 is a cross-sectional view along line III-III' in Figure 16;

[0085] Figure 18 is a flowchart of the fabrication method of the liquid crystal lens substrate shown in Figures 16 and 17;

[0086] Figure 19 is a schematic diagram of the structure of the liquid crystal lens module provided in the embodiment of this disclosure;

[0087] Figure 20 is a schematic diagram of a display device provided in an embodiment of this disclosure;

[0088] Figure 21 is a schematic diagram of another structure of the display device provided in the embodiments of this disclosure. Detailed Implementation

[0089] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be noted that the dimensions and shapes of the figures in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of known functions and known components are omitted.

[0090] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure and the claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “inner,” “outer,” “upper,” and “lower” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described object changes.

[0091] Liquid crystal lens modules, as novel optical devices, are widely used in various fields. They utilize the property that liquid crystal materials change their refractive index under the influence of an electric field to focus and disperse light. When a voltage is applied to the liquid crystal lens module, the orientation of the liquid crystal molecules changes, thereby altering the refractive index distribution of the liquid crystal layer and modulating the light.

[0092] In some embodiments, to improve the optical display effect, a number of liquid crystal lenses can be formed by controlling the liquid crystal layer through more electrodes. Therefore, the electrodes require more wiring space, resulting in a very small wiring space for individual electrodes and the common wiring space (i.e., PITCH) between electrode gaps. The size of the electrodes becomes increasingly thinner, and the size of the electrodes needs to be designed to be closer and closer to the process limits of the equipment.

[0093] However, in actual manufacturing, as electrodes become increasingly thinner, the risk of line breakage on flat interfaces within the display area is relatively low. However, when finer electrodes are routed along the ramp edges of the wiring area, they are prone to breakage during wet etching of the electrode material layer. This is because the etching solution drills through the ramp edges, resulting in significant electrode breakage (i.e., ITO STEP OPEN), as shown in Figure 1. These breakages cause electrical defects on the 3D display. Due to space constraints, there is no way to compensate for this by widening the electrodes at the ramp edges. In some embodiments, line breakage at the steps can be improved by reducing the step difference. For example, CN117116949A uses a trenching method to pre-embed the lower functional layer in a groove, thus reducing the step difference. This method requires a separate groove fabrication step, which is cumbersome. Furthermore, it is sometimes difficult to ensure that the functional layer is at the same height as the groove, still resulting in a certain step difference. This method is suitable for scenarios where the planarization layer material is organic resin; for scenarios using inorganic insulating layers, the planarization effect is not good.

[0094] To at least improve the aforementioned technical problems existing in related technologies, this disclosure provides a liquid crystal lens substrate. Figure 2 is a structural schematic diagram of the liquid crystal lens substrate provided in this disclosure embodiment. Figure 3 is an enlarged structural schematic diagram of region Z1 in Figure 2. Figure 4 is an enlarged structural schematic diagram of region Z2 in Figure 3. Figure 5 is another enlarged structural schematic diagram of region Z2 in Figure 3. Figure 6 is an enlarged structural schematic diagram of region Z3 in Figure 3. Figure 7 is another enlarged structural schematic diagram of region Z3 in Figure 3. Figure 8 is a cross-sectional view along line I-I' in Figures 4 to 6. Figure 9 is a cross-sectional view along line II-II' in Figures 6 and 7. As can be seen from Figures 2 to 9, the liquid crystal lens substrate provided in this disclosure embodiment includes:

[0095] The substrate 101 includes a display area AA and a non-display area BB located on at least one side of the display area AA. Figure 2 specifically illustrates the arrangement of the non-display area BB surrounding the display area AA. Optionally, the display area AA includes an array of red sub-pixel areas, green sub-pixel areas, blue sub-pixel areas, etc. The substrate 101 is a substrate that allows visible light to pass through, such as glass, quartz, plastic, etc., wherein the glass material can be alkali-free glass, alkali-containing glass, or tempered glass, etc.

[0096] Multiple traces 102 are located on the same side of the substrate 101. The multiple traces 102 are wound around the display area AA within the non-display area BB. For example, the traces 102 are wrapped around the display area AA once within the non-display area BB. The material of the traces 102 may include at least one metal material such as aluminum (Al), molybdenum (Mo), copper (Cu), gold (Au), titanium (Ti), nickel (Ni), and silver (Ag), and / or at least one alloy material such as aluminum-neodymium alloy (AlNd) and molybdenum-niobium alloy (MoNb). The traces 102 may be a single-layer structure or a multi-layer composite structure.

[0097] An insulating layer 103 is located on the side of the layer containing the multiple traces 102 away from the substrate 101. The insulating layer 103 includes a plurality of first vias V1 located in the non-display area BB, and a plurality of second vias V2 located at least in the non-display area BB. The orthographic projection of the plurality of first vias V1 on the substrate 101 lies within the orthographic projection of the multiple traces 102 on the substrate 101. The plurality of second vias V2 include an undercut angle β, and the orthographic projection of the plurality of second vias V2 on the substrate 101 intersects (e.g., is perpendicular to) the orthographic projection of the multiple traces 102 on the substrate 101.

[0098] Multiple first electrodes 104 are located on the side of the insulating layer 103 away from the layer containing the multiple traces 103. The multiple first electrodes 104 are located at least in the non-display area BB. The multiple first electrodes 104 are electrically connected to the multiple traces 102 through multiple first vias V1 penetrating the insulating layer 103. After a conductive film is deposited on the side of the insulating layer 103 away from the layer containing the multiple traces 103, a conductive film cannot be deposited at the undercut corner β, causing the conductive film to be interrupted at the second via V2, thus forming multiple first electrodes 104. In other words, adjacent first electrodes 104 are spaced apart by the second via V2. In some embodiments, the material of the first electrodes 104 may include at least one transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc aluminum oxide (AZO), or zinc gallium oxide (GZO). In some embodiments, the thickness of the conductive film is greater than or equal to 20 nm and less than or equal to 60 nm, for example, 20 nm, 30 nm, 40 nm, 50 nm, or 60 nm.

[0099] In the liquid crystal lens substrate provided in the present disclosure embodiment, since a conductive film cannot be deposited at the undercut corner β after the conductive film is deposited on the side of the insulating layer 103 away from the layer where the multiple traces 103 are located, the conductive film will be interrupted at the second via V2 to form multiple first electrodes 104. Therefore, it is not necessary to form the first electrodes 104 by etching, thereby avoiding the problem of the first electrode 104 breaking at the ramp trace 102 due to the drilling of the conductive film at the ramp by the wet etching solution. This improves the manufacturing yield of the first electrode 104.

[0100] In some embodiments, as shown in Figures 3 to 9, after a conductive film is deposited on the side of the insulating layer 103 away from the layer where the multiple traces 103 are located, a conductive film cannot be deposited at the undercut corner β. The conductive film is interrupted at the second via V2 to form multiple first electrodes 104. At the same time, a second electrode 105 located in the second via V2 is also formed. Based on this, the liquid crystal lens substrate provided in this disclosure may also include multiple second electrodes 105 located at least in the non-display area BB and disposed in the same layer and with the same material as the multiple first electrodes 104. The orthogonal projection of the multiple second electrodes 105 on the substrate 101 is located within the orthogonal projection of the multiple second via V2 on the substrate 101. The orthogonal projection of the multiple second electrodes 105 on the substrate 101 and the orthogonal projection of the undercut corner β on the substrate do not overlap with each other. This is equivalent to the size J of the second electrode 105 in the first direction X being less than or equal to the common bottom edge size B of the inverted trapezoidal structure V21 and the regular trapezoidal structure V22.

[0101] In some embodiments, as shown in FIG4, in the liquid crystal lens substrate provided in the embodiments of this disclosure, a plurality of second vias V2, a plurality of first electrodes 104, and a plurality of second electrodes 105 are located in the non-display area BB. In this case, the liquid crystal lens substrate may further include a plurality of third electrodes 106 located in the display area AA. The plurality of third electrodes 106 are integrally disposed with the plurality of first electrodes 104. For example, the Nth third electrode 106_N is integrally disposed with the Nth first electrode 104_N, and the (N+1)th third electrode 106_N+1 is integrally disposed with the (N+1)th first electrode 104_N+1, so that the voltage of the trace 102 is transmitted to the third electrode 106 through the first electrode 104. In this way, the third electrode 106 can drive the liquid crystal molecules to deflect and form a liquid crystal lens. In some embodiments, every n (n is the total number of traces 102) third electrodes 106 can be grouped together. Each third electrode 106 in a group of third electrodes 106 can be electrically connected to the trace 102 in a one-to-one correspondence, so that a group of third electrodes 106 can control the liquid crystal layer to form a liquid crystal lens.

[0102] In this disclosure, the first electrode 104 and the third electrode 106 are "integrated" to mean that the first electrode 104 and the third electrode 106 constitute a complete electrode. In other words, the first electrode 104 and the third electrode 106 are each part of the same complete electrode.

[0103] In some embodiments, as shown in FIG5 to FIG7, in the liquid crystal lens substrate provided in the present disclosure, a plurality of second vias V2, a plurality of first electrodes 104, and a plurality of second electrodes 105 are located in the display area AA and the non-display area BB. In this case, at least the first electrode 104 can be used to control the rotation of liquid crystal molecules, thereby eliminating the need to etch and form a third electrode 106 in the display area AA, simplifying the process flow and significantly reducing manufacturing costs.

[0104] In some embodiments, as shown in Figures 4 and 5, the second electrode 105 does not participate in the formation of the liquid crystal lens. Therefore, the second electrode 105 does not need to be driven by the trace 102, allowing a partial insulating layer 103 to exist between the second electrode 105 and the trace 102. In other words, the second via 105 can be a blind via that does not penetrate the insulating layer 103, and the second electrode 105 is in a floating state, with the second electrode 105 and the trace 102 being mutually insulated. In some embodiments, the insulating layer 103 may include a first sub-insulating layer 1031, and a second sub-insulating layer 1032 and a third sub-insulating layer 1033 sequentially located on the side of the first sub-insulating layer 1031 away from the substrate 101. As shown in Figure 8, the blind via may only penetrate the third sub-insulating layer 1033 and the second sub-insulating layer 1032, allowing the second electrode 105 and the trace 102 to be mutually insulated through the first sub-insulating layer 1031.

[0105] In some embodiments, as shown in Figures 6 and 7, the second electrode 105 can be electrically connected to the trace 102, so that both the first electrode 104 and the second electrode 105 participate in the formation of the liquid crystal lens. One of the first electrode 104 and the second electrode 105 can serve as the odd-numbered (2N+1)th electrode, and the other as the even-numbered (2N)th electrode. Figures 6 and 7 illustrate this with the first electrode 104 as the odd-numbered (2N+1)th electrode and the second electrode 105 as the even-numbered (2N)th electrode. This effectively reduces the spacing between adjacent electrodes, thereby reducing the electrode wiring size, increasing the number of traces in the same space, significantly improving wiring density, substantially enhancing the optical display effect, and broadening the application of liquid crystal lens modules in naked-eye 3D scenarios.

[0106] In some embodiments, as shown in Figures 6, 7, and 9, the second via V2 can be a through-hole th penetrating the first sub-insulating layer 1031, the second sub-insulating layer 1032, and the third sub-insulating layer 1033 at the intersection of the second electrode 105 and the trace 102 to be electrically connected, so that the second electrode 105 is electrically connected to the trace 102 at the through-hole th. Furthermore, the second via V2 can be a blind via in the area outside the intersection of the second electrode 105 and the trace 102 to be electrically connected, so that the second electrode 105 is insulated from the trace 102 that is not electrically connected. Optionally, in Figures 6 and 7, n (n is the total number of traces 102) first electrodes 104 and second electrodes 105 are set as a group, and the electrodes in a group can be electrically connected one-to-one with the traces 102, so that a group of electrodes can control the liquid crystal layer to form a liquid crystal lens.

[0107] In some embodiments, in the liquid crystal lens substrate provided in the present disclosure, as shown in FIG6, the through hole th and the first via hole V1 may be located in the non-display area BB (e.g., the first non-display area BB1 and the second non-display area BB2) on the opposite side of the display area AA, or, as shown in FIG7, the through hole th and the first via hole V1 may be located in the non-display area BB (e.g., the first non-display area BB1) on the same side of the display area AA.

[0108] In some embodiments, in the liquid crystal lens substrate provided in the present disclosure, the material of the first sub-insulating layer 1031 is different from the material of the second sub-insulating layer 1032, and the material of the second sub-insulating layer 1032 is the same as the material of the third sub-insulating layer 1033, so that the first via V1 can penetrate the second sub-insulating layer 1032 and the third sub-insulating layer 1033 through a single etching process, and can penetrate the first sub-insulating layer 1031 through another etching process; the second via V2 can penetrate the second sub-insulating layer 1032 and the third sub-insulating layer 1033 through a single etching process, and can penetrate the first sub-insulating layer 1031 at the electrical connection between the second electrode 105 and the trace 102 through another etching process. In some embodiments, the film of the second sub-insulating layer 1032 is more porous than that of the third sub-insulating layer 1033, that is, the film of the second sub-insulating layer 1032 is more porous and the film of the third sub-insulating layer 1033 is more dense. This facilitates the formation of the second via V2 shown in Figures 8 and 9, which has a gentler upper part and an undercut angle β at the bottom.

[0109] In some embodiments, in the liquid crystal lens substrate provided in the present disclosure, as shown in FIG8 and FIG9, the second via V2 includes an inverted trapezoidal structure V21 and a regular trapezoidal structure V22 that are disposed through each other. The inverted trapezoidal structure V21 penetrates the third sub-insulating layer 1033, and the regular trapezoidal structure V22 penetrates at least the second sub-insulating layer 1032. Specifically, the regular trapezoidal structure V22 penetrates the second sub-insulating layer 1032 and the first sub-insulating layer 1031 at the intersection where the second electrode 105 and the trace 102 need to be electrically connected. In the area where the second electrode 105 and the trace 102 do not need to be electrically connected, the regular trapezoidal structure V22 penetrates only the second sub-insulating layer 1032. The base angle of the regular trapezoidal structure V22 away from the inverted trapezoidal structure V21 is the undercut angle β. This second through-hole V2, which is approximately hourglass-shaped, not only facilitates the disconnection between the first electrode 104 and the second electrode 105, but also, due to the gentle slope of the inverted trapezoidal structure V21, effectively ensures that the first electrode 104 is not easily broken when climbing up the inverted trapezoidal structure V21.

[0110] To effectively disconnect the first electrode 104 from the second electrode 105 while ensuring the continuous arrangement of the first electrode 104, as shown in Figures 8 and 9, this disclosure allows for setting the base dimension of the inverted trapezoidal structure V21 away from the regular trapezoidal structure V22 to be A, the base dimension A' of the regular trapezoidal structure V22 away from the inverted trapezoidal structure V21 to be approximately the same as A, the shared base dimension of the inverted trapezoidal structure V21 and the regular trapezoidal structure V22 to be B, the dimension of the undercut angle β in the extension direction of the base of the inverted trapezoidal structure V21 (i.e., the first direction X) to be C, and the dimension of the undercut angle β in the stacked... The dimension in direction Z is D, the height of the trapezoidal structure V22 in the stacking direction Z is E, the distance between the first electrode 104 and the second electrode 105 in the extension direction of the waist of the inverted trapezoidal structure V21 is F, the material of the first sub-insulating layer 1031 includes silicon oxide, the material of the second sub-insulating layer 1032 and the material of the third sub-insulating layer 1033 include silicon nitride, and in the stacking direction Z: the thickness of the first sub-insulating layer 1031 is G, the thickness of the second sub-insulating layer 1032 is H, and the thickness of the third sub-insulating layer 1033 is I.

[0111] Wherein, 2μm≤A≤8μm, 1μm≤B≤6μm, 0.5μm≤C≤2μm, D≈E=H or H+I, 0.8≤F / E≤1.2, 20nm≤G≤50nm, 100nm≤H≤500nm, 100nm≤I≤300nm, for example, A is 2μm, 4μm, 6μm, 8μm, etc., B is 1μm, 2μm, 3μm, 4μm, 5μm, 6μm, etc., C is 0.5μm, 1μm, 1.5μm, 2μm, 100nm≤D≈E=H≤ 500nm, for example, D, E, H are 100nm, 200nm, 300nm, 400nm, 500nm, etc., 200nm≤D=H+I≤800nm, for example, D, E are 200nm, 300nm, 400nm, 500nm, 600nm, 700nm, 800nm, etc., F / E are 0.8, 0.9, 1, 1.1, 1.2, etc., G is 20nm, 30nm, 40nm, 50nm, etc., and I is 100nm, 200nm, 300nm, etc. In some embodiments, a second via V2 can be formed by etching. The longer the etching time, the larger the dimensions of A, B, and C.

[0112] In some embodiments, FIG10 corresponds to the scheme shown in FIG4 where the integrated first electrode 104 and third electrode 106 drive the liquid crystal layer to form a liquid crystal lens. In FIG4 and FIG10, the total wiring dimension P1 of the mask design for the third electrode 106 includes the dimension W of the gap V between adjacent third electrodes 106 and the line width S of the third electrode 106. The dimension W of the gap V between adjacent third electrodes 106 is the same as the common base dimension B of the inverted trapezoidal structure V21 and the regular trapezoidal structure V22. The dimension S of the third electrode 106 is the same as the dimension K of the first electrode 104, i.e., P1 = W + S. After the masking process, the actual dimension of the gap V between adjacent third electrodes 106 is S-DI, and the third electrode 106... The actual size of 6 is W-DI, usually W-DI = W, S-DI = S. After the masking process, in order to completely etch away the conductive material at the gap V, the etching width will be slightly larger than S-DI, that is, there will be an etching deviation e / b. However, the conductive material (e.g., ITO) plated on the wall of the second via V2 is also part of the first electrode 104, which is equivalent to compensating for the linewidth of the third electrode 106. Therefore, W-FI and W-DI(W) are basically the same, and S-FI and S-DI(S) are also basically equal. That is, in the actual product, P1 = W + S. In Figures 6 and 7, there are two wiring dimensions P2 and P3. P2 is equal to the sum of the size S of the first electrode 104 and the gap size L between the first electrode 104 and the second electrode 105. P3 is equal to the sum of the size M of the second electrode and the gap size L between the first electrode 104 and the second electrode 105. As can be seen from Figures 4, 6, 7 and 10, P1 is greater than P2 and P3. Therefore, the wiring density of the embodiments shown in Figures 6 and 7 is greater, which substantially improves the optical display effect.

[0113] Based on the same inventive concept, this disclosure provides a method for manufacturing the above-mentioned liquid crystal lens substrate, as shown in FIG11, which may include the following steps:

[0114] S1101, A substrate is provided, the substrate including a display area and a non-display area located on at least one side of the display area;

[0115] S1102. Patterning multiple traces around the display area on a substrate;

[0116] S1103. An insulating layer including multiple first vias and multiple second vias is patterned on the layer containing multiple traces; wherein, the multiple second vias are at least located in the non-display area, the multiple second vias include undercut corners, and the orthographic projections of the multiple second vias on the substrate intersect with the orthographic projections of the multiple traces on the substrate; the orthographic projections of the multiple first vias on the substrate are located within the orthographic projections of the multiple traces on the substrate.

[0117] S1104. A plurality of first electrodes are formed on an insulating layer, at least in the non-display area, such that the plurality of first electrodes are electrically connected to a plurality of traces through a plurality of first vias, and adjacent first electrodes are spaced apart through second vias.

[0118] In some embodiments, in the manufacturing method provided in this disclosure, in step S1103, an insulating layer including multiple second vias is patterned on the layer containing the multiple traces. The multiple second vias are located at least in the non-display area, and the multiple second vias include bottom chamfers. This can be specifically implemented in the following ways:

[0119] An insulating layer comprising a first sub-insulating layer, a second sub-insulating layer, and a third sub-insulating layer is formed by depositing a film on the layer containing multiple traces;

[0120] The process involves photoresist coating, masking, exposure, development, etching, and photoresist stripping to form multiple inverted trapezoidal structures that penetrate at least the third sub-insulating layer in the non-display area, and multiple upright trapezoidal structures that penetrate at least the second sub-insulating layer. The inverted trapezoidal structures and the upright trapezoidal structures are connected to form a second via, and the bottom corner of the upright trapezoidal structure away from the inverted trapezoidal structure is the bottom chamfer of the second via.

[0121] In some embodiments, in the manufacturing method provided in this disclosure, the deposition of the second sub-insulating layer and the third sub-insulating layer in step S1103 specifically includes:

[0122] A second sub-insulating layer is formed by depositing silane, ammonia and nitrogen in a gas ratio of 1:2:7 to 1:3:7 on the first sub-insulating layer.

[0123] A third sub-insulating layer is formed by depositing silane, ammonia and nitrogen in a gas ratio of 1:10:40 to 1:15:40 on the second sub-insulating layer.

[0124] In some embodiments, in the fabrication method provided in this disclosure, step S1103, which uses an etching process to form a plurality of inverted trapezoidal structures that penetrate at least the third sub-insulating layer in the non-display area and a plurality of upright trapezoidal structures that penetrate at least the second sub-insulating layer, specifically includes:

[0125] Using SF6:O2 with a gas ratio of 1:1 to 1:2 and an etching power of 6KW to 10KW, the third sub-insulating layer and the second sub-insulating layer are etched in a uniform etching mode to form multiple inverted trapezoidal structures that penetrate the third sub-insulating layer and multiple upright trapezoidal structures that penetrate the second sub-insulating layer, at least in the non-display area.

[0126] In some embodiments, in the fabrication method provided in this disclosure, after step S1103 uses SF6:O2 with a gas ratio of 1:1 to 1:2 and an etching power of 6KW to 10KW to etch the third sub-insulating layer and the second sub-insulating layer in a uniform etching mode to form multiple inverted trapezoidal structures penetrating the third sub-insulating layer and multiple upright trapezoidal structures penetrating the second sub-insulating layer at least in the non-display area, the method further includes:

[0127] Using a mixture of CF4 and O2, the first sub-insulating layer at the partial overlap between the trapezoidal structure and the trace is etched away, so that the trapezoidal structure is penetrated from the second sub-insulating layer to the first sub-insulating layer at the partial overlap with the trace.

[0128] In some embodiments, in the manufacturing method provided in this disclosure, the forming of an insulating layer including a plurality of first vias in the non-display area in step S1103 specifically includes:

[0129] Using SF6:O2 with a gas ratio of 1:3 to 1:4 and an etching power of 2KW to 10KW, the third sub-insulating layer and the second sub-insulating layer are etched in reactive particle etching mode to form multiple sub-vias that penetrate the third sub-insulating layer and the second sub-insulating layer in the non-display area and have approximately uniform apertures.

[0130] A mixture of CF4 and O2 gas is used to etch away the first sub-insulating layer under multiple sub-vias, so that multiple sub-vias penetrate into the first sub-insulating layer to form multiple first vias.

[0131] In some embodiments, in the manufacturing method provided in this disclosure, step S1104 involves depositing a plurality of first electrodes at least located in the non-display area on an insulating layer, such that adjacent first electrodes are spaced apart by second vias. Specifically, this includes:

[0132] A conductive layer is formed by depositing a film on an insulating layer. The conductive layer is separated in the non-display area by a plurality of second vias into a plurality of first electrodes overlapping the edges of the second vias and a plurality of second electrodes located within the plurality of second vias.

[0133] In some embodiments, in the fabrication method provided in this disclosure, after performing step S1104 of depositing a conductive layer on the insulating layer, and after the conductive layer is separated in the non-display area by a plurality of second vias into a plurality of first electrodes overlapping the edges of the second vias and a plurality of second electrodes located within the plurality of second vias, the following steps may also be performed:

[0134] The conductive layer is formed in the display area by using photoresist coating, masking, exposure, development, etching, and photoresist stripping processes to form multiple third electrodes that are integrally disposed with multiple first electrodes.

[0135] To better understand the technical solution of the manufacturing method provided in the embodiments of this disclosure, the following detailed description is based on the manufacturing of the liquid crystal lens substrate shown in FIG4, as shown in FIG12, including the following steps:

[0136] The first step involves selecting a glass substrate as the substrate 101. The glass material can be alkali-free glass, alkali-containing glass, or tempered glass, etc. Multiple traces 102 are then fabricated on the substrate 101 using magnetron sputtering, photoresist coating, masking, exposure, development, etching, and photoresist stripping processes, as shown in Figure 12(a). The traces 102 can be made of one or more of the following materials in a stacked structure: Al, Mo, Cu, Au, Ti, Ni, and Ag.

[0137] The second step, as shown in Figure 12(b), involves depositing an inorganic non-metallic insulating layer 103 on the layer containing the trace 102 using chemical vapor deposition. The insulating layer 103 consists of three parts: a first sub-insulating layer 1031 made of SiO2 with a thickness ranging from 20 nm to 50 nm; a second sub-insulating layer 1032 made of SiNx with a thickness ranging from 100 nm to 500 nm; and a third sub-insulating layer 1033 made of SiNx with a thickness ranging from 100 nm to 300 nm. The second sub-insulating layer 1032 and the third sub-insulating layer 1033 have different film qualities, with the third sub-insulating layer 1033 being more dense than the second sub-insulating layer 1032. The second sub-insulating layer 1032 and the third sub-insulating layer 1033 are fabricated by chemical vapor deposition. The main gases used are silane, ammonia and nitrogen. The gas ratio of silane, ammonia and nitrogen for the second sub-insulating layer 1032 is in the range of 1:2:7 to 1:3:7, and the gas ratio of silane, ammonia and nitrogen for the third sub-insulating layer 1033 is in the range of 1:10:40 to 1:15:40.

[0138] The third step, as shown in Figure 12(c), involves using exposure and development processes to form a photoresist layer PR in the peripheral wiring area, exposing the region to be fabricated as the second via V2. Then, under the cover of the photoresist layer PR, dry etching is used to etch the insulating layer 103. During the etching process, the source power, bias power, and gas ratio of the etching equipment are adjusted to achieve a homogeneous etching mode. Finally, the photoresist layer PR is stripped away. In some embodiments, the etching gas is a mixture of SF6 and O2, with an etching power of 6 kW to 10 kW, a source power of 8 kW, and a SF6 to O2 etching gas ratio of 1:1 to 1:2. Due to the use of a homogeneous etching mode, and because the SF6 etching gas cannot etch SiO2, after etching, a second via V2 is formed as shown in Figure 12(c), with a gentler upper section, a bottom chamfer β, and the SiO2 insulating layer remaining.

[0139] The fourth step involves using exposure and development processes to form a photoresist layer PR in the peripheral wiring area, exposing the region to be fabricated as the first via V1, as shown in Figure 12(d). Then, under the cover of the photoresist layer PR, dry step-by-step etching is performed. This step-by-step etching is divided into two steps: the first step uses a mixture of SF6 and O2 gas to etch away the second sub-insulating layer 1032 and the third sub-insulating layer 1033; the second step uses a mixture of CF4 and O2 gas to etch away the first sub-insulating layer 1031. Finally, the photoresist layer PR is stripped away, as shown in Figure 12(e). In this step, the RIE (Reactive Particle Etching) etching mode is achieved by adjusting the source power, bias power, and gas ratio of the etching equipment. Optionally, the etching power is 2KW to 10KW, for example, the source power is 8KW, the bias power is 2KW, and the ratio of SF6 and O2 etching gases is 1:3 to 1:4. After etching, the first via V1 connecting the trace 102 and the first electrode 104 in Figure 12 (e) is formed. Optionally, V1 is located on the same side of the display area AA.

[0140] The fifth step, as shown in Figure 12(f), involves depositing a 20nm to 60nm thick ITO thin film by magnetron sputtering to create the first electrode 104 of the non-display area BB. Since ITO film cannot be deposited at the undercut angle β of the second via V2, the presence of the undercut angle β after film deposition results in a first electrode 104 and a second electrode 105 that are disconnected from each other. The first electrode 104 is electrically connected to the trace 102 through the first via V1, and the second electrode 105 is located inside the second via V2 and is insulated from the trace 102 through the first sub-insulating layer 1031.

[0141] The sixth step involves photoresist coating, masking, exposure, development, etching, and photoresist stripping processes to form multiple third electrodes 106 integrally disposed with the multiple first electrodes 104 in the display area AA. Specifically, the alignment of the third electrodes 106 in the display area AA with the first electrodes 104 in the non-display area BB is mainly achieved through the alignment of the first via V1 with the display area AA (TV-AA). At this point, the liquid crystal lens substrate shown in Figure 4 is manufactured.

[0142] The difference between the fabrication method of the liquid crystal lens substrate shown in Figure 5 and that shown in Figure 4 is that in the third step, the second via V2 extends from the non-display area BB to the display area AA. The corresponding first electrode 104 and second electrode 105 are disconnected from each other in the display area AA and the non-display area BB. Thus, the first electrode 104 can drive the liquid crystal to deflect in the display area AA to form a liquid crystal lens, thereby eliminating the need to perform the operation in the sixth step to fabricate the third electrode 105 in the display area AA.

[0143] The fabrication method of the liquid crystal lens substrate shown in Figures 6 and 7 differs from that shown in Figure 4 in that: in the third step, the second via V2 extends from the non-display area BB to the display area AA, and the corresponding first electrode 104 and second electrode 105 are disconnected from each other in the display area AA and the non-display area BB; in addition, while forming the first via V1 connecting the first electrode 104 and the trace 102 in the fourth step, the second via V2 includes a through hole th at the intersection of the second electrode 105 and the trace 102 that needs to be electrically connected; thus, the first electrode 104 and the second electrode 105 can drive the liquid crystal to deflect in the display area AA to form a liquid crystal lens, thereby eliminating the need to perform the operation in the sixth step to fabricate the third electrode 105 in the display area AA.

[0144] In some embodiments, the liquid crystal lens substrate provided in this disclosure can also be the structure shown in FIG13. As can be seen from FIG13, the liquid crystal lens substrate of this disclosure may include, from bottom to top, a substrate 101, a trace 102, an insulating layer 103 having a first via V1, and a first electrode 104, and the first electrode 104 is electrically connected to the trace 102 through the first via V1. Regarding the liquid crystal lens substrate shown in FIG13, this disclosure provides a method for manufacturing a liquid crystal lens substrate, as shown in FIG14, including:

[0145] S1401, A substrate is provided, the substrate including a display area and a non-display area located on at least one side of the display area;

[0146] S1402. Patterning multiple traces around the display area on a substrate;

[0147] S1403. An insulating layer including multiple first vias is patterned on the layer where multiple traces are located, and the orthogonal projection of the multiple first vias on the substrate is located within the orthogonal projection of the multiple traces on the substrate.

[0148] S1404. Multiple partition structures extending from the display area to the non-display area are formed on the insulating layer, and the orthogonal projections of the multiple partition structures on the substrate do not overlap with the orthogonal projections of the multiple first vias on the substrate.

[0149] S1405. A conductive layer is formed by depositing a film on the layer containing multiple partition structures.

[0150] S1406. Remove multiple isolation structures, such that the conductive layers at the multiple isolation structures are removed simultaneously, and the remaining conductive layers form multiple first electrodes, and the multiple first electrodes are electrically connected to multiple traces through multiple first vias.

[0151] Therefore, the fabrication method shown in Figure 14 can reduce the risk of the first electrode breaking due to drilling by avoiding the wet etching process of the conductive layer, thereby improving the fabrication yield of the first electrode.

[0152] To better understand the technical solution of the fabrication method shown in Figure 14 of this disclosure, the fabrication method of the liquid crystal lens substrate shown in Figure 13 will be described in detail below as an example, as shown in Figure 15, including the following steps:

[0153] The first step, as shown in Figure 15(a), is to select a glass substrate as the substrate 101. The glass material can be alkali-free glass, alkali-containing glass, or tempered glass, etc. Multiple traces 102 are then fabricated on the substrate 101 using magnetron sputtering, photoresist coating, masking, exposure, development, etching, and photoresist stripping processes. The traces 102 can be made of one or more of the following materials in a stacked structure: Al, Mo, Cu, Au, Ti, Ni, and Ag.

[0154] The second step, as shown in Figure 15(b), is to deposit an insulating layer 103 composed of an inorganic non-metallic film on the layer where the trace 102 is located by chemical vapor deposition. Optionally, the insulating layer 103 can be a single film layer of SiNx or SiO2, or a composite film layer of SiNx and SiO2. The thickness of the insulating layer 103 ranges from 200 nm to 400 nm, for example, 300 nm.

[0155] The third step, as shown in Figure 15(c), is to use exposure and development processes to form a photoresist layer PR in the peripheral wiring area to expose the area to be fabricated as the first via V1. Then, under the cover of the photoresist layer PR, dry etching is used to form the first via V1 in the insulating layer 103. During the dry etching process, the etching mode can be adjusted by adjusting the source power, bias power, and gas ratio of the etching equipment.

[0156] The fourth step, as shown in Figure 15(d), involves using an exposure and development process to retain the photoresist layer PR only at the gap between the first electrode 104, without setting photoresist patterns at other locations. The thickness of the photoresist layer PR ranges from 1.0 μm to 3.0 μm, for example, 2.0 μm.

[0157] Step 6, as shown in Figure 15(e), uses magnetron sputtering to form an ITO film 104' with a thickness ranging from 20 nm to 60 nm, for example, 40 nm.

[0158] The seventh step, as shown in Figure 15(f), is to perform a photoresist lift-off process to remove the photoresist layer PR. After completion, the ITO pattern on the photoresist layer PR can be removed together to form multiple mutually spaced first electrodes 104.

[0159] On the other hand, this disclosure also provides a liquid crystal lens substrate, as shown in Figures 16 and 17, comprising: a substrate 101 from bottom to top, a first electrode 104, an insulating layer 103 having a first via V1, and a trace 102, wherein the trace 102 is electrically connected to the first electrode 104 through the first via V1. Optionally, for the fabrication of the liquid crystal lens substrate shown in Figures 16 and 17, this disclosure provides a fabrication method, as shown in Figure 18, which may include the following steps:

[0160] S1801, A substrate is provided, the substrate including a display area and a non-display area located on at least one side of the display area;

[0161] S1802, A plurality of first electrodes extending from the display area to the non-display area are patterned on the substrate;

[0162] S1803. An insulating layer including multiple first vias is patterned on the layer where multiple first electrodes are located, wherein the orthogonal projection of the multiple first vias on the substrate is located within the orthogonal projection of the multiple first electrodes on the substrate.

[0163] S1804. Multiple traces are patterned on the insulating layer and wound around the display area, such that the multiple traces are electrically connected to multiple first electrodes through multiple first vias.

[0164] As can be seen, in the liquid crystal lens substrate shown in Figures 16 to 18, the first electrode 104 is first formed on the substrate 101, and then the trace 102 is formed. This avoids the first electrode 104 climbing up the trace 102, and also prevents the wet etching solution from drilling the conductive film at the climbing point, which would cause the first electrode 104 to break at the climbing trace 102. This improves the manufacturing yield of the first electrode 104.

[0165] It should be noted that in the fabrication method provided in the embodiments of this disclosure, the patterning process involved in forming each layer structure may include not only some or all of the processes such as deposition, photoresist coating, masking, exposure, development, etching, and photoresist stripping, but may also include other processes, depending on the pattern to be formed in the actual fabrication process, and is not limited here. For example, a post-baking process may be included after development and before etching. The deposition process may be chemical vapor deposition, plasma-enhanced chemical vapor deposition, or physical vapor deposition, and is not limited here; the mask used in the masking process may be a half-tone mask, a single-slit mask, or a gray-tone mask, and is not limited here; the etching may be dry etching or wet etching, and is not limited here.

[0166] Based on the same inventive concept, this disclosure provides a liquid crystal lens module, as shown in FIG19, including a first substrate 001 and a second substrate 002 placed opposite each other, and a liquid crystal layer 003 located between the first substrate 001 and the second substrate 002. The first substrate 001 is any of the liquid crystal lens substrates provided in this disclosure. FIG19 illustrates the first substrate 001 as shown in FIG8. In some embodiments, the second substrate 002 may include a substrate 201 and a planar electrode 202 located on the side of the substrate 201 facing the liquid crystal layer 003. Other essential components of the liquid crystal lens module are understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting this disclosure.

[0167] Based on the same inventive concept, this disclosure provides a display device, as shown in Figures 20 and 21, including: a display panel PNL, and a liquid crystal lens module (LCL) located on the display side of the display panel PNL. The liquid crystal lens module (LCL) is the liquid crystal lens module described above in this disclosure. Optionally, the display panel PNL and the liquid crystal lens module (LCL) can be fixedly connected by optical adhesive (AD). In some embodiments, the display device provided in this disclosure can switch between 2D and 3D display modes. In 2D display mode, the liquid crystal lens module can be controlled to transmit light normally, while in 3D display mode, the liquid crystal lens module can be controlled to form a plurality of liquid crystal lenses. In some embodiments, the display panel PNL includes a plurality of pixel units arranged in an array, and each liquid crystal lens corresponds to at least one pixel unit.

[0168] In some embodiments, as shown in FIG20, the display panel PNL is an electroluminescent display panel, such as an organic light-emitting diode display panel or a quantum dot light-emitting diode display panel. In some embodiments, as shown in FIG21, the display panel PNL is a liquid crystal display panel. When the display panel PNL is a liquid crystal display panel, as shown in FIG21, the display device may further include a backlight module BLU located on the side of the display panel PNL opposite to the liquid crystal lens module LCL.

[0169] In some embodiments, the backlight module (BLU) can be a direct-lit backlight module or an edge-lit backlight module. Optionally, an edge-lit backlight module may include LED strips, stacked reflectors, light guide plates, diffusers, prism assemblies, etc., with the LED strips located on one side of the thickness direction of the light guide plate. A direct-lit backlight module may include a matrix light source, a reflector, diffuser, and brightness enhancement film stacked on the light-emitting side of the matrix light source, with the reflector including openings directly opposite the positions of the LEDs in the matrix light source. The LEDs in the LED strips and the LEDs in the matrix light source can be light-emitting devices (LEDs), such as quantum dot LEDs.

[0170] In some embodiments, the LEDs can also be micro-light-emitting devices (such as Mini LEDs and Micro LEDs). Sub-millimeter or even micrometer-scale micro-light-emitting devices, like organic light-emitting devices (OLEDs), are self-emissive devices. Like OLEDs, they offer advantages such as high brightness, ultra-low latency, and ultra-wide viewing angles. Furthermore, because inorganic light-emitting devices emit light based on more stable and lower-resistance metal semiconductors, they offer advantages over organic light-emitting devices (based on organic materials) in terms of lower power consumption, greater resistance to high and low temperatures, and longer lifespan. Moreover, when micro-light-emitting devices are used as backlights, they can achieve more precise dynamic backlighting effects, effectively improving screen brightness and contrast while also solving the glare problem caused by traditional dynamic backlighting between bright and dark areas of the screen, thus optimizing the visual experience.

[0171] In some embodiments, the display device provided in this disclosure can be any product or component with display function, such as a monitor, projector, 3D printer, virtual reality device, mobile phone, tablet computer, television, laptop computer, digital photo frame, navigator, smartwatch, fitness wristband, personal digital assistant, etc. Optionally, the display device provided in this disclosure includes, but is not limited to, components such as: radio frequency unit, network module, audio output & input unit, sensor, display unit, user input unit, interface unit, and control chip. Optionally, the control chip is a central processing unit, digital signal processor, system-on-a-chip (SoC), etc. For example, the control chip may also include memory, power module, etc., and achieve power supply and signal input / output functions through additionally provided wires, signal lines, etc. For example, the control chip may also include hardware circuits and computer-executable code. The hardware circuit may include conventional very large-scale integrated circuits (VLSI) or gate arrays, as well as existing semiconductors or other discrete components such as logic chips, transistors, etc.; the hardware circuit may also include field-programmable gate arrays, programmable array logic, programmable logic devices, etc. Furthermore, the above structure does not constitute a limitation on the display device provided in the embodiments of this disclosure. In other words, the display device provided in the embodiments of this disclosure may include more or fewer of the above components, or combine certain components, or arrange different components.

[0172] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0173] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of the embodiments of this disclosure. Therefore, if these modifications and variations to the embodiments of this disclosure fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include these modifications and variations.

Claims

1. A liquid crystal lens substrate, wherein, include: A substrate, the substrate including a display area and a non-display area located on at least one side of the display area; Multiple traces are located on the same side of the substrate, and the multiple traces are wound around the display area within the non-display area; An insulating layer is located on the side of the layer containing the plurality of traces away from the substrate. The insulating layer includes a plurality of first vias located in the non-display area and a plurality of second vias located at least in the non-display area. The plurality of second vias include undercut corners. The orthographic projections of the plurality of second vias on the substrate intersect the orthographic projections of the plurality of traces on the substrate. The orthographic projections of the plurality of first vias on the substrate are located within the orthographic projections of the plurality of traces on the substrate. A plurality of first electrodes are located on the side of the insulating layer away from the layer where the plurality of traces are located, and the plurality of first electrodes are at least located in the non-display area. The plurality of first electrodes are electrically connected to the plurality of traces through the plurality of first vias penetrating the insulating layer, and adjacent first electrodes are spaced apart through second vias.

2. The liquid crystal lens substrate as described in claim 1, wherein, It also includes at least a plurality of second electrodes located in the non-display area and disposed on the same layer as the plurality of first electrodes. The orthographic projection of the plurality of second electrodes on the substrate is located within the orthographic projection of the plurality of second vias on the substrate, and the orthographic projection of the plurality of second electrodes on the substrate does not overlap with the orthographic projection of the undercut angle on the substrate.

3. The liquid crystal lens substrate as described in claim 2, wherein, The plurality of second vias, the plurality of first electrodes, and the plurality of second electrodes are located in the non-display area; The liquid crystal lens substrate also includes a plurality of third electrodes located in the display area, and the plurality of third electrodes are integrally disposed with the plurality of first electrodes.

4. The liquid crystal lens substrate as described in claim 2, wherein, The plurality of second vias, the plurality of first electrodes, and the plurality of second electrodes are located in the display area and the non-display area.

5. The liquid crystal lens substrate as described in claim 3 or 4, wherein, The second via is a blind via, the second electrode is in a floating state, and the second electrode is insulated from the multiple traces.

6. The liquid crystal lens substrate as described in claim 5, wherein, The insulating layer includes a first sub-insulating layer, and a second sub-insulating layer and a third sub-insulating layer located sequentially on the side of the first sub-insulating layer away from the substrate, wherein the blind via penetrates the third sub-insulating layer and the second sub-insulating layer.

7. The liquid crystal lens substrate as described in claim 4, wherein, The second via is a through hole at the point where it overlaps with the trace, and the second electrode is electrically connected to the trace through the through hole.

8. The liquid crystal lens substrate as described in claim 7, wherein, The insulating layer includes a first sub-insulating layer, a second sub-insulating layer and a third sub-insulating layer stacked sequentially. The first sub-insulating layer is located between the second sub-insulating layer and the substrate. The via penetrates the third sub-insulating layer, the second sub-insulating layer and the first sub-insulating layer.

9. The liquid crystal lens substrate as described in claim 7 or 8, wherein, The through hole and the first via are located on the same side of the display area in the non-display area, or the through hole and the first via are located on the opposite side of the display area in the non-display area.

10. The liquid crystal lens substrate as described in claim 6 or 8, wherein, The material of the first sub-insulating layer is different from that of the second sub-insulating layer. The material of the second sub-insulating layer is the same as that of the third sub-insulating layer, but the film of the second sub-insulating layer is more porous than that of the third sub-insulating layer.

11. The liquid crystal lens substrate as described in claim 6, 8, or 10, wherein, The second via includes an inverted trapezoidal structure and a regular trapezoidal structure that are disposed through each other. The inverted trapezoidal structure penetrates the third sub-insulating layer, and the regular trapezoidal structure penetrates at least the second sub-insulating layer. The bottom angle of the regular trapezoidal structure away from the inverted trapezoidal structure is the bottom chamfer angle.

12. The liquid crystal lens substrate as claimed in claim 11, wherein, The inverted trapezoidal structure has a base dimension A that is far from the regular trapezoidal structure, and the inverted trapezoidal structure and the regular trapezoidal structure share a base dimension B, where 2μm≤A≤8μm and 1μm≤B≤6μm.

13. The liquid crystal lens substrate as described in claim 11 or 12, wherein, The dimension of the undercut angle in the direction of the extension of the bottom edge of the inverted trapezoidal structure is C, the dimension of the undercut angle in the stacking direction is D, the height of the regular trapezoidal structure in the stacking direction is E, 0.5μm≤C≤2μm, D≈E.

14. The liquid crystal lens substrate as claimed in claim 13, wherein, In the extending direction of the waist of the inverted trapezoidal structure, the distance between the first electrode and the second electrode is F, where 0.8 ≤ F / E ≤ 1.

2.

15. The liquid crystal lens substrate according to any one of claims 6, 8 to 14, wherein, The material of the first sub-insulating layer includes silicon oxide, and the materials of the second sub-insulating layer and the third sub-insulating layer include silicon nitride.

16. The liquid crystal lens substrate as claimed in claim 15, wherein, In the stacking direction: the thickness of the first sub-insulating layer is G, the thickness of the second sub-insulating layer is H, the thickness of the third sub-insulating layer is I, 20nm≤G≤50nm, 100nm≤H≤500nm, 100nm≤I≤300nm.

17. A method for manufacturing a liquid crystal lens substrate as described in any one of claims 1 to 16, wherein, include: A substrate is provided, the substrate including a display area and a non-display area located on at least one side of the display area; Multiple traces are patterned on the substrate and wound around the display area; An insulating layer comprising multiple first vias and multiple second vias is patterned on the layer containing the multiple traces; wherein, the multiple second vias are at least located in the non-display area, the multiple second vias include undercut corners, and the orthographic projections of the multiple second vias on the substrate intersect with the orthographic projections of the multiple traces on the substrate; the orthographic projections of the multiple first vias on the substrate are located within the orthographic projections of the multiple traces on the substrate; A plurality of first electrodes are deposited on the insulating layer to form at least one in the non-display area, such that the plurality of first electrodes are electrically connected to the plurality of traces through the plurality of first vias, and adjacent first electrodes are spaced apart through second vias.

18. The manufacturing method as described in claim 17, wherein, An insulating layer comprising multiple second vias is patterned on the layer containing the multiple traces, wherein the multiple second vias are located at least in the non-display area, and the multiple second vias include an undercut corner; specifically including: An insulating layer comprising a first sub-insulating layer, a second sub-insulating layer, and a third sub-insulating layer is formed by depositing a film on the layer containing the multiple traces; The process involves photoresist coating, photomask application, exposure, development, etching, and photoresist stripping to form multiple inverted trapezoidal structures penetrating at least the third sub-insulating layer in the non-display area, and multiple upright trapezoidal structures penetrating at least the second sub-insulating layer. The inverted trapezoidal structures and the upright trapezoidal structures are connected to form a second via, and the bottom angle of the upright trapezoidal structure away from the inverted trapezoidal structure is the bottom chamfer angle of the second via.

19. The manufacturing method as described in claim 18, wherein, The coating process forms a second and a third sub-insulating layer, specifically including: A second sub-insulating layer is formed by depositing silane, ammonia and nitrogen in a gas ratio of 1:2:7 to 1:3:7 on the first sub-insulating layer. A third sub-insulating layer is formed by depositing silane, ammonia, and nitrogen in a gas ratio of 1:10:40 to 1:15:40 on the second sub-insulating layer.

20. The manufacturing method as described in claim 19, wherein, The etching process is used to form a plurality of inverted trapezoidal structures penetrating at least the third sub-insulating layer within the non-display area, and a plurality of upright trapezoidal structures penetrating at least the second sub-insulating layer, specifically including: Using SF6:O2 with a gas ratio of 1:1 to 1:2 and an etching power of 6KW to 10KW, the third sub-insulating layer and the second sub-insulating layer are etched in a uniform etching mode to form multiple inverted trapezoidal structures penetrating the third sub-insulating layer and multiple upright trapezoidal structures penetrating the second sub-insulating layer, at least within the non-display area.

21. The manufacturing method as described in claim 20, wherein, Using an SF6:O2 gas ratio of 1:1 to 1:2 and an etching power of 6KW to 10KW, the third sub-insulating layer and the second sub-insulating layer are etched in a homogeneous etching mode to form multiple inverted trapezoidal structures penetrating the third sub-insulating layer and multiple upright trapezoidal structures penetrating the second sub-insulating layer, at least within the non-display area. The process further includes: Using a mixture of CF4 and O2, the first sub-insulating layer at the partial overlap between the trapezoidal structure and the trace is etched away, so that the trapezoidal structure is penetrated from the second sub-insulating layer to the first sub-insulating layer at the partial overlap with the trace.

22. The manufacturing method according to any one of claims 19 to 21, wherein, An insulating layer comprising a plurality of first vias is formed in the non-display area, specifically including: Using SF6:O2 with a gas ratio of 1:3 to 1:4 and an etching power of 2KW to 10KW, the third sub-insulating layer and the second sub-insulating layer are etched in reactive particle etching mode to form a plurality of sub-vias that penetrate the third sub-insulating layer and the second sub-insulating layer in the non-display area and have approximately uniform apertures. A mixed gas of CF4 and O2 is used to etch away the first sub-insulating layer under the plurality of sub-vias, so that the plurality of sub-vias penetrate into the first sub-insulating layer to form a plurality of first vias.

23. The manufacturing method according to any one of claims 17 to 22, wherein, A plurality of first electrodes are deposited on the insulating layer, at least located in the non-display area, such that adjacent first electrodes are spaced apart by the second vias, specifically including: A conductive layer is formed by depositing a film on the insulating layer. The conductive layer is at least separated in the non-display area by the plurality of second vias into a plurality of first electrodes overlapping the edges of the second vias, and a plurality of second electrodes located within the plurality of second vias.

24. The manufacturing method as described in claim 23, wherein, A conductive layer is deposited on the insulating layer to form a plurality of first electrodes overlapping the edges of the second vias in the non-display area, and a plurality of second electrodes located within the plurality of second vias. The conductive layer further includes: The conductive layer is formed in the display area by a process of photoresist coating, masking, exposure, development, etching, and photoresist stripping, thereby forming multiple third electrodes integrally disposed with the multiple first electrodes.

25. A method for manufacturing a liquid crystal lens substrate, wherein, include: A substrate is provided, the substrate including a display area and a non-display area located on at least one side of the display area; Multiple traces are patterned on the substrate and wound around the display area; An insulating layer including multiple first vias is patterned on the layer containing the multiple traces, wherein the orthographic projection of the multiple first vias on the substrate is located within the orthographic projection of the multiple traces on the substrate; A plurality of partition structures extending from the display area to the non-display area are formed on the insulating layer, wherein the orthogonal projections of the plurality of partition structures on the substrate do not overlap with the orthogonal projections of the plurality of first vias on the substrate. A conductive layer is formed by depositing a film on the layer containing the plurality of partition structures; The plurality of isolation structures are removed such that the conductive layers at the plurality of isolation structures are simultaneously removed, and the remaining conductive layers form a plurality of first electrodes, and the plurality of first electrodes are electrically connected to the plurality of traces through the plurality of first vias.

26. A liquid crystal lens substrate, wherein, include: A substrate, the substrate including a display area and a non-display area located on at least one side of the display area; A plurality of first electrodes are located on the same side of the substrate, and the plurality of first electrodes extend from the display area to the non-display area; An insulating layer is located on the side of the layer containing the plurality of first electrodes away from the substrate. The insulating layer includes a plurality of first vias located in the non-display area. The orthographic projection of the plurality of first vias on the substrate is located within the orthographic projection of the plurality of traces on the substrate. Multiple traces are located on the side of the insulating layer away from the layer containing the multiple first electrodes. The multiple traces are wound around the display area and are electrically connected to the multiple first electrodes through the multiple first vias.

27. A method for manufacturing a liquid crystal lens substrate as described in claim 26, wherein, include: A substrate is provided, the substrate including a display area and a non-display area located on at least one side of the display area; A plurality of first electrodes extending from the display area to the non-display area are patterned on the substrate. An insulating layer including multiple first vias is patterned on the layer containing the multiple first electrodes, wherein the orthographic projection of the multiple first vias on the substrate is located within the orthographic projection of the multiple first electrodes on the substrate; Multiple traces are patterned on the insulating layer and wound around the display area, such that the multiple traces are electrically connected to the multiple first electrodes through the multiple first vias.

28. A liquid crystal lens module, wherein, It includes a first substrate and a second substrate placed opposite each other, and a liquid crystal layer located between the first substrate and the second substrate, wherein the first substrate is a liquid crystal lens substrate as described in any one of claims 1 to 16, 26.

29. A display device, wherein, include: The display panel and the liquid crystal lens module located on the display side of the display panel, wherein the liquid crystal lens module is the liquid crystal lens module as described in claim 28.

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