Perovskite crystalline silicon laminated cell structure and preparation method thereof

Abstract

The invention discloses a perovskite crystalline silicon laminated cell structure and a preparation method thereof, the structure comprises a crystalline silicon bottom cell, a nanometer tunneling layer and a perovskite top cell which are arranged in sequence from bottom to top, and the nanometer tunneling layer is of a non-full coverage structure. By implementing the structure, the performance of the crystalline silicon / perovskite laminated solar cell can be improved, a perovskite film forming technology suitable for a suede crystalline silicon substrate is developed, the design of the middle tunneling layer is optimized to reduce light loss and non-radiative recombination loss, and the photoelectric performance and stability of the laminated solar cell are remarkably improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of solar cells, and particularly relates to a perovskite crystalline silicon laminated cell structure and a preparation method thereof. BACKGROUND

[0002] Solar energy is a new type of clean energy with great development potential, and it has attracted widespread attention due to its abundant resources and low cost. In the current technical system, photovoltaic cells are one of the main ways to realize the conversion of solar energy into electrical energy, among which single-crystal silicon, polycrystalline silicon and other types of solar cells have formed a relatively mature industrialization technology. In recent years, with the increasing demand for photoelectric conversion efficiency, perovskite / crystalline silicon laminated technology has gradually become a research hotspot in the photovoltaic field due to its unique advantages, and has been widely concerned by the industry. The development of this technology is of great significance to improve the photoelectric conversion efficiency of solar cells and reduce the manufacturing cost, thereby promoting the further development and application of solar power generation technology.

[0003] From a theoretical point of view, the effective photoelectric conversion efficiency of crystalline silicon / perovskite laminated solar cells can be as high as 40% or more, which is much higher than that of traditional crystalline silicon solar cells. The technical principle is to stack perovskite materials and crystalline silicon materials to form a heterojunction structure. By taking advantage of the characteristics of perovskite materials such as wide band gap, high absorption coefficient and high carrier mobility, as well as the advantages of crystalline silicon materials such as good stability and excellent electron transport performance, the photoelectric conversion efficiency of solar cells can be improved. However, in practical applications, although the photoelectric conversion efficiency of crystalline silicon / perovskite laminated solar cells has broken through 34%, such cells still lack support from actual power generation data, and their long-term stability is much worse than that of crystalline silicon cells, which is a challenge that needs to be addressed. Optimizing the overall cell structure is one of the key directions to improve the photoelectric performance and stability of laminated solar cells.

[0004] Currently, the preparation of most crystalline silicon / perovskite laminated solar cells still relies on polished crystalline silicon bottom cells, mainly because existing perovskite high-efficiency film formation processes such as solution method are mainly suitable for flat substrates, and mature solutions for non-flat substrates have not yet been formed. However, this approach has significant contradictions: on the one hand, existing commercial crystalline silicon cells generally use a textured surface structure to significantly reduce the reflectivity of incident light through light trapping effects, significantly improving light absorption efficiency; on the other hand, laminated structures based on polished crystalline silicon bottom cells generally lack this light absorption optimization design, resulting in severe light absorption loss, which leads to low short-circuit current density of the device and makes it difficult to break through the performance bottleneck. In addition, the design of the intermediate tunneling layer of existing crystalline silicon / perovskite laminated cells also has obvious defects, including insufficient light transmission leading to light loss and lateral conduction causing non-radiative recombination loss, which directly leads to a decrease in open-circuit voltage and fill factor, ultimately resulting in a loss of 2-3 percentage points in photoelectric conversion efficiency.

[0005] Therefore, it is necessary to design a new structure to improve the performance of the crystalline silicon / Perovskite tandem solar cell, develop a Perovskite film forming technology suitable for the textured crystalline silicon substrate, and optimize the design of the intermediate tunneling layer to reduce light loss and non-radiative recombination loss, thereby significantly improving the photoelectric performance and stability of the tandem solar cell. SUMMARY

[0006] The present application aims to overcome the defects of the prior art and provide a Perovskite crystalline silicon tandem cell structure and a preparation method thereof.

[0007] To solve the above technical problems, the present application aims to achieve the following technical solutions: a Perovskite crystalline silicon tandem cell structure is provided, which comprises a crystalline silicon bottom cell, a nano tunneling layer, and a Perovskite top cell arranged in sequence from bottom to top, wherein the nano tunneling layer is a non-full-coverage structure.

[0008] Further technical solutions are that the material of the nano tunneling layer is transparent conductive oxide nanoparticles, the transparent conductive oxide nanoparticles include at least one of indium tin oxide, zinc aluminum oxide, indium zinc oxide, tungsten indium oxide, and cadmium indium oxide, and the dispersion particle size is 5nm to 2000nm.

[0009] Further technical solutions are that the crystalline silicon bottom cell comprises a first metal electrode layer, a first transparent electrode layer, a P-type base doping layer, a base passivation layer, a silicon substrate, a base surface passivation layer, and an N-type base doping layer arranged in sequence from bottom to top.

[0010] Further technical solutions are that the Perovskite top cell comprises a hole transport layer, a Perovskite absorption layer, a passivation layer, an electron transport layer, a buffer layer, a second transparent electrode layer, a second metal electrode layer, and an anti-reflection layer arranged in sequence from bottom to top.

[0011] The present application also provides a preparation method of the above-mentioned Perovskite crystalline silicon tandem cell structure, and the manufacturing method of the nano tunneling layer comprises: coating a nano tunneling layer dispersion liquid on the crystalline silicon bottom cell to form a nano tunneling layer.

[0012] Further technical solutions are that the nano tunneling layer dispersion liquid is obtained by dissolving the material of the nano tunneling layer in a solvent and ultrasonic dissolution.

[0013] Further technical solutions are that the concentration of the nano tunneling layer dispersion liquid is 0.05mg / ml~5mg / ml, and the ultrasonic time is 10min~30min.

[0014] A further technical solution thereof is that the nano-tunneling layer is prepared by a spin coating method, comprising: coating the nano-tunneling layer dispersion liquid on the crystalline silicon bottom cell, and performing annealing operation; the spin coating rotation speed is set to 1000 rpm-6000 rpm, and the spin coating time is 25 s-100 s; the annealing temperature is 50-200 DEG C, and the annealing time is 5-40 min.

[0015] A further technical solution thereof is that the nano-tunneling layer is prepared by a spray coating method, comprising: coating the nano-tunneling layer dispersion liquid on the crystalline silicon bottom cell, and performing annealing operation; the spray coating rate is 1-80 cm / s, the annealing temperature is 0-150 DEG C, and the annealing time is 0-30 min.

[0016] A further technical solution thereof is that the preparation method of the crystalline silicon bottom cell comprises: A silicon substrate is provided, the surface of the crystalline silicon bottom cell has a textured structure, and the silicon substrate comprises a first surface and a second surface arranged oppositely; A base surface passivation layer and an N-type base doping layer are sequentially and layerwisely arranged on the first surface of the silicon substrate; A base passivation layer, a P-type base doping layer, a first transparent electrode layer and a first metal electrode layer are sequentially and layerwisely arranged on the second surface of the silicon substrate; A further technical solution thereof is that the preparation method of the perovskite top cell comprises: A hole transport layer, a perovskite absorption layer, a passivation layer, an electron transport layer, a buffer layer, a second transparent electrode layer, a second metal electrode layer and an anti-reflection layer are sequentially and layerwisely arranged on the side of the nano-tunneling layer away from the N-type base doping layer.

[0017] The beneficial effects of the present application compared with the prior art are that: the present application adopts a multilayer structure arranged from bottom to top in a crystalline silicon / perovskite laminated solar cell, comprising a crystalline silicon bottom cell, a nano-tunneling layer and a perovskite top cell arranged from bottom to top in sequence, in particular, the nano-tunneling layer is a non-full-coverage structure, which realizes effective adaptation to the textured crystalline silicon substrate. This design not only promotes high-quality film formation of the perovskite thin film and reduces light loss, but also optimizes the design of the intermediate tunneling layer, effectively cuts off the horizontal leakage current path and reduces the non-radiative recombination loss. These improvements work together to significantly improve the photoelectric conversion efficiency and stability of the laminated solar cell, and the photoelectric performance reaches a new height.

[0018] The present application will be further described below in conjunction with the drawings and specific embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed in the embodiment description. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without any creative effort.

[0020] Figure 1 A schematic diagram of a perovskite crystalline silicon stacked cell structure provided by the prior art is shown in the figure. Figure 2 A schematic diagram of a perovskite crystalline silicon stacked cell structure provided by the embodiment of the present application is shown in the figure. Figure 3 A schematic diagram of a preparation method of a perovskite crystalline silicon stacked cell structure provided by the embodiment of the present application is shown in the figure. Identification in the figure: 110, first metal electrode layer; 111, first transparent electrode layer; 112, P-type base doping layer; 113, base passivation layer; 114, silicon substrate; 115, base surface passivation layer; 116, N-type base doping layer; 117, nano tunneling layer; 118, full-coverage tunneling layer; 210, hole transport layer; 211, perovskite absorption layer; 212, passivation layer; 213, electron transport layer; 214, buffer layer; 215, second transparent electrode layer; 216, second metal electrode layer; 217, anti-reflection layer. DETAILED DESCRIPTION

[0021] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without any creative effort belong to the scope of protection of the present application.

[0022] It should be understood that, when used in the specification and the appended claims, the terms "comprise" and "include" indicate the presence of described features, integers, steps, operations, elements, and / or components, but do not exclude one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0023] It should also be understood that the terms used in the present application specification are only for the purpose of describing specific embodiments and are not intended to limit the present application. As used in the present application specification and the appended claims, the singular forms "a", "an" and "the" are intended to include the plural forms unless the context clearly indicates otherwise.

[0024] It should be further understood that the term "and / or" as used in the specification and in the claims, if any, means any one and / or all possible combinations of one or more of the associated listed items.

[0025] In the field of solar photovoltaic technology, perovskite / silicon tandem cells have become a research hotspot for improving solar energy utilization efficiency due to their theoretical photoelectric conversion efficiency of over 40%. This technology combines the wide band gap and high absorption coefficient characteristics of perovskite materials with the stability and excellent electron transport performance of silicon materials to construct a heterojunction structure to enhance photoelectric conversion efficiency. However, despite laboratory efficiencies exceeding 34%, such cells still face challenges in practical applications, such as poor long-term stability, lack of supporting measured data, and imperfect manufacturing processes. In particular, the current preparation process relies on polished rather than textured silicon bottom cells, resulting in significant light absorption loss. Defects in the design of the intermediate tunneling layer further limit the open-circuit voltage and fill factor, affecting the overall photoelectric conversion efficiency. Optimizing the cell structure, particularly improving the film formation process and tunneling layer design, is a key direction for improving the performance and stability of tandem solar cells.

[0026] To this end, embodiments of the present application provide a perovskite / silicon tandem cell structure to improve the performance of silicon / perovskite tandem solar cells, develop perovskite film formation technology suitable for textured silicon substrates, and optimize the design of the intermediate tunneling layer to reduce light loss and non-radiative recombination loss, significantly improving the photoelectric performance and stability of tandem solar cells.

[0027] Specifically, by introducing a non-full-coverage textured semi-filled tunneling layer structure and optimizing the materials and preparation processes of each layer, the aim is to improve the photoelectric performance and stability of silicon / perovskite tandem solar cells. Specific measures include using specific materials (such as transparent conductive oxide nanoparticle solution, PTAA, etc.) and processes (such as magnetron sputtering, evaporation, spin coating flash evaporation, etc.) to manufacture key components such as the hole transport layer 210, the nanometer tunneling layer 117, and the perovskite absorber layer 211. In particular, film formation technology suitable for the surface characteristics of textured silicon substrates is developed, effectively reducing light loss and non-radiative recombination loss, thereby significantly improving the photoelectric conversion efficiency and long-term stability of tandem solar cells. In addition, atomic layer deposition technology and the use of magnesium fluoride as an anti-reflection layer 217 further optimize cell performance.

[0028] In order to better understand the above technical solutions, the above technical solutions will be described in detail below in conjunction with the drawings in the specification and specific embodiments.

[0029] Please refer to Figure 2A perovskite crystalline silicon tandem cell structure, comprising a crystalline silicon bottom cell, a nano-tunneling layer 117 and a perovskite top cell arranged sequentially from bottom to top, wherein the nano-tunneling layer 117 is a non-full-coverage structure.

[0030] The non-full-coverage structure refers to a structure in which nanoparticles are filled on the textured surface of the crystalline silicon bottom cell.

[0031] The surface of the crystalline silicon bottom cell has a textured structure, comprising a first metal electrode layer 110, a first transparent electrode layer 111, a P-type base doping layer 112, a base passivation layer 113, a silicon substrate 114, a base surface passivation layer 115, and an N-type base doping layer 116 arranged sequentially from bottom to top; in this embodiment, the silicon substrate 114 is a textured silicon substrate, so that each film layer of the crystalline silicon bottom cell formed thereon has a textured structure.

[0032] The perovskite top cell comprises a hole transport layer 210, a perovskite absorption layer 211, a passivation layer 212, an electron transport layer 213, a buffer layer 214, a second transparent electrode layer 215, a second metal electrode layer 216, and an anti-reflection layer 217 arranged sequentially from bottom to top.

[0033] The first metal electrode layer 110 is usually made of a material with good electrical conductivity, such as silver (Ag), aluminum (Al), etc., as a current collecting layer.

[0034] The first transparent electrode layer 111 is made of ITO or similar transparent conductive oxide prepared by magnetron sputtering method, which ensures that light can effectively penetrate while providing good electrical performance.

[0035] The P-type base doping layer 112 is one of the bases for forming a p-n junction, which enhances the carrier separation efficiency.

[0036] The base passivation layer 113 reduces surface state defects and improves carrier lifetime.

[0037] The silicon substrate is a textured silicon substrate, and the textured design increases the light trapping efficiency, which helps to improve the overall photoelectric conversion efficiency.

[0038] The base surface passivation layer 115 further optimizes the surface quality and reduces non-radiative recombination loss.

[0039] The N-type base doping layer 116 and the P-type base doping layer 112 together form an efficient p-n junction.

[0040] The nano-tunneling layer 117 is particularly characterized by using nanoparticles to fill the textured surface of the crystalline silicon bottom cell, forming a non-full-coverage structure, and such a non-continuous coverage surface can improve the coverage integrity and thin film stability of the upper film layer prepared thereon, improve the interface transmission efficiency, and on the other hand, the non-continuous coverage structure has high light transmittance and lateral insulation characteristics, significantly reducing light loss and non-radiative recombination loss.

[0041] The hole transport layer 210 uses UV-ozone treated PTAA or other suitable materials to promote effective transmission of holes.

[0042] The perovskite absorption layer 211 is prepared by spin-coating flash evaporation method, and is a key component for efficient absorption of sunlight.

[0043] The passivation layer 212 can be selected from materials such as propylene diamine iodine, which plays a protective and passivation role, prevents degradation and improves stability.

[0044] The electron transport layer 213, such as ZnO or C 60 , is responsible for the rapid transmission of electrons.

[0045] The buffer layer 214, for example SnO2, further optimizes the interface characteristics and improves the device performance.

[0046] The second transparent electrode layer 215 again uses transparent conductive materials to ensure light transmission while collecting current.

[0047] The second metal electrode layer 216 is the final current collection layer, similar to the first metal electrode layer 110.

[0048] The anti-reflection layer 217 is the outermost layer, which uses materials such as magnesium fluoride to reduce light reflection and increase light absorption.

[0049] This structure design particularly focuses on solving the problem of film formation on the textured crystalline silicon substrate in traditional technology, and optimizes the design of the tunneling layer to achieve higher photoelectric conversion efficiency and better stability. The data of the embodiment shows that the nano-tunneling layer 117 prepared with a specific concentration can significantly improve the short-circuit current density, open-circuit voltage and final photoelectric conversion efficiency, providing solid technical support for the commercialization of high-efficiency stacked cells.

[0050] Comparing Figure 1 and Figure 2 It can be seen that traditional devices such as Figure 1As shown, 118 is actually a common tunneling layer, which belongs to the full-coverage tunneling layer 118; therefore, the conventional device is limited by the technical solution and cannot realize effective perovskite film formation on the textured silicon substrate. The structure of the embodiment successfully solves the problem of textured film formation and can stably prepare devices on the textured substrate, which solves the core bottleneck that the traditional technology cannot adapt to commercialized textured silicon cells from the source, and lays the foundation for the compatible industrialization of laminated cells and existing silicon industry.

[0051] Specifically, the material of the nano-tunneling layer 117 uses transparent conductive oxide nanoparticles, specifically including but not limited to: Indium Tin Oxide (ITO); Aluminum-doped Zinc Oxide (AZO); Indium Zinc Oxide (IZO); Indium Tungsten Oxide (IWO); Indium Cadmium Oxide (ICO); The dispersion particle size of these materials is between 5 to 2000 nanometers, which ensures good transparency and conductivity.

[0052] In an embodiment, referring to Figure 2 The material of the hole transport layer 210 is at least one of PTAA, poly-3-hexylthiophene, nickel oxide, molybdenum trioxide, cuprous iodide, and cuprous thiocyanate.

[0053] The hole transport layer 210 can use at least one of the following materials: Poly[bis (4-phenyl) (2, 4, 6-trimethylphenyl) amine] (PTAA); Poly-3-hexylthiophene (P3HT); Nickel oxide (NiOx); Molybdenum trioxide (MoO3); Cuprous iodide (CuI); Cuprous thiocyanate (CuSCN); These materials can effectively promote the migration of holes from the perovskite absorber layer 211 to the electrode.

[0054] In the ABX3 structure perovskite: A site is an organic cation, including but not limited to methylamine (CH3NH3 + or MA + ), formamidine (NH2CH=NH2 + or FA +ethylamine (CH3CH2NH3 + ) or cesium (Cs + ).

[0055] B site is a metal cation, mainly including lead (Pb 2+ ) and tin (Sn 2+ ).

[0056] X site is a halogen anion, including fluorine (F - ), chlorine (Cl - ), bromine (Br - ) and iodine (I - ).

[0057] This combination provides a wide range of chemical adjustment space to optimize photoelectric performance.

[0058] In an embodiment, referring to Figure 2 , the passivation layer 212 can be selected from at least one of the following materials: propylenediamine iodine (PDAD-I), and other similar compounds such as propylenediamine bromine (PDADBr), butylamine chloride (BACl), butylamine bromide (BABr), butylamine iodide (BAI), N, N-dimethyl-1, 3-propylenediamine hydrochloride (DMePDADCl), and dodecamine bromine (DDDADBr).

[0059] Magnesium fluoride (MgF2) or lithium fluoride (LiF), sodium fluoride (NaF), etc. can also be selected.

[0060] These materials help reduce surface defects and improve device stability.

[0061] In addition, the solvents that can be used for the ammonium salt precursor solution include but are not limited to: ethanol; isopropanol; methanol; dimethylformamide (DMF); G-butyrolactone (GBL); dimethyl sulfoxide (DMSO); N, N-dimethylacetamide (DMA); the solvent ratio can be flexibly adjusted in the range of 0-3:10-7 to adapt to different preparation needs.

[0062] The electron transport layer 213 can be selected from at least one of the following materials: zinc oxide (ZnO); tin dioxide (SnO2); titanium dioxide (TiO2); [6, 6]-phenyl C61 butyric acid methyl ester (PC 61 BM); carbon 60 (C 60 ); 2, 9-dimethyl-4, 7-diphenyl-1, 10-phenanthroline (BCP); these materials have excellent electron transport performance, which helps to improve the overall efficiency.

[0063] The buffer layer 214 can also be made of at least one of the following materials, such as zinc oxide (ZnO), tin dioxide (SnO2), titanium dioxide (TiO2).

[0064] The second metal electrode layer 216 can be made of at least one of silver (Ag), gold (Au), copper (Cu), aluminum (Al), carbon (C), etc.

[0065] The anti-reflection layer 217 can be made of at least one of the following materials, such as magnesium fluoride (MgF2), lithium fluoride (LiF), sodium fluoride (NaF), silicon oxide (SiO2), etc. These materials can effectively reduce light reflection and increase light absorption.

[0066] The thickness of the hole transport layer 210, the perovskite absorption layer 211, the electron transport layer 213, the second transparent electrode layer 215, the second metal electrode layer 216, and the anti-reflection layer 217 is generally set to be between 1 and 600 nanometers.

[0067] The thickness of the buffer layer 214 can be adjusted in the range of 0 to 30 nanometers. It is not only suitable for the current design of the stacked solar cell, but also suitable for the single-junction perovskite solar cell in the forward and reverse directions. Such a wide range of applications increases the value and practicality of this technical solution.

[0068] In this embodiment, the entire structure is prepared as follows: The substrate passivation layer 113 is prepared on the back of the silicon substrate 114, the P-type substrate doped layer 112 is prepared on the surface of the substrate passivation layer 113, the first transparent electrode layer 111 is prepared on the surface of the P-type substrate doped layer 112, the first metal electrode layer 110 is prepared on the surface of the first transparent electrode layer 111, the substrate surface passivation layer 115 is prepared on the surface of the silicon substrate, the N-type substrate doped layer 116 is prepared on the surface of the substrate surface passivation layer 115, the nanometer tunneling layer 117 is prepared on the surface of the tunneling layer, the hole transport layer 210 is prepared on the surface of the tunneling layer, the perovskite absorption layer 211 is prepared on the surface of the hole transport layer 210, the passivation layer 212 is prepared on the surface of the perovskite absorption layer 211, the electron transport layer 213 is prepared on the surface of the passivation layer 212, the buffer layer 214 is prepared on the surface of the electron transport layer 213, the second transparent electrode layer 215 is prepared on the buffer layer 214, the second metal electrode layer 216 is prepared on the surface of the second transparent electrode layer 215, and the anti-reflection layer 217 is prepared on the surface of the second metal electrode layer 216.

[0069] Specifically, the first transparent electrode layer 111 is prepared by a magnetron sputtering method.

[0070] The first metal electrode layer 110 is prepared by an evaporation method.

[0071] The nano-tunneling layer 117 is prepared by solution film forming methods such as spin coating, blade coating, and spraying; The nano-tunneling layer 117 can be prepared by a spin coating method or a spraying method. In the spin coating method, a nano-tunneling layer 117 dispersion liquid is prepared and ultrasonically dissolved. The concentration of the nano-tunneling layer 117 dispersion liquid is 0.05-5 mg / ml, and the ultrasonic time is 10-30 min. Then, spin coating is performed at a rotation speed of 1000-6000 rpm for 25-100 s. After spin coating, annealing is performed at a temperature of 50-200℃ for 5-40 min. In the spraying method, the nano-tunneling layer 117 dispersion liquid is sprayed on the surface of the substrate at a spraying rate of 1-80 cm / s. After spraying, annealing is performed at a temperature of 0-150℃ for 0-30 min. The hole transport layer 210 is treated by a UV-ozone machine (UV-Ozone) for 0-30 min before being prepared; The hole transport layer 210 can also be prepared by a magnetron sputtering method. Specifically, the prepared substrate is placed in a magnetron sputtering device, and the power is controlled to be 30-90 W. The hole transport layer 210 is prepared by a spin coating method or a magnetron sputtering method; The perovskite absorption layer 211 is prepared by a solution wet method; In the spin flash method, perovskite precursor liquid is prepared, and the perovskite precursor liquid is uniformly coated on the surface of the hole transport layer 210 at a rotation speed of 1000-6000 rpm for 20-120 s. After spin coating, flash evaporation is performed for 10-60 s at a temperature of 0-100℃. After flash evaporation, annealing is performed at a temperature of 50-150℃ for 5-40 min. The passivation layer 212 is prepared by an evaporation method, a spin coating method, or a spraying method; In the evaporation method, propylene diamine iodine is evaporated onto the surface of the perovskite absorption layer 211 at a vacuum degree of 1-5×10 -4 Pa, an evaporation rate of 0.05-1 Å / S, and an evaporation temperature of 50-400℃. After evaporation, annealing is performed at a temperature of 0-150℃ for 0-30 min. And / or, the passivation layer 212 can also be prepared by spin coating, specifically, a passivation layer 212 dispersion liquid is prepared and uniformly coated on the surface of the perovskite absorption layer 211, propylene diamine iodine is dissolved in an organic solvent including but not limited to methanol, ethanol or isopropanol, ultrasonic dissolution is performed and spin coating is performed, the propylene diamine iodine concentration is 0.1-6 mg / ml, the ultrasonic time is 0-30 min, the spin coating rotation speed is 1000-7000 rpm, and the spin coating time is 20-120 s. After spin coating, annealing is performed, the annealing temperature is 40-160℃, and the annealing time is 5-40 min; And / or, the passivation layer 212 can also be prepared by spray coating, specifically, a passivation layer 212 dispersion liquid is sprayed on the perovskite absorption layer 211, the spray rate is 0-100 cm / s, and after the spray coating, annealing is performed, the annealing temperature is 20-170℃, and the annealing time is 0-30 min; The electron transport layer 213 is prepared by spin coating, inkjet or evaporation; The spin coating method is used for the electron transport layer 213, specifically, an electron transport layer 213 dispersion liquid is uniformly coated on the surface of the passivation layer 212, the spin coating rotation speed is 500-4000 rpm, and the spin coating time is 10-80 s; And / or, the electron transport layer 213 can also be prepared by evaporation, specifically, the electron transport layer 213 material is evaporated to the surface of the passivation layer 212, the evaporation vacuum degree is 5×10 -5 -5×10 -4 Pa, the evaporation temperature is 100-400℃, and the evaporation rate is 0.05-1 Å / S; The buffer layer 214 is prepared by atomic layer deposition and plasma treatment; The atomic layer deposition method is used for the buffer layer 214, specifically, the buffer layer 214 material is deposited to the surface of the electron transport layer 213 by using an atomic layer deposition device, the deposition vacuum degree is 0-1×10 4 Pa, the deposition pipeline temperature is 50-150℃, and the deposition chamber temperature is 40-150℃.

[0072] The plasma treatment method, specifically, the sample with the prepared electron transport layer 213 is placed in a magnetron sputtering device, the power is controlled to be 30-300 W, the working gas is a mixed gas of argon and oxygen, the gas flow is controlled to be 5-50 sccm, the gas ratio is controlled to be 280:1 to 1:1, the substrate temperature is controlled to be 25-80 degrees, and the control time is 1-30 min.

[0073] The second transparent electrode layer 215 is prepared by magnetron sputtering or evaporation; The second transparent electrode layer 215 is prepared by a magnetron sputtering method, specifically, the transparent electrode material is sputtered to the surface of the buffer layer 214, and the power is controlled to be 30-200 W; Alternatively, the second transparent electrode layer 215 can also be prepared by an evaporation method, specifically, the transparent electrode material is evaporated to the surface of the buffer layer 214, the evaporation vacuum degree is 1x10 -5 -5x10 -4 Pa, the evaporation temperature is 1000-2000℃, and the evaporation rate is 0.05-3 Å / S; The second metal electrode layer 216 is prepared by an evaporation method; The evaporation method for preparing the second metal electrode layer 216 is similar to that for preparing the first metal electrode layer 110, except that the mask plate is different; The antireflection layer 217 is prepared by a magnetron sputtering method or an evaporation method; The magnetron sputtering method for preparing the antireflection layer 217 is similar to that for preparing the second transparent electrode layer 215; The evaporation method for preparing the antireflection layer 217 is similar to that for preparing the passivation layer 212, and the evaporation rate is 0-5 Å / S.

[0074] The light transmittance of the traditional tunneling layer is only 89%, resulting in a large amount of incident light being blocked, which affects the light absorption efficiency. However, the light transmittance of the perovskite-silicon tandem cell in the embodiment is significantly improved to 91%-95%, and the light transmittance of the embodiment 2 reaches 95%, which is 6 percentage points higher than that of the traditional device. Higher light transmittance means that more light can penetrate the tunneling layer and reach the crystalline silicon and perovskite absorption layer 211, thereby laying a foundation for the improvement of short-circuit current.

[0075] The sheet resistance of the tunneling layer of the traditional device is 300Ω, which shows obvious lateral conduction ability, which is easy to cause electron-hole recombination and reduce energy conversion efficiency. However, in the embodiment, the sheet resistance of the nano tunneling layer 117 reaches infinity, realizing complete lateral insulation and completely cutting off the lateral current path, fundamentally solving the problem of lateral leakage, reducing non-radiative recombination loss, and being beneficial to the substantial improvement of open-circuit voltage and fill factor.

[0076] The open-circuit voltage of the traditional device is only 1.61V, while in the embodiment, the open-circuit voltage is stabilized at 1.96V by optimizing the design of the nano tunneling layer 117, which is 0.35V higher than that of the traditional device, with an increase of 21.7%. This improvement is mainly due to the lateral insulation characteristics of the nano tunneling layer 117, which effectively reduces the carrier recombination loss and enhances the electric potential inside the device.

[0077] The short-circuit current density of the traditional device is only 19.2 mA / cm², while in this embodiment, the value is increased to 20.4-20.8 mA / cm², with a maximum increase of 8.3%. This is not only due to the increase in the light transmittance of the nano-tunneling layer 117, but also because of the use of the textured substrate design, which further reduces light reflection and increases the number of photo-generated carriers.

[0078] The photoelectric conversion efficiency of the traditional device is only 21.5%, which is at a low level in the industry. However, through the technical improvement of the embodiment, the photoelectric conversion efficiency has broken through 30% comprehensively, with excellent efficiency stability (31.9%-32.8%), fully demonstrating the reliability and advancement of its technical scheme, and providing strong support for the commercialization of high-efficiency stacked cells.

[0079] In this embodiment, the nano-tunneling layer 117 is prepared on the surface of the textured silicon substrate using the nanoparticle solution method, finally forming a non-full-coverage textured semi-filling tunneling layer structure with unique structural characteristics. This innovative structure breaks through the technical bottleneck in the preparation of traditional stacked cells, significantly improving the overall performance of the device, with the following specific advantages: This structure can effectively reduce the height difference of the textured substrate surface, so that the subsequent perovskite film prepared by the solution wet process can completely and uniformly cover the textured structure. The problem of film fracture or local thinning caused by substrate undulation is avoided, thereby fundamentally eliminating the risk of device short circuit. Through this structural design, the preparation yield of the perovskite film can be greatly improved, ensuring the stability and reliability of the device.

[0080] The nano-tunneling layer 117 in this structure has a lateral non-conducting characteristic, which can precisely limit the lateral transmission path of the carriers. By limiting the lateral movement of carriers in the inactive area, the invalid recombination of carriers is reduced, significantly reducing the non-radiative recombination loss of the device. Due to the reduction of non-radiative recombination loss, the carrier collection efficiency is significantly improved, further enhancing the overall performance of the device.

[0081] Since the nano-tunneling layer 117 adopts a non-full-coverage design, compared to the traditional full-coverage tunneling layer, the area of light blocking is greatly reduced. More incident light can penetrate the nano-tunneling layer 117 to reach the underlying crystalline silicon absorber layer, with significantly improved light transmittance. More incident light means stronger photo-generated carrier generation capability, thereby optimizing the photoelectric conversion performance of the device. By improving the light transmittance, not only the photoelectric conversion performance of the device is optimized, but also support is provided for the improvement of other key parameters such as open-circuit voltage and short-circuit current density.

[0082] In summary, the structure of the present embodiment has significant advantages in solving the problems of perovskite film coverage and short circuit, reducing non-radiative recombination loss, and improving light transmittance, etc. through the design of non-full coverage and semi-filling of the textured surface. This innovation not only breaks through the technical bottleneck of traditional stacked cell preparation, but also provides a solid technical foundation for the commercialization of high-efficiency stacked cells.

[0083] The perovskite crystalline silicon stacked cell structure described above adopts a multi-layer structure arranged from bottom to top in a crystalline silicon / perovskite stacked solar cell, including a crystalline silicon bottom cell, a nano-tunneling layer 117, and a perovskite top cell arranged in order from bottom to top. In particular, the nano-tunneling layer 117 is a non-full coverage structure, which effectively adapts to the textured crystalline silicon substrate. This design not only promotes high-quality film formation of the perovskite thin film and reduces light loss, but also optimizes the design of the intermediate tunneling layer, effectively cutting off the horizontal leakage current path and reducing non-radiative recombination loss. These improvements work together to significantly improve the photoelectric conversion efficiency and stability of the stacked solar cell, bringing its photoelectric performance to a new level.

[0084] In an embodiment, referring to Figure 3 The preparation method of the perovskite crystalline silicon stacked cell structure described above includes steps S110-S220.

[0085] S110, providing a silicon substrate 114, the surface of the crystalline silicon bottom cell has a textured structure, the silicon substrate 114 includes a first surface and a second surface arranged opposite to each other; S120, making a base surface passivation layer 115 and an N-type base doping layer 116 arranged in order and stacked on the first surface of the silicon substrate 114.

[0086] S130, making a base passivation layer 113, a P-type base doping layer 112, a first transparent electrode layer 111, and a first metal electrode layer 110 arranged in order and stacked on the second surface of the silicon substrate 114. S140, making a nano-tunneling layer 117 on the side of the N-type base doping layer 116 away from the silicon substrate.

[0087] The method for making the nano-tunneling layer 117 includes: applying a nano-tunneling layer 117 dispersion liquid on the crystalline silicon bottom cell to form the nano-tunneling layer 117. The nano-tunneling layer 117 dispersion liquid is obtained by dissolving the material of the nano-tunneling layer 117 in a solvent and ultrasonic dissolution. The concentration of the nano-tunneling layer 117 dispersion liquid is 0.05 mg / ml-5 mg / ml, and the ultrasonic time is 10 min-30 min.

[0088] In the embodiment, the nano-tunneling layer 117 is prepared by spin coating, including: coating the nano-tunneling layer 117 dispersion liquid on the crystalline silicon bottom cell, and performing annealing operation; the spin coating speed is set to 1000 rpm-6000 rpm, and the spin coating time is 25 s-100 s; the annealing temperature is 50-200℃, and the annealing time is 5-40 min.

[0089] Alternatively, the nano-tunneling layer 117 is prepared by spraying, including: coating the nano-tunneling layer 117 dispersion liquid on the crystalline silicon bottom cell, and performing annealing operation; the spraying speed is 1-80 cm / s, the annealing temperature is 0-150℃, and the annealing time is 0-30 min.

[0090] Specifically, when the spin coating method is used, the nano-tunneling layer 117 dispersion liquid is prepared, ultrasonic dissolution is performed, and after the spin coating is completed, annealing operation is performed; the concentration of the nano-tunneling layer 117 dispersion liquid is 0.05 mg / ml-5 mg / ml, and the ultrasonic time is 10 min-30 min. The spin coating speed is set to 1000 rpm-6000 rpm, and the spin coating time is 25 s-100 s. The annealing temperature is 50-200℃, and the annealing time is 5-40 min.

[0091] Or, When the spraying method is used, the nano-tunneling layer 117 dispersion liquid is prepared, the nano-tunneling layer 117 dispersion liquid is sprayed on the surface of the substrate, and after the spraying is completed, annealing operation is performed. The spraying speed is 1-80 cm / s, the annealing temperature is 0-150℃, and the annealing time is 0-30 min.

[0092] Specifically, when the spin coating method is used, the nano-tunneling layer 117 dispersion liquid is prepared, ultrasonic dissolution is performed, and after the spin coating is completed, annealing operation is performed; the concentration of the nano-tunneling layer 117 dispersion liquid is 0.05 mg / ml-5 mg / ml, and the ultrasonic time is 10 min-30 min. The spin coating speed is set to 1000 rpm-6000 rpm, and the spin coating time is 25 s-100 s. The annealing temperature is 50-200℃, and the annealing time is 5-40 min. When the spraying method is used, the nano-tunneling layer 117 dispersion liquid is prepared, the nano-tunneling layer 117 dispersion liquid is sprayed on the surface of the substrate, and after the spraying is completed, annealing operation is performed. The spraying speed is 1-80 cm / s, the annealing temperature is 0-150℃, and the annealing time is 0-30 min.

[0093] In Example One, the tunneling layer is prepared on the surface of the N-type base doped layer; specifically, the sample is placed behind the mask plate in the magnetron sputtering device, the power is controlled to be 60 W, the running time is 1 h, and the film thickness is 40 nm. In the embodiment two, the nano ITO particle dispersion liquid is prepared, the ITO nano particles with a particle radius of 500 nm are dispersed in an isopropyl alcohol solution, and ultrasonic is performed; the dispersion liquid concentration is 3 mg / ml, the ultrasonic time is 10 min, spin coating is performed, the spin coating speed is set to 1000 rpm, the spin coating time is 25 s, after the spin coating is completed, annealing operation is performed, the annealing temperature is 100℃, and the annealing time is 10 min.

[0094] In the embodiment three, the nano ITO particle dispersion liquid is prepared, the ITO nano particles with a particle radius of 500 nm are dispersed in an isopropyl alcohol solution, and ultrasonic is performed; the dispersion liquid concentration is 5 mg / ml, the ultrasonic time is 10 min, spin coating is performed, the spin coating speed is set to 1000 rpm, the spin coating time is 25 s, after the spin coating is completed, annealing operation is performed, the annealing temperature is 100℃, and the annealing time is 10 min.

[0095] In the embodiment four, the nano ITO particle dispersion liquid is prepared, the ITO nano particles with a particle radius of 500 nm are dispersed in an isopropyl alcohol solution, and ultrasonic is performed; the dispersion liquid concentration is 1 mg / ml, the ultrasonic time is 10 min, spin coating is performed, the spin coating speed is set to 1000 rpm, the spin coating time is 25 s, after the spin coating is completed, annealing operation is performed, the annealing temperature is 100℃, and the annealing time is 10 min.

[0096] The specially designed nano tunneling layer 117 adopts a non-full coverage rough surface half-filled tunneling layer structure, which is helpful to form a stable perovskite film layer on the rough surface of the crystalline silicon substrate.

[0097] S150, a hole transport layer 210, a perovskite absorption layer 211, a passivation layer 212, an electron transport layer 213, a buffer layer 214, a second transparent electrode layer 215, a second metal electrode layer 216, and a reflection reduction layer 217 are sequentially stacked on the side of the nano tunneling layer 117 away from the N-type substrate doping layer.

[0098] In the embodiment, the above steps S110-S130 belong to the preparation method of the crystalline silicon bottom cell, and the step S150 belongs to the preparation method of the perovskite top cell.

[0099] In the embodiment, the hole transport layer 210 can also be prepared by a magnetron sputtering method, specifically, the prepared substrate is placed in a magnetron sputtering device, the power is controlled to be 30-90 W; The perovskite absorption layer 211 adopts a spin flash evaporation method, specifically, a perovskite precursor solution is prepared, the perovskite precursor solution is uniformly coated on the surface of the hole transport layer, the spin speed is 1000-6000 rpm, and the spin time is 20-120 s. After spin coating, flash evaporation is performed, the flash evaporation time is 10-60 s, the flash evaporation temperature is 0-100°C, after flash evaporation, annealing treatment is performed, the annealing temperature is 50-150°C, and the annealing time is 5-40 min; Alternatively, the perovskite absorption layer 211 adopts a spin flash evaporation method, specifically, a perovskite precursor solution is prepared, the perovskite precursor solution is uniformly coated on the surface of the hole transport layer, the spin speed is 1000-6000 rpm, and the spin time is 20-120 s. After spin coating, flash evaporation is performed, the flash evaporation time is 10-60 s, the flash evaporation temperature is 0-100°C. After flash evaporation, annealing treatment is performed, the annealing temperature is 50-150°C, and the annealing time is 5-40 min; The passivation layer 212 adopts an evaporation method, specifically, propylene diamine iodine is evaporated to the surface of the perovskite absorption layer, the evaporation vacuum degree is 1-5x10 -4 Pa, the evaporation temperature is 50-400°C, and the evaporation rate is 0.05-1 Å / S. After evaporation, annealing is performed, the annealing temperature is 0-150°C, and the annealing time is 0-30 min; Alternatively, the passivation layer 212 can also adopt a spin coating method, specifically, a passivation layer 212 dispersion solution is prepared and uniformly coated on the surface of the perovskite absorption layer, propylene diamine iodine is dissolved in an organic solvent including but not limited to methanol, ethanol or isopropanol, ultrasonic dissolution and spin coating are performed, the propylene diamine iodine concentration is 0.1-6 mg / ml, the ultrasonic time is 0-30 min, the spin speed is 1000-7000 rpm, and the spin time is 20-120 s. After spin coating, annealing is performed, the annealing temperature is 40-160°C, and the annealing time is 5-40 min; Alternatively, the passivation layer 212 can also adopt a spray coating method, specifically, a passivation layer 212 dispersion solution is sprayed on the perovskite absorption layer, the spray rate is 0-100 cm / s, after spray coating, annealing is performed, the annealing temperature is 20-170°C, and the annealing time is 0-30 min; The electron transport layer 213 adopts a spin coating method, specifically, an electron transport layer dispersion solution is uniformly coated on the surface of the passivation layer 212, the spin speed is 500-4000 rpm, and the spin time is 10-80 s; Alternatively, the electron transport layer 213 can also adopt an evaporation method, specifically, an electron transport layer material is evaporated to the surface of the passivation layer 212, the evaporation vacuum degree is 5x10 -5 -5x10 -4Pa, evaporation rate is 0.05-1 A / S, and evaporation temperature is 100-400°C; The atomic layer deposition method is used to deposit the buffer layer 214 on the surface of the electron transport layer 213. The deposition vacuum is 0-1*10 4 Pa, the deposition tube temperature is 50-150°C, and the deposition chamber temperature is 40-150°C.

[0100] Alternatively, the low-temperature plasma treatment method is used to prepare the buffer layer 214. Specifically, the sample with the prepared electron transport layer 213 is placed in a magnetron sputtering device. The power is controlled to be 30-300W, the working gas is a mixture of argon and oxygen, the gas flow is controlled to be 5-50sccm, the gas ratio is controlled to be 280:1 to 1:1, the substrate temperature is controlled to be 25-80°C, and the control time is 1-30min.

[0101] The magnetron sputtering method is used to prepare the second transparent electrode layer 215. Specifically, the transparent electrode material is sputtered on the surface of the buffer layer 214, and the power is controlled to be 30-200W; Alternatively, the evaporation method can also be used to prepare the second transparent electrode layer 215. Specifically, the transparent electrode material is evaporated on the surface of the buffer layer 214, and the evaporation vacuum is 1*10 -5 -5*10 -4 Pa, evaporation rate is 0.05-3 A / S, and evaporation temperature is 1000-2000°C; The evaporation method is used to prepare the second metal electrode layer 216, which is similar to the first metal electrode layer 110 except that the mask plate is different; The magnetron sputtering method is used to prepare the anti-reflective layer 217, which is similar to the second transparent electrode layer 215; Alternatively, the evaporation method is used to prepare the anti-reflective layer 217, which is similar to the passivation layer 212, and the evaporation rate is 0-5A / S.

[0102] First, the substrate passivation layer 113 and the P-type substrate doping layer 112 are prepared on the back of the silicon substrate. This step ensures that the silicon substrate has good electrical properties and provides the necessary foundation for the subsequent device structure.

[0103] Next, the magnetron sputtering method is used to prepare the first transparent electrode layer 111. The specific operation is as follows: The sample is placed in a magnetron sputtering device.

[0104] The ITO target material is set, and the power is controlled to be 60W.

[0105] The running time is 1.5 hours to form a layer film with a thickness of 100nm.

[0106] Then, the first metal electrode layer 110 is prepared by using an evaporation method: The substrate sample is placed on the mask and put into the evaporation chamber.

[0107] When the evaporation vacuum degree reaches 2x10 -4 Pa, evaporation is performed.

[0108] The evaporation voltage is adjusted to the evaporation temperature, and the evaporation rate is controlled to be 2.5 Å / S.

[0109] Silver is evaporated on the layer film, and the final thickness is 200 nm.

[0110] In the traditional method, the tunneling layer is mainly prepared on the surface of the N-type substrate doped layer 116, and the specific steps are as follows: The sample is placed on the mask and placed in the magnetron sputtering device.

[0111] The power is controlled to be 60 W, and the running time is 1 hour.

[0112] The finally formed tunneling layer has a thickness of 40 nm.

[0113] In order to prepare the hole transport layer 210, the sample needs to be treated by UV-Ozone for 15 minutes, and then the following steps are performed: The above prepared substrate is placed in the magnetron sputtering device.

[0114] The power is controlled to be 30 W, and the running time is 60 minutes.

[0115] The nickel oxide (NiOx) material is deposited on the surface of the substrate, and the thickness is controlled to be 40 nm.

[0116] The perovskite absorption layer 211 is prepared by using a spin flash method, and the specific process is as follows: Prepare the perovskite precursor solution, weigh the powder and dissolve it in 1 ml of DMF and DMSO solvent, the solvent ratio is 8:2, and the magnetic stirring time is 30 minutes.

[0117] The sample is placed on the spin coater base, the spin coater speed is set to 3500 rpm, the spin coating time is 30 seconds, and the perovskite precursor solution amount is 120 ul.

[0118] After spin coating, the sample is placed on the flash table, the flash time is set to 30 seconds, and the flash temperature is 30°C.

[0119] After flash, annealing treatment is performed, the annealing temperature is set to 100°C, and the annealing time is 15 minutes. The finally formed perovskite absorption layer 211 has a thickness of about 500 nm.

[0120] The passivation layer 212 is prepared by evaporation: 3 mg of propylene diamine iodine is weighed and placed in a crucible.

[0121] The substrate sample is placed on a mask plate and put into the evaporation chamber.

[0122] When the evaporation vacuum reaches 2x10 -4 Pa, evaporation is performed, and the evaporation voltage is adjusted to the evaporation temperature.

[0123] The evaporation rate is controlled to be 0.1 Å / S, and the propylene diamine iodine is evaporated to a thickness of 4 nm.

[0124] After the end, the annealing table temperature is set to 100°C, and an annealing operation of 8 minutes is performed.

[0125] The electron transport layer 213 is prepared by evaporation: The substrate sample is placed on a mask plate and put into the evaporation chamber.

[0126] When the evaporation vacuum reaches 1x10 -4 Pa, evaporation is performed, and the evaporation voltage is adjusted to the evaporation temperature.

[0127] The evaporation rate is controlled to be 0.1-0.15 Å / S, and the C60 is evaporated to a final thickness of 20 nm.

[0128] The buffer layer 214 is prepared by atomic layer deposition: The atomic layer deposition device is set to a vacuum of 0.5x10 4 Pa, the deposition pipe temperature is between 60°C, and the deposition chamber temperature is 70°C.

[0129] The SnO2 is evaporated to a thickness of 15 nm.

[0130] Similar to the preparation of the first transparent electrode layer 111, the specific steps are as follows: The IZO target material is set, and the power is controlled to be 50 W.

[0131] The running time is 1 hour, and the finally formed layer film thickness is 100 nm.

[0132] Similar to the preparation of the first metal electrode layer 110, but the mask plate is different, and the specific steps are as follows: The substrate sample is placed on a mask plate and put into the evaporation chamber.

[0133] When the evaporation vacuum reaches a proper value, evaporation is performed, and the evaporation voltage is adjusted to the evaporation temperature.

[0134] The evaporation rate is controlled to be 0.1 Å / S, and the propylene diamine iodine is evaporated to a thickness of 4 nm.

[0135] Finally, the anti-reflective layer 217 is prepared by evaporation, with the following steps: Similar to the preparation of the passivation layer 212, the evaporation rate is controlled at 2 Å / S.

[0136] Magnesium fluoride is evaporated onto the layer film, with a final thickness of 100 nm.

[0137] In Example Two, when preparing the nano-tunneling layer 117, ITO nanoparticles with a particle radius of 500 nm are first dispersed in isopropyl alcohol to form a dispersion with a concentration of 1 mg / ml. The dispersion is treated with ultrasonic waves for 10 minutes to ensure uniform dispersion. The spin coating speed is set to 1000 rpm for 25 seconds. After spin coating, annealing is performed at 100°C for 10 minutes.

[0138] Using a lower concentration of nano-ITO particle dispersion can reduce material consumption while ensuring the quality of the tunneling layer, reducing costs. Low concentration helps to avoid the problem of agglomeration caused by too high particle density, thereby maintaining good electrical performance. Other steps remain consistent with traditional practices.

[0139] In Example Three, when preparing the nano-tunneling layer 117, similar to Example Two, but the dispersion concentration is adjusted to 3 mg / ml, and ultrasonic treatment is also required for 10 minutes; the spin coating conditions remain unchanged, i.e., 1000 rpm for 25 seconds. Annealing is performed at 100°C for 10 minutes. Other steps remain consistent with traditional practices.

[0140] Increasing the concentration of nanoparticles in the dispersion can enhance the conductivity and stability of the tunneling layer; a moderate concentration balances the relationship between cost and performance, providing a cost-effective option.

[0141] In Example Four, when preparing the nano-tunneling layer 117, ITO nanoparticles with a particle radius of 500 nm are dispersed in isopropyl alcohol to form a dispersion with a concentration of 5 mg / ml, and treated with ultrasonic waves for 10 minutes to ensure uniformity. The spin coating parameters are set to 1000 rpm for 25 seconds. Annealing is performed at 100°C for 10 minutes. Other steps remain consistent with traditional practices.

[0142] High concentration of nanoparticles can significantly improve the thickness and density of the tunneling layer, further enhancing the efficiency of electron transport. The enhanced tunneling layer can effectively prevent interface defects and impurity diffusion, thereby improving the stability and efficiency of the overall device.

[0143] From Example Two to Example Four, as the concentration of the nano-tunneling layer 117 increases, the manufacturing cost will correspondingly rise, but at the same time, performance will also be improved.

[0144] For cost-sensitive application scenarios, embodiment two is a more suitable choice; for high-performance requirements, consider the enhanced performance provided in embodiment four.

[0145] Using a solar simulator, a standard solar intensity calibration was performed, and a long-term IV test was performed on the embodiment device with an area of 1.0 cm2. The starting voltage was set to 2V, the cutoff voltage was set to 0V, the range was set to 100mA, and the results were rounded to two decimal places. The test results are shown in Table 1.

[0146] Table 1. Test results Device Tunnel layer sheet resistance (Ω) Tunnel layer light transmittance (%) Device open circuit voltage (V) Device short circuit current (mA / cm 2 ])]] Device photoelectric conversion efficiency (%) Example One 300 89 1.61 19.2 21.5 Example Two ∞ 95 1.96 20.8 32.4 Example Three ∞ 93 1.96 20.7 32.8 Example Four ∞ 91 1.96 20.4 31.9 The conventional device is limited by the technical solution and cannot effectively form a perovskite film on a textured silicon substrate. This limits its application in commercial textured silicon cells and hinders the compatible industrialization process of stacked cells with existing silicon industry.

[0147] This embodiment successfully solves the problem of textured film formation and stably prepares devices on a textured substrate. It solves the core bottleneck of "not being able to adapt to commercial textured silicon cells" from the source, laying the foundation for the compatible industrialization of stacked cells with existing silicon industry.

[0148] The light transmittance of the tunneling layer of the conventional device is 89%, and a large amount of incident light is blocked by the tunneling layer, resulting in insufficient light absorption.

[0149] The light transmittance of the tunneling layer of the device of the present embodiment is greatly improved to 91%-95%. In particular, the light transmittance of embodiment two reaches 95%, which is 6 percentage points higher than that of the conventional device. Higher light transmittance allows more incident light to penetrate the tunneling layer to reach the crystalline silicon and perovskite absorption layer 211, providing key support for subsequent short-circuit current improvement.

[0150] The sheet resistance of the tunneling layer of the conventional device is 300Ω, which has obvious lateral conduction ability and is easy to cause electron-hole lateral ineffective recombination.

[0151] The sheet resistance of the tunneling layer of the present embodiment all reaches ∞ (i.e. lateral insulation), completely blocking the lateral current path, and eliminating the non-radiative recombination loss caused by lateral leakage from the structure, creating conditions for the jump of open-circuit voltage and fill factor.

[0152] The open-circuit voltage of the conventional device is only 1.61V. The open-circuit voltage of the present embodiment is stably 1.96V, which is 0.35V higher than that of the conventional device, with an increase of 21.7%. This improvement is due to the lateral insulation characteristics of the tunneling layer eliminating the leakage, greatly reducing the carrier recombination loss, and significantly enhancing the built-in potential of the device.

[0153] The short-circuit current density of the conventional device is only 19.2 mA / cm2. In the embodiment, it is increased to 20.4-20.8 mA / cm2, with a maximum increase of 8.3% (Example 2 compared with Example 1). This increase is due to the increased light absorption caused by the improved light transmittance of the tunneling layer, and the light trapping effect of the textured substrate, which further reduces light reflection and increases the amount of photo-generated carriers.

[0154] The photoelectric conversion efficiency of the conventional device is only 21.5%, which is at the low level in the industry. The efficiency of the embodiment is broken through 30% comprehensively, and the efficiencies of Examples 2-4 are 32.4%, 32.8% and 31.9% respectively. The highest efficiency (Example 3) is increased by 11.3 percentage points compared with the conventional device, with an increase of more than 52%, and the device efficiency stability of the embodiment is excellent (31.9%-32.8%), which fully proves the reliability and advancement of the technical scheme, and provides key technical support for the commercialization of high-efficiency stacked cells.

[0155] Comparative Examples 2-4, when the preparation concentration is 3 mg / mL (Example 3), have the best effect. This is reflected in that Example 3 has a higher photoelectric conversion efficiency than Examples 2-4.

[0156] Example 3 not only has the highest photoelectric conversion efficiency of 32.8%, but also performs well in other core performance parameters such as open-circuit voltage and short-circuit current density, which proves that the concentration of 3 mg / mL of the nano-tunneling layer 117 is the best choice.

[0157] In summary, the embodiment improves and optimizes the conventional technology in many aspects, especially in solving the film forming problem of the textured substrate, improving the light transmittance and lateral insulation of the tunneling layer, and improving the overall photoelectric performance of the device, which provides solid technical support for the commercialization of perovskite-silicon stacked cells.

[0158] The above preparation method realizes the goal of improving the performance of crystalline silicon / perovskite tandem solar cells through a series of precise steps. First, the passivation layer 212 and the doped layer are deposited on the silicon substrate in sequence, and the base surface passivation layer 115 and the N-type doped layer are formed on the surface to optimize the charge transport and reduce the load loss. Then, the transparent electrode and the metal electrode layer are prepared by using magnetron sputtering and evaporation technology, respectively, which provides a good conductivity and stability basis for the subsequent layers. In particular, for the textured crystalline silicon substrate, the tunneling layer is prepared by using spin coating or spraying method, and the nickel oxide is deposited as a hole transport layer 210 after UV-Ozone treatment, which ensures that the perovskite film can uniformly and completely cover the textured structure, effectively solves the short circuit problem in the traditional process and reduces the non-radiative recombination loss. Subsequently, the perovskite absorber layer 211 is prepared by using spin-coating flash method, and the light absorption efficiency and carrier collection efficiency are further optimized by designing the electron transport layer 213, the buffer layer 214 and the anti-reflection layer 217. The whole process not only develops a perovskite film forming technology suitable for the textured crystalline silicon substrate, but also reduces the light loss and non-radiative recombination loss by optimizing the design of the intermediate tunneling layer, which significantly improves the photoelectric conversion efficiency and long-term stability of the tandem solar cell.

[0159] The above is only a specific embodiment of the present application, but the protection scope of the present application is not limited thereto. Any skilled person in the art can easily think of various equivalent modifications or replacements within the technical range disclosed by the present application, and these modifications or replacements should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A perovskite crystalline silicon tandem cell structure, characterized by, The solar cell comprises a crystalline silicon bottom cell, a nano-tunneling layer and a perovskite top cell arranged in sequence from bottom to top, wherein the nano-tunneling layer is a non-full-coverage structure.

2. The perovskite crystalline silicon tandem cell structure of claim 1, wherein, The material of the nano-tunneling layer is transparent conductive oxide nanoparticles, which comprises at least one of indium tin oxide, zinc aluminum oxide, indium zinc oxide, tungsten indium oxide and cadmium indium oxide, and the dispersion particle size is 5-2000 nm.

3. The perovskite crystalline silicon tandem cell structure of claim 1 or 2, wherein, The crystalline silicon bottom cell comprises a first metal electrode layer, a first transparent electrode layer, a P-type base doping layer, a base passivation layer, a silicon substrate, a base surface passivation layer and an N-type base doping layer arranged in sequence from bottom to top.

4. The perovskite crystalline silicon tandem cell structure of claim 1 or 2, wherein, The perovskite top cell comprises a hole transport layer, a perovskite absorption layer, a passivation layer, an electron transport layer, a buffer layer, a second transparent electrode layer, a second metal electrode layer and an anti-reflection layer arranged in sequence from bottom to top.

5. A method of manufacturing a perovskite crystalline silicon tandem cell structure according to any one of claims 1 to 4, characterized in that, The method for manufacturing the nano-tunneling layer comprises: coating a nano-tunneling layer dispersion liquid on the crystalline silicon bottom cell to form the nano-tunneling layer.

6. The method of claim 5, wherein the perovskite crystalline silicon tandem cell structure is prepared by the steps of: The nano-tunneling layer dispersion liquid is obtained by dissolving the material of the nano-tunneling layer in a solvent and ultrasonic dissolution. ​ 7. The method for preparing the perovskite-silicon tandem solar cell structure according to claim 6, characterized in that, The concentration of the nano-tunneling layer dispersion liquid is 0.05 mg / ml-5 mg / ml, and the ultrasonic time is 10 min-30 min.

8. The method for preparing the perovskite-silicon tandem solar cell structure according to claim 7, characterized in that, The nano-tunneling layer is prepared by a spin coating method, which comprises: coating the nano-tunneling layer dispersion liquid on the crystalline silicon bottom cell and performing annealing operation; the spin coating speed is set to 1000 rpm-6000 rpm, and the spin coating time is 25 s-100 s; the annealing temperature is 50-200 ℃, and the annealing time is 5-40 min.

9. The method for preparing the perovskite-silicon tandem solar cell structure according to claim 7, characterized in that, The nano-tunneling layer is prepared by a spray coating method, which comprises: coating the nano-tunneling layer dispersion liquid on the crystalline silicon bottom cell and performing annealing operation; the spray coating speed is 1-80 cm / s, the annealing temperature is 0-150 ℃, and the annealing time is 0-30 min.

10. The method for preparing the perovskite-silicon tandem solar cell structure according to claim 5, characterized in that, The method for manufacturing the crystalline silicon bottom cell comprises: providing a silicon substrate, the surface of the crystalline silicon bottom cell has a textured structure, and the silicon substrate comprises a first surface and a second surface arranged oppositely; manufacturing a base surface passivation layer and an N-type base doping layer arranged in sequence on the first surface of the silicon substrate; manufacturing a base passivation layer, a P-type base doping layer, a first transparent electrode layer and a first metal electrode layer arranged in sequence on the second surface of the silicon substrate. The method for manufacturing the perovskite top cell comprises: manufacturing a hole transport layer, a perovskite absorption layer, a passivation layer, an electron transport layer, a buffer layer, a second transparent electrode layer, a second metal electrode layer and an anti-reflection layer arranged in sequence on the side of the nano-tunneling layer away from the N-type base doping layer.

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