Data processing method, apparatus and system

Abstract

Disclosed in embodiments of the present application are a data processing method, apparatus and system. Specifically, DQPSK mapping is performed on p first data streams having undergone RS encoding to obtain a plurality of DP-DQPSK signals, each DP-DQPSK signal comprising a DQPSK signal in a first polarization direction and a DQPSK signal in a second polarization direction. Compared with a cascade FEC transmission scheme, the embodiments of the present application do not need to perform cascade FEC encoding before DQPSK mapping, so that the plurality of DP-DQPSK signals to be sent have a lower bit rate and Baud rate. Therefore, the data processing method provided by the embodiments of the present application has the advantages of low complexity, low power consumption, low delay and the like, can be applied to multiple transmission scenarios, and is particularly suitable for coherent transmission scenarios of 800 Gbps or above (such as 1.6 Tbps) in the future.

Description

A data processing method, device and system

[0001] The present application claims priority from the Chinese patent application No. 202410509410.2 filed on April 25, 2024, and entitled "A data processing method, device and system", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the field of communication technology, and in particular to a data processing method, device and system. BACKGROUND

[0003] Under the continuous promotion of 5G, cloud computing, big data, artificial intelligence, etc., high-speed optical transmission networks are developing towards large capacity, packetization and intelligentization. Optical communication systems use the amplitude, phase, polarization or frequency of light waves to carry information.

[0004] Using forward error correction (FEC) to perform error correction coding on the transmitted data can solve transmission errors and recover the original data sent by the sending end from the received data. A cascaded FEC transmission scheme is currently proposed, in which a sending device and a sending processing module are connected through a connection unit interface. The sending device performs first FEC encoding on the data to be transmitted, and sends the first FEC encoded data to the sending processing module. The sending processing module performs second FEC encoding on the first FEC encoded data, and performs symbol mapping on the second FEC encoded bit sequence to generate a corresponding symbol sequence, and finally transmits the generated symbol sequence to the receiving end through an optical fiber. The second FEC encoding usually uses soft decision decoding, which has high complexity and power consumption. Furthermore, convolution interleaving is performed between the first FEC encoding and the second FEC encoding to improve the overall performance of the cascaded FEC scheme, which has high latency. The existing cascaded FEC encoding scheme cannot adapt to future 800Gbps or above (such as 1.6Tbps, etc.) coherent scenarios with low complexity, low power consumption and low latency, which is a problem that needs to be solved in the future. SUMMARY

[0005] The embodiments of the present application provide a data processing method, device and system. The embodiments have the advantages of low complexity, low power consumption and low latency, and can be applied to many transmission scenarios, especially suitable for future 800Gbps or above (such as 1.6Tbps, etc.) coherent transmission scenarios.

[0006] In a first aspect, an embodiment of the present application provides a data processing method. Specifically, first, p pieces of first data streams encoded by Reed-Solomon (RS) are acquired, p is a positive integer multiple of 4, and p is an integer power of 2. Then, differential quadrature phase shift keying (DQPSK) is performed on the p pieces of first data streams to obtain multiple pieces of dual-polarization (DP) DQPSK signals, each piece of DP-DQPSK signal including a DQPSK signal in a first polarization direction and a DQPSK signal in a second polarization direction.

[0007] It should be understood that for the concatenated FEC coding scheme using RS encoding for outer code, introducing inner code will cause the coding redundancy to be improved, and the required baud rate is higher, and the inner code uses soft decision decoding, which requires obtaining soft value information, resulting in higher overall power consumption of the concatenated FEC coding scheme. In this embodiment, the p pieces of first data streams encoded by RS are mapped to multiple pieces of DP-DQPSK signals by DQPSK, compared with the concatenated FEC coding scheme, the embodiment of the present application does not need to perform the concatenated FEC coding including the inner code before DQPSK mapping, reduces the coding redundancy caused by the inner code, so that the multiple pieces of DP-DQPSK signals to be sent have lower bit rate and baud rate. Since the present scheme does not need to perform inner code encoding, it naturally will not use soft decision decoding, and does not need to obtain soft value information, which is conducive to reducing the overall power consumption. Moreover, DQPSK modulation can better resist colored noise. Therefore, the data processing method provided by the embodiment of the present application has the advantages of low complexity, low power consumption, low latency, etc., and can be applied to many transmission scenarios, and is especially suitable for future 800 Gbps or more (such as 1.6 Tbps, etc.) coherent transmission scenarios.

[0008] In some possible embodiments, the DQPSK mapping of the p pieces of first data streams to obtain multiple pieces of DP-DQPSK signals includes: DQPSK mapping of the p pieces of first data streams to obtain q pieces of DP-DQPSK signals, q = p / 2 or q = p / 4. That is, it can be that every 2 pieces of first data streams are mapped to 1 piece of DP-DQPSK signal by DQPSK, or every 4 pieces of first data streams are mapped to 1 piece of DP-DQPSK signal by DQPSK, so that it can be applied to many different scenarios.

[0009] In some possible implementation manners, p = 8, q = p / 2 = 4; or p = 16, q = p / 4 = 4 or q = p / 2 = 8; or p = 32, q = p / 4 = 8. Here, multiple corresponding relationships of values of p and q are given, which expand the application scenarios of the scheme. It should be noted that for the scheme of obtaining q = 4 DP-DQPSK signals through DQPSK mapping, the baud rate of each DP-DQPSK signal is 106.25 G Baud. For the 1.6T direct detection scheme widely used in short-distance scenarios, PAM4 modulation is adopted, data is transmitted through 8 channels, and the baud rate is also 106.25 G Baud. That is, in the data processing method provided in the present application, part of the devices of the existing 1.6T direct detection scheme can be used, which has the advantage of low cost.

[0010] In some possible implementation manners, each a RS adjacent RS symbol in each first data stream is from a RS RS code word, a RS is greater than or equal to 4 and is an integer power of 2. For example, each 4 adjacent RS symbols in each first data stream are from 4 RS code words. Wherein, the code length of the RS code is counted in units of symbols, and the symbol in the RS code can be referred to as an RS symbol. For example, the RS code adopts RS(544, 514) code, which can also be referred to as KP4 code, and the code length of the RS code is 544 RS symbols, that is, the code word of the RS code includes 544 RS symbols, and one RS symbol includes 10 bits. Each 4 adjacent RS symbols in each first data stream are from 4 RS code words, p is a positive integer multiple of 4, and p is an integer power of 2, so as to have good anti-colored noise performance.

[0011] In some possible implementation manners, the p first data streams are obtained through Physical Media Attachment (PMA) processing based on symbol multiplexing from 16 second data streams, and the 16 second data streams are obtained through Physical coding sublayer (PCS) processing including RS encoding from service data to be sent. Here, a specific implementation manner of obtaining the p first data streams through data processing on the service data to be sent is provided, which improves the integrity of the scheme. For example, the bit rate of the data stream after 1.6T PCS processing is 1700G bits per second. After DQPSK mapping, 4 DP-DQPSK signals are obtained, and the bit rate corresponding to the 4 DP-DQPSK signals is the same as the bit rate before DQPSK mapping, and the baud rate (also referred to as symbol rate) is 106.25G Baud. For the 1.6T direct detection scheme widely used in a short-distance scenario, PAM4 modulation is used, data is transmitted through 8 channels, and the baud rate is also 106.25G Baud. That is, in the data processing method provided in the present application, part of the device of the existing 1.6T direct detection scheme can be used, and the cost is low.

[0012] In some possible implementation manners, the p first data streams are obtained through t:p PMA processing from t signals, and the t signals are obtained through 16:t PMA processing from the 16 second data streams, and t is a positive integer multiple of 4. Here, a scheme of obtaining the p first data streams through two-step PMA processing on the second data streams after PCS processing is provided, which can better adapt to the application scenario shown in FIG. 2, wherein one step of PMA processing is performed by the sending device, and the other step of PMA processing is performed by the sending processing module.

[0013] In some possible implementation manners, the p first data streams are obtained through 16:p PMA processing from the 16 second data streams. Here, a scheme of obtaining the p first data streams through one-step PMA processing on the second data streams after PCS processing is provided, which can better adapt to the application scenario shown in FIG. 3, and the PMA processing is performed by the sending device.

[0014] In some possible implementation manners, the p first data streams are obtained through t:p PMA processing based on symbol multiplexing from t signals. That is, for the application scenario shown in FIG. 2, the sending processing module performs t:p PMA processing based on symbol multiplexing on the t signals from the sending device to obtain the p first data streams, which perfects the data processing flow of the sending processing module.

[0015] In some possible implementation manners, t = 8, p = 8; or, t = 16, p = 8; or, t = 8, p = 16; or, t = 16, p = 16. Several possible implementation manners of t:p PMA processing are given here, which improves the expansibility of the scheme.

[0016] In some possible implementation manners, the p first data streams are obtained by processing the service data to be sent through PCS processing including RS encoding. Here, a manner of directly obtaining the p first data streams by processing the service data to be sent through PCS processing is provided, and PMA processing is not required, which facilitates flexible selection of different implementation manners according to actual needs.

[0017] In some possible implementation manners, the manner of participating in DQPSK mapping by the p = 8 first data streams is also applicable to a scenario of containing two 800G services, which improves the compatibility of the scheme. Specifically, 4 first data streams in a first group of the p first data streams are obtained by processing 4 first signals through 4:4 PMA processing, the 4 first signals are obtained by processing 32 third data streams through 32:4 PMA processing, and the 32 third data streams are obtained by processing first service data to be sent through PCS processing including RS encoding. 4 first data streams in a second group of the p first data streams are obtained by processing 4 second signals through 4:4 PMA processing, the 4 second signals are obtained by processing 32 fourth data streams through 32:4 PMA processing, and the 32 fourth data streams are obtained by processing second service data to be sent through PCS processing including RS encoding.

[0018] In some possible implementation, the way of participating in DQPSK mapping for p=8 first data streams can also be applied to the scenario of containing 4 400G services, which improves the compatibility of the scheme. 2 first data streams in the first group of p first data streams are obtained by processing 2 third signals by 2:2 PMA, the 2 third signals are obtained by processing 16 fifth data streams by 16:2 PMA, and the 16 fifth data streams are obtained by processing third service data to be sent by PCS including RS encoding. 2 first data streams in the second group of p first data streams are obtained by processing 2 fourth signals by 2:2 PMA, the 2 fourth signals are obtained by processing 16 sixth data streams by 16:2 PMA, and the 16 sixth data streams are obtained by processing fourth service data to be sent by PCS including RS encoding. 2 first data streams in the third group of p first data streams are obtained by processing 2 fifth signals by 2:2 PMA, the 2 fifth signals are obtained by processing 16 seventh data streams by 16:2 PMA, and the 16 seventh data streams are obtained by processing fifth service data to be sent by PCS including RS encoding. 2 first data streams in the fourth group of p first data streams are obtained by processing 2 sixth signals by 2:2 PMA, the 2 sixth signals are obtained by processing 16 eighth data streams by 16:2 PMA, and the 16 eighth data streams are obtained by processing sixth service data to be sent by PCS including RS encoding.

[0019] In some possible implementation, the data processing including DQPSK mapping on p first data streams to obtain q DP-DQPSK signals includes: DQPSK mapping on every 2 first data streams in the p first data streams to obtain 1 DP-DQPSK signal, to obtain q=p / 2 DP-DQPSK signals in total. Wherein, the DQPSK mapping obtains 2 bits from each input first data stream, and uses the 2 bits as the phase change of adjacent two symbols in the DQPSK signal according to the mapping rule. It should be understood that the 2 bits mapped to 1 DP-DQPSK symbol come from 4 data streams, which is beneficial to resist colored noise.

[0020] In some possible implementation, the DQPSK mapping on every first data stream in the p first data streams to obtain the DQPSK signal in one polarization direction of 1 DP-DQPSK signal ensures that the DQPSK mapping on every 2 first data streams can obtain 1 DP-DQPSK signal.

[0021] In some possible implementation, the data processing including DQPSK mapping on the p first data streams to obtain q DP-DQPSK signals includes: DQPSK mapping on every 4 first data streams in the p first data streams to obtain 1 DP-DQPSK signal, so as to obtain q = p / 4 DP-DQPSK signals. It should be understood that the 4 bits mapped to 1 DP-DQPSK symbol come from 4 data streams, which is beneficial to combat colored noise.

[0022] In some possible implementation, DQPSK mapping on every 2 first data streams in the p first data streams to obtain DQPSK signals in one polarization direction of 1 DP-DQPSK signal ensures that DQPSK mapping on every 4 first data streams can obtain 1 DP-DQPSK signal.

[0023] In some possible implementation, the data processing method provided by the embodiment of the present application is applied to the scenarios including Ethernet, optical transport network and space optical communication.

[0024] In the second aspect, the embodiment of the present application provides a data processing apparatus, which includes an acquisition unit and a processing unit. The acquisition unit is configured to acquire p first data streams after RS encoding, p is a positive integer multiple of 4, and p is an integer power of 2. The processing unit is configured to perform DQPSK mapping on the p first data streams to obtain a plurality of DP-DQPSK signals, each DP-DQPSK signal including a DQPSK signal in a first polarization direction and a DQPSK signal in a second polarization direction.

[0025] In some possible implementation, the processing unit is specifically configured to perform DQPSK mapping on the p first data streams to obtain q DP-DQPSK signals, q = p / 2 or q = p / 4.

[0026] In some possible implementation, p = 8, q = p / 2 = 4; or p = 16, q = p / 4 = 4 or q = p / 2 = 8; or p = 32, q = p / 4 = 8.

[0027] In some possible implementation, every a RS adjacent RS symbols in each first data stream come from a RS RS codeword, a RS is greater than or equal to 4 and is an integer power of 2. For example, every 4 adjacent RS symbols in each first data stream come from 4 RS codewords.

[0028] In some possible implementation manners, the p first data streams are obtained from the 16 second data streams through PMA processing based on symbol multiplexing, and the 16 second data streams are obtained from the service data to be sent through PCS processing including RS encoding.

[0029] In some possible implementation manners, the p first data streams are obtained from the t signals through t:p PMA processing, and the t signals are obtained from the 16 second data streams through 16:t PMA processing, where t is a positive integer multiple of 4.

[0030] In some possible implementation manners, the p first data streams are obtained from the 16 second data streams through 16:p PMA processing.

[0031] In some possible implementation manners, the p first data streams are obtained from the t signals through t:p PMA processing based on symbol multiplexing.

[0032] In some possible implementation manners, t=8 and p=8, or t=16 and p=8, or t=8 and p=16, or t=16 and p=16.

[0033] In some possible implementation manners, the p first data streams are obtained from the service data to be sent through PCS processing including RS encoding.

[0034] In some possible implementation manners, p=8. Four first data streams in the first group of the p first data streams are obtained from the four first signals through 4:4 PMA processing, the four first signals are obtained from the 32 third data streams through 32:4 PMA processing, and the 32 third data streams are obtained from the first service data to be sent through PCS processing including RS encoding. Four first data streams in the second group of the p first data streams are obtained from the four second signals through 4:4 PMA processing, the four second signals are obtained from the 32 fourth data streams through 32:4 PMA processing, and the 32 fourth data streams are obtained from the second service data to be sent through PCS processing including RS encoding.

[0035] In some possible implementation manners, p=8. 2 first data streams in the first group of the p first data streams are obtained through 2:2 PMA processing on 2 third signals, the 2 third signals are obtained through 16:2 PMA processing on 16 fifth data streams, and the 16 fifth data streams are obtained through PCS processing including RS encoding on third service data to be sent. 2 first data streams in the second group of the p first data streams are obtained through 2:2 PMA processing on 2 fourth signals, the 2 fourth signals are obtained through 16:2 PMA processing on 16 sixth data streams, and the 16 sixth data streams are obtained through PCS processing including RS encoding on fourth service data to be sent. 2 first data streams in the third group of the p first data streams are obtained through 2:2 PMA processing on 2 fifth signals, the 2 fifth signals are obtained through 16:2 PMA processing on 16 seventh data streams, and the 16 seventh data streams are obtained through PCS processing including RS encoding on fifth service data to be sent. 2 first data streams in the fourth group of the p first data streams are obtained through 2:2 PMA processing on 2 sixth signals, the 2 sixth signals are obtained through 16:2 PMA processing on 16 eighth data streams, and the 16 eighth data streams are obtained through PCS processing including RS encoding on sixth service data to be sent.

[0036] In some possible implementation manners, the processing unit is specifically configured to perform DQPSK mapping on every 2 first data streams in the p first data streams to obtain 1 DP-DQPSK signal, so as to obtain a total of q=p / 2 DP-DQPSK signals.

[0037] In some possible implementation manners, each first data stream in the p first data streams is subjected to DQPSK mapping to obtain a DQPSK signal in one polarization direction of 1 DP-DQPSK signal.

[0038] In some possible implementation manners, the processing unit is specifically configured to perform DQPSK mapping on every 4 first data streams in the p first data streams to obtain 1 DP-DQPSK signal, so as to obtain a total of q=p / 4 DP-DQPSK signals.

[0039] In some possible implementation manners, each 2 first data streams in the p first data streams is subjected to DQPSK mapping to obtain a DQPSK signal in one polarization direction of 1 DP-DQPSK signal.

[0040] In some possible implementation manners, the data processing apparatus provided by the embodiments of the present application is applied to the scenarios of Ethernet, optical transport network and space optical communication.

[0041] In a third aspect, a chip is provided, which is configured to perform the method according to any of the embodiments of the first aspect.

[0042] In a fourth aspect, an embodiment of the present application provides an optical module. The optical module comprises a processor and an interface. The processor is configured to perform the method as described in any of the embodiments of the first aspect, and the interface is configured to transmit signals from the processor or transmit signals received by the processor to the processor.

[0043] In a fifth aspect, an embodiment of the present application provides a transmitting device. The transmitting device comprises a host device and an optical module as described in any of the embodiments of the fourth aspect. The optical module is configured to generate an optical signal according to data from the host device, and transmit the optical signal.

[0044] In a sixth aspect, an embodiment of the present application provides a device. The device comprises a processor and an interface. The processor is configured to perform the method as described in any of the embodiments of the first aspect, and the interface is configured to transmit signals from the processor or transmit signals received by the processor to the processor. The device can be a router, a switch, a server, an optical transport network device, or the like.

[0045] In a seventh aspect, an embodiment of the present application provides a communication system. The communication system comprises a transmitting device as described in the fifth aspect and a receiving device. The transmitting device is configured to transmit an optical signal to the receiving device.

[0046] In an eighth aspect, an embodiment of the present application provides a computer-readable storage medium. The computer-readable storage medium stores instructions. When the instructions are executed by a computer, the method as described in any of the embodiments of the first aspect is implemented.

[0047] In a ninth aspect, an embodiment of the present application provides a computer program product. The computer program product comprises program instructions. When the computer program product is executed, the method as described in any of the embodiments of the first aspect is implemented. BRIEF DESCRIPTION OF DRAWINGS

[0048] FIG. 1 is a schematic diagram of a communication system to which an embodiment of the present application is applied;

[0049] FIG. 2 is a schematic diagram of a process of data transmission in the communication system shown in FIG. 1;

[0050] FIG. 3 is a schematic diagram of another communication system to which an embodiment of the present application is applied;

[0051] FIG. 4 is a schematic diagram of a process of a data processing method provided by an embodiment of the present application;

[0052] FIG. 5(a) is a flowchart of a data processing method corresponding to an embodiment of the present application;

[0053] FIG. 5(b) is a flowchart of another data processing method corresponding to an embodiment of the present application;

[0054] Figure 5(c) is another data processing flow chart corresponding to the data processing method in the embodiments of the present application;

[0055] Figure 5(d) is another data processing flow chart corresponding to the data processing method in the embodiments of the present application;

[0056] Figure 5(e) is another data processing flow chart corresponding to the data processing method in the embodiments of the present application;

[0057] Figure 6(a) is another data processing flow chart corresponding to the data processing method in the embodiments of the present application;

[0058] Figure 6(b) is another data processing flow chart corresponding to the data processing method in the embodiments of the present application;

[0059] Figure 6(c) is another data processing flow chart corresponding to the data processing method in the embodiments of the present application;

[0060] Figure 7 is a schematic diagram of one embodiment of DQPSK mapping of p first data streams in the embodiments of the present application;

[0061] Figure 8 is a schematic diagram of another embodiment of DQPSK mapping of p first data streams in the embodiments of the present application;

[0062] Figure 9(a) is another data processing flow chart corresponding to the data processing method in the embodiments of the present application;

[0063] Figure 9(b) is another data processing flow chart corresponding to the data processing method in the embodiments of the present application;

[0064] Figure 10(a) is another data processing flow chart corresponding to the data processing method in the embodiments of the present application;

[0065] Figure 10(b) is another data processing flow chart corresponding to the data processing method in the embodiments of the present application;

[0066] Figure 11 is another data processing flow chart corresponding to the data processing method in the embodiments of the present application;

[0067] Figure 12 is a schematic diagram of one structure of a data processing apparatus in the embodiments of the present application;

[0068] Figure 13 is a schematic diagram of one structure of an optical module in the embodiments of the present application;

[0069] Figure 14 is a schematic diagram of one structure of a transmitting device in the embodiments of the present application. DETAILED DESCRIPTION

[0070] The embodiment of the present application provides a data processing method, device and system. The method has the advantages of low complexity, low power consumption and low latency, and can be applied to more transmission scenarios, and is especially suitable for future 800Gbps or above (such as 1.6Tbps) coherent transmission scenarios.

[0071] It should be noted that the terms "first", "second", and the like in the specification and claims of the present application and the above-described drawings are used to distinguish similar objects, and are not intended to limit a specific order or sequence. It should be understood that the above terms can be interchanged as appropriate, so that the embodiments described in the present application can be implemented in an order other than that described in the present application. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units does not have to be limited to only those steps or units clearly listed, but can include other steps or units that are not clearly listed or inherent to the process, method, product or device.

[0072] FIG. 1 is a schematic diagram of a communication system to which the embodiment of the present application is applied. As shown in FIG. 1, the communication system includes a sending device 01, a sending processing module 02, a channel transmission medium 03, a receiving processing module 04 and a receiving device 05. Taking the communication system as a data center network, the sending device 01 and the receiving device 05 can be switches, routers or servers, and the sending device 01 is also referred to as a client-side device located at the sending end, and the receiving device 05 is also referred to as a client-side device located at the receiving end, and the channel transmission medium 03 can be an optical fiber. The client-side device is also referred to as a host-side device. The client-side device includes a client-side chip and an interface. The client-side chip is also referred to as a host-side chip. The connection interface between the sending device 01 and the sending processing module 02 can be connected through an attachment unit interface (AUI), and the connection interface between the receiving device 05 and the receiving processing module 04 can be connected through an AUI. The sending processing module 02 and the receiving processing module 04 can be optical modules, electrical modules, connectors or other modules that process data during data transmission. For example, the processing module can be an LR optical module, such as a 1600LR module (a kind of coherent optical module). In addition, the sending device 01, the sending processing module 02, the channel transmission medium 03, the receiving processing module 04 and the receiving device 05 in the communication system can support bidirectional transmission, or can support unidirectional transmission, which is not limited here.

[0073] Figure 2 is a schematic diagram of a process of data transmission in the communication system shown in Figure 1. As shown in Figure 2, in the process of transmitting data from the transmitting device 01 to the receiving device 05, the transmitting device 01 is configured to perform Reed-Solomon (RS) encoding on the data, and then transmit the RS encoded data to the transmitting processing module 02. The transmitting processing module 02 is configured to perform differential quadrature phase shift keying (DQPSK) mapping on the RS encoded data to obtain q pieces of dual-polarization (DP) DQPSK signals (DP-DQPSK signals), and transmit the q pieces of DP-DQPSK signals to the receiving processing module 04 via the channel transmission medium 03. The receiving processing module 04 is configured to perform DP-DQPSK demapping on the received q pieces of DP-DQPSK signals, and transmit the DP-DQPSK demapped data to the receiving device 05. The receiving device 05 is configured to perform decoding on the received data.

[0074] FIG. 3 is a schematic diagram of another communication system to which embodiments of the present application are applied. As shown in FIG. 3, the communication system includes a sending device 01, a channel transmission medium 03, and a receiving device 05. The sending device 01 performs RS encoding and DQPSK mapping to obtain q pieces of DP-DQPSK signals and sends the q pieces of DP-DQPSK signals to the channel transmission medium 03. The receiving device 05 performs DP-DQPSK demapping and decoding on the data received from the channel transmission medium 03. Taking the communication system as a data center network, the sending device 01 and the receiving device 05 can be switches, routers, servers, or the like, and the sending device 01 is also referred to as a client-side device or a host device at the sending end, and the receiving device 05 is also referred to as a client-side chip at the receiving end, and the channel transmission medium 03 can be an optical fiber. The client-side device includes a client-side chip and an interface. The client-side chip is also referred to as a host chip. The sending device 01, the channel transmission medium 03, and the receiving device 05 in the communication system can support bidirectional transmission or unidirectional transmission, which is not limited here. That is, the sending device 01 shown in FIG. 3 also integrates the functions of the sending processing module 02 shown in FIG. 2, and the receiving device 05 shown in FIG. 3 also integrates the functions of the receiving processing module 04 shown in FIG. 2. That is, the sending device 01 shown in FIG. 3 also integrates the functions of the sending processing module 02 shown in FIG. 2, and the receiving device 05 shown in FIG. 3 also integrates the functions of the receiving processing module 04 shown in FIG. 2. At this time, the sending device 01 can also use linear-drive pluggable optics (LPO) technology, co-packaged optics (CPO) technology, or near packaged optics (NPO) technology.

[0075] It should be noted that the above is an exemplary description of the application scenarios of the data processing method provided by the embodiments of the present application, and does not constitute a limitation on the application scenarios of the data processing method. Those skilled in the art can know that the application scenarios can be adjusted according to application requirements as the business requirements change, and the embodiments of the present application do not enumerate them one by one.

[0076] FIG. 4 is a flowchart of a data processing method provided by an embodiment of the present application. It should be understood that the data processing method is applied to a sending end, for example, can be implemented by the sending processing module 02 shown in FIG. 2, or can be implemented by the sending device 01 shown in FIG. 3.

[0077] 101, obtaining p pieces of first data streams that are RS encoded.

[0078] In the embodiments of the present application, the p first data streams are all RS encoded data streams. It should be noted that the code length of the RS code in the embodiments of the present application is counted in units of symbols, and the symbol in the RS code can be referred to as RS symbol. For example, the RS code adopts RS(544, 514) code, also known as KP4 code, and the code length of the RS code is 544 RS symbols, that is, the code word of the RS code includes 544 RS symbols, and one RS symbol contains 10 bits. Specifically, every 4 adjacent RS symbols in each first data stream come from 4 RS code words, p is an integer multiple of 4, and p is an integer power of 2. Typically, p is 4, 8, 16 or 32, etc.

[0079] For example, the integer p is 8 or 16 when applied to 1.6T Ethernet (1.6 Terabit Ethernet, referred to as 1.6TE) service transmission. For another example, the integer p is 16 or 32 when applied to 3.2T Ethernet service transmission.

[0080] 102. DQPSK mapping is performed on the p first data streams to obtain q DP-DQPSK signals.

[0081] It should be understood that the DP-DQPSK signal includes a DQPSK signal in an X polarization direction and a DQPSK signal in a Y polarization direction, wherein the X polarization direction and the Y polarization direction are orthogonal to each other. The X polarization direction can also be referred to as a first polarization direction, and the Y polarization direction can also be referred to as a second polarization direction.

[0082] In some applications, DQPSK mapping is performed on every 2 first data streams in the p first data streams to obtain 1 DP-DQPSK signal, so as to obtain a total of q = p / 2 DP-DQPSK signals. Specifically, one of every 2 first data streams is DQPSK mapped to obtain a signal of 1 DP-DQPSK signal in the X polarization direction, and the other of every 2 first data streams is DQPSK mapped to obtain a signal of 1 DP-DQPSK signal in the Y polarization direction. For example, p = 8, q = p / 2 = 4. For another example, p = 16, q = p / 2 = 8.

[0083] In some applications, DQPSK mapping is performed on each of the p first data streams to obtain q = p / 4 DP-DQPSK signals. Specifically, DQPSK mapping is performed on 2 of the 4 first data streams to obtain a DP-DQPSK signal in the X polarization direction, and DQPSK mapping is performed on the other 2 of the 4 first data streams to obtain a DP-DQPSK signal in the Y polarization direction. For example, p = 16, and q = p / 4 = 4. For another example, p = 32, and q = p / 4 = 8.

[0084] It should be noted that the DQPSK mapping in the X polarization direction and the DQPSK mapping in the Y polarization direction can also be collectively referred to as DP-DQPSK mapping.

[0085] For service transmission of 1.6T Ethernet, the total bit rate of the p first data streams is 106.25 x 2 x 8 = 1700G bits per second. It should be understood that the bit rate in the present application is a nominal rate, and in actual applications, there is an offset range of the bit rate, for example, ±V0 (ppm) error, where V0 can be 20, 25, 50, or 100, etc. Each 4 consecutive RS symbols in each first data stream come from 4 different RS code words, and each first data stream is also referred to as a symbol-quartet stream. In some specific applications, the first data stream also undergoes Physical Media Attachment (PMA) processing based on symbol multiplexing, and the PMA based on symbol multiplexing is also referred to as PMA-S. More specifically, the first data stream is obtained through PMA processing based on symbol-quartet multiplexing. It should be noted that in the embodiments of the present application, m0:m1 PMA means that m0 input data streams are symbol-multiplexed to obtain m1 output data streams. In some specific applications, the first data stream also undergoes Physical coding sublayer (PCS) processing.

[0086] Fig. 5(a) is a data processing flow diagram corresponding to the data processing method in the embodiment of the present application. As shown in Fig. 5(a), 1.6T service data is processed by 1.6T PCS to obtain 16 PCS channel data streams, also referred to as 16 PCS Lanes. Specifically, the 1.6T PCS processing includes four RS encoding processing units, i.e., RS-A, RS-B, RS-C and RS-D in the figure. The encoded data stream obtained after the four RS encoding processing units is subjected to symbol distribution and interleave to obtain 16 PCS Lanes. Among them, the symbol distribution is in 10-bit granularity. Every four adjacent RS symbols in the 16 PCS Lanes come from four different RS codewords. The 16 PCS Lanes are subjected to 1.6T 16:8PMA based on 4-symbol multiplexing to obtain 8 1.6T AUI-8 signals. The bit rate of each signal in the 8 1.6T AUI-8 signals is 212.5G bits per second, which is subjected to PAM4 modulation, and the corresponding baud rate (also referred to as symbol rate) is 106.25GBaud, that is, the total bit rate of the 8 1.6T AUI-8 signals is 106.25x2x8=1700G bits per second. Considering 1.6T Ethernet service, the 1.6T PCS is also referred to as 1.6T BASE-R PCS, and the 1.6T 16:8PMA is also referred to as 1.6T BASE-R 16:8PMA. The 1.6T PCS processing and the 1.6T 16:8PMA are implemented by operating in the transmitting device 01. The transmitting processing module 02 receives the 8 1.6T AUI-8 signals, which are first subjected to 1.6T 8:8PMA to obtain p=8 first data streams, and then subjected to DQPSK mapping to obtain q=p / 2=4 to-be-transmitted DP-DQPSK signals.

[0087] Figure 5(b) is another data processing flow diagram corresponding to the data processing method in the embodiments of the present application. As shown in Figure 5(b), the 1.6T service data is processed by 1.6T PCS to obtain 16 PCS lane data streams, also referred to as 16 PCS Lanes. The 1.6T PCS processing includes 4 RS encoding processing units, namely RS-A, RS-B, RS-C and RS-D in the figure. The encoded data stream obtained after passing through the 4 RS encoding processing units is subjected to symbol distribution and interleaving to obtain 16 PCS Lanes. Among them, the symbol distribution has a granularity of 10 bits. The total bit rate of the 16 PCS Lanes is 106.25x16=1700G bits per second. The 16 PCS Lanes are processed by 1.6T 16:16PMA based on 4-symbol multiplexing to obtain 16 1.6T AUI-16 signals. The bit rate of each of the 16 1.6T AUI-16 signals is 106.25G bits per second, which is subjected to PAM4 modulation, and the corresponding baud rate (also referred to as symbol rate) is 53.125G Baud, that is, the total bit rate of the 16 1.6T AUI-16 signals is 106.25x16=1700G bits per second. The 1.6T PCS processing and the 1.6T 16:16PMA are implemented by operating in the transmitting device 01. The transmitting processing module 02 receives the 16 1.6T AUI-16 signals, first processes them by 1.6T 16:8PMA to obtain p=8 first data streams, and then performs DQPSK mapping to obtain q=p / 2=4 DP-DQPSK signals to be transmitted.

[0088] Figure 5(c) is another data processing flow diagram corresponding to the data processing method in the embodiments of the present application. As shown in Figure 5(c), the 1.6T service data is processed by 1.6T PCS to obtain 16 PCS lane data streams, also referred to as 16 PCS Lanes. The 1.6T PCS processing includes 4 RS encoding processing units, namely RS-A, RS-B, RS-C and RS-D in the figure. The encoded data stream obtained after passing through the 4 RS encoding processing units is subjected to symbol distribution and interleaving to obtain 16 PCS Lanes. Among them, the symbol distribution has a granularity of 10 bits. The total bit rate of the 16 PCS Lanes is 106.25x16=1700G bits per second. The 16 PCS Lanes are processed by 1.6T 16:8PMA based on 4-symbol multiplexing to obtain p=8 first data streams, and subjected to DQPSK mapping to obtain q=p / 2=4 DP-DQPSK signals to be transmitted. The 1.6T PCS processing, the 1.6T 16:8PMA and the DQPSK mapping are implemented by operating in the transmitting device 01.

[0089] Fig. 6(a) is another data processing flow chart corresponding to the data processing method in the embodiment of the present application. As shown in Fig. 6(a), the 1.6T service data is processed by 1.6T PCS to obtain 16 PCS channel data streams, also referred to as 16 PCS Lanes. The 1.6T PCS processing includes four RS encoding processing units, i.e., RS-A, RS-B, RS-C and RS-D in the figure. The encoded data stream obtained after the four RS encoding processing units is subjected to symbol distribution and interleaving to obtain 16 PCS Lanes. Among them, the symbol distribution is in 10-bit granularity. The 16 PCS Lanes are subjected to 1.6T 16:8PMA based on 4-symbol multiplexing to obtain 8 1.6T AUI-8 signals. The bit rate of each of the 8 1.6T AUI-8 signals is 212.5G bits per second, which is subjected to PAM4 modulation, and the corresponding baud rate (also referred to as symbol rate) is 106.25G Baud, that is, the total bit rate of the 8 1.6T AUI-8 signals is 106.25x2x8=1700G bits per second. Considering the 1.6T Ethernet service, the 1.6T PCS is also referred to as 1.6T BASE-R PCS, and the 1.6T 16:8PMA is also referred to as 1.6T BASE-R 16:8PMA. The 1.6T PCS processing and the 1.6T 16:8PMA are implemented by operating in the transmitting device 01. The transmitting processing module 02 receives the 8 1.6T AUI-8 signals, first subjects them to 1.6T 8:16PMA to obtain p=16 first data streams, and then performs DQPSK mapping to obtain q=p / 4=4 to-be-transmitted DP-DQPSK signals.

[0090] Figure 6(b) is another data processing flow chart corresponding to the data processing method in the embodiments of the present application. As shown in Figure 6(b), the 1.6T service data is processed by 1.6T PCS to obtain 16 PCS lane data streams, also referred to as 16 PCS Lanes. The 1.6T PCS processing includes 4 RS encoding processing units, namely RS-A, RS-B, RS-C and RS-D in the figure. The encoded data stream obtained after passing through the 4 RS encoding processing units is subjected to symbol distribution and interleaving to obtain 16 PCS Lanes. The 16 PCS Lanes are subjected to 1.6T 16:16 PMA based on 4-symbol multiplexing to obtain 16 1.6T AUI-16 signals. The bit rate of each of the 16 1.6T AUI-16 signals is 106.25 Gbit / s, which is subjected to PAM4 modulation, and the corresponding baud rate (also referred to as symbol rate) is 53.125 G Baud. The total bit rate of the 16 1.6T AUI-16 signals is 106.25x16=1700 Gbit / s. The 1.6T PCS processing and the 1.6T 16:16 PMA are implemented by operating in the transmitting device 01. The transmitting processing module 02 receives the 16 1.6T AUI-16 signals, first passes through the 1.6T 16:16 PMA to obtain p=16 first data streams, and then performs DQPSK mapping to obtain q=p / 4=4 DP-DQPSK signals to be transmitted.

[0091] Figure 6(c) is another data processing flow chart corresponding to the data processing method in the embodiments of the present application. As shown in Figure 6(c), the 1.6T service data is processed by 1.6T PCS to obtain 16 PCS lane data streams, also referred to as 16 PCS Lanes. The 1.6T PCS processing includes 4 RS encoding processing units, namely RS-A, RS-B, RS-C and RS-D in the figure. The encoded data stream obtained after passing through the 4 RS encoding processing units is subjected to symbol distribution and interleaving to obtain 16 PCS Lanes. The total bit rate of the 16 PCS Lanes is 106.25x16=1700 Gbit / s. The 16 PCS Lanes are taken as p=16 first data streams, subjected to DQPSK mapping to obtain q=p / 4=4 DP-DQPSK signals to be transmitted. The 1.6T PCS processing and the DQPSK mapping are implemented by operating in the transmitting device 01.

[0092] It should be noted that in the scenarios of 1.6T service in FIG. 5(a), FIG. 5(b) and FIG. 5(c), there are p = 8 first data streams participating in DQPSK mapping. In the scenarios of 1.6T service in FIG. 6(a), FIG. 6(b) and FIG. 6(c), there are p = 16 first data streams participating in DQPSK mapping. For the mode of p = 8 first data streams participating in DQPSK mapping, in addition to being applicable to the above-mentioned scenarios of 1.6T service, it can also be applicable to other service scenarios including 2 800G services, 4 400G services, etc., with a total rate of 1.6T.

[0093] FIG. 5(d) is another data processing flow diagram corresponding to the data processing method in the embodiments of the present application. As shown in FIG. 5(d), consider a 2 800G service scenario, wherein 32 PCS Lanes are obtained for each 800G service data after 800G PCS processing. Specifically, each 800G PCS processing includes 4 RS encoding processing units, namely RS-A, RS-B, RS-C and RS-D in the figure. The encoded data stream obtained after the 4 RS encoding processing units is subjected to symbol distribution and interleaving to obtain 32 PCS Lanes. The symbol distribution is in 10-bit granularity. The 32 PCS Lanes are subjected to 800G 32:4PMA based on 4-symbol multiplexing to obtain 4 800G AUI-4 signals. The 2 800G service data are subjected to the above-mentioned 800G PCS and 800G 32:4PMA to obtain a total of 2 groups of 800G AUI-4 signals, a total of 8 signal streams. The bit rate of each signal in the 2 groups of 800G AUI-4 signals is 212.5G bits per second, which is subjected to PAM4 modulation, and the corresponding baud rate (also referred to as symbol rate) is 106.25G Baud, that is, the total bit rate of the 2 groups of 800G AUI-4 signals is 106.25 x 2 x 4 x 2 = 1700G bits per second. The transmitting end processing module 02 receives the 2 groups of 800G AUI-4 signals, and each group of 800G AUI-4 signals is subjected to 800G 4:4PMA to obtain 4 first data streams, a total of p = 8 first data streams, and then the 8 first data streams are subjected to DQPSK mapping to obtain q = p / 2 = 4 DP-DQPSK signals to be transmitted.

[0094] Fig. 5(e) is another data processing flow diagram corresponding to the data processing method in the embodiments of the present application. As shown in Fig. 5(e), four 400G service scenarios are considered, wherein each 400G service data is processed by 400G PCS to obtain 16 PCS Lanes. Specifically, each 400G PCS processing includes two RS encoding processing units, for example, the 400G PCS processing can include RS-A and RS-B, and the 400G PCS processing can also include RS-C and RS-D. The encoded data stream obtained by the two RS encoding processing units is then subjected to symbol distribution and interleaving to obtain 16 PCS Lanes. Among them, the symbol distribution has a granularity of 10 bits. The 16 PCS Lanes are subjected to 400G 16:2PMA based on 4-symbol multiplexing to obtain 2 400G AUI-2 signals. Four 400G service data are processed by the above-mentioned 400G PCS and 400G 16:2PMA to obtain a total of 4 groups of 400G AUI-2 signals, a total of 8 signal streams. The bit rate of each signal in the four groups of 400G AUI-2 signals is 212.5G bits per second, which adopts PAM4 modulation, and the corresponding baud rate (also known as symbol rate) is 106.25G Baud, that is, the total bit rate of the four groups of 400G AUI-2 signals is 106.25x2x4x2=1700G bits per second. The transmitting end processing module 02 receives the four groups of 400G AUI-2 signals, and each group of 400G AUI-2 signals is subjected to 400G 2:2PMA to obtain two first data streams, a total of p=8 first data streams, and then the 8 first data streams are subjected to DQPSK mapping to obtain q=p / 2=4 DP-DQPSK signals to be transmitted.

[0095] It should be noted that in the data processing method provided in the present application, four DP-DQPSK signals to be transmitted are obtained by DQPSK mapping, and the baud rate of each DP-DQPSK signal is 106.25G Baud. For the 1.6T direct detection scheme widely used in short distance scenarios, PAM4 modulation is adopted, and data is transmitted through 8 channels, and the baud rate is also 106.25G Baud. That is, in the data processing method provided in the present application, part of the existing 1.6T direct detection scheme can be used, which has the advantage of low cost.

[0096] It should also be understood that the baud rate in the present application is a nominal rate, and in actual application, the baud rate of the DP-DQPSK signal will have a certain error range, for example, the baud rate has a ±V1 (ppm) error, wherein V1 can be 20, 25, 50 or 100, etc.

[0097] The way of performing DQPSK mapping on the p first data streams will be described in detail below in combination with the value of p.

[0098] For the scenario of p = 8. For example, as shown in FIG. 5(a), 8 first data streams are acquired from a 1.6T 8:8 PMA. For another example, as shown in FIG. 5(b) and FIG. 5(c), 8 first data streams are acquired from a 1.6T 16:8 PMA. For yet another example, as shown in FIG. 5(d), a total of 8 first data streams are acquired from 2 groups of 800G 32:4 PMAs. For still another example, as shown in FIG. 5(e), a total of 8 first data streams are acquired from 4 groups of 400G 16:2 PMAs.

[0099] FIG. 7 is a schematic diagram of an embodiment of the present application for DQPSK mapping of p first data streams. As shown in FIG. 7, taking p = 8 as an example, every 2 first data streams in the p = 8 first data streams (i.e., first data stream 0-first data stream 7) are subjected to DP-DQPSK mapping to obtain 1 DP-DQPSK signal, and a total of q = 4 DP-DQPSK signals are obtained. Specifically, the 8 first data streams are subjected to DQPSK mapping to obtain a DQPSK signal of 1 DP-DQPSK signal in one polarization direction. For example, first data stream 0 is subjected to DQPSK mapping to obtain a DQPSK signal of DP-DQPSK signal 0 in the X polarization direction, first data stream 1 is subjected to DP-DQPSK mapping to obtain a DQPSK signal of DQPSK signal 0 in the Y polarization direction, and so on.

[0100] It should be understood that the DQPSK mapping acquires 2 consecutive bits (A, B) from the input first data stream i (0≤i≤7), and uses the 2 bits as the phase change between adjacent two symbols in the DQPSK signal according to the mapping rule shown in Table 1 below. The phase change is expressed in radians. Table 1 also shows the mapping relationship between the two bits and the DQPSK symbol value.

[0101] Table 1

[0102] Considering 1.6T services, the total bit rate of the 8 first data streams and the 4 DP-DQPSK signals is 106.25×2×4×2 = 1700G bits per second. The baud rate corresponding to the 4 DP-DQPSK signals is 106.25G Baud. For the 1.6T direct detection scheme widely used in short-distance scenarios, PAM4 modulation is used to transmit data through 8 channels, and the baud rate is also 106.25G Baud. That is, in the data processing method proposed in the present application, part of the devices of the existing 1.6T direct detection scheme can be used, which has the advantage of low cost.

[0103] It should be noted that the first data processing of p=8 can be applied to a service scenario including 1 1.6T service, 2 800G services, 4 400G services, and a total of 1.6T rate service, and can be applied to a wider scenario.

[0104] For the scenario of p=16. For example, as shown in FIG. 6(a), 16 first data streams are obtained from the 1.6T 8:16PMA. For another example, as shown in FIG. 6(b), 16 first data streams are obtained from the 1.6T 16:16PMA. For another example, as shown in FIG. 6(c), 16 first data streams are obtained from the 1.6T PCS.

[0105] FIG. 8 is another embodiment of DQPSK mapping of p first data streams in the embodiment of the present application. As shown in FIG. 8, every 4 first data streams in the p=16 first data streams (i.e., first data stream 0-first data stream 15) are subjected to DP-DQPSK mapping to obtain 1 DP-DQPSK signal, and a total of q=4 DP-DQPSK signals are obtained. Specifically, every 2 first data streams in the 16 first data streams are subjected to DQPSK mapping to obtain a DQPSK signal in one polarization direction of the 1 DP-DQPSK signal. For example, first data stream 0 and first data stream 1 are subjected to DQPSK mapping to obtain a DQPSK signal in the X polarization direction of the DP-DQPSK signal 0, first data stream 2 and first data stream 3 are subjected to DQPSK mapping to obtain a DQPSK signal in the Y polarization direction of the DP-DQPSK signal 0, and so on.

[0106] It should be understood that the DQPSK mapping obtains 1 bit from the input 2 first data streams, respectively, and a total of 2 bits (A, B), and uses the mapping rule shown in Table 1 as the phase change of the adjacent two symbols in the DQPSK signal.

[0107] It should be noted that the data processing method proposed in the present application has a bit rate of 1700G bits per second corresponding to the data stream processed by the 1.6T PCS. After DQPSK mapping, 4 DP-DQPSK signals are obtained, and the corresponding bit rate is the same as the bit rate before DQPSK mapping, and the corresponding baud rate (also known as symbol rate) is 106.25G Baud. For the 1.6T direct detection scheme widely used in short distance scenarios, PAM4 modulation is used to transmit data through 8 channels, and the baud rate is also 106.25G Baud. That is, in the data processing method proposed in the present application, part of the existing 1.6T direct detection scheme can be used, which has the advantage of low cost.

[0108] It should be understood that, compared with the existing concatenated FEC scheme, the embodiment of the present application does not need to perform concatenated FEC encoding before DQPSK mapping, so that the multiple to-be-sent DP-DQPSK signals have lower bit rates and baud rates. Therefore, the data processing method proposed in the present application has the advantages of low complexity, low power consumption, low latency, etc., and can be applied to more transmission scenarios, and is particularly suitable for future 800 Gbps or above (such as 1.6 Tbps, etc.) coherent transmission scenarios.

[0109] The above data processing method considering 1.6T Ethernet service transmission is given below for a data processing method facing future 3.2T service transmission.

[0110] FIG. 9(a) is another data processing flowchart corresponding to the data processing method in the embodiment of the present application. FIG. 9(b) is another data processing flowchart corresponding to the data processing method in the embodiment of the present application. As shown in FIG. 9(a) and FIG. 9(b), in some specific applications, p = 16 and q = 8.

[0111] As shown in FIG. 9(a), the 3.2T service data is processed by 3.2T PCS to obtain 16 PCS lane data streams, also referred to as 16 PCS Lanes. The 1.6T PCS processing includes 4 RS encoding processing units, i.e., RS-A, RS-B, RS-C and RS-D in the figure. The encoded data stream obtained after the 4 RS encoding processing units is subjected to symbol distribution and interleaving to obtain 16 PCS Lanes. Among them, the symbol distribution has a granularity of 10 bits. The 16 PCS Lanes are subjected to 3.2T 16:16PMA based on 4-symbol multiplexing to obtain 16 3.2T AUI-16 signals. The 3.2T PCS processing and the 3.2T 16:16PMA are implemented by operating in the transmitting end device 01. The transmitting end processing module 02 receives the 16 1.6T AUI-16 signals, first performs 3.2T 16:16PMA to obtain p = 16 first data streams, and then performs DQPSK mapping to obtain q = p / 2 = 8 to-be-sent DP-DQPSK signals. At this time, the baud rate (also referred to as symbol rate) corresponding to each DP-DQPSK signal is 106.25G Baud.

[0112] As shown in FIG. 9(b), the 3.2T service data is processed by the 3.2T PCS to obtain 16 PCS lane data streams, also referred to as 16 PCS Lanes. The 3.2T PCS processing includes four RS encoding processing units, namely RS-A, RS-B, RS-C and RS-D in the figure. The encoded data streams obtained through the four RS encoding processing units are subjected to symbol distribution and interleaving to obtain 16 PCS Lanes. The 16 PCS Lanes are taken as p=16 first data streams, subjected to DQPSK mapping to obtain q=p / 2=8 DP-DQPSK signals to be transmitted. The 3.2T PCS processing and the DQPSK mapping are implemented by operating in the transmitting device 01. At this time, the baud rate (also referred to as symbol rate) corresponding to each DP-DQPSK signal is 106.25G Baud.

[0113] FIG. 10(a) is another data processing flow diagram corresponding to the data processing method in the embodiment of the present application. FIG. 10(b) is another data processing flow diagram corresponding to the data processing method in the embodiment of the present application. As shown in FIG. 10(a) and FIG. 10(b), in some specific applications, p=16 and q=4.

[0114] As shown in FIG. 10(a), the 3.2T service data is processed by the 3.2T PCS to obtain 16 PCS lane data streams, also referred to as 16 PCS Lanes. The 1.6T PCS processing includes four RS encoding processing units, namely RS-A, RS-B, RS-C and RS-D in the figure. The encoded data streams obtained through the four RS encoding processing units are subjected to symbol distribution and interleaving to obtain 16 PCS Lanes. The symbol distribution is taken as 10-bit granularity. The 16 PCS Lanes are subjected to 3.2T 16:16PMA based on 4-symbol multiplexing to obtain 16 3.2T AUI-16 signals. The 3.2T PCS processing and the 3.2T 16:16PMA are implemented by operating in the transmitting device 01. The transmitting processing module 02 receives the 16 1.6T AUI-16 signals, first subjected to 3.2T 16:16PMA to obtain p=16 first data streams, and then subjected to DQPSK mapping to obtain q=p / 4=4 DP-DQPSK signals to be transmitted. At this time, the baud rate (also referred to as symbol rate) corresponding to each DP-DQPSK signal is 212.5G Baud.

[0115] As shown in FIG. 10(b), the 3.2T service data is processed by 3.2T PCS to obtain 16 PCS lane data streams, also referred to as 16 PCS Lanes. The 3.2T PCS processing includes four RS encoding processing units, namely RS-A, RS-B, RS-C and RS-D in the figure. The encoded data streams obtained through the four RS encoding processing units are subjected to symbol distribution and interleaving to obtain 16 PCS Lanes. The 16 PCS Lanes are taken as p=16 first data streams, and subjected to DQPSK mapping to obtain q=p / 4=4 DP-DQPSK signals to be transmitted. The 3.2T PCS processing and DQPSK mapping are implemented by operation in the transmitting device 01. At this time, the baud rate (also referred to as symbol rate) corresponding to each DP-DQPSK signal is 212.5G Baud.

[0116] FIG. 11 is another data processing flowchart corresponding to the data processing method in the embodiments of the present application. As shown in FIG. 11, in some specific applications, p=32 and q=8. The 3.2T service data is processed by 3.2T PCS to obtain 32 PCS lane data streams, also referred to as 32 PCS Lanes. The 3.2T PCS processing includes four RS encoding processing units, namely RS-A, RS-B, RS-C and RS-D in the figure. The encoded data streams obtained through the four RS encoding processing units are subjected to symbol distribution and interleaving to obtain 32 PCS Lanes. The 32 PCS Lanes are taken as p=32 first data streams, and subjected to DQPSK mapping to obtain q=p / 4=8 DP-DQPSK signals to be transmitted. The 3.2T PCS processing and DQPSK mapping are implemented by operation in the transmitting device 01. At this time, the baud rate (also referred to as symbol rate) corresponding to each DP-DQPSK signal is 106.25G Baud.

[0117] FIG. 12 is a structural schematic diagram of a data processing apparatus in the embodiments of the present application. As shown in FIG. 12, the data processing apparatus includes an acquisition unit 201 and a processing unit 202. The acquisition unit 201 is configured to perform the operation of step 101 in the above embodiments, and the processing unit 202 is configured to perform the operation of step 102 in the above embodiments. It should be understood that the data processing apparatus provided by the present application can also be implemented in other manners. For example, the division of the units in the above apparatus is merely a logical function division, and other division manners can be adopted in actual implementation, for example, a plurality of units or components can be combined or integrated into another system. In addition, each functional unit in the embodiments of the present application can be integrated in a processing unit, or each can be a separate physical unit, or two or more functional units can be integrated in a processing unit. The above integrated unit can be implemented in the form of hardware or software functional units.

[0118] Figure 13 is a schematic diagram of a structure of an optical module according to an embodiment of the present application. As shown in Figure 13, the optical module includes a processor 301 and an interface 302, the processor 301 is configured to perform the operation of step 102 in the above embodiment. In a possible implementation, the processor 301 includes the processing unit 202 shown in Figure 12. The interface 302 can be a transceiver or an input / output interface, and the interface 302 is configured to receive a signal from another device and transmit the signal to the processor 301 or transmit a signal from the processor 301 to another device. As an example, the processor 301 performs the DQPSK mapping to obtain a DP-DQPSK signal, and transmits the DP-DQPSK signal through the interface 302, and in this example, the interface 302 can specifically refer to an electrical interface. As another example, the processor 301 performs the DQPSK mapping to obtain a DP-DQPSK signal, and a modulator in the optical module performs signal processing such as electro-optical conversion on the DP-DQPSK signal to obtain an optical signal, and then transmits the optical signal through the interface 302, and in this example, the interface 302 can specifically refer to an optical interface. Optionally, the optical module can further include a memory 303, wherein the memory 303 is configured to store program instructions and data.

[0119] Generally, an optical module includes optoelectronic devices, a processor, and an interface, etc., and the optoelectronic devices include a transmitter and a receiver. The transmitting end of the optical module converts an electrical signal into an optical signal and transmits the optical signal through an optical fiber, and the receiving end of the optical module receives an optical signal and converts the optical signal into an electrical signal.

[0120] It should be noted that the types of optical modules in the embodiments of the present application include, but are not limited to, normal optical modules, near package optics (NPO) modules, co-packaged optics (CPO) modules, and the like. The functions that can be implemented by the normal optical modules include, but are not limited to, digital signal processing (DSP) and clock data recovery (CDR), and the like. For example, the normal optical module converts an analog signal into a digital signal, performs DSP on the digital signal, and then converts the digital signal into an analog signal to be sent to a host-side device. Since the DSP needs to be retimed, the normal optical module can also be referred to as a retimed module. The normal optical module is connected to the host-side device through an attachment unit interface (AUI). The NPO module and the CPO module do not have a pluggable optical module physical package form, and are closer to the host-side device. The NPO module and the CPO module can also be referred to as optical engines. The NPO technology or the CPO technology is a technology of "packaging" the host-side device (or the host-side chip) and the optical engine. When the host-side device and the optical engine are packaged by using the NPO technology, the optical engine can be referred to as an NPO module. When the host-side device and the optical engine are packaged by using the CPO technology, the optical engine can be referred to as a CPO module.

[0121] FIG. 14 is a schematic structural diagram of a sending device in an embodiment of the present application. As shown in FIG. 14, the sending device includes a host-side device 401 and an optical module 402. The host-side device 401 is configured to send data to the optical module 402. The optical module 402 generates an optical signal according to the data sent by the host-side device 401, and sends the optical signal through a channel. For example, the host-side device can be a switch, a router, a server, or the like. The sending device can be a communication device including the host-side device 401 and the optical module 402. It should be understood that the sending device in the embodiments of the present application is named based on the direction of data flow, and does not limit the functions of the device. For example, the sending device can also have a receiving function.

[0122] The embodiments of the present application also provide an optical transport network (OTN) device, which comprises a line side device and a client side device. The client side device can also be referred to as a tributary side device in some scenarios. The line side device comprises a processor and an interface. The processor is configured to execute the data processing method described in the above embodiments. The interface can be a transceiver or an input / output interface. The interface is configured to receive a signal from another device outside the line side device and transmit the signal to the processor, or transmit a signal from the processor to another device outside the line side device.

[0123] The embodiments of the present application also provide a chip. The chip integrates a circuit for implementing the functions of the processor described above and one or more interfaces. As an example, the chip integrates a memory. As another example, when the chip does not integrate a memory, the chip can be connected to an external memory through the interface. The chip can complete the method steps of any one or more of the above embodiments. Alternatively, the chip implements the actions performed by the data processing device in the above embodiments according to program codes stored in the memory.

[0124] As an example, the chip in the embodiments of the present application can be a central processing unit (CPU), and can also be another general-purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or another programmable logic device, a transistor logic device, a hardware component or any combination thereof. The general-purpose processor can be a microprocessor, or can be any conventional processor, and can also be a processing circuit implementing specific functions.

[0125] The embodiments of the present application also provide a computer readable storage medium, which comprises a program or instructions, and when the program or instructions are executed on a computer, the program or instructions cause the computer to implement the method performed by the above method embodiments.

[0126] It should be understood that the processor mentioned in the embodiments of the present application can be implemented by hardware or software. When implemented by hardware, the processor can be a logic circuit, an integrated circuit or the like. When implemented by software, the processor can be a general-purpose processor, which implements by reading software codes stored in a memory. The memory can exist independently and be connected to the processor, or the memory can be integrated with the processor.

[0127] As an example, the processor in the embodiments of the present application can be a central processing unit (CPU), and can also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, transistor logic devices, hardware components or any combination thereof. The general-purpose processor can be a microprocessor or any conventional processor, and can also be a processing circuit that implements specific functions.

[0128] The memory in the embodiments of the present application can be a random access memory (RAM), a flash memory, a read-only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrically EPROM (EEPROM), a register, a hard disk, a mobile hard disk, a CD-ROM, or any other form of storage medium well known in the art. An exemplary storage medium is coupled to the processor, such that the processor can read information from, and write information to, the storage medium. Of course, the storage medium can be a component of the processor. The processor and the storage medium can be located in an ASIC. The ASIC can be located in a network device or a terminal device. Of course, the processor and the storage medium can also exist as separate components in a network device or a terminal device.

[0129] In the above embodiments, all or part of the embodiments can be implemented by software, hardware, firmware or any combination thereof.

[0130] When implemented by using hardware, the data processing method provided by the embodiments of the present application can be implemented without reading software codes or instructions, for example, by using a CPU, a DSP, an ASIC, an FPGA, other programmable logic devices, transistor logic devices, hardware components or any combination thereof.

[0131] When implemented using software, the functions can be implemented using one or more computer programs or instructions stored or executed in at least one computer-readable medium. The computer-readable medium can be a machine-readable storage device, a machine-readable storage substrate, a memory device, or a computer-readable signal. The computer-readable medium can include, but is not limited to, floppy diskettes, optical disks, CD-ROMs, DVDs, read-only memory (ROM), random access memory (RAM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), magnetic or optical cards, flash memory, or any other suitable type of machine-readable medium. Suitable machine-readable media for storing or transmitting software include hardware- or software-readable media that store data which can be accessed by one or more computer systems. A computer-readable medium stores computer-executable instructions or data that, in combination with the computer system, cause the computer system to operate. For example, a non-transitory computer-readable medium comprising a computer-readable medium that does not undergo a transformation during transmission is any medium that stores data that is not transmitted but is accessed by the computer system. Examples of non-transitory computer-readable media include random access memory (RAM), read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory, etc. In contrast, a transitory computer-readable medium is a computer-readable medium that undergoes a transformation during transmission. Examples of transitory computer-readable media include carrier waves, optical signals, and the like. The computer system can include a processor, a memory, and input and output devices. The memory stores computer-executable instructions or data that, in combination with the computer system, cause the computer system to operate. For example, the memory can store a computer program that, when executed by the computer system, causes the computer system to perform one or more processes.

[0132] Finally, it should be noted that the above merely illustrates the present application by way of example, and the scope of the present application is not limited thereto. Any person skilled in the art can easily make modifications or substitutions within the technical scope disclosed in the present application, and all such modifications or substitutions should be encompassed within the scope of the present application. Therefore, the scope of the present application should be determined by the scope of the claims.

Claims

1. A data processing method, characterized by, The method comprises: obtaining p first data streams subjected to Reed-Solomon (RS) encoding, p being a positive integer multiple of 4 and p being an integer power of 2; performing differential quadrature phase shift keying (DQPSK) mapping on the p first data streams to obtain a plurality of dual polarization (DP)-DQPSK signals, each of the DP-DQPSK signals comprising a DQPSK signal in a first polarization direction and a DQPSK signal in a second polarization direction.

2. The method of claim 1, wherein, The DQPSK mapping on the p first data streams to obtain the plurality of DP-DQPSK signals comprises: performing DQPSK mapping on the p first data streams to obtain q DP-DQPSK signals, q = p / 2 or q = p / 4.

3. The method of claim 2, wherein, p = 8, q = p / 2 = 4; or, p = 16, q = p / 4 = 4 or q = p / 2 = 8; or, p = 32, q = p / 4 = 8.

4. The method according to any one of claims 1 to 3, characterized in that, each of the first data streams is from a RS RS code word RS a RS is an integer power of 2 greater than or equal to 4.

5. The method according to any one of claims 1 to 4, characterized in that, The p first data streams are obtained from 16 second data streams subjected to physical media attachment (PMA) processing based on symbol multiplexing, the 16 second data streams being obtained from service data to be transmitted subjected to physical coding sublayer (PCS) processing comprising RS encoding.

6. The method of claim 5, wherein, The p first data streams are obtained from t signals subjected to t:p PMA processing, the t signals being obtained from the 16 second data streams subjected to 16:t PMA processing, t being a positive integer multiple of 4.

7. The method of claim 5, wherein, The p first data streams are obtained from the 16 second data streams subjected to 16:p PMA processing.

8. The method according to any one of claims 1 to 4, characterized in that, The p first data streams are obtained from t signals subjected to t:p PMA processing based on symbol multiplexing.

9. The method according to claim 6 or 8, characterized in that, t = 8, p = 8; or, t = 16, p = 8; or, t = 8, p = 16; or, t = 16, p = 16.

10. The method according to any one of claims 1 to 4, characterized in that, The p first data streams are obtained from service data to be transmitted subjected to PCS processing comprising RS encoding.

11. The method according to any one of claims 1 to 4, characterized in that, p＝8； The 4 first data streams in a first group of the p first data streams are obtained from 4 first signals subjected to 4:4 PMA processing, the 4 first signals being obtained from 32 third data streams subjected to 32:4 PMA processing, the 32 third data streams being obtained from first service data to be transmitted subjected to PCS processing comprising RS encoding. The 4 first data streams in a second group of the p first data streams are obtained from 4 second signals subjected to 4:4 PMA processing, the 4 second signals being obtained from 32 fourth data streams subjected to 32:4 PMA processing, the 32 fourth data streams being obtained from second service data to be transmitted subjected to PCS processing comprising RS encoding.

12. The method according to any one of claims 1 to 4, characterized in that, p＝8； The 2 first data streams in the first group of the p first data streams are obtained from 2 third signals subjected to 2:2 PMA processing, the 2 third signals being obtained from 16 fifth data streams subjected to 16:2 PMA processing, the 16 fifth data streams being obtained from third service data to be transmitted subjected to PCS processing comprising RS encoding. The 2 first data streams in the 2nd group of the p first data streams are obtained by 2:2 PMA processing on 2 fourth signals, the 2 fourth signals are obtained by 16:2 PMA processing on 16 sixth data streams, and the 16 sixth data streams are obtained by processing fourth service data to be transmitted by PCS including RS encoding; The 2 first data streams in the 3rd group of the p first data streams are obtained by 2:2 PMA processing on 2 fifth signals, the 2 fifth signals are obtained by 16:2 PMA processing on 16 seventh data streams, and the 16 seventh data streams are obtained by processing fifth service data to be transmitted by PCS including RS encoding; The 2 first data streams in the 4th group of the p first data streams are obtained by 2:2 PMA processing on 2 sixth signals, the 2 sixth signals are obtained by 16:2 PMA processing on 16 eighth data streams, and the 16 eighth data streams are obtained by processing sixth service data to be transmitted by PCS including RS encoding.

13. The method according to any one of claims 1 to 12, characterized in that, The data processing on the p first data streams includes DQPSK mapping to obtain q dual-polarization DP-DQPSK signals, including: DQPSK mapping is performed on every 2 first data streams in the p first data streams to obtain 1 DP-DQPSK signal, to obtain a total of q = p / 2 DP-DQPSK signals.

14. The method of claim 13, wherein, Each of the p first data streams is subjected to DQPSK mapping to obtain a DQPSK signal in one polarization direction of the 1 DP-DQPSK signal.

15. The method according to any one of claims 1 to 12, characterized in that, The data processing on the p first data streams includes DQPSK mapping to obtain q dual-polarization DP-DQPSK signals, including: DQPSK mapping is performed on every 4 first data streams in the p first data streams to obtain 1 DP-DQPSK signal, to obtain a total of q = p / 4 DP-DQPSK signals.

16. The method of claim 15, wherein, Each of the p first data streams is subjected to DQPSK mapping to obtain a DQPSK signal in one polarization direction of the 1 DP-DQPSK signal.

17. The method of any one of claims 1 to 16, wherein, The data processing method is applied to scenarios including Ethernet, optical transport network, and space optical communication.

18. The method of any one of claims 1 to 17, wherein, Every 4 adjacent RS symbols in each of the first data streams are respectively from 4 RS code words.

19. A data processing apparatus, characterized by The data processing apparatus includes an acquisition unit and a processing unit. The acquisition unit is configured to acquire p first data streams subjected to Reed-Solomon (RS) encoding, p is a positive integer multiple of 4, and p is an integer power of 2. The processing unit is configured to perform differential quadrature phase shift keying (DQPSK) mapping on the p first data streams to obtain multiple dual-polarization (DP) DQPSK signals, and each of the DP-DQPSK signals includes a DQPSK signal in a first polarization direction and a DQPSK signal in a second polarization direction.

20. The data processing apparatus according to claim 19, wherein, The processing unit is specifically configured to perform DQPSK mapping on the p first data streams to obtain q DP-DQPSK signals, q = p / 2 or q = p / 4.

21. The data processing apparatus according to claim 20, wherein, p = 8, q = p / 2 = 4; Or, p = 16, q = p / 4 = 4 or q = p / 2 = 8. Or, p = 32, q = p / 4 = 8.

22. The data processing apparatus according to any one of claims 19 to 21, wherein, Each 4 adjacent RS symbols in each of the first data streams are from 4 RS codewords respectively.

23. A chip, characterized by The chip is configured to perform the method of any one of claims 1-18.

24. An optical module characterized by comprising: The optical module comprises a processor configured to perform the method of any one of claims 1-18, and an interface configured to transceive signals.

25. A transmitting device, comprising: The transmitting device comprises a host-side device and the optical module of claim 24, wherein the optical module is configured to generate an optical signal based on data from the host-side device and transmit the optical signal.

26. A communication system, characterized by Comprising: The transmitting device of claim 25 and the receiving device, wherein the transmitting device is configured to transmit signals to the receiving device.

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