Time synchronization device, time synchronization system, time synchronization method, and program

Abstract

This time synchronization device is provided with: an internal clock and a slave clock; a frequency synchronization unit that synchronizes the frequency of the internal clock with the frequency of the master clock of a time master apparatus; a downlink time difference convergence unit that converges a downlink time difference which is the time difference between a packet transmission time from the time master apparatus and a packet reception time stamped by the internal clock; an uplink time difference convergence unit that converges an uplink time difference which is the time difference between a packet transmission time stamped by the internal clock and a packet reception time at the time master apparatus; and a time synchronization unit that synchronizes the time of the slave clock with the time of the master clock on the basis of the convergence result of the downlink time difference and the convergence result of the uplink time difference.

Description

Time synchronization device, time synchronization system, time synchronization method and program

[0001] The present disclosure relates to a time synchronization device, a time synchronization system, a time synchronization method, and a program.

[0002] As a protocol for time synchronization between devices, IEEE (Institute of Electrical and Electronics Engineers) 1588-2008 (IEEE1588v2) that defines the Precision Time Protocol (PTP) is known. As a related technique, for example, Patent Document 1 describes a technique for performing time synchronization with high precision in a time synchronization device that performs time synchronization using PTP without using a synchronous Ethernet signal (SyncE).

[0003] Patent No. 6198075

[0004] Related technologies such as those described in Patent Document 1 use a time synchronization protocol conforming to IEEE 1588-2008, which assumes that the upstream delay (STMD; Slave to Master Delay) and the downstream delay (MTSD; Master to Slave Delay) are the same. Therefore, if there is a difference between the upstream delay and the downstream delay, that difference appears as a time difference between the master clock and the slave clock.

[0005] In view of the above problems, one of the objects of the present disclosure is to provide a time synchronization device, a time synchronization system, a time synchronization method, and a program that are capable of reducing the time difference between a master clock and a slave clock.

[0006] A time synchronization device according to one aspect of the present disclosure comprises an internal clock and a slave clock, a frequency synchronization means for synchronizing the frequency of the internal clock with the frequency of a master clock of a time master device, a downstream time difference convergence means for converging a downstream time difference, which is the time difference between the packet transmission time from the time master device and the packet reception time stamped by the internal clock, an upstream time difference convergence means for converging an upstream time difference, which is the time difference between the packet transmission time stamped by the internal clock and the packet reception time at the time master device, and a time synchronization means for synchronizing the time of the slave clock with the time of the master clock based on the convergence results of the downstream time difference and the upstream time difference.

[0007] A time synchronization system according to one aspect of the present disclosure comprises an internal clock and a slave clock, a frequency synchronization means for synchronizing the frequency of the internal clock with the frequency of a master clock of a time master device, a downstream time difference convergence means for converging a downstream time difference, which is the time difference between the packet transmission time from the time master device and the packet reception time stamped by the internal clock, an upstream time difference convergence means for converging an upstream time difference, which is the time difference between the packet transmission time stamped by the internal clock and the packet reception time at the time master device, and a time synchronization means for synchronizing the time of the slave clock with the time of the master clock based on the convergence results of the downstream time difference and the upstream time difference.

[0008] A time synchronization method according to one aspect of the present disclosure synchronizes the frequency of an internal clock with the frequency of a master clock of a time master device, converges a downstream time difference, which is the time difference between the packet transmission time from the time master device and the packet reception time stamped by the internal clock, converges an upstream time difference, which is the time difference between the packet transmission time stamped by the internal clock and the packet reception time at the time master device, and synchronizes the time of a slave clock with the time of the master clock based on the convergence results of the downstream time difference and the upstream time difference.

[0009] A program according to one aspect of the present disclosure is a program for causing a computer to execute a process of synchronizing the frequency of an internal clock with the frequency of a master clock of a time master device, converging a downstream time difference, which is the time difference between the packet transmission time from the time master device and the packet reception time stamped by the internal clock, converging an upstream time difference, which is the time difference between the packet transmission time stamped by the internal clock and the packet reception time at the time master device, and synchronizing the time of a slave clock with the time of the master clock based on the convergence results of the downstream time difference and the upstream time difference.

[0010] According to the present disclosure, it is possible to reduce the time difference between the master clock and the slave clock.

[0011] FIG. 1 is a configuration diagram showing an example of the configuration of a time synchronization device according to a basic example. FIG. 1 is a configuration diagram showing an example of the configuration of a PTP frequency synchronization unit according to a basic example. FIG. 2 is a configuration diagram showing an example of the configuration of a packet filter processing unit according to a basic example. FIG. 3 is a configuration diagram showing an example of the configuration of a PTP time synchronization unit according to a basic example. FIG. 4 is a configuration diagram showing an example of the configuration of a time synchronization device according to some embodiments. FIG. 5 is a flowchart showing an example of a time synchronization method according to some embodiments. FIG. 6 is a flowchart showing an example of the operation of a time slave device according to some embodiments. FIG. 7 is a configuration diagram showing an example of the configuration of a time synchronization system according to some embodiments. FIG. 8 is a diagram showing the relationship between the clocks of the time master device and the time slave device according to some embodiments. FIG. 9 is a graph showing an example of the operation results of the MTSD servo and the STMD servo according to some embodiments. FIG. 10 is a graph showing another example of the operation results of the MTSD servo and the STMD servo according to some embodiments. FIG. 11 is a timing chart showing specific examples of the timing of the time master device and the time slave device according to some embodiments. FIG. 12 is a configuration diagram showing an example of the configuration of a PDV filter according to some embodiments. FIG. 13 is a configuration diagram showing an example of the configuration of an MTSD servo according to some embodiments. FIG. 14 is a configuration diagram showing an example of the configuration of an STMD servo according to some embodiments. FIG. 15 is a configuration diagram showing an example of the configuration of computer hardware according to some embodiments.

[0012] Hereinafter, embodiments will be described with reference to the drawings. In each drawing, the same elements are given the same reference numerals, and duplicate explanations will be omitted as necessary. Note that the arrows shown in each drawing are examples for explanation purposes and do not limit the type or direction of signals.

[0013] (Basic Example) First, a basic example that forms the basis of the embodiment will be described.

[0014] 1 shows an example of the configuration of a time synchronization device 500 according to the basic example. The time synchronization device 500 is a time slave device that performs time synchronization with a time master device using PTP.

[0015] In PTP, a t1 packet (Sync Message), a t2 packet (Follow-up Message), a t3 packet (Delay Request Message), and a t4 packet (Delay Response Message) are transmitted and received between a time master device and a time slave device, and the times of these transmissions and receptions are used. A downstream delay time (MTSD) is calculated from the difference between the time (t1) when the time master device transmits the t1 packet and the time (t2) when the time slave device receives the t1 packet, and an upstream delay time (STMD) is calculated from the difference between the time (t3) when the time slave device transmits the t3 packet and the time (t4) when the time master device receives the t3 packet, and time synchronization is performed based on these delay times.

[0016] The basic example is an example based on Patent Document 1, and has an internal clock that is frequency-synchronized with the time master device on the sending side, and although there is a time offset with the sending clock, it is used under conditions where frequency synchronization is established. Therefore, even if the internal clock is used to time input and output packets, delays cannot be determined, but it is possible to determine whether the packet arrival time is earlier or later than the previous value.

[0017] In the example of FIG. 1 , the time synchronization device 500 includes a PTP frequency synchronization unit 600 , a packet filter processing unit 700 , and a PTP time synchronization unit 800 .

[0018] The PTP frequency synchronization unit 600 is a PTP frequency servo that performs frequency synchronization with the time master device.

[0019] In the example of FIG. 2, the PTP frequency synchronization unit 600 includes a t2′ packet time stamp unit 610, a phase detector (PD) 620, an infinite impulse response (IIR) filter 630, a phase interpolation (PI) controller 640, and an internal clock 650.

[0020] The PTP frequency synchronization unit 600 controls the operation of the internal clock 650 with a PLL (Phase Locked Loop) using a phase comparator 620, an IIR filter 630, and a PI controller 640 so that the time difference (t2'-t1) between the packet transmission time (t1) from the time master device and the packet reception time (t2') stamped by the t2' packet stamping unit 610 using the internal clock 650 is constant. In other words, the PTP frequency synchronization unit 600 synchronizes the frequency of the output signal (time) of the internal clock 650 with the frequency of the output signal (time) of the time master device.

[0021] The packet filter processing unit 700 constitutes a packet delay variation (PDV) filter that determines packet delay variation using the time of the frequency-synchronized internal clock 650. The PTP frequency synchronization unit 600, packet filter processing unit 700, and PTP time synchronization unit 800 may be collectively referred to as the PDV filter. Fig. 3 shows an example of the configuration of the packet filter processing unit 700.

[0022] In the example of Figure 3, the packet filter processing unit 700 includes a t1 packet receiving unit 710, a Follow-up Message (t2 packet) receiving unit 711, a t3 packet transmitting unit 712, a t4 packet receiving unit 713, a t2' packet embossing unit 730, a t2'-t1 calculation unit 731, a t2'-t1 shortest time search and holding unit 732, a t2'-t1 correction unit 733, a t1 correction value update unit 734, a t3' packet embossing unit 740, a t4-t3' calculation unit 741, a t4-t3' shortest time search and holding unit 742, a t4-t3' correction unit 743, and a t4 correction value update unit 744.

[0023] The packet filter processing unit 700 corrects the packet transmission time (t1) based on the shortest time difference (t2'-t1; MTSD') between the packet transmission time (t1) from the time master device and the packet reception time (t2') stamped by the t2' packet stamping unit 730 using the internal clock 650. Specifically, the t2'-t1 shortest time search and storage unit 732 searches for the shortest time from the time difference (t2'-t1) calculated by the t2'-t1 calculation unit 731 and stores it. The t2'-t1 shortest time search and storage unit 732 separates and outputs the stored shortest time (min PDV) and other times (other min PDV). The t2'-t1 correction unit 733 generates a correction value for the downlink time based on the result of the t2'-t1 shortest time search and storage unit 732. The t2'-t1 correction unit 733 calculates a correction value from the difference between the shortest time (min PDV) and the time other than the shortest time (other min PDV) of the time difference (t2'-t1). The t1 correction value update unit 734 adds the correction value to the Correction Field of the t1 packet.

[0024] The packet filter processing unit 700 also corrects the packet reception time (t4) based on the shortest time difference (t4-t3'; STMD') between the packet transmission time (t3') stamped by the t3' packet stamping unit 740 using the internal clock 650 and the packet reception time (t4) at the time master device. Specifically, the t4-t3' shortest time search and storage unit 742 searches for and stores the shortest time from the time difference (t4-t3') calculated by the t4-t3' calculation unit 741. The t4-t3' shortest time search and storage unit 742 separates and outputs the stored shortest time (min PDV) and other times (other min PDV). The t4-t3' correction unit 743 generates a correction value for the uplink time based on the results of the t4-t3' shortest time search and storage unit 742. The t4-t3' correction unit 743 calculates a correction value from the difference between the shortest time (min PDV) and the time other than the shortest time (other min PDV) of the time difference (t4-t3'). The t4 correction value update unit 744 adds the correction value to the Correction Field of the t4 packet.

[0025] The PTP time synchronization unit 800 is a PTP time servo that performs time synchronization with the time master device. FIG. 4 shows an example of the configuration of the PTP time synchronization unit 800.

[0026] In the example of Figure 4, the PTP time synchronization unit 800 includes an OCXO (Oven Controlled Crystal Oscillator) 810, a slave clock 820, a t2 packet time-stamping unit 830, a t2-t1 calculation unit 831, a t3 packet time-stamping unit 832, a t4-t3 calculation unit 833, a complementation unit 834, an adder 835, and a PI controller 836.

[0027] The PTP time synchronization unit 800 calculates a downstream delay time (t2-t1; MTSD) from the packet transmission time (t1) corrected by the packet filter processing unit 700 and the packet reception time (t2) stamped by the t2 packet stamping unit 830 using the slave clock 820, and calculates an upstream delay time (t4-t3; STMD) from the packet transmission time (t3) stamped by the slave clock 820 and the packet reception time (t4) corrected by the packet filter processing unit 700 using the complementation unit 834, adder 835, and PI controller 836 to PLL-control the operation of the slave clock 820 so that the downstream delay time (t4-t3) and the upstream delay time (t2-t1) are equal. In other words, the PTP time synchronization unit 800 synchronizes the output signal (time) of the slave clock 820 with the output signal (time) of the time master device.

[0028] In this way, in the basic example, frequency synchronization is performed before time synchronization, and an internal clock is generated from the reproduced frequency. The internal clock then stamps the packet arrival time (t2') and packet transmission time (t3'). Based on the shortest MTSD' and shortest STMD' times, the difference between MTSD' and t2' calculated from the packet transmitted each time and the difference between MTSD' and STMD' is stored in the Correction Field area of ​​IEEE 1588-2008, and time synchronization is performed using the shortest delay time.

[0029] As in the basic example, the relevant time synchronization method uses a time synchronization protocol conforming to IEEE 1588-2008. However, IEEE 1588-2008 is a protocol that assumes that the upstream and downstream delays are identical. Therefore, if there is a difference between the upstream and downstream delays, that difference appears as a time difference. Strictly speaking, the time is degraded by half a minute of the delay difference. Currently, international recommendations define time correction using Assisted Partial Timing, which uses absolute time such as the Global Navigation Satellite System (GNSS). However, using GNSS is difficult in terms of functional implementation, operation, and security. Furthermore, since the problem of delay difference cannot be avoided even with protocols other than IEEE 1588, it is extremely difficult to devise a new protocol.

[0030] Therefore, in this embodiment, based on the configuration of the basic example, the problem of time correction when the upstream delay and downstream delay are asymmetrical is solved, making it possible to suppress the time difference between the master clock and the slave clock to zero.

[0031] (First Embodiment) Next, a first embodiment will be described. In this embodiment, an outline of several embodiments will be described.

[0032] 5 shows an example of the configuration of a time synchronization device 10 according to some embodiments. The time synchronization device 10 is a time slave device (time slave device) that performs time synchronization with a time master device (time master device). The time synchronization device 10 may be a wireless time synchronization device that performs wireless communication with the time master device, or a wired time synchronization device that performs wired communication with the time master device.

[0033] 5 , the time synchronization device 10 includes an internal clock 11, a slave clock 12, a frequency synchronization unit 13, a downstream time difference convergence unit 14, an upstream time difference convergence unit 15, and a time synchronization unit 16. For example, the internal clock 11 is included in the frequency synchronization unit 13. The slave clock 12 is included in the time synchronization unit 16.

[0034] The frequency synchronization unit 13 synchronizes the frequency of the internal clock with the frequency of the master clock of the time master device. For example, the frequency synchronization unit 13 corresponds to the PTP frequency synchronization unit 600.

[0035] The downstream time difference convergence unit 14 converges the downstream time difference, which is the time difference (MTSD') between the packet transmission time from the time master device and the packet reception time stamped by the internal clock 11. For example, the downstream time difference convergence unit 14 may acquire the time difference from the packet filter processing unit 700. The downstream time difference convergence unit 14 may converge the downstream time difference based on the provisional upstream time difference and the repeatedly measured downstream time difference. For example, the downstream time difference convergence unit 14 may be configured by a time servo and include a clock for downstream time difference convergence, a measurement unit for measuring the downstream time difference, and a comparison unit for controlling the clock for downstream time difference convergence in accordance with the comparison result between the provisional upstream time difference and the measured downstream time difference.

[0036] The upstream time difference convergence unit 15 converges the upstream time difference, which is the time difference (STMD') between the packet transmission time stamped by the internal clock 11 and the packet reception time at the time master device. The upstream time difference convergence unit 15 may acquire the time difference from the packet filter processing unit 700. The upstream time difference convergence unit 15 may converge the upstream time difference based on the provisional downstream time difference and the repeatedly measured upstream time difference. For example, the upstream time difference convergence unit 15 may be configured with a time servo and include a clock for upstream time difference convergence, a measurement unit for measuring the upstream time difference, and a comparison unit for controlling the clock for upstream time difference convergence in accordance with the comparison result between the provisional downstream time difference and the measured upstream time difference.

[0037] The time synchronization unit 16 synchronizes the time of the slave clock 12 with the time of the master clock based on the convergence result of the downstream time difference by the downstream time difference convergence unit 14 and the convergence result of the upstream time difference by the upstream time difference convergence unit 15. For example, the time synchronization unit 16 corresponds to the PTP time synchronization unit 800.

[0038] The time synchronization device 10 may also include a calculation unit that calculates a time correction value based on the convergence result of the downlink time difference and the convergence result of the uplink time difference. In this case, the time synchronization unit 16 may synchronize the time of the slave clock with the time of the master clock based on the calculated time correction value. The calculation unit may calculate the time difference between the master clock and the internal clock by adding half of the convergence result of the downlink time difference and half of the convergence result of the uplink time difference, and calculate the time correction value based on this time difference. The calculation unit may calculate a downlink delay time based on the time difference between the master clock and the internal clock and the downlink time difference, calculate an uplink delay time based on the time difference between the master clock and the internal clock and the uplink time difference, and calculate the time correction value based on the downlink delay time and the uplink delay time. For example, the time synchronization unit 16 may correct either the time difference between the packet transmission time from the time master device and the packet reception time stamped by the slave clock, or the time difference between the packet transmission time stamped by the slave clock and the packet reception time at the time master device, using a time correction value, and synchronize the time of the slave clock with the time of the master clock.

[0039] Note that each unit in the time synchronization device 10 may be included in one device or multiple devices, or may be included in a time synchronization system including one device or multiple devices. That is, the time synchronization system may include the internal clock 11, the slave clock 12, the frequency synchronization unit 13, the downstream time difference convergence unit 14, the upstream time difference convergence unit 15, and the time synchronization unit 16. The units in the time synchronization device 10 may be distributed. For example, the time synchronization device 10 may include the internal clock 11, the slave clock 12, the frequency synchronization unit 13, and the time synchronization unit 16, and another device may include the downstream time difference convergence unit 14 and the upstream time difference convergence unit 15.

[0040] 6 shows an example of a time synchronization method according to some embodiments. For example, the time synchronization method according to some embodiments is performed by the time synchronization device 10 of FIG.

[0041] 6, first, the frequency synchronization unit 13 synchronizes the frequency of the internal clock 11 with the frequency of the clock of the time master device. (S11) For example, the frequency synchronization unit 13 performs frequency synchronization with the time master device in the same manner as the PTP frequency synchronization unit 600.

[0042] Next, the downstream time difference convergence unit 14 converges the downstream time difference (S12), which is the time difference (MTSD') between the packet transmission time from the time master device and the packet reception time stamped by the internal clock 11. For example, the downstream time difference convergence unit 14 converges the downstream time difference by a time servo operation based on the provisional upstream time difference and the repeatedly measured downstream time difference.

[0043] Next, the upstream time difference convergence unit 15 converges the upstream time difference, which is the time difference (STMD') between the packet transmission time stamped by the internal clock 11 and the packet reception time at the time master device (S13). For example, the upstream time difference convergence unit 15 converges the upstream time difference by time servo operation based on the provisional downstream time difference and the repeatedly measured upstream time difference.

[0044] Next, the time synchronization unit 16 synchronizes the time of the slave clock 12 with the time of the master clock based on the convergence results of the downstream time difference and the upstream time difference (S14). For example, the time synchronization unit 16 synchronizes the time of the slave clock 12 with the time of the master clock using a time correction value based on the convergence results of the downstream time difference and the upstream time difference.

[0045] As described above, in this embodiment, in a time synchronization device based on the configuration of the basic example, the downstream time difference (MTSD') and the upstream time difference (STMD') are converged, and time synchronization is performed based on the convergence results. This makes it possible to reduce the time difference between the master clock and the slave clock. In other words, the actual delay can be determined from the convergence results of MTSD' and STMD', and time synchronization is performed using a time correction value based on the actual delay, thereby making it possible to reduce the time difference between the master clock and the slave clock to zero.

[0046] Second Embodiment Next, a second embodiment will be described. In this embodiment, a specific example of the first embodiment will be described.

[0047] <Operational Example> First, an operational example of the time slave device 100 according to some embodiments will be described. Fig. 7 shows an operational example of the time slave device 100. Fig. 8 shows an example of the configuration of a time synchronization system 1 including the time slave device 100. For example, the time synchronization system 1 includes a time slave device 100 and a time master device 200. The time slave device 100 includes a PDV filter 110, an MTSD servo 120, an STMD servo 130, and a correction value calculation unit 140. Each component will be described later. The PDV filter 110 has the same configuration as in the basic example.

[0048] 7, the time slave device 100 provisionally loads the internal clock 650 with the t1 packet (S101). First, the t1 packet receiver 710 receives the t1 packet from the time master device 200 and sets the time (timestamp) of the received t1 packet in the internal clock 650.

[0049] Next, the time slave device 100 operates the PDV filter 110 to obtain provisional MTSD' and STMD' (provisional PDV values) (S102). The t2'-t1 shortest time search and hold unit 732 and the t4-t3' shortest time search and hold unit 742 select the shortest provisional MTSD' and STMD' values ​​from the MTSD' and STMD' values ​​calculated by the t2'-t1 calculation unit 731 and the t4-t3' calculation unit 741. For example, the initial values ​​of provisional MTSD' and STMD' may be the values ​​calculated initially or the shortest time within a predetermined period of time. The t2'-t1 shortest time search and hold unit 732 and the t4-t3' shortest time search and hold unit 742 store the selected provisional MTSD' and STMD' values. The packet filter processing unit 700 determines the MTSD correction value and the STMD correction value by using the held provisional MTSD' and STMD' as the shortest time. The PTP time synchronization unit 800 performs time synchronization using the MTSD correction value and the STMD correction value.

[0050] Next, the time slave device 100 waits until the PTP time servo is synchronized (S103). The time slave device 100 waits until time synchronization is stable in order to start the operation of the MTSD servo 120 and the STMD servo 130. For example, the time slave device 100 may wait until the proportional term of the transfer function in the PLL control of the PTP time servo (PTP time synchronization unit 800) becomes zero. For example, the time slave device 100 may include a storage unit that stores a synchronization flag, and may set the synchronization flag to ON when the PTP time servo is synchronized.

[0051] Next, the time slave device 100 passes the provisional MTSD' and STMD' to the MTSD servo 120 and the STMD servo 130 (S104). After the PTP time servo is synchronized (for example, after the synchronization flag is turned on), the t2'-t1 shortest time search and hold unit 732 and the t4-t3' shortest time search and hold unit 742 output the held provisional MTSD' and STMD' to the MTSD servo 120 and the STMD servo 130.

[0052] Next, the time slave device 100 operates the MTSD servo 120 (S105). When the provisional MTSD' and STMD' are given in S104, the original MTSD' can be calculated from the provisional MTSD' by servo operation. Therefore, the MTSD servo 120 performs one-way time servo operation based on the actually measured MTSD' and the acquired provisional STMD'. The MTSD servo 120 outputs the converged result (PDVmtsd) of the time servo operation to the correction value calculation unit 140. Because the convergence result of the MTSD servo 120 includes half of the internal clock, the correction value calculation unit 140 holds half of the convergence result.

[0053] Next, the time slave device 100 operates the STMD servo 130 (S106). When the provisional MTSD' and STMD' are provided in S104, the original STMD' can be determined from the provisional STMD' through servo operation. Therefore, the STMD servo 130 performs a one-way time servo operation based on the actually measured STMD' and the acquired provisional MTSD'. Note that while two-way time servo processing is also possible, one-way processing is preferable considering the implementation scale and processing speed. The STMD servo 130 outputs the converged result (PDVstmd) of the time servo operation to the correction value calculation unit 140. Because the converged result of the STMD servo 130 includes half of the internal clock, the correction value calculation unit 140 holds half of the converged result.

[0054] Next, the time slave device 100 calculates the original delay from the operation results of the MTSD servo 120 and the STMD servo 130 (S107). The correction value calculation unit 140 adds the information about the MTSD servo 120 obtained in S105 (half of the convergence result) and the information about the STMD servo 130 obtained in S106 (half of the convergence result) to calculate the time difference between the master clock and the internal clock. The correction value calculation unit 140 calculates the original delay from the provisional MTSD' and STMD' obtained in S104 and the calculated time difference between the master clock and the internal clock.

[0055] Next, the time slave device 100 sets the Correction Field based on the calculated original delay (S108). The correction value calculation unit 140 outputs the calculated original delay as a correction value to the t1 correction value update unit 734 or the t4 correction value update unit 744. The t1 correction value update unit 734 or the t4 correction value update unit 744 adds the correction value to the Correction Field of the t1 packet or the t4 packet.

[0056] By performing the above processing, the time difference between the master clock and the slave clock can be made zero. Basically, this processing needs to be performed only once, but if this processing is not performed periodically in case the master clock is changed or frequency synchronization cannot be ensured, the slave time may become out of sync. For this reason, the user may set a periodic processing time and perform the processing in Figure 7 periodically.

[0057] <Specific Example> Next, a specific example of a time synchronization method according to some embodiments will be described. Fig. 9 shows the relationship between the master clock of the time master device 200 and the internal clock of the time slave device 100. When a t1 packet is transmitted from the time master device 200 (time X of the master clock), it arrives at the time slave device 100 (time X' of the internal clock) after a certain delay. If t2' is stamped using the internal clock and the time difference (MTSD' = PDVmtsd) is measured, the following relationship holds: t2' = Delay + (X - X') = PDVmtsd ... Equation (1)

[0058] X-X' is the time difference between the master clock and the internal clock. In other words, from equation (1), if the difference between the master clock (reference clock) and the internal clock is known, the actual delay can be determined. In this embodiment, this relationship is used to enable asymmetric delay correction.

[0059] To achieve this, time synchronization can be achieved using the values ​​of PDVmtsd (MTSD') and PDVstmd (STMD') obtained from the PDV filter 110. However, since the PDV value is a fixed value, it is not possible to generate a clock. Therefore, in this embodiment, as will be described later with reference to Figures 14 and 15, time servos (MTSD servo 120 and STMD servo 130) are configured using the original delay and PDV value. This means that by setting one of the time servos to the PDV value and the other to the original delay, synchronization is achieved at half the time of the internal clock. By operating these time servos independently at MTSD and STMD and then adding up the halves of the time, the time difference between the master clock and the slave internal clock can be determined.

[0060] FIG. 10 shows an example of the operation results of the MTSD servo 120 and the STMD servo 130. The horizontal axis represents time, and the numbers represent clock count values. Here, one count is 16 ms (i.e., 50 is 16 ms x 50 = 80 ms). In the example of FIG. 10, the servo value of the MTSD servo 120 (the difference between the PDV value on the STMD side and the original delay on the MTSD side) converges to 13 μs. For example, in the MTSD servo 120, if the PDV value on the STMD side is "248" and the original delay on the MTSD side is "261," the servo value becomes 13 μs. Furthermore, the servo value of the STMD servo 130 (the difference between the PDV value on the MTSD side and the original delay on the STMD side) converges to 7 μs. For example, in the STMD servo 130, if the PDV value on the MTSD side is "251" and the original delay on the STMD side is "258," the servo value will be 7 μs. In this case, the time difference between the master clock and the internal clock will be "10 μs," which is 1 / 2 of 13 + 7 = 20. This value appears as a numerical value within the servo, so there is no need to measure it on a waveform.

[0061] 11 shows another example of the operation results of the MTSD servo 120 and the STMD servo 130 (the horizontal axis is the same as in FIG. 10). In the example of FIG. 11, the servo value of the MTSD servo 120 converges to 18 μs. Also, the servo value of the STMD servo 130 converges to 12 μs. In this case, the time difference between the master clock and the internal clock is 15 μs, which is 1 / 2 of 18 + 12 = 30.

[0062] The timing chart in Figure 12 shows the timing when the servo value (PDVmtsd) on the MTSD side is 13 μs, the servo value (PDVstmd) on the STMD side is 7 μs, and the time difference between the master clock and the internal clock is 10 μs, as shown in the example in Figure 10.

[0063] In this embodiment, since the difference with the internal clock cannot be calculated when time is synchronized in both directions, both the MTSD and STMD operate the servos in 1-way mode. In this case, the STMD side is in the opposite direction, so the actual delay appears to be in the positive direction. Therefore, if the time difference is known, the MTSD side adds the internal clock minutes (difference) and the STMD side subtracts the internal clock minutes (difference), thereby making it possible to calculate the actual delay.

[0064] For example, if the PDV value on the MTSD side is "251," and the difference between the master clock and the internal clock is "10" as shown in Figure 12, then the actual delay is "261." This value is known to the servo on the slave side, but is not actually expressed numerically. Similarly, if the PDV value on the STMD side is "248," and the difference between the master clock and the internal clock is "10," then the actual delay is "238." From the above, the time difference between the master and slave is 261 - 238 = 1 / 2 of 23, or "11.5 nanoseconds." By correcting this value using the Correction Field in the PTP, the time difference between the master and slave can be reduced to "zero."

[0065] <Configuration Example> Next, a configuration example of a time synchronization system 1 according to several embodiments will be described. As shown in Fig. 8, the time synchronization system 1 includes a time slave device 100 and a time master device 200. The time synchronization system 1 is a system that performs time synchronization between the time slave device 100 and the time master device 200 using PTP. The time slave device 100 and the time master device 200 may be wireless communication devices capable of wireless communication, or may be wired communication devices capable of wired communication.

[0066] The time master device 200 is a time synchronization device that operates as a master in PTP time synchronization. The time master device 200 transmits and receives PTP packets to and from the time slave device 100 via a wireless transmission path or a wired transmission path.

[0067] The time slave device 100 is a time synchronization device that operates as a slave in PTP time synchronization. The time slave device 100 transmits and receives PTP packets to and from the time master device 200 via a wireless transmission path or a wired transmission path. The time slave device 100 includes a PDV filter 110, an MTSD servo 120, an STMD servo 130, and a correction value calculation unit 140. The MTSD servo 120, the STMD servo 130, and the correction value calculation unit 140 are not limited to being located inside the time slave device 100, but may also be located outside the time slave device 100. For example, the MTSD servo 120, the STMD servo 130, and the correction value calculation unit 140 may be located in a cloud-based computer system.

[0068] The PDV filter 110 is a time synchronization unit that includes a packet filter, similar to the basic example in Fig. 1. As will be described later, the PDV filter 110, like the basic example, includes a PTP frequency synchronization unit 600, a packet filter processing unit 700, and a PTP time synchronization unit 800. The time slave device 100 includes three PTP time servos: the PTP time synchronization unit 800 of the PDV filter 110, an MTSD servo 120, and an STMD servo 130. The three time servos may be implemented independently, or one time servo may implement the three functions.

[0069] The PDV filter 110 loads the time of the t1 packet into the internal clock 650 and synchronizes the frequency of the internal clock 650 with the frequency of the time master device 200. The PDV filter 110 calculates the time difference (MTSD') between the packet transmission time (t1) from the time master device 200 and the packet reception time (t2') stamped by the internal clock 650, and stores a provisional MTSD' (provisional shortest time). It also calculates the time difference (STMD') between the packet transmission time (t3') stamped by the internal clock 650 and the packet reception time (t4) at the time master device 200, and stores the provisional STMD' (provisional shortest time). The PDV filter 110 outputs the provisional MTSD' and STMD' to the MTSD servo 120 and the STMD servo 130. The PDV filter 110 acquires the correction value calculated by the correction value calculation unit 140, stores the acquired correction value in the Correction Field, and performs time synchronization with the time master device 200. The PDV filter 110 may output an OFM (Offset From Master) from the time of the time master device 200 and the time of the time slave device 100. Note that the time slave device 100 performs time correction using the PDV filter 110 itself, and therefore is completely independent of the physical layer (wired, wireless, etc.) of the PTP packet.

[0070] The MTSD servo 120 acquires the provisional MTSD' (PDVmtsd) and STMD' (PDVstmd) from the PDV filter 110, and converges the MTSD' by time servo operation. The MTSD servo 120 converges the MTSD' based on the provisional STMD' and the MTSD' that is actually measured repeatedly, and outputs the convergence result (PDVstmd) to the correction value calculation unit 140.

[0071] The STMD servo 130 acquires the provisional MTSD' (PDVmtsd) and STMD' (PDVstmd) from the PDV filter 110, and converges the STMD' by time servo operation. The STMD servo 130 converges the STMD' based on the provisional MTSD' and the STMD' that is actually measured repeatedly, and outputs the convergence result (PDVstmd) to the correction value calculation unit 140.

[0072] The correction value calculation unit 140 calculates a correction value to be used in the PDV filter 110 based on the convergence result of the MTSD' (PDVmtsd) obtained by the MTSD servo 120 and the convergence result of the STMD' (PDVstmd) obtained by the STMD servo 130. The correction value calculation unit 140 calculates the time difference between the master clock and the internal clock based on the acquired convergence results of the MTSD' and STMD', calculates the original delay from the time difference, and calculates a correction value based on the original delay.

[0073] 13 shows an example of the configuration of the PDV filter 110 according to some embodiments, and in particular shows an example of the configuration of the packet filter processing unit 700. The PDV filter 110 includes a PTP frequency synchronization unit 600, a packet filter processing unit 700, and a PTP time synchronization unit 800, similar to the basic example in FIG.

[0074] The PTP frequency synchronization unit 600 has the same configuration as that shown in FIG. 2 , and the PTP time synchronization unit 800 has the same configuration as that shown in FIG. 4 . As described above, the PTP frequency synchronization unit 600 and the PTP time synchronization unit 800 each have an internal clock 650 and a slave clock 820 as independent clocks (PTP Epoch Counters). The reason for having independent clocks is that each clock has a different purpose. As described above, the internal clock 650 of the PTP frequency synchronization unit 600 is a clock used to determine the quality of received packets, and is generated based on the jitter-wonder-free clean clock output from the OCXO 810. As its name suggests, the slave clock 820 of the PTP time synchronization unit 800 is a clock used to synchronize the time with the master time. The slave clock 820 is a so-called time synchronization clock and serves as a clock within the device.

[0075] In the example of Figure 13, the packet filter processing unit 700 has the same configuration as in Figure 3, but the outputs of the t2'-t1 shortest time search and hold unit 732 and the t4-t3' shortest time search and hold unit 742 and the inputs of the t1 correction value update unit 734 and the t4 correction value update unit 744 are different.

[0076] The basic operation of the packet filter processing unit 700 will be described. First, in the downstream direction, the t1 packet receiving unit 710 receives a Sync message (t1 packet) from the time master device 200. The t2' packet stamping unit 730 stamps the time at which the t1 packet receiving unit 710 receives the t1 packet using the internal clock 650 generated by the PTP frequency synchronization unit 600, and sets this time as t2' time. The t2'-t1 calculation unit 731 obtains the t1 time from the Follow-up Message received by the Follow-up Message receiving unit 711, and calculates the difference between the stamped t2' time and the obtained t1 time (t2'-t1; MTSD').

[0077] Note that, since the explanation here is based on the 2-step (2-way) method that is common in IEEE 1588v2, the value obtained from the Follow-up Message by the Follow-up Message receiving unit 711, which is the true time of t1, is set as the t1 time, but either the 1-step (1-way) method or the 2-step method may be adopted. The 1-step method is the same as the 2-step method, except that information on the t1 time is included in the t1 packet.

[0078] The t2'-t1 calculation unit 731 outputs the calculated t2'-t1 (MTSD') to the t2'-t1 shortest time search and hold unit 732. The t2'-t1 shortest time search and hold unit 732 finds the shortest time from the time difference (t2'-t1) calculated by the t2'-t1 calculation unit 731 and holds a provisional MTSD' (shortest time). The t2'-t1 shortest time search and hold unit 732 separates the held shortest time (min PDV) from times other than the shortest (other min PDV; for example, the calculated MTSD'), and outputs them to the t2'-t1 correction unit 733. The t2'-t1 shortest time search and hold unit 732 also outputs the held provisional MTSD' to the MTSD servo 120 and the STMD servo 130.

[0079] The t2'-t1 correction unit 733 (downstream time correction unit) calculates a correction value for MTSD based on the shortest MTSD' time (provisional MTSD') and a time other than the shortest time output from the t2'-t1 shortest time search and hold unit 732. The t2'-t1 correction unit 733 uses the difference between the shortest MTSD' time (provisional MTSD') and a time other than the shortest time as a correction value. The t1 correction value update unit 734 adds the correction value calculated by the t2'-t1 correction unit 733 to the Correction Field of the t1 packet. In addition, the t1 correction value update unit 734 acquires the correction value calculated by the correction value calculation unit 140 and adds the acquired correction value to the Correction Field of the t1 packet.

[0080] In the upstream direction, the t3' packet stamping unit 740, as in the downstream direction, stamps the transmission time of the t3 packet transmitted from the PTP time synchronization unit 800 using the internal clock 650 generated by the PTP frequency synchronization unit 600, and sets this time as the t3' time. The stamped t3' time is used only by the packet filter processing unit 700, and is not overwritten on the t3 time in the original t3 packet. Therefore, the t3 packet transmitting unit 712 transmits the packet from the PTP time synchronization unit 800 as a Delay Request Message (t3 packet) to the time master device 200 as is.

[0081] The t4 packet receiver 713 receives a t4 (Delay Response Message) packet transmitted from the time master device 200. The t4-t3' calculation unit 741 acquires the t4 time from the t4 packet received by the t4 packet receiver 713, and calculates the difference between the acquired t4 time and the stamped t3' time (t4-t3'; STMD').

[0082] The t4-t3' calculation unit 741 outputs the calculated t4-t3' (STMD') to the t4-t3' shortest time search and hold unit 742. The t4-t3' shortest time search and hold unit 742 finds the shortest time from the time difference (t4-t3') calculated by the t4-t3' calculation unit 741, and holds a provisional STMD' (shortest time). The t4-t3' shortest time search and hold unit 742 separates the held shortest time (min PDV) from times other than the shortest (other min PDV), and outputs them to the t4-t3' correction unit 743. The t4-t3' shortest time search and hold unit 742 also outputs the held provisional STMD' to the MTSD servo 120 and the STMD servo 130.

[0083] The t4-t3' correction unit 743 (upstream time correction unit) calculates a correction value for the STMD based on the shortest time of the STMD' (provisional STMD') and a time other than the shortest time output from the t4-t3' shortest time search and holding unit 742. The t4-t3' correction unit 743 uses the difference between the shortest time of the STMD' (provisional STMD') and a time other than the shortest time as a correction value. The t4 correction value update unit 744 adds the correction value calculated by the t4-t3' correction unit 743 to the Correction Field of the t4 packet. In addition, the t4 correction value update unit 744 acquires the correction value calculated by the correction value calculation unit 140 and adds the acquired correction value to the Correction Field of the t4 packet.

[0084] As described above, time synchronization with a certain time difference becomes possible by provisionally acquiring a time packet and correcting the time based on that packet.

[0085] Furthermore, from the above explanation, the t2' packet embossing unit 730 and the t3' packet embossing unit 740 of the packet filter processing unit 700 require a clock that is frequency-synchronized with the time master device 200 and is jitter- and wander-free. The reason for this is that if frequency synchronization is not achieved, an error will occur in each embossed time, and if there is jitter or wander, the wrong time will be embossed even if frequency synchronization is achieved.

[0086] Therefore, similar to the basic example, frequency synchronization with the time master device and jitter- and wonder-free clock reproduction are achieved by implementing a PTP frequency synchronization unit 600. The configuration of the PTP frequency synchronization unit 600 is as shown in FIG.

[0087] The basic operation of the PTP frequency synchronization unit 600 will be described. First, the t2' packet stamping unit 610 stamps the time when the t1 packet is received by the t1 packet receiving unit 710 using the internal clock 650, and designates this time as t2'. Next, the phase comparator 620 extracts the t1 time from the follow-up message received by the follow-up message receiving unit 711 and compares the t1 time with the t2' time (i.e., performs a phase comparison). The phase comparator 620 can also be said to compare the t1 time with the time (=phase) from a time counter (internal clock 650) comprised of a DCO (digital oscillator). The differential signal resulting from this comparison is filtered by the IIR filter 630, which removes jitter and noise to produce a smoothed differential signal. The smoothed differential signal is then proportionally and integrally processed by the PI controller 640, which outputs the resulting control signal to the DCO in the internal clock 650, ultimately converging the differential signal to a constant value. This allows frequency synchronization to be achieved.

[0088] The master oscillator (clock CLK) of the DCO in the internal clock 650 is an external OCXO 810. The reason for using an OCXO is that by minimizing the frequency drift of the DCO, it becomes possible to lower the DC loop gain of the PTP frequency synchronization unit 600, thereby enabling the reproduction of a highly accurate clock. Why a DCO is used, why PI control is necessary, and the PI control method for the DCO are all the same as for a normal digital PLL.

[0089] The PTP time synchronization unit 800 has a general configuration for performing time synchronization by PTP. For example, the configuration of the PTP time synchronization unit 800 is as shown in FIG.

[0090] The basic operation of the PTP time synchronization unit 800 will be described. First, a slave clock 820 is constructed based on the clock CLK of the OCXO 810, which is the reference oscillation source. The t2 packet stamping unit 830 stamps the time when the t1 packet receiving unit 710 receives the t1 packet using the slave clock 820, and sets this time as t2 time. After receiving the t1 packet, the t3 packet stamping unit 832 stamps the time when the t3 packet is transmitted using the slave clock 820, and sets this time as t3 time. The t3 packet stamping unit 832 inserts this time into the t3 packet, and transmits it from the t3 packet transmitting unit 712 to the time master device 200.

[0091] The t2-t1 calculation unit 831 obtains the time t1 from the Follow-up Message received by the Follow-up Message receiving unit 711, and calculates the difference (t2-t1; MTSD) between the stamped time t2 and the obtained time t1. At this time, the t2-t1 calculation unit 831 calculates the time difference using the Correction Field of the t1 packet updated by the packet filter processing unit 700.

[0092] The t4-t3 calculation unit 833 acquires the t4 time from the t4 packet received by the t4 packet receiving unit 713, and calculates the difference between the acquired t4 time and the stamped t3 time (t4-t3; STMD). At this time, the t4-t3 calculation unit 833 calculates the time difference using the Correction Field of the t4 packet updated by the packet filter processing unit 700.

[0093] In order to perform PLL control so that the values ​​of t2-t1 (MTSD) and t4-t3 (STMD) are the same, the two's complement of STMD (-STMD) is calculated by a complementing unit 834, and MTSD and -STMD are added by an adder 835. The result of the addition is subjected to proportional and integral processing by a PI controller 836, and the digital oscillator (DCO) in the slave clock 820 is PLL-controlled based on the phase (time) data generated by the PI controller 836. This series of processes is known as time servo processing in PTP.

[0094] 14 shows an example of the configuration of an MTSD servo 120 according to some embodiments. In the example of Fig. 14, the MTSD servo 120 includes an STMD holding unit 121, an MTSD measuring unit 122, a delay difference comparing unit 123, and an MTSD slave clock 124.

[0095] The MTSD servo 120 configures a time servo using the original delay on the MTSD side and the PDV value on the STMD side. In the MTSD servo 120, one of the time servos is the fixed PDV value on the STMD side (STMD holding unit 121), and the other is the original delay on the MTSD side (MTSD measurement unit 122). The STMD holding unit 121 counts up according to the granularity of the internal clock. The delay difference comparison unit 123 compares the fixed PDV value on the STMD side with the original delay on the MTSD side, and adjusts the MTSD slave clock 124. The MTSD slave clock 124 controls addition to the time t2' of the MTSD measurement unit 122. The servo value of the MTSD servo 120 is the difference between the PDV value on the STMD side and the original delay on the MTSD side.

[0096] 15 shows an example of the configuration of an STMD servo 130 according to some embodiments. In the example of Fig. 15, the STMD servo 130 includes an MTSD holding unit 131, an STMD measuring unit 132, a delay difference comparing unit 133, and an STMD slave clock 134.

[0097] The STMD servo 130 configures a time servo using the original delay on the STMD side and the PDV value on the MTSD side. In the STMD servo 130, one of the time servos is the MTSD side fixed PDV value (MTSD holding unit 131), and the other is the original delay on the STMD side (STMD measurement unit 132). The MTSD holding unit 131 counts up according to the granularity of the internal clock. The delay difference comparison unit 133 compares the MTSD side fixed PDV value with the original delay on the STMD side, and adjusts the STMD slave clock 134. The STMD slave clock 134 controls addition to the time t3' of the STMD measurement unit 132. The servo value of the STMD servo 130 is the difference between the MTSD side PDV value and the original delay on the STMD side.

[0098] As described above, in this embodiment, frequency synchronization is performed before time synchronization, and an internal clock is generated from the recovered frequency. This internal clock then stamps the packet arrival time (t2) and packet transmission time (t3'). Provisional MTSD' and STMD' are then stored. Using these provisional values ​​as a reference, the differences between the MTSD' and STMD' calculated from t2' and t3' of each transmitted packet and the differences between the MTSD' and STMD' are stored in the Correction Field area, thereby enabling synchronization at a certain provisional time. This embodiment utilizes the idea that if the time difference between the master clock and the internal clock is known from the provisional MTSD' and STMD', the actual delay can be calculated from the provisional MTSD' and STMD'. In other words, by calculating the difference between the master clock and the internal clock from the provisional MTSD' and STMD', the actual delay can be calculated from the provisional MTSD' and STMD', and therefore the time difference can also be calculated. This time difference is then stored in the Correction Field area.

[0099] Furthermore, to calculate the time difference between the master clock and the internal clock, the idea that the MTSD side and the STMD side can each calculate the time based on half the internal clock using one-way time servo is utilized. Servo-processing the delay based on the master time and the time based on the internal clock means that the calculated time corresponds to half the internal clock. In this embodiment, in the asymmetric correction time synchronization method, half of the time difference between the master clock and the internal clock is generated from the time servo on the PDVmtsd side based on the PDV value generated by the PDV filter, and half of the time difference between the master clock and the internal clock is also generated from the time servo on the PDVstmd side. This makes it possible to calculate the time difference between the master clock and the internal clock, so that the original delay component can be calculated, and by correcting the time difference in the Correction Field area, the time difference between the master clock and the slave clock can be reduced to zero.

[0100] As a result, in this embodiment, in a time synchronization system, asymmetric correction can be performed without using equipment for time correction such as GNSS, measuring instruments, etc. Furthermore, since the physical layer of the packet frame is not limited, asymmetric correction can be performed without depending on wired or wireless transmission paths.

[0101] The present disclosure is not limited to the above-described embodiment, and can be modified as appropriate within the scope of the present disclosure.

[0102] Each component in the above-described embodiments may be configured with hardware or software, or both, and may be configured with one piece of hardware or software, or may be configured with multiple pieces of hardware or software. Each device, such as a time synchronization device (time master device, time slave device), and each function (processing) may be realized by a computer 20 having a processor 21 such as a CPU and a memory 22 serving as a storage device, as shown in FIG. 16. For example, a program for performing the method in the embodiment (time synchronization method) may be stored in the memory 22, and each function may be realized by the processor 21 executing the program stored in the memory 22.

[0103] These programs include instructions (or software code) that, when loaded into a computer, cause the computer to perform one or more functions described in the embodiments. The programs may be stored on a non-transitory computer-readable medium or a tangible storage medium. By way of example and not limitation, computer-readable media or tangible storage media include random-access memory (RAM), read-only memory (ROM), flash memory, solid-state drive (SSD) or other memory technology, CD-ROM, digital versatile disc (DVD), Blu-ray disc or other optical disk storage, magnetic cassette, magnetic tape, magnetic disk storage or other magnetic storage device. The programs may also be transmitted on a transitory computer-readable medium or communication medium. By way of example and not limitation, transitory computer-readable media or communication media include electrical, optical, acoustic, or other forms of propagated signals.

[0104] Although the present disclosure has been described above with reference to the embodiments, the present disclosure is not limited to the above-described embodiments. Various modifications that can be understood by those skilled in the art can be made to the configuration and details of the present disclosure within the scope of the present disclosure. Furthermore, each embodiment can be combined with other embodiments as appropriate.

[0105] Each drawing is merely an example for describing one or more embodiments. Each drawing may not relate to only one particular embodiment, but may also relate to one or more other embodiments. As will be understood by those skilled in the art, various features or steps described with reference to any one drawing can be combined with features or steps shown in one or more other drawings to create, for example, an embodiment not explicitly shown or described. Not all features or steps shown in any one drawing are necessary to describe an exemplary embodiment, and some features or steps may be omitted. The order of steps described in any drawing may be changed as appropriate.

[0106] Some or all of the above embodiments can be described as, but are not limited to, the following supplementary notes: (Supplementary Note 1) A time synchronization device comprising an internal clock and a slave clock, frequency synchronization means for synchronizing the frequency of the internal clock with the frequency of a master clock of a time master device, downstream time difference convergence means for converging a downstream time difference, which is the time difference between a packet transmission time from the time master device and a packet reception time stamped by the internal clock, upstream time difference convergence means for converging an upstream time difference, which is the time difference between the packet transmission time stamped by the internal clock and a packet reception time at the time master device, and time synchronization means for synchronizing the time of the slave clock with the time of the master clock based on the convergence results of the downstream time difference and the upstream time difference. (Supplementary Note 2) The time synchronization device according to Supplementary Note 1, wherein the downlink time difference convergence means converges the downlink time difference based on the provisional downlink time difference and the repeatedly measured downlink time difference, and the uplink time difference convergence means converges the uplink time difference based on the provisional downlink time difference and the repeatedly measured uplink time difference. (Supplementary Note 3) The time synchronization device according to Supplementary Note 2, wherein the downlink time difference convergence means comprises: a clock for downlink time difference convergence, a measurement means for measuring the downlink time difference, and a comparison means for controlling the clock for downlink time difference convergence in accordance with a comparison result between the provisional uplink time difference and the measured downlink time difference. (Supplementary Note 4) The time synchronization device according to Supplementary Note 2, wherein the uplink time difference convergence means comprises: a clock for uplink time difference convergence, a measurement means for measuring the uplink time difference, and a comparison means for controlling the clock for uplink time difference convergence in accordance with a comparison result between the provisional downlink time difference and the measured uplink time difference. (Supplementary Note 5) A time synchronization device as described in any one of Supplementary Notes 1 to 4, further comprising a calculation means for calculating a time correction value based on the convergence result of the downlink time difference and the convergence result of the uplink time difference, and the time synchronization means synchronizes the time of the slave clock with the time of the master clock based on the time correction value.(Supplementary Note 6) The time synchronization device according to Supplementary Note 5, wherein the calculation means calculates the time difference between the master clock and the internal clock by adding half of the convergence result of the downlink time difference to half of the convergence result of the uplink time difference, and calculates the time correction value based on the time difference. (Supplementary Note 7) The time synchronization device according to Supplementary Note 6, wherein the calculation means calculates a downlink delay time based on the time difference between the master clock and the internal clock and the downlink time difference, calculates an uplink delay time based on the time difference between the master clock and the internal clock and the uplink time difference, and calculates the time correction value based on the downlink delay time and the uplink delay time. (Appendix 8) The time synchronization device described in any one of Appendices 5 to 7, wherein the time synchronization means corrects either the time difference between the packet transmission time from the time master device and the packet reception time stamped by the slave clock, or the time difference between the packet transmission time stamped by the slave clock and the packet reception time at the time master device, using the time correction value, thereby synchronizing the time of the slave clock with the time of the master clock. (Supplementary Note 9) A time synchronization system comprising: an internal clock and a slave clock, frequency synchronization means for synchronizing the frequency of the internal clock with the frequency of a master clock of a time master device, downstream time difference convergence means for converging a downstream time difference which is the time difference between the packet transmission time from the time master device and the packet reception time stamped by the internal clock, upstream time difference convergence means for converging an upstream time difference which is the time difference between the packet transmission time stamped by the internal clock and the packet reception time at the time master device, and time synchronization means for synchronizing the time of the slave clock with the time of the master clock based on the convergence result of the downstream time difference and the convergence result of the upstream time difference. (Supplementary Note 10) A time synchronization system according to Supplementary Note 9, comprising a time synchronization device and a convergence device, wherein the time synchronization device comprises the internal clock, the slave clock, and the time synchronization means, and the convergence device comprises the downstream time difference convergence means and the upstream time difference convergence means.(Supplementary Note 11) The time synchronization system according to Supplementary Note 9 or 10, wherein the downlink time difference convergence means converges the downlink time difference based on the provisional downlink time difference and the repeatedly measured downlink time difference, and the uplink time difference convergence means converges the uplink time difference based on the provisional downlink time difference and the repeatedly measured uplink time difference. (Supplementary Note 12) The time synchronization system according to any one of Supplementary Notes 9 to 11, further comprising: calculation means for calculating a time correction value based on a convergence result of the downlink time difference and a convergence result of the uplink time difference, and the time synchronization means synchronizes the time of the slave clock with the time of the master clock based on the time correction value. (Supplementary Note 13) The time synchronization system according to Supplementary Note 12, wherein the calculation means adds half of the convergence result of the downlink time difference to half of the convergence result of the uplink time difference to calculate the time difference between the master clock and the internal clock, and calculates the time correction value based on the time difference. (Supplementary Note 14) The time synchronization system according to Supplementary Note 13, wherein the calculation means calculates a downstream delay time based on the time difference between the master clock and the internal clock and the downstream time difference, calculates an upstream delay time based on the time difference between the master clock and the internal clock and the upstream time difference, and calculates the time correction value based on the downstream delay time and the upstream delay time. (Supplementary Note 15) A time synchronization method comprising: synchronizing the frequency of an internal clock with the frequency of a master clock of a time master device, converging a downstream time difference which is the time difference between the packet transmission time from the time master device and the packet reception time stamped by the internal clock, converging an upstream time difference which is the time difference between the packet transmission time stamped by the internal clock and the packet reception time at the time master device, and synchronizing the time of a slave clock with the time of the master clock based on the convergence result of the downstream time difference and the convergence result of the upstream time difference. (Supplementary Note 16) The time synchronization method according to Supplementary Note 15, wherein the downlink time difference is converged based on the provisional uplink time difference and the repeatedly measured downlink time difference, and the uplink time difference is converged based on the provisional downlink time difference and the repeatedly measured uplink time difference.(Supplementary Note 17) The time synchronization method according to Supplementary Note 15 or 16, calculating a time correction value based on the convergence result of the downstream time difference and the convergence result of the upstream time difference, and synchronizing the time of the slave clock with the time of the master clock based on the time correction value. (Supplementary Note 18) A program for causing a computer to execute processes of: synchronizing the frequency of an internal clock with the frequency of a master clock of a time master device, converging a downstream time difference which is the time difference between the packet transmission time from the time master device and the packet reception time stamped by the internal clock, converging an upstream time difference which is the time difference between the packet transmission time stamped by the internal clock and the packet reception time at the time master device, and synchronizing the time of the slave clock with the time of the master clock based on the convergence result of the downstream time difference and the convergence result of the upstream time difference. (Supplementary Note 19) The program according to Supplementary Note 18, which converges the downlink time difference based on the provisional uplink time difference and the repeatedly measured downlink time difference, and converges the uplink time difference based on the provisional downlink time difference and the repeatedly measured uplink time difference. (Supplementary Note 20) The program according to Supplementary Note 18 or 19, which calculates a time correction value based on the convergence result of the downlink time difference and the convergence result of the uplink time difference, and synchronizes the time of the slave clock with the time of the master clock based on the time correction value.

[0107] Some or all of the elements (e.g., configurations and functions) described in Supplementary Notes 2 to 8 that are dependent on Supplementary Note 1 (time synchronization device) may also be dependent on Supplementary Note 9 (time synchronization system), Supplementary Note 15 (time synchronization method), and Supplementary Note 18 (program) in the same dependency relationship as Supplementary Notes 2 to 8. Some or all of the elements described in any Supplementary Note may be applied to various hardware, software, recording means for recording software, systems, and methods.

[0108] 1 Time synchronization system 10 Time synchronization device 11 Internal clock 12 Slave clock 13 Frequency synchronization unit 14 Downstream time difference convergence unit 15 Upstream time difference convergence unit 16 Time synchronization unit 20 Computer 21 Processor 22 Memory 100 Time slave device 110 PDV filter 120 MTSD servo 121 STMD holding unit 122 MTSD measurement unit 123 Delay difference comparison unit 124 MTSD slave clock 130 STMD servo 131 MTSD holding unit 132 STMD measurement unit 133 Delay difference comparison unit 134 STMD slave clock 140 Correction value calculation unit 200 Time master device 500 Time synchronization device 600 PTP frequency synchronization unit 610 t2' packet time stamping unit 620 Phase comparator 630 IIR filter 640 PI controller 650 Internal clock 700 Packet filter processing unit 710 t1 packet receiving unit 711 Follow-up message receiving unit 712 t3 packet transmitting unit 713 t4 packet receiving unit 730 t2' packet embossing unit 731 t2'-t1 calculation unit 732 t2'-t1 shortest time search and holding unit 733 t2'-t1 correction unit 734 t1 correction value updating unit 740 t3' packet embossing unit 741 t4-t3' calculation unit 742 t4-t3' shortest time search and holding unit 743 t4-t3' correction unit 744 t4 correction value updating unit 800 PTP time synchronization unit 810 OCXO 820 Slave clock 830 t2 packet embossing unit 831 t2-t1 calculation unit 832 t3 packet time stamping unit 833 t4-t3 calculation unit 834 complementation unit 835 adder 836 PI controller

Claims

1. A time synchronization device comprising: an internal clock and a slave clock; frequency synchronization means for synchronizing the frequency of the internal clock with the frequency of a master clock of a time master device; downstream time difference convergence means for converging a downstream time difference, which is the time difference between the packet transmission time from the time master device and the packet reception time stamped by the internal clock; upstream time difference convergence means for converging an upstream time difference, which is the time difference between the packet transmission time stamped by the internal clock and the packet reception time at the time master device; and time synchronization means for synchronizing the time of the slave clock with the time of the master clock based on the convergence results of the downstream time difference and the upstream time difference.

2. The time synchronization device described in claim 1, wherein the downlink time difference convergence means converges the downlink time difference based on the provisional uplink time difference and the repeatedly measured downlink time difference, and the uplink time difference convergence means converges the uplink time difference based on the provisional downlink time difference and the repeatedly measured uplink time difference.

3. The time synchronization device described in claim 2, wherein the downstream time difference convergence means comprises: a clock for downstream time difference convergence; measurement means for measuring the downstream time difference; and comparison means for controlling the clock for downstream time difference convergence according to the comparison result between the provisional upstream time difference and the measured downstream time difference.

4. The time synchronization device described in claim 2, wherein the upstream time difference convergence means comprises: a clock for upstream time difference convergence; a measurement means for measuring the upstream time difference; and a comparison means for controlling the clock for upstream time difference convergence according to the comparison result between the provisional downstream time difference and the measured upstream time difference.

5. A time synchronization device according to any one of claims 1 to 4, further comprising a calculation means for calculating a time correction value based on the convergence result of the downstream time difference and the convergence result of the upstream time difference, and the time synchronization means synchronizes the time of the slave clock with the time of the master clock based on the time correction value.

6. The time synchronization device according to claim 5, wherein the calculation means adds half of the convergence result of the downlink time difference to half of the convergence result of the uplink time difference to calculate the time difference between the master clock and the internal clock, and calculates the time correction value based on the time difference.

7. The time synchronization device described in claim 6, wherein the calculation means calculates a downstream delay time based on the time difference between the master clock and the internal clock and the downstream time difference, calculates an upstream delay time based on the time difference between the master clock and the internal clock and the upstream time difference, and calculates the time correction value based on the downstream delay time and the upstream delay time.

8. A time synchronization device as described in any one of claims 5 to 7, wherein the time synchronization means corrects either the time difference between the packet transmission time from the time master device and the packet reception time stamped by the slave clock, or the time difference between the packet transmission time stamped by the slave clock and the packet reception time at the time master device, using the time correction value, thereby synchronizing the time of the slave clock with the time of the master clock.

9. A time synchronization system comprising: an internal clock and a slave clock; frequency synchronization means for synchronizing the frequency of the internal clock with the frequency of a master clock of a time master device; downstream time difference convergence means for converging a downstream time difference, which is the time difference between the packet transmission time from the time master device and the packet reception time stamped by the internal clock; upstream time difference convergence means for converging an upstream time difference, which is the time difference between the packet transmission time stamped by the internal clock and the packet reception time at the time master device; and time synchronization means for synchronizing the time of the slave clock with the time of the master clock based on the convergence results of the downstream time difference and the upstream time difference.

10. A time synchronization system according to claim 9, comprising a time synchronization device and a convergence device, wherein the time synchronization device comprises the internal clock, the slave clock, and the time synchronization means, and the convergence device comprises the downstream time difference convergence means and the upstream time difference convergence means.

11. A time synchronization system as described in claim 9 or 10, wherein the downlink time difference convergence means converges the downlink time difference based on the provisional uplink time difference and the repeatedly measured downlink time difference, and the uplink time difference convergence means converges the uplink time difference based on the provisional downlink time difference and the repeatedly measured uplink time difference.

12. A time synchronization system as claimed in any one of claims 9 to 11, further comprising a calculation means for calculating a time correction value based on the convergence result of the downstream time difference and the convergence result of the upstream time difference, and the time synchronization means synchronizes the time of the slave clock with the time of the master clock based on the time correction value.

13. The time synchronization system described in claim 12, wherein the calculation means adds half of the convergence result of the downlink time difference to half of the convergence result of the uplink time difference to calculate the time difference between the master clock and the internal clock, and calculates the time correction value based on the time difference.

14. The time synchronization system described in claim 13, wherein the calculation means calculates a downstream delay time based on the time difference between the master clock and the internal clock and the downstream time difference, calculates an upstream delay time based on the time difference between the master clock and the internal clock and the upstream time difference, and calculates the time correction value based on the downstream delay time and the upstream delay time.

15. A time synchronization method comprising: synchronizing the frequency of an internal clock with the frequency of a master clock of a time master device; converging a downstream time difference, which is the time difference between the packet transmission time from the time master device and the packet reception time stamped by the internal clock; converging an upstream time difference, which is the time difference between the packet transmission time stamped by the internal clock and the packet reception time at the time master device; and synchronizing the time of a slave clock with the time of the master clock based on the convergence results of the downstream time difference and the upstream time difference.

16. A time synchronization method as described in claim 15, wherein the downlink time difference is converged based on the provisional uplink time difference and the repeatedly measured downlink time difference, and the uplink time difference is converged based on the provisional downlink time difference and the repeatedly measured uplink time difference.

17. A time synchronization method according to claim 15 or 16, further comprising: calculating a time correction value based on the convergence result of the downstream time difference and the convergence result of the upstream time difference; and synchronizing the time of the slave clock with the time of the master clock based on the time correction value.

18. A program for causing a computer to execute the following processes: synchronizing the frequency of an internal clock with the frequency of the master clock of a time master device; converging a downstream time difference, which is the time difference between the packet transmission time from the time master device and the packet reception time stamped by the internal clock; converging an upstream time difference, which is the time difference between the packet transmission time stamped by the internal clock and the packet reception time at the time master device; and synchronizing the time of a slave clock with the time of the master clock based on the convergence results of the downstream time difference and the upstream time difference.

19. The program according to claim 18, wherein the downlink time difference is converged based on the provisional uplink time difference and the repeatedly measured downlink time difference, and the uplink time difference is converged based on the provisional downlink time difference and the repeatedly measured uplink time difference.

20. A program as described in claim 18 or 19, which calculates a time correction value based on the convergence result of the downlink time difference and the convergence result of the uplink time difference, and synchronizes the time of the slave clock with the time of the master clock based on the time correction value.

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