A latch circuit resistant to single event multiple bit upsets

Abstract

The application relates to an anti-single-event multi-bit upset latch circuit, which comprises a clock control inverter circuit controlled by clock signals CK1 and CK2 to be turned on or turned off, and data signals are transmitted to a latch unit when the clock control inverter circuit is turned on; the latch unit receives the data signals from the clock control inverter circuit and performs the latching of the data signals through the control of the clock signals CK1 and CK2; an SEU monitoring unit monitors whether a single-event upset occurs at a data sensitive node in the latch unit, and if the single-event upset occurs at the monitored latch unit, the data channel is switched to other latch units through a chip selection control unit; the chip selection control unit controls the opening or closing of the output of the latch unit according to the monitoring result of the SEU monitoring unit; and an inverter circuit inverts the data signals output by the chip selection control unit or the clock signals; the application has good single-event hardening capability and can realize the anti-single-event multi-bit upset.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of circuit design, and particularly relates to a latch circuit capable of resisting single-event multi-bit upset. BACKGROUND

[0002] In the application fields of aerospace, satellite and space exploration, it is required to ensure that electronic components, devices and systems can work normally in the space radiation or artificial radiation environment, and the anti-radiation performance has become an important index of integrated circuit design. Single-event upset (SEU) refers to the phenomenon that the logic state of a device is reversed due to the bombardment of a single high-energy particle on the sensitive area of the integrated circuit device. The error data generated by single-event upset may cause incorrect instructions and trigger system function disorder, and may even cause catastrophic accidents. Single-event upset mainly occurs in a timing circuit. When a high-energy particle bombards the sensitive node of the timing circuit, the charged particles interact with the semiconductor material to generate electron-hole pairs. These carriers move under the action of concentration gradient and electric field and accumulate at the sensitive node. When the accumulation reaches a certain degree, the level at the sensitive node is changed, and the storage state of the timing circuit is changed, i.e. single-event upset.

[0003] For digital integrated circuit design, the latch circuit is the most basic unit, and the anti-radiation performance thereof is very crucial and important. With the reduction of process size, the problems such as reduction of storage charge of the sensitive node and single-particle incident track covering multiple devices all affect the anti-single-event upset capability of the integrated circuit, and the anti-radiation hardening technology against single-event upset will become the focus of people's research.

[0004] At present, widely used circuit structures for improving the anti-single-event upset capability, such as DICE structure and triple modular redundancy structure, are proved to be effective for anti-single-event upset, but with the progress of technology and the reduction of device size, the hardening effect of these structures is getting worse and worse. Moreover, these two structures are only effective for anti-single-event unit upset, and cannot be used for anti-single-event multi-bit upset. They cannot meet the single-event hardening requirements under nanometer technology. SUMMARY

[0005] The technical problem of the application is to overcome the deficiencies of the prior art, and to provide a latch circuit structure capable of resisting single-event multi-bit upset and realizing anti-multi-bit single-event upset hardening.

[0006] In order to solve the above technical problems, the application discloses the following technical scheme:

[0007] A latch circuit capable of resisting single-event multi-bit upset, comprising:

[0008] A clock-controlled inverter circuit controlled to be turned on or turned off by clock signals CK1 and CK2, and transmitting a data signal to a latch unit when turned on.

[0009] a latch unit, receiving a data signal from the clock control inverter circuit, and latching the data signal by controlling clock signals CK1 and CK2;

[0010] an SEU monitoring unit, monitoring whether a single event upset occurs at a data sensitive node inside the latch unit, and switching a data channel to another latch unit through the chip select control unit if a single event upset occurs at the monitored latch unit, otherwise, not switching;

[0011] a chip select control unit, controlling the opening or closing of the latch unit according to the monitoring result of the SEU monitoring unit;

[0012] an inverter circuit, inverting the data signal or the clock signal output by the chip select control unit.

[0013] In the latch circuit against single event multi-bit upset as described above, the clock control inverter circuit includes a first clock control inverter circuit, a second clock control inverter circuit and a third clock control inverter circuit; the latch unit includes a first latch unit, a second latch unit and a third latch unit; the SEU monitoring unit includes a first SEU monitoring unit and a second SEU monitoring unit; and the inverter circuit includes a first inverter circuit, a second inverter circuit and a third inverter circuit.

[0014] In the latch circuit against single event multi-bit upset as described above, an output end of the first clock control inverter circuit is connected to an input end of the first latch unit and an input end in1 of the first SEU monitoring unit;

[0015] An output end of the first latch unit is connected to an input end in2 of the first SEU monitoring unit and an input end in1 of the chip select control unit;

[0016] Output ends out1 and out2 of the first SEU monitoring unit are respectively connected to input ends S1 and S1N of the chip select control unit;

[0017] An output end of the second clock control inverter circuit is connected to an input end of the second latch unit and an input end in1 of the second SEU monitoring unit;

[0018] An output end of the second latch unit is connected to an input end in2 of the second SEU monitoring unit and an input end in2 of the chip select control unit;

[0019] Output ends out1 and out2 of the second SEU monitoring unit are respectively connected to input ends S2 and S2N of the chip select control unit;

[0020] An output end of the third clock control inverter circuit is connected to an input end of the third latch unit;

[0021] The output terminal of the third latch unit is connected with the input terminal in3 of the chip selection control unit;

[0022] The output terminal of the chip selection control unit is connected with the input terminal of the inverter circuit;

[0023] The second inverter circuit and the third inverter circuit are connected in series, and are used for providing clock signals CK1 and CK2 for the first clock control inverter circuit, the second clock control inverter circuit, the third clock control inverter circuit, the first SEU monitoring unit and the second SEU monitoring unit;

[0024] The input terminal of the second inverter circuit is connected with an input clock signal CLK; the second inverter circuit outputs a clock signal CK1, and the third inverter circuit outputs a clock signal CK2.

[0025] In the latch circuit with anti-single event multi-bit upset mentioned above, the clock signals CK1 and CK2 are complementary clock signals, that is, the clock signal CK1 is an inverse signal of the clock signal CLK, and the clock signal CK2 is an inverse signal of the clock signal CK1; the clock signals CK1 and CK2 jointly control the propagation of the data signal in the latch circuit.

[0026] In the latch circuit with anti-single event multi-bit upset mentioned above, the clock control inverter circuit is a group of inverter circuits controlled by complementary clock signals, and includes a PMOS transistor P21, a PMOS transistor P22, an NMOS transistor N21 and an NMOS transistor N22.

[0027] The PMOS transistor P21, the PMOS transistor P22, the NMOS transistor N21 and the NMOS transistor N22 are connected in series.

[0028] The gate of the PMOS transistor P22 is connected with the clock signal CK1, and the gate of the NMOS transistor N21 is connected with the clock signal CK2.

[0029] The gates of the PMOS transistor P21 and the NMOS transistor N22 are used as the input terminal of the clock control inverter circuit, and are used for connecting with an input signal.

[0030] In the latch circuit with anti-single event multi-bit upset mentioned above, the latch unit includes an inverter D31 and an inverter D32.

[0031] The inverter D32 includes a PMOS transistor P31, a PMOS transistor P32, an NMOS transistor N31 and an NMOS transistor N32 connected in series; the gate of the PMOS transistor P32 is connected with the clock signal CK1, and the gate of the NMOS transistor N31 is connected with the clock signal CK2.

[0032] The input signal in is connected with the input terminal of the inverter D31 and the output terminal of the inverter D32 respectively.

[0033] The output end of the inverter D31 is as an output end out of the latch unit and is connected to the gate of the PMOS tube P31 and the NMOS tube N32 at the same time.

[0034] In the latch circuit for resisting single event upset multi-bit flip, the SEU monitoring unit comprises an XOR gate XOR1, an inverter D41 and an inverter D42.

[0035] The inverter D41 comprises a PMOS tube P41, a PMOS tube P42 and an NMOS tube N41 connected in series.

[0036] The input signal in1 and in2 are connected to the two input ends of the XOR gate XOR1 respectively.

[0037] The output end of the XOR gate XOR1 is connected to the gate of the PMOS tube P41.

[0038] The output end of the inverter D41 is connected to the input end of the inverter D42.

[0039] The inverter D41 outputs a control signal out2 and the inverter D42 outputs a control signal out1.

[0040] In the latch circuit for resisting single event upset multi-bit flip, the chip selection control unit comprises a delay unit, a delay unit, an inverter D51, an inverter D52, an inverter D53, an inverter D54 and an inverter D55.

[0041] The input signal in1 is connected to the input end of the first delay unit.

[0042] The input signal in2 is connected to the input end of the second delay unit.

[0043] The input signal in3 is connected to the gate of the PMOS P57 and the NMOS N58;

[0044] The gate of the PMOS P52 and the gate of the NMOS N55 are connected to the control signal S1N respectively;

[0045] The gate of the NMOS N51 and the gate of the PMOS P56 are connected to the control signal S1 respectively;

[0046] The gate of the PMOS P54 and the gate of the NMOS N57 are connected to the control signal S2N respectively;

[0047] The gate of the NMOS N53 and the gate of the PMOS P58 are connected to the control signal S2 respectively;

[0048] The output of the inverter D52 and the output of the inverter D55 are connected to the input of the inverter D53 together, and the output of the inverter D53 is connected to the gate of the PMOS P55 and the gate of the NMOS N56 respectively;

[0049] The output of the inverter D51 and the output of the inverter D54 are connected to the output signal out of the chip select control unit together.

[0050] In the above anti-single event upset multi-bit flip latch circuit, the delay unit is composed of a plurality of inverters;

[0051] The first delay unit is used for making the signal S1 and the signal S1N arrive earlier in time sequence than the input signal of the inverter D51;

[0052] The second delay unit is used for making the signal S2 and the signal S2N arrive earlier in time sequence than the input signal of the inverter D52.

[0053] In the above anti-single event upset multi-bit flip latch circuit, the latch circuit adopts the combination of the circuit hardening technology and the layout hardening technology to realize the anti-single event upset hardening of the internal nodes.

[0054] Compared with the prior art, the embodiment of the present application has at least the following beneficial effects:

[0055] (1), the embodiment of the present application discloses an anti-single event upset multi-bit flip latch circuit structure, whether the latch unit occurs single event upset is judged through SEU monitoring unit, if the SEU is monitored, the standby latch unit is automatically switched through the chip select control unit circuit, and the single event upset hardening is realized.

[0056] (2), two standby latch units are preferably adopted in the embodiment of the present application, and the multi-bit single event upset hardening is realized.

[0057] (3), the embodiment of the application preferably adopts the form of combination of circuit design and layout design, and has good reinforcement effect. BRIEF DESCRIPTION OF DRAWINGS

[0058] Figure 1 for the circuit structure diagram of the latch circuit structure resisting single event multiple bit upset in the embodiment of the application;

[0059] Figure 2 for the circuit structure diagram of the clock control inverter circuit in the embodiment of the application;

[0060] Figure 3 for the circuit structure diagram of the latch unit in the embodiment of the application;

[0061] Figure 4 for the circuit structure diagram of the SEU monitoring unit in the embodiment of the application;

[0062] Figure 5 for the circuit structure diagram of the chip select control unit in the embodiment of the application;

[0063] Figure 6 for the circuit structure diagram of the delay unit in the embodiment of the application;

[0064] Figure 7 for the simulation waveform of the N2 node of the general latch circuit detecting SEU;

[0065] Figure 8 for the simulation waveform of the N2 and N4 nodes of the latch circuit detecting SEU at the same time in the embodiment of the application. DETAILED DESCRIPTION

[0066] The application will be further described in detail below in combination with the drawings and specific embodiments:

[0067] The embodiment of the application discloses a latch circuit structure resisting single event multiple bit upset, which comprises a clock control inverter circuit, a latch unit, an SEU monitoring unit, a chip select control unit and an inverter circuit.

[0068] The clock control inverter circuit is used for controlling the propagation of the data signal in the latch circuit, and the clock control inverter circuit is controlled to be turned on or turned off by the clock signals CK1 and CK2, and the data signal is transmitted to the latch unit when the clock control inverter circuit is turned on.

[0069] The latch unit receives the data signal from the clock control inverter circuit, and the data signal is latched through the control of the clock signals CK1 and CK2.

[0070] The SEU monitoring unit monitors whether a single-event upset (SEI) has occurred at a data-sensitive node within the latch unit. If an SEI occurs in the monitored latch unit, the chip select control unit switches the data channel to another latch unit; otherwise, no switching occurs. For example, if an SEI occurs in the first latch unit, the chip select control unit switches the data channel to the second latch unit; otherwise, no switching occurs. If an SEI also occurs in the second latch unit, the chip select control unit switches the data channel to the third latch unit; otherwise, no switching occurs, and so on.

[0071] The chip select control unit controls the opening or closing of the latch unit output based on the monitoring results of the SEU monitoring unit;

[0072] An inverter circuit is used to invert the data signal or clock signal output by the chip select control unit.

[0073] like Figure 1 As shown, in this embodiment, the latch circuit structure resisting single-event multi-bit flip includes: a clock-controlled inverter circuit, a latch unit, a SEU monitoring unit, a chip select control unit 107, and an inverter circuit; wherein, the clock-controlled inverter circuit may specifically include: a first clock-controlled inverter circuit 101, a second clock-controlled inverter circuit 102, and a third clock-controlled inverter circuit 103; the latch unit may specifically include: a first latch unit 104, a second latch unit 105, and a third latch unit 106; the SEU monitoring unit may specifically include: a first SEU monitoring unit 109 and a second SEU monitoring unit 110; the inverter circuit may specifically include: a first inverter circuit 108, a second inverter circuit 111, and a third inverter circuit 112.

[0074] The output end of the first clock control inverter circuit 101 is connected with the input end of the first latch unit 104 and the input end in1 of the first SEU monitoring unit 109; the output end of the first latch unit 104 is connected with the input end in2 of the first SEU monitoring unit 109 and the input end in1 of the chip select control unit 107; the output ends out1 and out2 of the first SEU monitoring unit 109 are connected with the input ends S1 and S1N of the chip select control unit 107 respectively; the output end of the second clock control inverter circuit 102 is connected with the input end of the second latch unit 105 and the input end in1 of the second SEU monitoring unit 110; the output end of the second latch unit 105 is connected with the input end in2 of the second SEU monitoring unit 110 and the input end in2 of the chip select control unit 107; the output ends out1 and out2 of the second SEU monitoring unit 110 are connected with the input ends S2 and S2N of the chip select control unit 107 respectively; the output end of the third clock control inverter circuit 103 is connected with the input end of the third latch unit 106; the output end of the third latch unit 106 is connected with the input end in3 of the chip select control unit 107; the output end of the chip select control unit 107 is connected with the input end of the inverter circuit 108.

[0075] In the embodiment, the latch circuit structure against single event multiple bit upset can further comprise a second inverter circuit 111 and a third inverter circuit 112, wherein the second inverter circuit 111 and the third inverter circuit 112 are connected in series to provide clock signal CK1 and clock signal CK2 for the first clock control inverter circuit 101, the second clock control inverter circuit 102, the third clock control inverter circuit 103, the first SEU monitoring unit 109 and the second SEU monitoring unit 110.

[0076] Preferably, the input end of the second inverter circuit 111 is connected with the input clock signal CLK; the second inverter circuit 111 outputs clock signal CK1 and the third inverter circuit 112 outputs clock signal CK2, wherein the clock signal CK1 and the clock signal CK2 are complementary clock signals, that is, the clock signal CK1 is the inverse signal of the clock signal CLK and the clock signal CK2 is the inverse signal of the clock signal CK1; the clock signal CK1 and the clock signal CK2 jointly control the propagation of the data signal in the latch circuit.

[0077] In the embodiment, the clock control inverter circuit is an inverter circuit controlled by a group of complementary clock signals. Figure 2As shown in the figure, the clock control inverter circuit comprises a PMOS tube P21, a PMOS tube P22, an NMOS tube N21 and an NMOS tube N22. The PMOS tube P21, the PMOS tube P22, the NMOS tube N21 and the NMOS tube N22 are connected in series. The gate of the PMOS tube P22 is connected to the clock signal CK1, and the NMOS tube N21 is connected to the clock signal CK2; the gates of the PMOS tube P21 and the NMOS tube N22 are connected together as the input end of the clock control inverter circuit, for connecting the input signal.

[0078] In the embodiment, the latch unit is used to store data according to the timing signal. Figure 3 As shown in the figure, the latch unit is specifically composed of an inverter D31 and an inverter D32, wherein the inverter D32 comprises a PMOS tube P31, a PMOS tube P32, an NMOS tube N31 and an NMOS tube N32 connected in series.

[0079] Preferably, the gate of the PMOS tube P32 is connected to the clock signal CK1, and the gate of the NMOS tube N31 is connected to the clock signal CK2. The input signal in is connected to the input end of the inverter D31 and the output end of the inverter D32 respectively. The output end of the inverter D31 is connected to the output signal out of the latch unit, and is also connected to the gates of the PMOS tube P31 and the NMOS tube N32.

[0080] Preferably, for the latch unit, when the clock input signal CK1 is low "0" and the clock input signal CK2 is high "1", the PMOS tube P32 and the NMOS tube N31 are both in the open state, so that the latch of the data signal can be realized. When the clock input signal CK1 is high "1" and the clock input signal CK2 is low "0", the PMOS tube P32 and the NMOS tube N31 are both in the closed state, so that the output signal out cannot be transmitted to the input end in through the inverter D32, and the latch of the data signal cannot be realized.

[0081] Preferably, for the latch unit, the layout reinforcement technology is combined to isolate the sensitive nodes of the first latch unit, the second latch unit and the third latch unit. The probability that the first latch unit, the second latch unit and the third latch unit are flipped at the same time is reduced, so that the purpose of resisting single event upset is achieved.

[0082] In the embodiment, the SEU monitoring unit has two data input ends, one clock signal input end and two control signal output ends. Figure 4 As shown in the figure, the SEU monitoring unit can specifically comprise an XOR gate XOR1, an inverter D41 and an inverter D42.

[0083] Preferably, the inverter D41 comprises a PMOS transistor P41, a PMOS transistor P42 and an NMOS transistor N41 connected in series; the gates of the PMOS transistor P42 and the NMOS transistor N41 are connected together as a clock signal input terminal of the SEU monitoring unit, for receiving the clock signal CK1; the input signals in1 and in2 are connected to two input terminals of an XOR gate XOR1 respectively; the output terminal of the XOR gate XOR1 is connected to the gate of the PMOS transistor P41; the output terminal of the inverter D41 is connected to the input terminal of an inverter D42; the inverter D41 outputs a control signal out2, and the inverter D42 outputs a control signal out1; wherein the control signal out1 and the control signal out2 are complementary signals, i.e. the signal out1 is the inverse signal of the signal out2.

[0084] Preferably, for the SEU monitoring unit, when the clock input signal CK1 is high "1", the PMOS transistor P42 is in a closed state, the NMOS transistor N41 is in an open state, the output signal out2 remains low "0", the output control signal out1 remains high "1", and at this time the SEU monitoring unit is in a functional closed state. The purpose is to shield the false detection caused by the normal state change of the data input signal D.

[0085] Preferably, for the SEU monitoring unit, when the clock input signal CK1 is low "0" and the states of the input signals in1 and in2 are different, the XOR gate XOR1 outputs high "1", the PMOS transistor P41 is in a closed state, the NMOS transistor N41 is in a closed state, the output signal out2 remains low "0", and the output control signal out1 remains high "1".

[0086] Preferably, for the SEU monitoring unit, when the clock input signal CK1 is low "0" and the input signals in1 and in2 are high "1" or low "0" at the same time, the XOR gate XOR1 outputs low "0", the PMOS transistor P41 and the PMOS transistor P42 are in an open state, the NMOS transistor N41 is in a closed state, the output signal out2 outputs high "1", and the output signal out1 outputs low "0".

[0087] Preferably, for the SEU monitoring unit, when the clock input signal CK1 is low "0", the first SEU monitoring unit 109 monitors the internal sensitive nodes N1 and N2 of the first latch unit 104, when the sensitive node N1 and the sensitive node N2 are detected to be the same logic state at a very short time, then the first latch unit 104 occurs SEU, when the sensitive node N1 and the sensitive node N2 are detected to be opposite logic states, then the first latch unit 104 does not occur SEU; the second SEU monitoring unit 110 monitors the internal sensitive nodes N3 and N4 of the second latch unit 105, when the sensitive node N3 and the sensitive node N4 are detected to be the same logic state at a very short time, then the second latch unit 105 occurs SEU, when the sensitive node N3 and the sensitive node N4 are detected to be opposite logic states, then the second latch unit 105 does not occur SEU.

[0088] In the embodiment, the chip selection control unit has three data input terminals, four control signal input terminals and one data signal output terminal. As shown in Figure 5 The chip selection control unit specifically includes: delay unit 501, delay unit 502, inverter D51, inverter D52, inverter D53, inverter D54 and inverter D55; wherein the inverter D51 includes: PMOS tube P51, PMOS tube P52, NMOS tube N51 and NMOS tube N52 connected in series; the inverter D52 includes: PMOS tube P53, PMOS tube P54, NMOS tube N53 and NMOS tube N54 connected in series; the inverter D54 includes: PMOS tube P55, PMOS tube P56, NMOS tube N55 and NMOS tube N56 connected in series; the inverter D55 includes: PMOS tube P57, PMOS tube P58, NMOS tube N57 and NMOS tube N58 connected in series;

[0089] Preferably, the input signal in1 is connected to the input end of the delay unit 501; the output end of the delay unit 501 is respectively connected to the gate of the PMOS P51 and the NMOS N52; the input signal in2 is connected to the input end of the delay unit 502; the output end of the delay unit 502 is respectively connected to the gate of the PMOS P53 and the NMOS N54; the input signal in3 is connected to the gate of the PMOS P57 and the NMOS N58; the gate of the PMOS P52 and the gate of the NMOS N55 are respectively connected to the control signal S1N; the gate of the NMOS N51 and the gate of the PMOS P56 are respectively connected to the control signal S1; the gate of the PMOS P54 and the gate of the NMOS N57 are respectively connected to the control signal S2N; the gate of the NMOS N53 and the gate of the PMOS P58 are respectively connected to the control signal S2; the output end of the inverter D52 and the output end of the inverter D55 are commonly connected to the input end of the inverter D53; the output end of the inverter D53 is respectively connected to the gate of the PMOS P55 and the gate of the NMOS N56; the output end of the inverter D51 and the output end of the inverter D54 are commonly used as the output signal out of the chip select control unit.

[0090] Preferably, the delay unit can be specifically composed of several inverters. As shown in the figure, Figure 6 the width-length ratio of the MOS tube constituting the inverter and the inverter series are determined according to the circuit simulation results of the used process; the delay unit 501 is used to make the signal S1 and the signal S1N arrive earlier in time sequence than the input signal of the inverter D51; the delay unit 502 is used to make the signal S2 and the signal S2N arrive earlier in time sequence than the input signal of the inverter D52. The purpose is to close the inverter D51 in time before the single event upset signal is transmitted to the inverter D51, or to close the inverter D52 in time before the single event upset signal is transmitted to the inverter D52 when the SEU signal is monitored. The single event upset signal is blocked from being transmitted to the next stage circuit.

[0091] Preferably, for the chip select control unit, when the control input signal S1 is high "1" and the control input signal S1N is low "0", the PMOS P52 and the NMOS P51 are in the open state, the PMOS P56 and the NMOS P55 are in the closed state, and the data input signal in1 is transmitted to the output end out in turn through the delay unit 501 and the inverter D51. This is the case where the first latch unit 104 does not occur SEU.

[0092] Preferably, for the chip select control unit, when the control input signal S1 is low "0", the control input signal S1N is high "1", the control input signal S2 is high "1", and the control input signal S2N is low "0", the PMOS P52 and NMOS P51 are in the closed state, the PMOS P56 and NMOS P55 are in the open state, the PMOS P54 and NMOS P53 are in the open state, the PMOS P58 and NMOS P57 are in the closed state, and the data input signal in2 is transmitted to the output end out through the delay unit 502, the inverter D52, the inverter D53 and the inverter D54 in turn. This is the case where the first latch unit 104 has SEU and the second latch unit 105 has no SEU.

[0093] Preferably, for the chip select control unit, when the control input signal S1 is low "0", the control input signal S1N is high "1", the control input signal S2 is low "0", and the control input signal S2N is high "1", the PMOS P52 and NMOS P51 are in the closed state, the PMOS P56 and NMOS P55 are in the open state, the PMOS P54 and NMOS P53 are in the closed state, the PMOS P58 and NMOS P57 are in the open state, and the data input signal in3 is transmitted to the output end out through the inverter D55, the inverter D53 and the inverter D54 in turn. This is the case where the first latch unit 104 and the second latch unit 105 have SEU.

[0094] In the embodiment, the latch circuit structure is resistant to single event upset and multi-bit flip in all cases except the case where the first latch unit, the second latch unit and the third latch unit all have single event upset. As shown in FIG. 6, the simulation waveform is given when the N2 node and the N4 node of the latch circuit in the embodiment detect SEU at the same time. As can be seen from the figure, the output waveform of the latch output end Q has no error flip. Figure 8 As shown in FIG. 7, the simulation waveform is given when the N2 node of the general latch circuit detects SEU. After particle bombardment, the output waveform of the latch output end Q has error flip. Figure 7

[0095] The above description is only the best specific embodiment of the present application, but the protection scope of the present application is not limited to this. Any change or replacement within the technical range disclosed by the present application can be easily thought by those skilled in the art, which should be covered in the protection scope of the present application.

[0096] The contents not described in detail in the specification of the present application are the known technology of the skilled in the art.​

Claims

1. A latch circuit against single event multiple bit upset, characterized by, The clock control inverter circuit is controlled to be turned on or turned off by clock signals CK1 and CK2, and data signals are transmitted to the latch unit when the clock control inverter circuit is turned on; The clock control inverter circuit includes a first clock control inverter circuit (101), a second clock control inverter circuit (102), and a third clock control inverter circuit (103); The latch unit receives data signals from the clock control inverter circuit and performs latch of the data signals by controlling clock signals CK1 and CK2; the latch unit includes a first latch unit (104), a second latch unit (105), and a third latch unit (106); The SEU monitoring unit monitors whether single event upsets occur at internal data sensitive nodes of the latch unit; if single event upsets occur at the monitored latch unit, the data channel is switched to other latch units through the chip selection control unit; otherwise, no switching is performed. The SEU monitoring unit includes a first SEU monitoring unit (109) and a second SEU monitoring unit (110); The chip selection control unit controls the opening or closing of the output of the latch unit according to the monitoring result of the SEU monitoring unit; The inverter circuit is used for inverting data signals or clock signals output by the chip selection control unit; The inverter circuit includes a first inverter circuit (108), a second inverter circuit (111), and a third inverter circuit (112); An output end of the first clock control inverter circuit (101) is connected to an input end of the first latch unit (104) and an input end in1 of the first SEU monitoring unit (109); An output end of the first latch unit (104) is connected to an input end in2 of the first SEU monitoring unit (109) and an input end in1 of the chip selection control unit (107); Output ends out1 and out2 of the first SEU monitoring unit (109) are respectively connected to input ends S1 and S1N of the chip selection control unit (107); An output end of the second clock control inverter circuit (102) is connected to an input end of the second latch unit (105) and an input end in1 of the second SEU monitoring unit (110); An output end of the second latch unit (105) is connected to an input end in2 of the second SEU monitoring unit (110) and an input end in2 of the chip selection control unit (107); Output ends out1 and out2 of the second SEU monitoring unit (110) are respectively connected to input ends S2 and S2N of the chip selection control unit (107); An output end of the third clock control inverter circuit (103) is connected to an input end of the third latch unit (106); An output end of the third latch unit (106) is connected to an input end in3 of the chip selection control unit (107); An output end of the chip selection control unit (107) is connected to an input end of the inverter circuit (108); The second inverter circuit (111) and the third inverter circuit (112) are connected in series and are used for providing clock signals CK1 and clock signals CK2 for the first clock control inverter circuit (101), the second clock control inverter circuit (102), the third clock control inverter circuit (103), the first SEU monitoring unit (109), and the second SEU monitoring unit (110). ​ An input terminal of the second inverter circuit (111) is connected to an input clock signal CLK; the second inverter circuit (111) outputs a clock signal CK1, and the third inverter circuit (112) outputs a clock signal CK2.

2. The latch circuit against single event multiple bit upsets according to claim 1, characterized in that, The clock signal CK1 and the clock signal CK2 are complementary clock signals, that is, the clock signal CK1 is an inverted signal of the clock signal CLK, and the clock signal CK2 is an inverted signal of the clock signal CK1; the clock signal CK1 and the clock signal CK2 jointly control the propagation of a data signal in a latch circuit.

3. The latch circuit against single event multiple bit upsets according to claim 1 or 2, characterized in that, The clock control inverter circuit is a set of inverter circuits controlled by complementary clock signals, and includes a PMOS transistor P21, a PMOS transistor P22, an NMOS transistor N21, and an NMOS transistor N22. The PMOS transistor P21, the PMOS transistor P22, the NMOS transistor N21, and the NMOS transistor N22 are connected in series. A gate of the PMOS transistor P22 is connected to the clock signal CK1, and a gate of the NMOS transistor N21 is connected to the clock signal CK2. Gates of the PMOS transistor P21 and the NMOS transistor N22 jointly serve as an input terminal of the clock control inverter circuit, and are used to connect to an input signal.

4. The latch circuit against single event multiple bit upsets according to claim 1 or 2, characterized in that, The latch unit includes an inverter D31 and an inverter D32. The inverter D32 includes a PMOS transistor P31, a PMOS transistor P32, an NMOS transistor N31, and an NMOS transistor N32 connected in series. An input terminal of the inverter D31 and an output terminal of the inverter D32 are connected to the input signal in, respectively. An output terminal of the inverter D31 serves as an output terminal out of the latch unit, and is connected to gates of the PMOS transistor P31 and the NMOS transistor N32.

5. The latch circuit against single event multiple bit upsets according to claim 1 or 2, characterized in that, The SEU monitoring unit includes an XOR gate XOR1, an inverter D41, and an inverter D42. The inverter D41 includes a PMOS transistor P41, a PMOS transistor P42, and an NMOS transistor N41 connected in series. Two input terminals of the XOR gate XOR1 are connected to the input signals in1 and in2, respectively. An output terminal of the XOR gate XOR1 is connected to a gate of the PMOS transistor P41. An output terminal of the inverter D41 is connected to an input terminal of the inverter D42. The inverter D41 outputs a control signal out2, and the inverter D42 outputs a control signal out1; the control signal out1 and the control signal out2 are complementary signals, that is, the signal out1 is an inverted signal of the signal out2.

6. The latch circuit against single event multiple bit upsets according to claim 1 or 2, characterized in that, The chip select control unit comprises a delay unit (501), a delay unit (502), an inverter D51, an inverter D52, an inverter D53, an inverter D54 and an inverter D55; wherein the inverter D51 comprises PMOS tubes P51, P52, NMOS tubes N51 and N52 connected in series; the inverter D52 comprises PMOS tubes P53, P54, NMOS tubes N53 and N54 connected in series; the inverter D54 comprises PMOS tubes P55, P56, NMOS tubes N55 and N56 connected in series; and the inverter D55 comprises PMOS tubes P57, P58, NMOS tubes N57 and N58 connected in series. An input signal in1 is connected to the input end of the delay unit 501; and the output ends of the delay unit 501 are connected to the gates of the PMOS tube P51 and the NMOS tube N52 respectively. An input signal in2 is connected to the input end of the delay unit 502; and the output ends of the delay unit 502 are connected to the gates of the PMOS tube P53 and the NMOS tube N54 respectively. An input signal in3 is connected to the gates of the PMOS tube P57 and the NMOS tube N58. The gates of the PMOS tube P52 and the NMOS tube N55 are connected to control signals S1N respectively. The gates of the NMOS tube N51 and the PMOS tube P56 are connected to control signals S1 respectively. The gates of the PMOS tube P54 and the NMOS tube N57 are connected to control signals S2N respectively. The gates of the NMOS tube N53 and the PMOS tube P58 are connected to control signals S2 respectively. The output end of the inverter D52 and the output end of the inverter D55 are connected to the input end of the inverter D53; and the output end of the inverter D53 is connected to the gates of the PMOS tube P55 and the NMOS tube N56 respectively. The output end of the inverter D51 and the output end of the inverter D54 are used as the output signal out of the chip select control unit.

7. The latch circuit of claim 6, wherein, The delay units (501, 502) are composed of several inverters; The delay unit (501) is used to make the signals S1 and S1N arrive earlier than the input signal of the inverter D51 in time sequence. The delay unit (502) is used to make the signals S2 and S2N arrive earlier than the input signal of the inverter D52 in time sequence.

8. The latch circuit against single event multiple bit upsets according to claim 1 or 2, characterized in that, The latch circuit adopts a combination of circuit hardening technology and layout hardening technology to realize the anti-single event upset hardening of internal nodes.

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