Multiple phase clock generator, memory device, and method of generating multiple phase clocks

Abstract

Multi-phase clock generators, memory devices, and methods of generating multi-phase clocks are provided. The multi-phase clock generator includes a first variable delay line and a second variable delay line; a first phase splitter configured to phase split a first phase-delayed clock output from a clock tree to output a first divided clock and a third divided clock; a second phase splitter configured to phase split a second phase-delayed clock output from the clock tree to output a second divided clock and a fourth divided clock; a first duty cycle detector configured to detect a first duty cycle error between the first divided clock and the third divided clock; and a second duty cycle detector configured to detect a second duty cycle error between the second divided clock and the fourth divided clock. The first variable delay line is controlled according to the first duty cycle error, and the second variable delay line is controlled according to the second duty cycle error.

Description

[0001] Cross-references to related applications

[0002] This patent application claims the benefit of priority to Korean Patent Application No. 10-2020-0057543, filed on May 14, 2020, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Exemplary embodiments of this disclosure relate to a multiphase clock generator, a memory device including the multiphase clock generator, and a method for generating a multiphase clock for the memory device. Background Technology

[0004] In input / output (I / O) interface methods that synchronize data with clock signals and transmit synchronized data between the system's memory and memory controller, it is crucial to ensure proper synchronization of data with clock signals. Because Dynamic Random Access Memory (DRAM) operates at high speeds, it can utilize Delay-Locked Loop (DLL) circuitry to synchronize data with clock signals.

[0005] The DLL circuit includes a coarse delay line with high delay resolution and a fine delay line with low delay resolution. Summary of the Invention

[0006] An exemplary embodiment of the present invention provides a multiphase clock generator, a memory device including the multiphase clock generator, and a method for generating a multiphase clock for the memory device.

[0007] Exemplary embodiments of the present invention provide a multiphase clock generator that can be implemented in a small area, a memory device including the multiphase clock generator, and a method for generating a multiphase clock for the memory device.

[0008] According to an exemplary embodiment of the present invention, a multiphase clock generator includes: a first variable delay line, a second variable delay line, a fixed delay line, a delay line controller, a phase controller, a clock tree, a first phase splitter, a second phase splitter, a first duty cycle detector, and a second duty cycle detector. The first variable delay line is configured to receive a reference clock and generate a delayed clock. The second variable delay line is configured to receive the delayed clock and generate a second phase delayed clock. The fixed delay line is configured to receive the delayed clock and generate a first phase delayed clock. The delay line controller is configured to control the first variable delay line based on a first phase difference between the reference clock and a feedback clock. The phase controller is configured to control the second variable delay line based on a second phase difference between the delayed clock and the second phase delayed clock. The clock tree is configured to receive the first phase delayed clock and the second phase delayed clock. The first phase splitter is configured to perform phase splitting on the first phase delayed clock output from the clock tree to output a first divided clock and a third divided clock. The second phase splitter is configured to perform phase splitting on the second phase delayed clock output from the clock tree to output a second divided clock and a fourth divided clock. A first duty cycle detector is configured to detect a first duty cycle error between a first divided clock and a third divided clock. A second duty cycle detector is configured to detect a second duty cycle error between a second divided clock and a fourth divided clock. A first variable delay line is controlled according to the first duty cycle error, and a second variable delay line is controlled according to the second duty cycle error.

[0009] According to an exemplary embodiment of the present invention, a memory device including a multiphase clock generator includes: a delay-locked loop circuit, a clock tree, a fixed delay line, a second variable delay line, a phase controller, a first phase splitter, a second phase splitter, a first duty cycle detector, and a second duty cycle detector. The delay-locked loop circuit is configured to receive a reference clock and output a delayed clock. The clock tree is configured to receive a delayed clock and output a delayed clock. The fixed delay line is configured to receive a delayed clock and output a first phase delayed clock. The second variable delay line is configured to phase-shift the delayed clock to generate a second phase delayed clock. The phase controller is configured to control the second variable delay line based on a second phase difference between the delayed clock and the second phase delayed clock. The first phase splitter is configured to phase-split the first phase delayed clock to output a first divided clock and a third divided clock. The second phase splitter is configured to phase-split the second phase delayed clock to output a second divided clock and a fourth divided clock. The first duty cycle detector is configured to detect a first duty cycle error between the first divided clock and the third divided clock. The second duty cycle detector is configured to detect a second duty cycle error between the second and fourth divided clocks. The delay-locked loop circuit is controlled according to the first duty cycle error, and the second variable delay line is controlled according to the second duty cycle error.

[0010] According to an exemplary embodiment of the present invention, a method for generating a multiphase clock for a memory device includes: initiating a delay-locked loop operation to receive a reference clock and generate a delayed clock; performing a coarse-locking operation on the reference clock; determining whether the coarse-locking operation is completed; when the coarse-locking operation is completed, performing a fine-locking operation simultaneously performing a first duty cycle error correction operation between a first divided clock and a third divided clock corresponding to the delayed clock; performing phase separation on at least one phase delayed clock generated based on the delayed clock to generate a phase-divided clock; and performing a second duty cycle error correction operation between a second divided clock and a fourth divided clock corresponding to the phase-divided clock. Attached Figure Description

[0011] This disclosure will become clearer from the following detailed description, taken in conjunction with the accompanying drawings.

[0012] Figure 1 This is a schematic block diagram of a multiphase clock generator according to an exemplary embodiment of the present invention.

[0013] Figure 2 yes Figure 1 Detailed block diagrams of the first and second variable delay lines are shown.

[0014] Figure 3 This is a flowchart illustrating an operation method of a multiphase clock generator according to an exemplary embodiment of the present invention.

[0015] Figure 4 It is shown Figure 3 The timing diagram shown indicates the start of the DLL operation.

[0016] Figure 5 yes Figure 3 The timing diagram shown is a rough lock operation.

[0017] Figure 6 This is a timing diagram of the phase shift operation during the execution of duty cycle error correction operation according to an exemplary embodiment of the present invention.

[0018] Figure 7 This is a block diagram of a multiphase clock generator according to an exemplary embodiment of the present invention.

[0019] Figure 8 This is a schematic block diagram illustrating an exemplary embodiment of the invention, showing the process of generating a multiphase clock by a multiphase clock generator.

[0020] Figure 9 This is a block diagram of a memory device according to an exemplary embodiment of the present invention.

[0021] Figure 10This is a perspective view of a memory chip according to an exemplary embodiment of the present invention.

[0022] Figure 11 This is a block diagram of a computing system according to an exemplary embodiment of the present invention.

[0023] Figure 12 This is a block diagram of a vehicle electronic system according to an exemplary embodiment of the present invention.

[0024] Figure 13 This is a block diagram of a mobile device according to an exemplary embodiment of the present invention.

[0025] Figure 14 This is a block diagram of a computing system according to an exemplary embodiment of the present invention.

[0026] Figure 15 This is a block diagram of a data center that applies a memory device according to an exemplary embodiment. Detailed Implementation

[0027] In the following description, exemplary embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0028] In the multiphase clock generator, the memory device including the multiphase clock generator, and the method for generating the multiphase clock of the memory device according to an exemplary embodiment of the present invention, a 90-degree phase clock is generated from the output of a delay-locked loop (DLL), the duty cycle of the generated 90-degree phase clock and the duty cycle of the DLL are compensated, and the multiphase clock is generated by phase separation.

[0029] Figure 1 This is a schematic block diagram of a multiphase clock generator 100 according to an exemplary embodiment of the present invention.

[0030] Reference Figure 1 The multiphase clock generator 100 includes a clock buffer (CLK BUF) 110.

[0031] (e.g., buffer circuit), first variable delay line (VDL1) 120, delay line controller (VDL CNTL) 124 (e.g., control circuit), phase detector (PD) 127 (e.g., phase detection circuit), replicator 128, fixed delay line (FDL) 130, second variable delay line (VDL2) 140, phase controller (PHASE CNTL) 144 (e.g., control circuit), clock tree (CLK TREE) 150, first phase splitter (PS1) 161, second phase splitter (PS2) 162, first duty cycle detector (DCD1) 163 (e.g., detector circuit), second duty cycle detector (DCD2) 164 (e.g., detector circuit) and output buffer (DOUT) 170 (e.g., buffer circuit).

[0032] The multiphase clock generator 100 receives an input clock CK (e.g., a clock signal), generates a reference clock DLLIN_CK from the input clock CK, and divides the frequency of the reference clock DLLIN_CK to generate first divided clocks to fourth divided clocks PDLL0, PDLL90, PDLL180 and PDLL270, which have a 90-degree phase difference from each other.

[0033] The clock buffer (CLK BUF) 110 can buffer the input clock CK to generate the reference clock DLLIN_CK.

[0034] The first variable delay line (VDL1) 120 receives a reference clock DLLIN_CK from the clock buffer 110 and delays the reference clock DLLIN_CK according to a first phase difference or a first duty cycle error to output a delayed clock DLL_CK0. The first phase difference may include the phase difference between the reference clock DLLIN_CK and the first phase delayed clock DLL_CK0D of the fixed delay line 130. The first duty cycle error may be the duty cycle error between the first divided clock PDLL0 and the third divided clock PDLL180. However, the first phase difference and the first duty cycle error are not limited to these.

[0035] In this embodiment, the delay line controller (VDL CNTL) 124 controls the first variable delay line 120 based on a code value corresponding to the phase difference. For example, the delay line controller 124 can determine the on / off state of the delay units constituting the first variable delay line 120 based on the code value to control the delay of the reference clock DLLIN_CK.

[0036] Phase detector (PD) 127 detects the phase between the feedback clock FBCLK and the reference clock DLLIN_CK.

[0037] The replicator 128 may have a delay amount substantially the same as the clock path of the delayed reference clock DLLIN_CK. In an embodiment, the replicator 128 delays its signal by the same amount as the first variable delay line (VDL1) 120 delays the reference clock DLLIN_CK. In an exemplary embodiment, the replicator 128 is implemented by a delay circuit.

[0038] The fixed delay line (FDL) 130 receives the delayed clock DLL_CK0 from the first variable delay line 120 and outputs the first phase delayed clock DLL_CK0D.

[0039] The second variable delay line (VDL2) 140 receives the delayed clock DLL_CK0 from the first variable delay line 120 and outputs a second phase delayed clock DLL_CK90 based on a phase control code value corresponding to the second phase difference or a second duty cycle error. In this embodiment, the phase control code value is a value corresponding to the phase difference between the delayed clock DLL_CK0 and the second phase delayed clock DLL_CK90, and the second duty cycle error is the duty cycle error between the second divider clock PDLL90 and the fourth divider clock PDLL270. However, the second phase difference and the second duty cycle error are not limited to these.

[0040] The phase controller (PHASE CNTL) 144 outputs a phase control code value corresponding to the phase difference between the delayed clock DLL_CK0 and the second phase delayed clock DLL_CK90.

[0041] Clock tree (CLK TREE) 150 receives a first phase-delayed clock DLL_CK0D and a second phase-delayed clock DLL_CK90. The first phase-delayed clock DLL_CK0D and the second phase-delayed clock DLL_CK90 can be transmitted within the semiconductor memory device via an internal path. Clock tree 150 outputs the first phase-delayed clock DLL_CK0D to a first phase splitter (PS1) 161 and outputs the second phase-delayed clock DLL_CK90 to a second phase splitter (PS2) 162.

[0042] The first phase splitter (PS1) 161 receives the first phase delay clock DLL_CK0D and performs phase splitting on the first phase delay clock DLL_CK0D to output the first divided clock PDLL0 and the third divided clock PDLL180.

[0043] The second phase splitter (PS2) 162 receives the second phase delay clock DLL_CK90 and performs phase separation on the second phase delay clock DLL_CK90 to output the second divided clock PDLL90 and the fourth divided clock PDLL270.

[0044] The first duty cycle detector (DCD1) 163 is configured to detect a first duty cycle error between the first divided clock PDLL0 and the third divided clock PDLL180.

[0045] The second duty cycle detector (DCD2) 164 is configured to detect a second duty cycle error between the second divided clock PDLL90 and the fourth divided clock PDLL270.

[0046] The output buffer 170 can buffer the first divided clock to the fourth divided clock PDLL0, PDLL90, PDLL180 and PDLL270 with different phases output from the first phase splitter 161 and the second phase splitter 162, and can output the buffered first divided clock to the fourth divided clock PDLL0, PDLL90, PDLL180 and PDLL270 to the outside.

[0047] Multiphase clocks (e.g., 4-phase clocks) are used to address the internal bandwidth limitations of memory devices. The offset between these multiphase clocks needs to be corrected. Previous multiphase clock generators included complex multiphase detectors that occupied a large area and consumed significant power.

[0048] The multiphase clock generator 100, according to an exemplary embodiment of the present invention, is configured to correct the duty cycle of a zero-division clock to compensate for the offset between 0 degrees and 180 degrees, and uses a delay-locked loop (DLL) to correct the phase difference to compensate for the offset between 0 degrees and 90 degrees. Therefore, the multiphase clock generator 100 can reduce power consumption and can be implemented with a less complex structure.

[0049] Each of the first variable delay line 120 and the second variable delay line 140 according to an exemplary embodiment of the present invention includes a coarse delay line and a fine delay line.

[0050] Figure 2 yes Figure 1 Detailed block diagrams of the first variable delay line 120 and the second variable delay line 140 are shown. (Refer to...) Figure 2 The first variable delay line 120 includes a first coarse delay line (COARSE DL1) 121, a first fine delay line (FINE DL1) 122, and a first duty cycle correction circuit (DCC1) 123.

[0051] In an embodiment, the first coarse delay line (COARSE DL1) 121 uses cascaded first coarse delay units to delay the reference clock DLLIN_CK. Each of the first coarse delay units can be turned on / off according to a first coarse code CC1. For example, a delay unit turned on according to the first coarse code CC1 has a first coarse delay amount. A delay unit turned on according to the first coarse code CC1 can be bypassed.

[0052] In an embodiment, the first fine delay line (FINE DL1) 122 uses first fine delay units to delay the clock output from the first coarse delay line 121. Each of the first fine delay units can be turned on / off according to a first fine code FC1. For example, a delay unit turned on according to the first fine code FC1 has a first fine delay amount. A delay unit turned on according to the first fine code FC1 can be bypassed.

[0053] In an exemplary embodiment, phase detector (PD) 127 detects a first phase difference between a reference clock DLLIN_CK and a feedback clock FBCLK. Delay line controller 124 may include a coarse delay line controller (CDL CNTL) 125 and a fine delay line controller (FDL CNTL) 126. The coarse delay line controller 125 generates a first coarse code CC1 corresponding to the first phase difference. The fine delay line controller 126 generates a first fine code PC1 corresponding to the first phase difference.

[0054] The first duty cycle correction circuit (DCC1) 123 controls the clock output from the first fine delay line 122 based on the first duty cycle error. The first duty cycle error can be output from the first duty cycle detector (DCD1) 163. In an embodiment, the delayed clock DLL_CK0 output from the first duty cycle correction circuit 123 is sent to the fixed delay line 130 and the second variable delay line 140.

[0055] Continue to refer to Figure 2 The second variable delay line 140 includes a second coarse delay line (COARSE DL2) 141, a second fine delay line (FINE DL2) 142, and a second duty cycle correction circuit (DCC2) 143.

[0056] In an embodiment, the second coarse delay line (COARSE DL2) 141 uses cascaded second coarse delay units to delay the clock DLL_CK0. In an embodiment, each of the second coarse delay units is turned on / off according to the second coarse code CC2.

[0057] The second fine delay line (FINE DL2) 142 uses the second fine delay unit to delay the clock output from the second coarse delay line 141. In an embodiment, each of the second fine delay units is turned on / off according to the second fine code FC2.

[0058] In an exemplary embodiment, the phase controller (PHASE CNTL) 144 generates a second coarse code CC2 and a second fine code FC2 corresponding to a second phase difference between the delayed clock DLL_CK0 and the clock output from the second fine delay line 142.

[0059] The second duty cycle correction circuit (DCC2) 143 controls the clock output from the second fine delay line 142 based on the second duty cycle error. The second duty cycle error can be output from the second duty cycle detector (DCD2) 164. In this embodiment, the second phase delay clock DLL_CK90 output from the second duty cycle correction circuit 143 is sent to the clock tree 150 (see...). Figure 1 ).

[0060] Figure 3 This is a flowchart illustrating an operation method of a multiphase clock generator 100 according to an exemplary embodiment of the present invention. (Refer to...) Figures 1 to 3 The operation of the multiphase clock generator 100 will be described below.

[0061] For ease of description, it will be assumed that the multiphase clock generator 100 is installed in the memory device. During the power-on of the memory device, the multiphase clock generator 100 begins to operate (S110).

[0062] The multiphase clock generator 100 receives an input clock CK and uses the input clock CK to initiate a delay-locked loop (DLL) operation (S120). The DLL operation can be performed through the following steps: a first variable delay line (VDL1) 120 delays a reference clock DLLIN_CK; a variable delay line controller (VDL CNTL) 124 determines the amount of delay of the first variable delay line 120 based on a first phase difference; a phase detector (PD) 127 detects the first phase difference between the reference clock DLLIN_CK and the feedback clock FBCLK; and a replicator 128 delays the first phase-delayed clock DLL_CK0D by a predetermined value to output the feedback clock FBCLK. The DLL operation can include coarse-locking and fine-locking operations.

[0063] A coarse locking operation is performed based on the first phase difference (S130). Then, it is determined whether the coarse locking operation is complete (S140). If the coarse locking operation is not complete, the process proceeds to S130.

[0064] When the coarse locking operation is completed, a first duty cycle error correction operation (e.g., DCC0) and a fine locking operation are performed on the delay path of the reference clock DLLIN_CK (S150). Phase splitting is then performed by the corresponding phase splitter (S160). Phase splitting can be performed simultaneously with the first duty cycle error correction operation or the fine locking operation. For example, the reference clock DLLIN_CK, its delayed clock DLL_CK0, or the first phase delayed clock DLL_CK0D and the second phase delayed clock DLL_CK90 of the delayed clock DLL_CK0 can be phase-split by their respective phase splitters. A second duty cycle error correction operation (e.g., DCC90) is performed between the phase-divided clocks (e.g., PDLL90 and PDLL270) with phase (S170).

[0065] In an exemplary embodiment, phase separation may further include: through a fixed delay line (FDL) 130 (see... Figure 1 The delayed clock DLL_CK0 is output as the first phase delayed clock DLL_CK0D, and transmitted through the variable delay line (VDL2) 140 (see...). Figure 1 The process involves generating a second-phase delayed clock DLL_CK90 from a delayed clock DLL_CK0, performing phase separation on a first-phase delayed clock DLL_CK0D to generate a first-divided clock PDLL0 and a third-divided clock PDLL180, and performing phase separation on the second-phase delayed clock DLL_CK90 to generate a second-divided clock PDLL90 and a fourth-divided clock PDLL270. In an exemplary embodiment, the first-phase delayed clock DLL_CK0D has the same phase as the delayed clock DLL_CK0, and the second-phase delayed clock DLL_CK90 is obtained by phase-shifting the delayed clock DLL_CK0 by 90 degrees.

[0066] In an exemplary embodiment, from clock tree 150 (see...) Figure 1 The steps of receiving the first phase delay clock DLL_CK0D and the second phase delay clock DLL_CK90 and outputting the first phase delay clock DLL_CK0D and the second phase delay clock DLL_CK90 by the clock tree 150 can also include Figure 3 In the method.

[0067] Figure 4 It is shown Figure 3 The timing diagram shown indicates the start of the DLL operation.

[0068] Reference Figure 4 Describes the initial timing sequence at the start of DLL operations. For example... Figure 4As shown, the reference clock DLLIN_CK and the feedback clock FBCLK are in an unlocked state. A DLL operation can be initiated to lock the feedback clock FBCLK to the reference clock DLLIN_CK.

[0069] In an exemplary embodiment, the delayed clock DLL_CK0, the first phase delayed clock DLL_CK0D, and the second phase delayed clock DLL_CK90 are identical in their initial states. For example, the initial transitions from logic low to logic high of the delayed clock DLL_CK0, the first phase delayed clock DLL_CK0D, and the second phase delayed clock DLL_CK90 can occur substantially simultaneously.

[0070] In an exemplary embodiment, the first divided clock PDLL0 and the third divided clock PDLL180 are phase-split by a phase splitter to have opposite phases. Similarly, the second divided clock PDLL90 and the fourth divided clock PDLL270 are phase-split by a phase splitter to have opposite phases.

[0071] Figure 5 yes Figure 3 The timing diagram for a rough locking operation is shown. (Refer to...) Figure 5 After a predetermined time, the first to fourth frequency divider clocks PDLL0, PDLL90, PDLL180 and PDLL270 are output. At the same time, through a coarse locking operation, the first to fourth frequency divider clocks PDLL0, PDLL90, PDLL180 and PDLL270 have different phases at the same time point.

[0072] Figure 6 This is a timing diagram of the phase shift operation during duty cycle error correction operation according to an exemplary embodiment of the present invention. (Refer to...) Figure 6 It detects duty cycle error between 0 and 180 degrees and can perform duty cycle error correction based on the detected error. A 90-degree phase shift operation can be performed simultaneously with the duty cycle error correction operation.

[0073] like Figure 6 As shown, the second phase-delayed clock DLL_CK90 can be generated by performing a 90-degree phase shift operation on the first phase-delayed clock DLL_CKD0. Additionally, the first divider clock PDLL0 can be phase-shifted by 90 degrees to generate the second divider clock PDLL90.

[0074] exist Figures 1 to 6In this embodiment, the replicator 128 (e.g., circuitry) feeds back a first phase-delayed clock DLL_CK0D output from the fixed delay line (FDL) 130 to perform DLL operations. However, embodiments of this disclosure are not limited thereto. According to embodiments, the replicator feeds back the output clock of the first variable delay line 120 to perform DLL operations.

[0075] Figure 7 This is a block diagram of a multiphase clock generator 100a according to an exemplary embodiment of the present invention. (Refer to...) Figure 7 The multiphase clock generator 100a includes a clock buffer 110, a first variable delay line 120, a delay line controller 124, a phase detector 127, a replicator 128a (e.g., a circuit), a fixed delay line 130a, a second variable delay line 140a, a phase controller 144a, a clock tree 150a, a first phase splitter 161a, a second phase splitter 162a, a first duty cycle detector 163, a second duty cycle detector 164, and an output buffer 170.

[0076] like Figure 7 As shown, with Figure 1 Compared to the multiphase clock generator 100 shown, the multiphase clock generator 100a includes: a replicator 128a that receives feedback from a first variable delay line 120, a clock tree 150a connected to the first variable delay line 120, a fixed delay line 130a for the delayed clock DLL_CK0 of the delayed clock tree 150a, a second variable delay line 140a that controls the phase of the delayed clock DLL_CK0 of the clock tree 150a, and a phase controller 144a that controls the second variable delay line 140a.

[0077] Figure 8 This is a schematic block diagram illustrating an exemplary embodiment of the invention, showing the process of generating a multiphase clock using a multiphase clock generator. (Refer to...) Figure 8 During the DLL operation, the reference clock REF CLK can be divided into four phase clocks with different phases through phase shifting and phase separation. An externally received single-phase clock can be divided into four phase clocks through DLL operation, phase shifting operation, or phase separation operation.

[0078] In an exemplary embodiment, during the phase shift period, the clock can be switched from the DLL clock (e.g., Figure 1 The first phase clock (e.g., DLL_CK0) is separated from the DLL_CK0. Figure 1 DLL_CK0D) and the second phase clock (e.g., Figure 1 (DLL_CK90). The DLL clock can be a clock output by performing a DLL operation on the clock path of the reference clock REF CLK.

[0079] In an exemplary embodiment, during the phase separation period, the first phase clock is separated from the first phase clock phase (e.g., Figure 1 PDLL0) and the third phase clock (e.g., Figure 1 The PDLL180), and the second phase clock is separated from the second phase clock phase (e.g., Figure 1 PDLL90) and the fourth phase clock (e.g., Figure 1 (PDLL270).

[0080] In an exemplary embodiment, duty cycle error correction corresponding to the duty cycle error is performed between the first phase clock and the third phase clock. In an exemplary embodiment, duty cycle error correction corresponding to the duty cycle error is performed between the second phase clock and the fourth phase clock.

[0081] The multiphase clock generator according to the exemplary embodiments can be applied to memory devices.

[0082] Figure 9 This is a block diagram of a memory device 200 according to an exemplary embodiment of the present invention. (Refer to...) Figure 9 The memory device 200 includes a memory cell array 210, a row decoder 220, a column decoder 230, a sense amplifier circuit 240, an address register 250, memory bank control logic 252, a refresh counter 254, a row address multiplexer (RA MUX) 256, a column address latch (CA LATCH) 258, control logic 260, a repair control circuit 266, a timing control circuit 264, an input / output (I / O) gate circuit 270, an error correction circuit 280, a data input / output (I / O) buffer 282, and a PBT circuit 290.

[0083] The memory cell array 210 may include a first memory bank 211 to an eighth memory bank 218. However, the number of memory banks in the memory cell array 210 is not limited to this.

[0084] The line decoder 220 may include first storage line decoders 221 to eighth storage line decoders 228, which are respectively connected to the first storage bank 211 to the eighth storage bank 218.

[0085] The column decoder 230 may include first storage column decoders 231 to eighth storage column decoders 238, which are respectively connected to the first storage bank 211 to the eighth storage bank 218.

[0086] The readout amplifier circuit 240 may include first memory readout amplifiers 241 to eighth memory readout amplifiers 248 respectively connected to the first memory bank 211 to the eighth memory bank 218.

[0087] The first memory bank 211 to the eighth memory bank 218, the first memory bank row decoder 221 to the eighth memory bank row decoder 228, the first memory bank column decoder 231 to the eighth memory bank column decoder 238, and the first memory bank sense amplifier 241 to the eighth memory bank sense amplifier 248 can each constitute the first memory bank to the eighth memory bank. Each of the first memory bank 211 to the eighth memory bank 218 may include multiple memory cells MC formed at the intersection of word line WL and bit line BL.

[0088] Address register 250 can receive and store address ADDR, which has bank address BANK_ADDR, row address ROW_ADDR, and column address COL_ADDR, from the external memory controller. Address register 250 can provide the received bank address BANK_ADDR to the bank control logic 252, the received row address ROW_ADDR to the row address multiplexer 256, and the received column address COL_ADDR to the column address latch 258.

[0089] The bank control logic 252 can generate a bank control signal in response to the bank address BANK_ADDR. In the first bank row decoder 221 to the eighth bank row decoder 228, the bank row decoder corresponding to the bank address BANK_ADDR can be activated in response to the bank control signal. In the first bank column decoder 231 to the eighth bank column decoder 238, the bank column decoder corresponding to the bank address BANK_ADDR can be activated in response to the bank control signal.

[0090] The row address multiplexer 256 can receive the row address ROW_ADDR from the address register 250 and the refresh row address REF_ADDR from the refresh counter 254. The row address multiplexer 256 can selectively output either the row address ROW_ADDR or the refresh row address REF_ADDR as the row address RA. The row address RA output from the row address multiplexer 256 can be applied to each of the first memory bank row decoders 221 to the eighth memory bank row decoders 228.

[0091] In the first to eighth bank row decoders 221, the bank row decoder activated by the bank control logic 252 can decode the row address RA output from the row address multiplexer 256 to activate the word line corresponding to the row address. For example, the activated bank row decoder can apply a word line drive voltage to the word line corresponding to the row address. In addition, the activated bank row decoder can activate the word line corresponding to the row address and can simultaneously activate the redundant word line corresponding to the redundant row address output from the repair control circuit 266.

[0092] Column address latch 258 can receive column address COL_ADDR from address register 250 and can temporarily store the received column address COL_ADDR. Additionally, column address latch 258 can incrementally increment the received column address COL_ADDR in burst mode. Column address latch 258 can apply the temporarily stored or incrementally incremented column address COL_ADDR to each of the first bank column decoders 231 to the eighth bank column decoders 238.

[0093] In the first to eighth bank column decoders 231, the bank column decoder activated by the bank control logic 252 can activate the sense amplifiers corresponding to the bank address BANK_ADDR and the column address COL_ADDR through the input / output gating circuit 270. Furthermore, the activated bank column decoder can perform a column repair operation in response to the column repair signal CRP output from the repair control circuit 266.

[0094] Control logic 260 can control the operation of memory device 200. For example, control logic 260 can generate control signals to cause memory device 200 to perform write or read operations. Control logic 260 may include command decoder 261 for decoding commands (CMD) received from memory controller, and mode register group 262 for setting the operating mode of memory device 200.

[0095] For example, command decoder 261 can decode the write enable signal / WE, row address strobe signal / RAS, column address strobe signal / CAS, and chip select signal / CS to generate operation control signals ACT, PCH, WE, and RD corresponding to the command CMD. Control logic 260 can provide the operation control signals ACT, PCH, WE, and RD to timing control circuitry 264. The operation control signals ACT, PCH, WR, and RD may include an active signal ACT, a precharge signal PCH, a write signal WR, and a read signal RD. Timing control circuitry 264 can generate a first control signal CTL1 for controlling the voltage level of word line WL and a second control signal CTL2 for controlling the voltage level of bit line BL in response to the operation control signals ACT, PCH, WR, and RD, and can provide the first control signal CTL1 and the second control signal CTL2 to memory cell array 210.

[0096] Repair control circuit 266 can generate repair control signals CRP and SRP for controlling the repair operation of the first and second cell regions of at least one memory bank, based on the row address ROW_ADDR and column address COL_ADDR of the address ADDR (or access address) and the fuse information of each word line. Repair control circuit 266 can provide redundant row addresses to the corresponding memory bank row decoder, provide column repair signals CRP to the corresponding memory bank column decoder, and provide selection and enable signals SRA to the block control circuit associated with the corresponding redundant array block. Additionally, repair control circuit 266 can generate an hPPR word line activation signal in response to the address ADDR in hPPR mode stored in mode register group 262. Furthermore, repair control circuit 266 can generate an sPPR word line activation signal sPPR_WL_EN in response to the address ADDR in sPPR mode stored in mode register group 1262. Furthermore, the repair control circuit 266 can disable the sPPR logic in sPPR_OFF mode and can generate a normal word line activation signal to access previous data. In an exemplary embodiment, the repair control circuit 266 modifies the repair unit based on the address ADDR and fuse information. For example, the repair control circuit 266 can change the type and quantity of the address ADDR and fuse information.

[0097] The input / output gating circuit 270 may include a plurality of input / output gate circuits. Each of the plurality of input / output gate circuits may include circuitry for gating input / output data, and may also include input data masking logic, a data latch for storing data output from the first memory bank 211 to the eighth memory bank 218, and a write driver for writing data to the first memory bank 211 to the eighth memory bank 218.

[0098] Error correction circuit 280 can generate parity bits based on the data bits of data DQ provided from data input / output buffer 282 during a write operation, and can provide a codeword CW including data DQ and parity bits to input / output gating circuit 270, which can write the codeword CW into memory. Furthermore, error correction circuit 280 can receive the codeword CW read from a single memory bank from input / output gating circuit 270 during a read operation. In an embodiment, error correction circuit 280 performs ECC decoding on data DQ using the parity bits included in the read codeword CW to correct at least one erroneous bit included in data DQ, and provides at least one corrected erroneous bit to data input / output buffer 282.

[0099] In an exemplary embodiment, the codeword CW to be read from one of the first to eighth memory banks 211 is read by the sense amplifier corresponding to that memory bank and stored in a data latch. After ECC decoding is performed by the error correction circuit 280, the codeword CW stored in the data latch can be provided to the memory controller through the data input / output buffer 282. After ECC encoding is performed by the error correction circuit 280, the data DQ to be written to one of the first to eighth memory banks 211 can be written to that memory bank by the write driver.

[0100] The data input / output buffer 282 can provide data DQ to the error correction circuit 280 according to the clock CLK provided from the memory controller during a write operation, and can provide data DQ provided from the error correction circuit 280 to the memory controller during a read operation.

[0101] In an exemplary embodiment, the data input / output buffer 282 includes Figures 1 to 8 The multiphase clock generator (MPC) 100 described in [the document] (see [document name]) Figure 1 An externally received clock can be divided into multiple phases. These divided clocks can be used to perform data output operations.

[0102] The PBT circuit 290 can perform parallel test operations on each of the test data received from the outside and in the memory bank, perform repair operations when errors are correctable, and output result values ​​based on the results. Furthermore, the PBT circuit 290 can consider the memory bank qualified in response to the test pass signal PBTPASS, regardless of the result value of the test operation on the corresponding memory bank. In an exemplary embodiment, during the parallel bit test operation, the test pass signal PBTPASS is output from the mode register group 262.

[0103] Memory devices (e.g., DRAM) can divide an external clock and use the divided clock to overcome internal frequency limitations. For example, a divided clock may include four phases. The data output terminals of the memory device can restore the divided clock to the same frequency as the received external clock. However, when a memory device uses a multi-phase clock, offsets may occur between the multiple phases. When the divided clock is restored to the same frequency as the external clock, this offset can cause duty cycle errors.

[0104] A memory device 200 according to an exemplary embodiment of the present invention includes a multiphase clock generator (MPC) to precisely match the phase relationship between multiple phases to 90 degrees. The multiphase clock generator (MPC) of this disclosure can correct duty cycle errors of a divided clock by inputting a divided clock to a duty cycle detector (DCC) to compensate for an offset between 0 and 180 degrees (or an offset between 90 and 270 degrees). Alternatively, the multiphase clock generator (MPC) according to embodiments of this disclosure can use a 90-degree phase shift to generate a multiphase clock to correct for the offset between 0 and 90 degrees. In this case, a ring oscillator can be used to perform the phase shift operation.

[0105] The memory device according to the exemplary embodiments can be implemented as a stacked memory device.

[0106] Figure 10 This is a perspective view of a memory chip according to an exemplary embodiment of the present invention. (Refer to...) Figure 10 The memory chip 1000 includes a first memory wafer 1100 to a third memory wafer 1300 stacked in a direction perpendicular to the substrate, and a through-silicon via (TSV). The number of stacked memory wafers is not limited to... Figure 10 The quantities shown. For example, the first memory chip 1100 and the second memory chip 1200 may be slave chips, and the third memory chip 1300 may be a master chip or a buffer chip.

[0107] The first memory chip 1100 may include a first memory cell array 1110 and a first through-electrode region 1120 for accessing the first memory cell array 1110. The second memory chip 1200 may include a second memory cell array 1210 and a second through-electrode region 1220 for accessing the second memory cell array 1210. The first through-electrode region 1120 may refer to a region in which through-electrodes for communication between the first memory chip 1100 and the third memory chip 1300 are disposed in the first memory chip 1100. Similarly, the second through-electrode region 1220 may refer to a region in which through-electrodes for communication between the second memory chip 1200 and the third memory chip 1300 are disposed in the second memory chip 1200. The through-electrodes may provide an electrical path between the first memory chip 1100 and the third memory chip 1300.

[0108] The first memory chip 1100 to the third memory chip 1300 can be electrically connected to each other via through electrodes. For example, the number of through electrodes can be hundreds to thousands, and the through electrodes can be arranged in a matrix. The third memory chip 1300 includes a first peripheral circuit 1310 and a second peripheral circuit 1320. The first peripheral circuit 1310 may include circuitry for accessing the first memory chip 1100, and the second peripheral circuit 1320 may include circuitry for accessing the second memory chip 1200. In an exemplary embodiment, each of the first peripheral circuit 1310 and the second peripheral circuit 1320 can be electrically connected to each other via through electrodes. Figures 1 to 9 The method for generating a multiphase clock and the memory device described herein are used to implement this.

[0109] The memory device according to the exemplary embodiments can be applied to a computing system.

[0110] Figure 11 This is a block diagram of a computing system 2000 according to an exemplary embodiment of the present invention. (Refer to...) Figure 11 The computing system 2000 includes at least one volatile memory module (DIMM) 2100, at least one non-volatile memory module (NVDIMM) 2200, and at least one central processing unit (CPU) 2300.

[0111] The Computing System 2000 can be used as one of many devices, such as a computer, portable computer, ultra-mobile personal computer (UMPC), workstation, data server, netbook, personal data assistant (PDA), network tablet, cordless phone, mobile phone, smartphone, e-book, portable multimedia player (PMP), digital camera, digital recorder / player, digital picture / video recorder / player, portable game console, navigation system, black box, 3D TV, device capable of wirelessly sending and receiving information, wearable device, one of the various electronic devices constituting a home network, one of the various electronic devices constituting a computer network, one of the various electronic devices constituting a telematics network, radio frequency identification (RFID) device, or one of the various electronic devices constituting a computing system.

[0112] At least one non-volatile memory module 2200 may include at least one non-volatile memory. In an exemplary embodiment, the at least one non-volatile memory may include NAND flash memory, vertical NAND flash memory (VNAND), NOR flash memory, resistive random access memory (RRAM), phase-change memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), spin-transfer torque random access memory (STT-RAM), or thyristor random access memory (TRAM).

[0113] In an exemplary embodiment of the present invention, at least one of the volatile memory module 2100 and the non-volatile memory module 2200 is implemented to perform... Figures 1 to 9 The multiphase clock generation operation described in [the document].

[0114] In an embodiment, the volatile memory module 2100 and the non-volatile memory module 2200 can be connected to the central processing unit 2300 via a DDRx interface (where x is an integer of 1 or greater).

[0115] At least one central processing unit 2300 may be implemented as controlling a volatile memory module 2100 and a non-volatile memory module 2200. In an exemplary embodiment, the central processing unit 2300 may include a general-purpose microprocessor, a multi-core processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), or a combination thereof.

[0116] The memory device according to the exemplary embodiments can be applied to automotive systems.

[0117] Figure 12 This is a block diagram of a vehicle electronic system 3000 according to an exemplary embodiment of the present invention. (Refer to...) Figure 12 The vehicle electronic system 3000 includes at least one electronic control unit (ECU) 3100, a memory device 3200, a dynamic range sensor (DVS) 3300, a display device 3400, and a communication processor 3500.

[0118] The electronic control unit (ECU) 3100 can be implemented to control overall operation. The ECU 3100 can process image data received from the DVS 3300. The ECU 3100 may include a neural processing unit (NPU). The NPU can compare the images received from the DVS 3300 with a learned model to quickly determine the optimal image for driving.

[0119] The memory device 3200 can be implemented to store a learning model associated with the operation of the NPU. The memory device 3200 may include a volatile or non-volatile memory device. For example, the memory device 3200 may include DRAM or PRAM. Specifically, the memory device 3200 can perform reference... Figures 1 to 9 The multiphase clock generation operation is described.

[0120] The Dynamic Range Sensor (DVS) 3300 can be implemented to sense the environment outside a vehicle. The DVS 3300 can output an event signal in response to changes in the relative intensity of light. The DVS 3300 may include a pixel array comprising multiple DVS pixels and an address event processor.

[0121] The display device 3400 can be configured to display images processed by the ECU 3100 or images transmitted by the communication processor 3500.

[0122] The communication processor 3500 can be implemented to send processed images to an external device (e.g., an external vehicle) or to receive images from an external vehicle. For example, the communication processor 3500 can be implemented to perform wired or wireless communication with an external device.

[0123] Furthermore, at least one embodiment of this disclosure can be applied to mobile devices.

[0124] Figure 13 This is a block diagram of a mobile device 4000 according to an exemplary embodiment of the present invention. (Refer to...) Figure 13 The mobile device 4000 includes an application processor 4100, at least one DRAM (e.g., 4210, 4220, etc.), at least one storage device 4300, at least one sensor 4400, a display device 4500, an audio device 4600, a network processor 4700, and at least one input / output (I / O) device 4800. For example, the mobile device 4000 can be implemented as a laptop computer, mobile phone, smartphone, tablet PC, or wearable computer.

[0125] Application processor 4100 can be implemented to control the overall operation of mobile device 4000. Application processor 4100 can execute applications that provide internet browsers, games, and videos. In an exemplary embodiment, application processor 4100 may include a single core or multiple cores. For example, application processor 4100 may include multiple cores, such as dual-core, quad-core, or hexa-core. In an exemplary embodiment, application processor 4100 may also include a cache memory disposed internally or externally thereon.

[0126] Application processor 4100 may include controller (CNTL) 4110, neural processing unit (NPU) 4120, and interface (IF) 4130. In an exemplary embodiment, NPU 4120 is optional and may be omitted.

[0127] In an exemplary embodiment, the application processor 4100 is implemented as a system-on-a-chip (SoC). The kernel of the operating system driving on the SoC may include an input / output (I / O) scheduler and a device driver for controlling the storage device 4300. The device driver may control the access performance of the storage device 4300 with reference to the number of synchronization queues managed by the I / O scheduler, or it may control the CPU mode or dynamic voltage-frequency scaling (DVFS) level within the SoC.

[0128] DRAM 4210 can be connected to controller 4110. DRAM 4210 can store data required for the operation of application processor 4100. For example, DRAM 4210 can temporarily store operating system (OS) and application data, or it can be used as execution space for various software codes. DRAM 4220 can be connected to NPU 4120. DRAM 4220 can store data associated with artificial intelligence (AI) operations.

[0129] Compared to I / O devices or flash memory, DRAM 4210 offers relatively high latency and bandwidth (BW). DRAM 4210 can be initialized during the power-on time of the mobile device 4000. When loading operating system and application data, DRAM 4210 can be used as a temporary storage location for operating system and application data, or as space for executing various software code. Mobile systems can perform multitasking to load multiple applications simultaneously, and the switching and execution speed between applications can be used as performance metrics or indicators of the mobile system.

[0130] DRAMs 4210 and 4220 may include, for example Figures 1 to 9 The multiphase clock generator receives a single-phase clock to generate a multiphase clock.

[0131] Storage device 4300 can be connected to interface 4130. In an exemplary embodiment, interface 4130 can operate using at least one of the following communication protocols: Double Data Rate (DDR), DDR2, DDR3, DDR4, Low Power DDR (LPDDR), Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC, Peripheral Component Interconnect (PCI), Non-Volatile Memory Fast (NVMe), PCI Fast (PCIe), SATA Attached Serial (SATA), Small Computer Small Interface (SCSI), Serial Attached SCSI (SAS), USB Attached SCSI (UAS), Internet SCSI (iSCSI), Fibre Channel, and Ethernet Fibre Channel (FCoE). In an exemplary embodiment, any storage device 4300 is included in the mobile device 4000 in an embedded form. In an exemplary embodiment, any storage device 4300 is included in the mobile device 4000 in a removable manner.

[0132] Storage device 4300 can be implemented to store user data. For example, storage device 4300 can store data collected from sensor 4400 or network data, augmented reality (AR) / virtual reality (VR) data, and high-definition (HD) 4K content. Storage device 4300 may include at least one non-volatile memory device. For example, storage device 4300 may include a solid-state drive (SSD) or an embedded multimedia card (eMMC).

[0133] In an exemplary embodiment, the storage device 4300 may be implemented as an additional chip within the application processor 4100, or may be formed together with the application processor 4100 as a single package. In an exemplary embodiment, the storage device 4300 may be mounted using various types of packages. For example, the storage device 4300 can be mounted using packages such as: PoP, Ball Grid Array (BGA), Chip Scale Package (CSP), Plastic Leaded Chip Carrier (PLCC), Plastic Dual In-line Package (PDIP), Die-in Waffle Pack, Wafer Scale Package, Chip on Board (COB), Ceramic Dual In-line Package (CERDIP), Plastic Metric Quad Flat Package (MQFP), Thin Quad Flat Package (TQFP), Small Integrated Circuit (SOIC), Shrink Small Package (SSOP), Thin Small Package (TSOP), Thin Quad Flat Package (TQFP), System-in-Package (SIP), Multi-chip Package (MCP), Wafer-level Fabricated Package (WFP), or Wafer-level Processed Stacked Package (WSP).

[0134] Sensor 4400 can be implemented to sense the external environment of mobile device 4000. In an exemplary embodiment, sensor 4400 includes an image sensor that senses an image. In this case, sensor 4400 can send the generated image information to application processor 4100. In an exemplary embodiment, sensor 4400 includes a biosensor that detects biological information. For example, sensor 4400 can detect fingerprints, iris patterns, vascular patterns, heart rate, or blood glucose, and can generate sensing data corresponding to the sensed information. However, sensor 4400 is not limited to image sensors and biosensors. For example, sensor 4400 according to an exemplary embodiment of this disclosure can include any sensor, such as an illuminance sensor, an acoustic sensor, or an accelerometer.

[0135] Display device 4500 can be implemented to output data. For example, display device 4500 can output image data sensed by sensor 4400, or data calculated by application processor 4100. Audio device 4600 can be implemented to output voice data to an external entity or sense external voice. Network processor 4700 can be implemented to communicate with external devices via wired or wireless communication methods. Input / output device 4800 can be implemented to input data to or output data from mobile device 4000. Input / output device 4800 may include devices that provide digital input and output functions, such as Universal Serial Bus (USB), storage devices, digital cameras, SD cards, touch screens, DVDs, modems, or network adapters.

[0136] At least one embodiment of this disclosure can be applied to various types of computing systems (e.g., CPU / GPU / NPU platforms).

[0137] Figure 14 This is a block diagram of a computing system 5000 according to an exemplary embodiment of the present invention. (Refer to...) Figure 14 The computing system 5000 includes a central processing unit (CPU) 5110, a graphics processing unit (GPU) 5120 (e.g., an accelerator), a neural processing unit (NPU), a dedicated processing unit connected to a system bus 5001, a memory device 5210 or a storage device 5220 connected to the system bus 5001, and an input / output (I / O) device 5310, a modem 5320, a network device 5330, or a storage device 5340 connected to an expansion bus 5002. The expansion bus 5002 can be connected to the system bus 5001 via an expansion bus interface 5003.

[0138] In an exemplary embodiment, CPU 5110 includes an on-chip cache 5111, and GPU 5120 includes an on-chip cache 5121. The NPU may also include an on-chip cache. In an exemplary embodiment, CPU 5110 includes an off-chip cache 5112, and GPU 5120 includes an off-chip cache 5122. Although in Figure 14 Not shown, but the NPU may also include off-chip cache. In an exemplary embodiment, off-chip cache 5112 can be internally connected to CPU 5110, GPU 5120, and NPU via different buses. In an exemplary embodiment, on-chip / off-chip cache includes volatile memory such as dynamic random access memory (DRAM) and static random access memory (SRAM), or non-volatile memory such as NAND flash memory, phase random access memory (PRAM), and resistive random access memory (RRAM).

[0139] In an exemplary embodiment, main memory 5114 and main memory 5124 are connected to CPU 5110 and GPU 5120 via corresponding memory controllers 5113 and 5123. In an embodiment, the main memory can be connected to the NPU via the memory controller. In an exemplary embodiment, memory 5116 and memory 5126 are connected to CPU 5110 and GPU 5120 via corresponding bridges 5115 and 5125. In an embodiment, the memory can be connected to the NPU via a bridge. Bridges 5115 and 5125 (or bridges for the NPU) may include memory controllers that control the corresponding memory 5116 and memory 5126. In an exemplary embodiment, each of bridges 5115 and 5125 (or bridges for the NPU) may be implemented as a network device, a wireless network device, a switch, a bus, a cloud, or an optical channel.

[0140] In an exemplary embodiment, memories 5124, 5126 include GPU memory. GPU memory can hold commands and data interacting with the GPU. Commands and data can be copied from main memory or a storage device. GPU memory can store image data and has higher bandwidth than main memory. GPU memory can have its clock separate from the CPU. The GPU can read image data from GPU memory and process the read image data before writing the image data back to GPU memory. GPU memory can be configured to accelerate graphics processing.

[0141] In an exemplary embodiment, memories 5124 and 5126 include NPU memory. The NPU memory may be main memory for storing commands and data interacting with the NPU. Commands and data can be copied from main memory or a storage device. The NPU memory can hold weight data for the neural network. The bandwidth of the NPU memory can be higher than that of the main memory. The NPU memory can have its clock separate from the CPU. During training, the NPU can write weight data back to the NPU memory after reading and updating the read weight data. The NPU memory can be configured to accelerate machine learning, such as neural network training and inference.

[0142] In an exemplary embodiment, each of the memories 5114, 5116, 5124, 5126, and 5210 can be implemented to perform... Figures 1 to 9 The memory chip described in the article features a multiphase clock generation operation.

[0143] In an exemplary embodiment, the main memory includes volatile memory such as DRAM and SRAM, or non-volatile memory such as NAND flash memory, PRAM, and RRAM. The main memory has lower latency and lower capacity than each of memory 5210 and storage device 5220.

[0144] CPU 5110, GPU 5120, or NPU can access memory 5210 and storage device 5220 via system bus 5001. Memory 5210 can be controlled by memory controller 5211. Memory controller 5211 can be connected to system bus 5001. Storage device 5220 can be controlled by storage controller 5221. Storage controller 5221 can be connected to system bus 5001.

[0145] Storage device 5220 can be implemented to store data. Storage controller 5221 can be implemented to read data from storage device 5220 and send the read data to a host. Storage controller 5221 can be implemented to store the sent data in storage device 5220 in response to a host request. Each of storage device 5220 and storage controller 5221 may include a buffer that stores metadata, a read cache to store frequently accessed data, or a cache to improve write efficiency. For example, a write cache may receive and process a specific number of write requests. Storage device 5220 may include volatile memory such as a hard disk drive (HDD) or non-volatile memory such as NVRAM, SSD, SCM, and new memory.

[0146] At least one embodiment of this disclosure can be applied to a data server system.

[0147] Figure 15 This is a block diagram of a data center 7000 using a memory device according to an exemplary embodiment. (Refer to...) Figure 15 Data center 7000 is a facility for collecting and providing services for various types of data, and may also be referred to as a data storage center. Data center 7000 can be a system for managing search engines and databases, and can be a computing system used in companies such as banks or organizations such as government agencies. Data center 7000 includes application servers 7100 to 7100n and storage servers 7200 to 7200m. The number of application servers 7100 to 7100n and the number of storage servers 7200 to 7200m can vary according to exemplary embodiments, and the number of application servers 7100 to 7100n and the number of storage servers 7200 to 7200m can differ from each other.

[0148] Application server 7100 includes at least one processor 7110 and at least one memory (MEM) 7120. Storage server 7200 includes at least one processor 7210 and at least one memory 7220. As an example, processor 7210 can control the overall operation of storage server 7200 and can access memory 7220 to execute commands and / or data stored in memory 7220. Memory 7220 can be double data rate synchronous DRAM (DDR SDRAM), high bandwidth memory (HBM), hybrid memory cube (HMC), dual in-line memory module (DIMM), Optane DIMM, or non-volatile DIMM (NVMDIMM).

[0149] The number of processors 7210 and memory 7220 included in storage server 7200 can vary. In an exemplary embodiment, processors 7210 and memory 7220 provide processor-memory pairs. In an exemplary embodiment, the number of processors 7210 and the number of memory 7220 are different from each other. Processor 7210 may include a single-core processor or a multi-core processor. The description of storage server 7200 can be similarly applied to application server 7100. In an exemplary embodiment, application server 7100 does not include storage device 7150. Storage server 7200 may include at least one storage device 7250. According to an exemplary embodiment, the number of storage devices 7250 included in storage server 7200 can vary. At least one of storage devices 7150, 7250, 7150n, and 7150m can be implemented to divide a reference clock and use the divided reference clock as a multiphase clock, such as... Figures 1 to 8 As shown.

[0150] Application servers 7100 to 7100n and storage servers 7200 to 7200m can communicate with each other via network 7300. Network 7300 can be implemented using Fibre Channel (FC) or Ethernet. FC can be a medium for relatively high-speed data transmission and can employ optical switches to provide high performance and / or high availability. Storage servers 7200 to 7200m can be provided as file storage, block storage, or object storage, depending on the access method of network 7300.

[0151] In an exemplary embodiment, network 7300 is a storage area network (SAN). For example, the SAN could be an FC-SAN implemented using an FC network and according to the FC protocol (FCP). As another example, the SAN could be an IP-SAN implemented using a TCP / IP network and according to the SCSI over TCP / IP or Internet SCSI (iSCSI) protocol. In an exemplary embodiment, network 7300 is a general-purpose network such as a TCP / IP network. For example, network 7300 could be implemented according to protocols such as FC over Ethernet (FCoE), Network Attached Storage (NAS), or NVMe over Fabric (NVMe-oF).

[0152] In the following description, we will focus on both application server 7100 and storage server 7200. The description of application server 7100 can be applied to another application server 7100n, and the description of storage server 7200 can be applied to another storage server 7200m.

[0153] Application server 7100 can store data requested by users or clients in one of storage servers 7200 to 7200m via network 7300. Furthermore, application server 7100 can retrieve data requested by users or clients from one of storage servers 7200 to 7200m via network 7300. For example, application server 7100 can be implemented as a web server or a database management system (DBMS).

[0154] Application server 7100 can access memory 7120n or storage device 7150n included in another application server 7100n via network 7300, or access memory 7220 to 7220m or storage device 7250 to 7250m included in storage servers 7200 to 7200m via network 7300. Therefore, application server 7100 can perform various operations on data stored in application servers 7100 to 7100n and / or storage servers 7200 to 7200m. For example, application server 7100 can run commands to move or copy data between application servers 7100 to 7100n and / or storage servers 7200 to 7200m. In this scenario, data can be moved from storage servers 7200 to 7200m to storage devices 7250 to 7250m via storage devices 7220 to 7220m, or data can be moved directly to storage devices 7120 to 7120n of application servers 7100 to 7100n. Data moved via network 7300 may be encrypted for security or privacy purposes.

[0155] In the storage server 7200, the interface (NIC) 7254 can provide a physical connection between the processor 7210 and the controller (CTRL) 7251, as well as a physical connection between the NIC 7240 and the controller 7251. For example, the interface 7254 can be implemented using a Direct Attach Storage Device (DAS) method, in which the storage device 7250 is directly connected to a dedicated cable. Alternatively, the interface 7254 can be implemented using various interface types, such as Advanced Technology Attachment (ATA), Serial ATA (SATA), External SATA (e-SATA), Small Computer Small Interface (SCSI), Serial Attached SCSI (SAS), Peripheral PCI Component Interconnect (PCI Express), PCIe (NV Express), NVMe (NVM Express), IEEE 1394, Universal Serial Bus (USB), Secure Digital (SD) card, Multimedia Card (MMC), Embedded Multimedia Card (eMMC), Universal Flash Memory (UFS), Embedded Universal Flash Memory (eUFS), or Compact Flash Memory (CF) card interface.

[0156] The storage server 7200 may also include a switch 7230 and a NIC 7240. Under the control of the processor 7210, the switch 7230 can selectively connect the processor 7210 and the storage device 7250 to each other, or selectively connect the NIC 7240 and the storage device 7250 to each other.

[0157] In an exemplary embodiment, NIC 7240 may include a network interface card or a network adapter. NIC 7240 can be connected to network 7300 via a wired interface, wireless interface, Bluetooth interface, or optical interface. NIC 7240 may include internal memory, a DSP, or a host bus interface, and can be connected to processor 7210 and / or switch 7230 via the host bus interface. The host bus interface may be implemented as one of the above examples of interface 7254. In an exemplary embodiment, NIC 7240 may be integrated with at least one of processor 7210, switch 7230, and storage device 7250.

[0158] In storage servers 7200 to 7200m or application servers 7100 to 7100n, the processor can send data to storage devices 7150 to 7150n and 7250 to 7250m, or send commands to memories 7120 to 7120n and 7220 to 7220m to program or retrieve data. In this case, error correction can be performed on the data using an error correction code (ECC) engine. The data undergoes Data Bus Inversion (DBI) or Data Masking (DM) and may include Cyclic Redundancy Check (CRC) information. For security or privacy, the data can be encrypted.

[0159] Storage devices 7150 to 7150m and 7250 to 7250m can send control signals and command / address signals to NAND flash memory devices 7252 to 7252m in response to a read command received from the processor. Therefore, when reading data from NAND flash memory devices 7252 to 7252m, the read enable signal RE can be input as a data output control signal for outputting data to the DQ bus. The read enable signal RE can be used to generate a data strobe DQS. Command and address signals can be latched in the page buffer based on the rising or falling edge of the write enable signal WE.

[0160] Controller 7251 can control the overall operation of storage device 7250. In an exemplary embodiment, controller 7251 includes static random access memory (SRAM). Controller 7251 can write data to NAND flash memory device 7252 in response to a write command, or can read data from NAND flash memory device 7252 in response to a read command. For example, write and / or read commands can be provided from processor 7210 in storage server 7200, processor 7210m in another storage server 7200m, or processors 7110 and 7110n in application servers 7100 and 7100n. DRAM 7253 can temporarily store (buffer) data to be written to or read from NAND flash memory device 7252. In addition, DRAM 7253 can store metadata. Metadata is user data or data generated by controller 7251 to manage NAND flash memory device 7252. Storage device 7250 may include a security element (SE) for security or privacy.

[0161] An external clock is divided to generate a divided clock, which can be used to overcome the internal frequency limitations of high-speed DRAM. The divided clock may include four phases that are restored to the same frequency as the external clock at the output terminal. When using a multi-phase clock, offsets occur between the multiple phases. When the divided clock is restored to the same frequency as the external clock, a duty cycle error occurs. Therefore, operation is required to precisely match the phase relationships between the multiple phases by 90 degrees. In at least one embodiment of this disclosure, the duty cycle error of the divided clock is corrected by inputting the divided clock to a duty cycle detector to compensate for the offset between 0 and 180 degrees (or the offset between 90 and 270 degrees). The offset between 0 and 90 degrees can be corrected using a ring oscillator for generating the multi-phase clock via a 90-degree phase shift.

[0162] A multiphase clock generator according to an exemplary embodiment of the present invention includes two duty cycle detectors, a duty cycle corrector, a clock tree, a timing controller, a half-phase offset corrector, and a 90-degree phase shifter. In an exemplary embodiment, a 90-degree phase clock is generated using the DLL output signal. In an exemplary embodiment, the offset between 0 degrees and 180 degrees is corrected by adjusting the offset rate of the duty cycle error of the divided clock, and a 90-degree clock and a 270-degree clock are generated using a 90-degree phase shift of the 0-degree clock. In an exemplary embodiment, the fixed delay line is a minimum delay replicator before variable delay line operation. In an exemplary embodiment, the 90-degree phase clock is generated after the DLL is locked (including a first duty cycle error correction DCC0), and a second duty cycle error correction (only falling DCC90) can be additionally performed.

[0163] In the multiphase clock generator, memory device including the multiphase clock generator, and method for generating a multiphase clock for the memory device described above according to exemplary embodiments, the duty cycle between multiphase clocks can be controlled while performing DLL operation on a single-phase clock, and therefore, a reliable multiphase clock can be generated even in a small area.

[0164] Although exemplary embodiments of the inventive concept have been shown and described above, it will be apparent to those skilled in the art that modifications and variations can be made to these embodiments without departing from the scope of the inventive concept.

Claims

1. A multiphase clock generator, comprising: The first variable delay line is configured to receive a reference clock and generate a delayed clock. A second variable delay line is configured to receive the delayed clock and generate a second phase delayed clock; A fixed delay line is configured to receive the delayed clock and generate a first phase delayed clock; A delay line controller is configured to control the first variable delay line based on a first phase difference between the reference clock and the feedback clock; A phase controller is configured to control the second variable delay line based on a second phase difference between the delayed clock and the second phase delayed clock; The clock tree is configured to receive the first phase-delayed clock and the second phase-delayed clock; The first phase splitter is configured to phase-split the first phase-delayed clock received from the clock tree to output a first divided clock and a third divided clock. The second phase splitter is configured to phase-split the second phase-delayed clock received from the clock tree to output a second divided clock and a fourth divided clock. A first duty cycle detector is configured to detect a first duty cycle error between the first divided clock and the third divided clock; as well as A second duty cycle detector is configured to detect a second duty cycle error between the second divided clock and the fourth divided clock. The first variable delay line is controlled according to the first duty cycle error, and the second variable delay line is controlled according to the second duty cycle error.

2. The multiphase clock generator according to claim 1 further includes: A clock buffer is configured to buffer the first phase clock and output the reference clock.

3. The multiphase clock generator according to claim 1 further includes: A replicator is configured to receive the first phase-delayed clock from the fixed delay line and output the feedback clock; as well as A phase detector is configured to detect a first phase difference between the feedback clock from the replicator and the reference clock.

4. The multiphase clock generator according to claim 3, wherein, The first variable delay line includes: A first coarse delay line is configured to receive the reference clock and delay the reference clock according to a first coarse code value; A first fine delay line is configured to receive a clock output from a first coarse delay line and delay the clock from the first coarse delay line according to a first fine code value; and A first duty cycle error corrector is configured to correct the clock received from the first fine delay line based on the first duty cycle error.

5. The multiphase clock generator according to claim 4, wherein, The delay line controller includes: A coarse delay line controller is configured to output the first coarse code value in response to the first phase difference; and A fine delay line controller is configured to output the first fine code value in response to the first phase difference.

6. The multiphase clock generator according to claim 3, wherein, The second variable delay line includes: A second coarse delay line is configured to receive the delayed clock and delay the delayed clock according to a second coarse code value; The second fine delay line is configured to receive the clock output from the second coarse delay line and delay the clock output from the second coarse delay line according to the second fine code value; and The second duty cycle error corrector is configured to correct the clock output from the second fine delay line based on the second duty cycle error.

7. The multiphase clock generator according to claim 6, wherein, The phase controller outputs the second coarse code value and the second fine code value based on the second phase difference between the delayed clock and the clock output from the second fine delay line.

8. The multiphase clock generator according to claim 1, wherein, The first phase-delayed clock has the same phase as the reference clock, and The phase of the second phase-delayed clock is offset by 90 degrees relative to the phase of the reference clock.

9. The multiphase clock generator according to claim 1, wherein, The first frequency divider clock has the same phase as the reference clock. The phase of the second divided clock is offset by 90 degrees relative to the phase of the reference clock. The phase of the third frequency divider clock is offset by 180 degrees relative to the phase of the reference clock, and The phase of the fourth frequency divider clock is offset by 270 degrees relative to the phase of the reference clock.

10. The multiphase clock generator according to claim 1, further comprising: The output buffer is configured to receive the first divided clock, the second divided clock, the third divided clock, and the fourth divided clock, and to output data.

11. A memory device including a multiphase clock generator, the memory device comprising: The delay-locked loop circuit is configured to receive a reference clock and output a delayed clock. A clock tree is configured to receive the delayed clock and output the delayed clock. A fixed delay line is configured to receive the delayed clock and output a first phase delayed clock; The second variable delay line is configured to phase-shift the delayed clock to generate a second phase delayed clock; A phase controller is configured to control the second variable delay line based on a second phase difference between the delayed clock and the second phase delayed clock; The first phase splitter is configured to split the phase of the first phase-delayed clock to output a first divided clock and a third divided clock. The second phase splitter is configured to split the phase of the second phase-delayed clock to output a second divided clock and a fourth divided clock. A first duty cycle detector is configured to detect a first duty cycle error between the first divided clock and the third divided clock; as well as A second duty cycle detector is configured to detect a second duty cycle error between the second divided clock and the fourth divided clock. The delay-locked loop circuit is controlled according to the first duty cycle error, and The second variable delay line is controlled according to the second duty cycle error.

12. The memory device according to claim 11, wherein, The delay-locked loop circuit includes: A first variable delay line is configured to receive the reference clock and generate the delayed clock; The replicator is configured to receive the delayed clock output from the first variable delay line and output a feedback clock; A phase detector is configured to detect a first phase difference between the reference clock and the feedback clock; and A delay line controller is configured to control the first variable delay line based on the first phase difference.

13. The memory device according to claim 12, wherein, The first variable delay line includes: A first coarse delay line is configured to receive the reference clock and delay the reference clock according to a first coarse code value; A first fine delay line is configured to receive a clock output from a first coarse delay line and delay the clock from the first coarse delay line according to a first fine code value; and A first duty cycle error corrector is configured to correct the clock from the first fine delay line based on the first duty cycle error.

14. The memory device according to claim 13, wherein, The delay line controller includes: A coarse delay line controller is configured to output the first coarse code value in response to a first phase difference; and A fine delay line controller is configured to output the first fine code value in response to a first phase difference.

15. The memory device according to claim 11, wherein, The first phase splitter and the second phase splitter separate the received clock into phases with a 180-degree difference.

16. A method for generating a multiphase clock for a memory device, the method comprising: Initiate delay-locked loop operation to receive a reference clock and generate a delayed clock; Perform a coarse locking operation on the reference clock; Determine whether the coarse locking operation has been completed; When the coarse locking operation is completed, a fine locking operation is performed simultaneously with the first duty cycle error correction operation performed between the first and third frequency divider clocks corresponding to the delayed clock; At least one phase-delayed clock generated based on the aforementioned delayed clock is phase-separated to generate a phase-separated clock; as well as A second duty cycle error correction operation is performed between the second and fourth frequency division clocks corresponding to the phase clock.

17. The method of claim 16, further comprising: If the coarse locking operation is not completed, the coarse locking operation is re-executed.

18. The method according to claim 16, wherein, The phase separation includes: The delayed clock is output as the first phase delayed clock through a fixed delay line; A second phase delayed clock is generated by passing the delayed clock through a variable delay line; Phase separation is performed on the first phase-delayed clock to generate the first frequency-divided clock and the third frequency-divided clock; and Phase separation is performed on the second phase-delayed clock to generate the second frequency-divided clock and the fourth frequency-divided clock.

19. The method according to claim 18, wherein, The phase of the first phase-delayed clock is the same as the phase of the delayed clock, and The phase of the second phase-delayed clock is offset by 90 degrees relative to the phase of the delayed clock.

20. The method of claim 18, further comprising: The first phase-delayed clock and the second phase-delayed clock are received through the clock tree; as well as The first phase delay clock and the second phase delay clock are output through the clock tree.

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