Semiconductor structure and manufacturing method therefor

Abstract

The present disclosure relates to a semiconductor structure and a manufacturing method therefor. The semiconductor structure comprises a substrate, a first gate dielectric layer, a first gate, a second gate dielectric layer, a second gate, and a gate lead-out electrode. The substrate comprises a well region of a first conductivity type. A trench is formed in the well region. The first gate dielectric layer at least covers a sidewall of the trench. The thickness of the first gate dielectric layer at the top of the trench is greater than the thickness of the first gate dielectric layer at the bottom of the trench. The first gate covers the surface of the first gate dielectric layer distant from the well region, and fills the trench. The second gate dielectric layer is located on the surface of the well region. The second gate is located on the surface of the second gate dielectric layer distant from the well region. The gate lead-out electrode is electrically connected to both the first gate and the second gate.

Description

Semiconductor structure and method of manufacturing the same TECHNICAL FIELD

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor structure and a method of manufacturing the same. BACKGROUND

[0002] With the continuous development and progress of semiconductor technology, semiconductor devices have become an indispensable important electronic component in modern industry.

[0003] In the application of semiconductor devices, the size of the specific on-resistance determines the power consumption of the device and even the entire chip. In order to reduce the specific on-resistance of the semiconductor device and increase the on-state conduction current, the current technical solution is to use conventional electric field optimization technologies such as reduced surface field technology, super junction technology, field plate technology, etc. However, due to the existence of "silicon limit", there is an upper limit for the performance improvement of semiconductor devices by using these technologies. SUMMARY

[0004] Based on this, the present disclosure provides a semiconductor structure and a method of manufacturing the same, which can reduce the specific on-resistance of the semiconductor device and increase the on-state conduction current, thereby improving the performance of the semiconductor device.

[0005] In one aspect, the present disclosure provides a semiconductor structure, comprising: a substrate, a first gate dielectric layer, a first gate electrode, a second gate dielectric layer, a second gate electrode, and a gate lead-out electrode. The substrate comprises a well region of a first conductivity type. The well region has a trench therein. The first gate dielectric layer covers at least the sidewall of the trench. The thickness of the first gate dielectric layer at the top of the trench is greater than the thickness at the bottom of the trench. The first gate electrode covers the surface of the first gate dielectric layer away from the well region and fills the trench. The second gate dielectric layer is located on the surface of the well region. The second gate electrode is located on the surface of the second gate dielectric layer away from the well region. The gate lead-out electrode is electrically connected to the first gate electrode and the second gate electrode.

[0006] In one embodiment, the material of the first gate electrode comprises doped polysilicon.

[0007] In one embodiment, the ion concentration of the doped polysilicon at the top of the trench is lower than the ion concentration at the bottom of the trench.

[0008] In one embodiment, the doping concentration of the doped polysilicon gradually increases in the direction from the top of the trench to the bottom of the trench.

[0009] In one embodiment, the semiconductor structure further comprises: a bottom semiconductor layer and a buried dielectric layer. The buried dielectric layer is located on the bottom semiconductor layer, and the substrate is located on the surface of the buried dielectric layer away from the bottom semiconductor layer. The bottom of the first gate electrode is in direct contact with the buried dielectric layer.

[0010] In one embodiment, the semiconductor structure further comprises: a drift region of the first conductivity type, a body region of the second conductivity type, a source region, a drain region, a source region lead-out electrode and a drain region lead-out electrode. The drift region of the first conductivity type is located in the well region and is located on a side of the second gate away from the first gate, and the drift region of the first conductivity type has a spacing with the second gate. The body region of the second conductivity type is located in the well region and is located between the second gate and the first gate. The source region is located in the body region. The drain region is located in the drift region. The source region lead-out electrode is electrically connected with the source region. The drain region lead-out electrode is electrically connected with the drain region.

[0011] In one embodiment, the source region comprises, in sequence from the second gate to a direction away from the second gate, a first source diffusion region of the first conductivity type, a second source diffusion region of the second conductivity type and a third source diffusion region of the first conductivity type. The drain region comprises a drain region of the second conductivity type.

[0012] In one embodiment, in a direction from a top of the trench to a bottom of the trench, the thickness of the first gate dielectric layer gradually decreases.

[0013] Another aspect of the present disclosure further provides a method for manufacturing a semiconductor structure, comprising: obtaining a substrate, the substrate comprising a well region of a first conductivity type; forming a trench in the well region; forming a first gate dielectric layer covering at least a sidewall of the trench; the thickness of the first gate dielectric layer at a top of the trench is greater than the thickness at a bottom of the trench; forming a first gate in the trench with the first gate dielectric layer; forming a second gate dielectric layer on a surface of the well region; forming a second gate on the second gate dielectric layer away from the surface of the well region; forming a gate lead-out electrode, the gate lead-out electrode being electrically connected with the first gate and the second gate.

[0014] In one embodiment, the first gate dielectric layer covering at least the sidewall of the trench is formed by using a thermal oxidation process to form the first gate dielectric layer with a thickness gradually decreasing in a direction from the top of the trench to the bottom of the trench.

[0015] In one embodiment, the first gate is formed in the trench by filling polycrystalline silicon in the trench, the polycrystalline silicon comprising undoped polycrystalline silicon or lightly doped polycrystalline silicon. The polycrystalline silicon is subjected to ion implantation to increase the doping concentration of the polycrystalline silicon, and high-temperature push well is performed to obtain the first gate.

[0016] In one embodiment, the ion implantation to increase the doping concentration of the polycrystalline silicon comprises multi-channel ion implantation of different energies, so that the doping concentration of the polycrystalline silicon of the first gate gradually increases from the top of the trench to the bottom of the trench.

[0017] In one embodiment, the obtaining the substrate comprises: obtaining a wafer having a bottom semiconductor layer, a buried dielectric layer, and the substrate; the buried dielectric layer is on the bottom semiconductor layer, and the substrate is on a surface of the buried dielectric layer away from the bottom semiconductor layer; and the forming the trench in the well region comprises: forming a trench extending to the buried dielectric layer.

[0018] In one embodiment, the method further comprises: forming a drift region of the first conductivity type in the well region, the drift region being located on a side of the second gate away from the first gate and having a spacing with the second gate; forming a body region of the second conductivity type in the well region, the body region being located between the second gate and the first gate; forming a drain region in the drift region and forming a source region in the body region.

[0019] In one embodiment, the forming the gate lead electrode comprises: forming the gate lead electrode, a source region lead electrode, and a drain region lead electrode, the source region lead electrode being electrically connected to the source region, and the drain region lead electrode being electrically connected to the drain region.

[0020] In one embodiment, the forming the drain region in the drift region and the source region in the body region comprises: forming an ion implantation region of the first conductivity type in the body region and forming the drain region in the drift region; performing ion implantation of the second conductivity type in the ion implantation region to form a second source diffusion region of the second conductivity type, wherein the ion implantation region is divided into a first source diffusion region of the first conductivity type and a third source diffusion region of the first conductivity type; and the first source diffusion region, the second source diffusion region, and the third source diffusion region together constitute the source region.

[0021] The semiconductor structure and the preparation method thereof provided by the present disclosure can have / at least have the following advantages:

[0022] In the embodiments of the present disclosure, in addition to the second gate dielectric layer and the second gate located on the surface of the well region of the substrate, the first gate dielectric layer and the first gate are sequentially arranged in the trench of the well region, and the thickness of the first gate dielectric layer at the top of the trench is greater than the thickness of the first gate dielectric layer at the bottom of the trench. In this way, the first gate and the second gate are led out together by using the gate lead electrode, the threshold voltages of the first gate and the second gate can be consistent, that is, it can be ensured that the first gate in the trench can be turned on at the same time as the second gate. In this way, when the corresponding device of the semiconductor structure is turned on, the first gate dielectric layer of the trench sidewall and the first gate in the trench will form a new conduction path along the trench sidewall under the influence of the potential difference near the trench. The newly added current conduction path along the trench sidewall can significantly increase the on-state conduction current of the semiconductor device while basically not changing the withstand voltage of the device, improve the current density of the device, and reduce the specific on-resistance of the device, thereby improving the performance of the semiconductor device.

[0023] In addition, the present disclosure improves the doping concentration of the polysilicon by filling the trench with undoped polysilicon or lightly doped polysilicon in advance, and then performing ion implantation and high-temperature push-out on the polysilicon to obtain the first gate. In this way, the different doping concentrations of the first gate from the top of the trench to the bottom of the trench can be adjusted to match the gradually decreasing thickness of the first gate dielectric layer from the top of the trench to the bottom of the trench. In this way, the first gate and the second gate can be ensured to be turned on at the same time, thereby further ensuring that the on-state current is significantly improved while the device withstand voltage is basically unchanged, and the specific on-resistance is reduced. BRIEF DESCRIPTION OF DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative labor.

[0025] FIG. 1 is a schematic diagram of a cross-sectional structure of a semiconductor structure provided in some embodiments of the present disclosure.

[0026] FIG. 2 is a schematic diagram of a flow of a preparation method of a semiconductor structure provided in some embodiments of the present disclosure.

[0027] FIG. 3 is a schematic diagram of a flow of forming a first gate in a preparation method of a semiconductor structure provided in some embodiments of the present disclosure.

[0028] FIG. 4 is a schematic diagram of a flow of forming a drift region, a body region, a drain region and a source region in a preparation method of a semiconductor structure provided in some embodiments of the present disclosure.

[0029] FIG. 5 is another schematic diagram of a flow of forming a drain region and a source region in a preparation method of a semiconductor structure provided in some embodiments of the present disclosure.

[0030] FIG. 6 is a schematic diagram of a cross-sectional structure of a structure obtained in step S100 in a preparation method of a semiconductor structure provided in some embodiments of the present disclosure.

[0031] FIG. 7a is a schematic diagram of a cross-sectional structure of a structure obtained after forming an etching stop material layer in a preparation method of a semiconductor structure provided in some embodiments of the present disclosure; FIG. 7b is a schematic diagram of a cross-sectional structure of a structure obtained after forming a photoresist in a preparation method of a semiconductor structure provided in some embodiments of the present disclosure; FIG. 7c is a schematic diagram of a cross-sectional structure of a structure obtained after forming an etching stop layer in a preparation method of a semiconductor structure provided in some embodiments of the present disclosure; and FIG. 7d is a schematic diagram of a cross-sectional structure of a structure obtained in step S200 in a preparation method of a semiconductor structure provided in some embodiments of the present disclosure.

[0032] FIG. 8 is a schematic diagram of a cross-sectional structure of a structure obtained in step S300 in a method for manufacturing a semiconductor structure according to some embodiments of the present disclosure.

[0033] FIG. 9 is a schematic diagram of a cross-sectional structure of a structure obtained after filling the trench with polysilicon in a method for manufacturing a semiconductor structure according to some embodiments of the present disclosure.

[0034] FIG. 10 is a schematic diagram of a cross-sectional structure of a structure obtained in step S401 in a method for manufacturing a semiconductor structure according to some embodiments of the present disclosure.

[0035] FIG. 11 is a schematic diagram of a cross-sectional structure of a structure obtained in step S402 in a method for manufacturing a semiconductor structure according to some embodiments of the present disclosure.

[0036] FIG. 12 is a schematic diagram of a cross-sectional structure of a structure obtained after forming a gate material layer and a gate oxide material layer in a method for manufacturing a semiconductor structure according to some embodiments of the present disclosure.

[0037] FIG. 13 is a schematic diagram of a cross-sectional structure of a structure obtained in step S600 in a method for manufacturing a semiconductor structure according to some embodiments of the present disclosure.

[0038] FIG. 14 is a schematic diagram of a cross-sectional structure of a structure obtained in step S652 in a method for manufacturing a semiconductor structure according to some embodiments of the present disclosure.

[0039] FIG. 15 is a schematic diagram of a cross-sectional structure of a structure obtained in step S653 in a method for manufacturing a semiconductor structure according to some embodiments of the present disclosure.

[0040] Legend of reference numerals: 1 - substrate; 11 - well region; 111 - trench; 112 - drift region; 113 - body region; 114 - source region; 1141 - first source diffusion region; 1142 - second source diffusion region; 1143 - third source diffusion region; 115 - drain region; 120 - etching stop material layer; 12 - etching stop layer; 13 - photoresist; 21 - first gate dielectric layer; 220 - polysilicon; 22 - first gate electrode; 310 - gate oxide material layer; 31 - second gate dielectric layer; 320 - gate material layer; 32 - second gate electrode; 4 - gate lead electrode; 5 - bottom semiconductor layer; 6 - buried dielectric layer; 7 - source lead electrode; 8 - drain lead electrode. DETAILED DESCRIPTION

[0041] In order to facilitate the understanding of the present disclosure, the present disclosure will be described more fully below with reference to the accompanying drawings. The preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided so that the disclosure of the present disclosure is more thorough and comprehensive.

[0042] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in the description of the disclosure herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure.

[0043] It should be understood that, although the terms first, second, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure, and, similarly, a first element, component, region, layer or section could be termed a second element, component, region, layer or section. For example, a first current collector structure can be termed a second current collector structure, and, similarly, a second current collector structure can be termed a first current collector structure; the first current collector structure and the second current collector structure are different current collector structures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is inverted, entities described as "below" or "under" other entities or features would then be oriented "above" or "over" the other entities or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. For example, where an element or feature is described as "below" another element or feature, it can be oriented below that element or feature or above that element or feature. Similarly, the term "above" can encompass both an orientation of above and below. For example, where an element or feature is described as "above" another element or feature, it can be oriented above that element or feature or below that element or feature. The spatially relative terms in this specification are thus intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative terms in this description are to be interpreted accordingly.

[0044] As used herein, the singular forms "a", "an" and "the" include plural referents unless the context clearly dictates otherwise. It should also be understood that, when the term "comprising" is used in the present specification, it is intended to indicate the presence of one or more integers, features, steps, operations, elements, components, and / or combinations thereof, but that the integer, feature, step, operation, element, component, and / or combination so described is / are not necessarily exhaustive or exhaustive in nature. Also, as used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0045] With the continuous development and progress of semiconductor technology, semiconductor devices have become an important electronic component indispensable to modern industry. The trench structure applied on the substrate material of silicon-on-insulator (SOI) is mainly used to realize the mutual isolation of different devices or functional modules. The filling medium of the trench is usually insulating oxide and low-doped or undoped polysilicon, etc., and the trench usually adopts a scheme of not leading out or leading out and grounding.

[0046] In the application of semiconductor devices, the size of the specific on-resistance determines the power consumption of the device and even the energy consumption of the entire chip. In order to reduce the specific on-resistance of the semiconductor device and increase the on-state conduction current, the current technical solution is to use conventional electric field optimization technologies such as reducing the surface field technology, super-junction technology, field plate technology, etc. However, due to the existence of "silicon limit", these technologies have an upper limit for the performance improvement of semiconductor devices.

[0047] Based on this, the present disclosure provides a semiconductor structure and a preparation method thereof, which can reduce the specific on-resistance of the semiconductor device and increase the on-state conduction current, thereby improving the performance of the semiconductor device. The detailed content will be described in the subsequent embodiments.

[0048] It should be noted that in the embodiments of the present disclosure, the first conductivity type is P type, and the second conductivity type is N type, or the first conductivity type is N type, and the second conductivity type is P type. Hereinafter, the first conductivity type is N type, and the second conductivity type is P type are exemplarily described.

[0049] Referring to FIG. 1, the present disclosure provides a semiconductor structure according to some embodiments. The semiconductor structure comprises a substrate 1, a first gate dielectric layer 21, a first gate 22, a second gate dielectric layer 31, a second gate 32, and a gate lead electrode 4. The substrate 1 comprises a well region 11 of a first conductivity type. The well region 11 has a trench 111 therein. The first gate dielectric layer 21 covers at least the sidewall of the trench 111. The thickness of the first gate dielectric layer 21 at the top of the trench 111 is greater than the thickness at the bottom of the trench 111. The first gate 22 covers the surface of the first gate dielectric layer 21 away from the well region 11, and fills the trench 111. The second gate dielectric layer 31 is located on the surface of the well region 11. The second gate 32 is located on the surface of the second gate dielectric layer 31 away from the well region 11. The gate lead electrode 4 is electrically connected to the first gate 22 and the second gate 32.

[0050] In the semiconductor structure, in addition to the second gate dielectric layer 31 and the second gate electrode 32 located on the surface of the well region 11 of the substrate 1, the first gate dielectric layer 21 and the first gate electrode 22 are sequentially arranged in the trench 111 of the well region 11, and the thickness of the first gate dielectric layer 21 at the top of the trench 111 is greater than the thickness of the first gate dielectric layer 21 at the bottom of the trench 111. Thus, the first gate electrode 22 and the second gate electrode 32 are led out together by the gate lead electrode 4, the threshold voltages of the first gate electrode 22 and the second gate electrode 32 are consistent, and the first gate electrode 22 in the trench 111 can be ensured to be turned on at the same time as the second gate electrode 32. Thus, when the corresponding device of the semiconductor structure is turned on, the first gate dielectric layer 21 at the sidewall of the trench 111 and the first gate electrode 22 in the trench 111 form a new conduction path along the sidewall of the trench 111 under the influence of the potential difference. The newly added current conduction path along the sidewall of the trench 111 can significantly increase the on-state conduction current of the semiconductor device while basically not changing the withstand voltage of the device, improve the current density of the device, and reduce the specific on-resistance of the device, thereby improving the performance of the semiconductor device.

[0051] In addition, the semiconductor structure can also be combined with an electric field optimization technology (such as a surface field technology, a super junction technology, a field plate technology, etc.) to further improve the performance of the semiconductor device.

[0052] In some embodiments, the first gate dielectric layer 21 and the second gate dielectric layer 31 can include conventional dielectric materials such as oxides, nitrides, and oxynitrides of silicon having a dielectric constant of from about 4 to about 20 (measured in vacuum), or the first gate dielectric layer 21 and the second gate dielectric layer 31 can include a generally higher dielectric constant dielectric material having a dielectric constant of from about 20 to at least about 100. Such higher dielectric constant dielectric materials can include, but are not limited to, hafnium oxide, hafnium silicates, titanium oxide, barium strontium titanate (BSTs), and lead zirconium titanate (PZTs). In one embodiment, the first gate dielectric layer 21 and the second gate dielectric layer 31 are gate oxide layers.

[0053] In some embodiments, the material of the first gate electrode 22 includes doped polysilicon. Illustratively, the material of the first gate electrode 22 includes heavily doped polysilicon. Thus, the first gate electrode 22 and the second gate electrode 32 can be further ensured to be turned on at the same time, at which the heavily doped polysilicon (i.e., the first gate electrode 22) in the trench 111 and the first gate dielectric layer 21 at the sidewall of the trench form a conduction path along the sidewall of the trench under the influence of the potential difference, thereby further ensuring that the on-state conduction current is significantly improved while the withstand voltage of the device is basically not changed, and the specific on-resistance is reduced.

[0054] In some examples, the heavily doped polysilicon includes P-type doped polysilicon.

[0055] In some examples, the doping concentration of the heavily doped polysilicon is: 1x10 18 cm -3 ~ 1x10 20 cm -3 . For example, the doping concentration of the heavily doped polysilicon can be 1x10 18 cm -3 , 5x10 18 cm -3 , 1x10 19 cm -3 , 5x10 19 cm -3 , or 1x10 20 cm -3 , etc.

[0056] In some embodiments, the ion concentration of the doped polysilicon of the first gate 22 is lower at the top of the trench 111 and higher at the bottom of the trench 111. Further, the doping concentration of the doped polysilicon gradually increases in the direction from the top to the bottom of the trench 111.

[0057] In some embodiments, referring to FIG. 1, the semiconductor structure further includes a bottom semiconductor layer 5 and a buried dielectric layer 6. The buried dielectric layer 6 is located on the bottom semiconductor layer 5, and the substrate 1 is located on the surface of the buried dielectric layer 6 away from the bottom semiconductor layer 5. The bottom of the trench 111 extends to the buried dielectric layer 6. The bottom semiconductor layer 5, the buried dielectric layer 6, and the silicon (Si) substrate together constitute a silicon-on-insulator (SOI) structure. In the embodiment shown in FIG. 1, the bottom of the first gate 22 directly contacts the buried dielectric layer 6.

[0058] Here, it needs to be particularly pointed out that, compared with a double-gate semiconductor device formed on a common silicon substrate, the double-gate semiconductor device formed based on SOI in the embodiment of the present disclosure has better parasitic parameters, smaller isolation area in the same voltage application range, and better performance in high-temperature resistance and radiation resistance, etc.

[0059] In some embodiments, referring to FIG. 1, the trench 111 penetrates the substrate 1, and the bottom of the trench 111 extends to the buried dielectric layer 6. In some examples, the thickness of the substrate 1 is less than 10 microns. In some examples, the thickness of the substrate 1 is greater than 10 microns. In some examples, the thickness of the substrate 1 is greater than 20 microns.

[0060] In some embodiments, referring to FIG. 1, the semiconductor structure further comprises: a drift region 112 of the first conductivity type, a body region 113 of the second conductivity type, a source region 114, a drain region 115, a source region lead-out electrode 7, and a drain region lead-out electrode 8. The drift region 112 of the first conductivity type is located in the well region 11 and is located on a side of the second gate 32 away from the first gate 22, and the drift region 112 of the first conductivity type has a spacing with the second gate 32. The body region 113 of the second conductivity type is located in the well region 11 and is located between the second gate 32 and the first gate 22. The source region 114 is located in the body region 113. The drain region 115 is located in the drift region 112. The source region lead-out electrode 7 is electrically connected with the source region 114. The drain region lead-out electrode 8 is electrically connected with the drain region 115.

[0061] In some embodiments, referring to FIG. 1, the source region 114 comprises, in order from the second gate 32 to a direction away from the second gate 32, a first source diffusion region 1141 of the first conductivity type, a second source diffusion region 1142 of the second conductivity type, and a third source diffusion region 1143 of the first conductivity type. The drain region 115 comprises a drain region of the second conductivity type.

[0062] In some examples, the first source diffusion region 1141 of the first conductivity type and the third source diffusion region 1143 of the first conductivity type can each be a heavily doped (for example, N+) region of the first conductivity type. The second source diffusion region 1142 of the second conductivity type and the drain region of the second conductivity type can each be a heavily doped (for example, P+) region of the second conductivity type.

[0063] In some embodiments, the thickness of the first gate dielectric layer 21 gradually decreases in a direction from the top of the trench 111 to the bottom of the trench 111.

[0064] In some embodiments, the thickness of the first gate dielectric layer 21 gradually and uniformly decreases in a direction from the top of the trench 111 to the bottom of the trench 111.

[0065] Some embodiments of the present disclosure further provide a semiconductor structure preparation method for preparing the semiconductor structure in the foregoing embodiments. Referring to FIG. 2 and in combination with FIG. 1, the semiconductor structure preparation method comprises steps S100-S600.

[0066] S100, obtaining a substrate, the substrate comprising a well region of a first conductivity type.

[0067] S200, forming a trench in the well region.

[0068] S300, forming a first gate dielectric layer covering at least a sidewall of the trench; the thickness of the first gate dielectric layer at the top of the trench is greater than the thickness at the bottom of the trench.

[0069] S400, forming the first gate in the trench with the first gate dielectric layer.

[0070] S500, forming the second gate dielectric layer on the surface of the well region.

[0071] S600, forming the second gate on the surface of the second gate dielectric layer away from the well region.

[0072] S700, forming the gate lead-out electrode, which is electrically connected to the first gate and the second gate.

[0073] The semiconductor structure and the preparation method thereof, in addition to the second gate dielectric layer 31 and the second gate 32 on the surface of the well region 11 of the substrate 1, the first gate dielectric layer 21 and the first gate 22 are sequentially arranged in the trench 111 of the well region 11, and the thickness of the first gate dielectric layer 21 at the top of the trench 111 is greater than the thickness at the bottom of the trench 111. By using the gate lead-out electrode 4 to lead out the first gate 22 and the second gate 32 together, the threshold voltages of the first gate 22 and the second gate 32 can be consistent, that is, it can be ensured that the first gate 22 in the trench 111 can be turned on at the same time as the second gate 32. In this way, when the corresponding device of the semiconductor structure is turned on, the first gate dielectric layer 21 on the sidewall of the trench 111 and the first gate 22 in the trench 111 will form a new conduction path along the sidewall of the trench 111 near the trench 111 under the influence of the potential difference. The newly added current conduction path along the sidewall of the trench 111 can significantly increase the on-state conduction current of the semiconductor device while basically not changing the withstand voltage of the device, improve the current density of the device, and reduce the specific on-resistance of the device, thereby improving the performance of the semiconductor device. Moreover, the preparation method of the semiconductor structure can also be combined with an electric field optimization technology (such as a surface field technology, a super-junction technology, a field plate technology, etc.) to further improve the performance of the semiconductor device.

[0074] In some embodiments, step S100 comprises: obtaining a wafer with a bottom semiconductor layer, a buried dielectric layer, and a substrate. The buried dielectric layer is located on the bottom semiconductor layer, and the substrate is located on the surface of the buried dielectric layer away from the bottom semiconductor layer.

[0075] In some embodiments, step S200 comprises: forming a trench extending to the buried dielectric layer.

[0076] In some embodiments, step S200 comprises: forming a trench 111 extending through the substrate 1 to the buried dielectric layer. In some examples, the thickness of the substrate 1 is less than 10 microns. In some examples, the thickness of the substrate 1 is greater than 10 microns. In some examples, the thickness of the substrate 1 is greater than 20 microns.

[0077] In some embodiments, step S300 comprises forming the first gate dielectric layer with a gradually decreasing thickness from the top of the trench to the bottom of the trench by using a thermal oxidation process.

[0078] In some embodiments, referring to FIG. 3, step S400 comprises steps S401 and S402.

[0079] S401, filling the trench with polysilicon, the polysilicon comprising undoped polysilicon or lightly doped polysilicon.

[0080] S402, performing ion implantation on the polysilicon to increase the doping concentration of the polysilicon, and performing high-temperature push-out to obtain the first gate.

[0081] In some embodiments, referring to FIG. 4, after step S600 and before step S700, further comprising steps S651 to S653.

[0082] S651, forming a drift region of the first conductivity type in the well region, the drift region being located on a side of the second gate away from the first gate and having a spacing from the second gate.

[0083] S652, forming a body region of the second conductivity type in the well region, the body region being located between the second gate and the first gate.

[0084] S653, forming a drain region in the drift region and forming a source region in the body region.

[0085] In some embodiments, step S700 forms the gate lead electrode, the source region lead electrode and the drain region lead electrode simultaneously. The source region lead electrode is electrically connected to the source region. The drain region lead electrode is electrically connected to the drain region.

[0086] In some embodiments, referring to FIG. 5, step S653 comprises steps S6531 and S6532.

[0087] S6531, forming an ion implantation region of the first conductivity type in the body region and forming the drain region in the drift region.

[0088] S6532, performing ion implantation of the second conductivity type in the ion implantation region to form a second source diffusion region of the second conductivity type, and dividing the ion implantation region into a first source diffusion region of the first conductivity type and a third source diffusion region of the first conductivity type; the first source diffusion region, the second source diffusion region and the third source diffusion region collectively constitute the source region.

[0089] It should be understood that although the steps in the flowcharts of FIGS. 2-5 are shown in sequential order, such that each step is performed after the preceding step has been completed, the steps do not necessarily have to be performed in this order. Unless specifically stated in the specification, the steps shown in the flowcharts need not be performed in the order shown. Rather, unless specifically stated in the specification, the steps can be performed in any order, or in some cases, simultaneously. Further, at least some of the steps in FIGS. 2-5 can include multiple steps or stages, which need not necessarily be performed at the same time, but can be performed at different times, and the order of the steps or stages need not necessarily be sequential, but can be performed in an alternating or interleaved manner with other steps or stages of other steps.

[0090] To make the method for manufacturing the semiconductor structure clearer, some possible implementation manners of the method for manufacturing the semiconductor structure are described in detail below in combination with FIG. 1 and FIGS. 6-15.

[0091] In step S100, referring to FIG. 6, a wafer with a bottom semiconductor layer 5, a buried dielectric layer 6 and a substrate 1 is obtained. The buried dielectric layer 6 is located on the bottom semiconductor layer 5, and the substrate 1 is located on a surface of the buried dielectric layer 6 away from the bottom semiconductor layer 5.

[0092] In some examples, the bottom semiconductor layer 5 can be a silicon layer. The buried dielectric layer 6 includes an oxide layer, for example, a silicon oxide layer.

[0093] In some examples, the substrate 1 includes a well region 11 of a first conductivity type.

[0094] In some examples, the substrate 1 can be a silicon (Si) substrate. The bottom semiconductor layer 5, the buried dielectric layer 6 and the silicon (Si) substrate together constitute a silicon-on-insulator (SOI) structure.

[0095] Here, it should be particularly noted that, compared with a double-gate semiconductor device formed on a common silicon substrate, the double-gate semiconductor device formed based on SOI in the embodiment of the present disclosure has better parasitic parameters, smaller isolation area in the same voltage application range, and better performance in high-temperature resistance and radiation resistance.

[0096] In some examples, the well region 11 of the first conductivity type can be obtained by performing first conductivity type ion implantation on the substrate 1.

[0097] In step S200, referring to FIGS. 7a-7d, a trench 111 is formed in the well region 11, including forming the trench 111 extending to the buried dielectric layer 6.

[0098] In some examples, forming the trench 111 in the well region 11 includes:

[0099] Referring to FIG. 7a, a layer of etching stop material 120 is formed on the surface of the well region 11 away from the buried dielectric layer 6 by a physical vapor deposition or chemical vapor deposition process;

[0100] Referring to FIG. 7b, the photoresist 13 is coated, exposed and developed, and the photoresist 13 in the region where the trench 111 is to be formed is exposed and removed;

[0101] Referring to FIG. 7c, the etching stop material layer 120 is etched based on the photoresist 13 to form the etching stop layer 12;

[0102] Referring to FIG. 7d, the trench 111 is etched in the well region 11 based on the etching stop layer 12 by a reactive ion etching process.

[0103] In step S300, referring to FIG. 8, a first gate dielectric layer 21 is formed by a thermal oxidation process, which gradually decreases in thickness from the top of the trench 111 to the bottom of the trench 111. A layer of thermal oxide is formed in the trench 111 by thermal oxidation or the like. Because of the difference in the concentration of the oxidation gas at the top and the bottom of the trench 111, the thermal oxide layer at the top of the trench 111 is thicker.

[0104] In step S401, referring to FIGS. 9 and 10, the trench 111 is filled with polysilicon 220, which includes undoped polysilicon or lightly doped polysilicon.

[0105] In some examples, the trench 111 can be filled with polysilicon 220 by a deposition process. As shown in FIG. 10, the etching stop layer 12 and the excess polysilicon 220 at the top of the trench 111 are removed and planarized by a wet grinding process or the like.

[0106] In step S402, referring to FIG. 11, the polysilicon 220 is subjected to ion implantation to increase the doping concentration of the polysilicon, and high-temperature well pushing is performed to obtain the first gate 22.

[0107] For example, the photoresist 131 is used as a barrier layer for ion implantation and high-temperature push of the polysilicon 220 in the trench 111. Because the thickness of the first gate dielectric layer 21 at the top of the trench 111 is different from the thickness of the first gate dielectric layer 21 at the bottom of the trench 111, in order to ensure that the first gate 22 at the trench 111 can be turned on at the same time as the subsequently formed second gate during the subsequent device operation, the ion implantation at this position needs to be specially optimized, for example, multi-channel ion implantation with different energies is performed and the ion implantation concentration of each channel is adjusted respectively, so that the ion concentration of the polysilicon 220 at the top of the trench 111 is low and the ion concentration of the polysilicon 220 at the bottom of the trench 111 is high. Further, the doping concentration of the polysilicon 220 gradually increases from the top to the bottom of the trench 111. For different threshold voltage requirements, the corresponding ion implantation configuration also needs to be adjusted accordingly to achieve flexible adjustment of device performance. In addition, the subsequent high-temperature push thermal process also needs to be matched with the ion implantation to meet the design requirements. In FIG. 11, the arrows represent the implantation of impurity ions.

[0108] The present disclosure improves the doping concentration of the polysilicon by filling undoped polysilicon or lightly doped polysilicon in the trench 111 first, and then performing ion implantation and high-temperature push of the polysilicon 220 to obtain the first gate 22. In this way, the different doping concentrations of the first gate 22 in the direction from the top of the trench 111 to the bottom of the trench 111 can be adjusted to match the first gate dielectric layer 21 whose thickness gradually decreases from the top of the trench 111 to the bottom of the trench 111. In this way, the simultaneous opening of the first gate 22 and the second gate 32 can be further ensured, thereby further ensuring that the on-state conduction current is significantly improved while the device withstand voltage is basically unchanged, and the specific on-resistance is reduced.

[0109] In steps S500 and S600, please refer to FIG. 12 and FIG. 13, the second gate dielectric layer 31 is formed on the surface of the well region 11. The second gate 32 is formed on the surface of the second gate dielectric layer 31 away from the well region 11.

[0110] In some examples, forming the second gate dielectric layer 31 on the surface of the well region 11 and forming the second gate 32 on the surface of the second gate dielectric layer 31 away from the well region 11 comprises:

[0111] Please refer to FIG. 12, the gate oxide material layer 310 is formed on the surface of the well region 11, the first gate dielectric layer 21 and the first gate 22 by a thermal oxidation process; the gate material layer 320 is formed on the surface of the gate oxide material layer 310 by a deposition process.

[0112] Please refer to FIG. 13, the gate material layer 320 and the gate oxide material layer 310 are subjected to photolithography and reactive ion etching to obtain the second gate 32 and the second gate dielectric layer 31.

[0113] In step S651, referring to Fig. 14, a drift region 112 of the first conductivity type is formed in the well region 11, and the drift region 112 is located on the side of the second gate 32 away from the first gate 33, and has a spacing with the second gate 32.

[0114] In some examples, the ion implantation process can be used to form the drift region 112 of the first conductivity type in the well region 11.

[0115] In step S652, referring to Fig. 14, a body region 113 of the second conductivity type is formed in the well region 11, and the body region 113 is located between the second gate 32 and the first gate 22.

[0116] In some examples, the ion implantation process can be used to form the body region 113 of the second conductivity type in the well region 11.

[0117] In step S6531, referring to Fig. 15, an ion implantation region of the first conductivity type is formed in the body region 113, and a drain region 115 is formed in the drift region 112.

[0118] In step S6532, referring to Fig. 15, the ion implantation of the second conductivity type is performed in the ion implantation region, to form a second source diffusion region 1142 of the second conductivity type, and the ion implantation region is divided into a first source diffusion region 1141 of the first conductivity type and a third source diffusion region 1143 of the first conductivity type; the first source diffusion region 1141, the second source diffusion region 1142 and the third source diffusion region 1143 collectively constitute a source region 114.

[0119] In step S700, referring to Fig. 1, a gate lead electrode 4 is formed, and the gate lead electrode 4 is electrically connected with the first gate 22 and the second gate 32. Step S700 forms the gate lead electrode 4, and at the same time, a source region lead electrode 7 and a drain region lead electrode 8 are formed. The source region lead electrode 7 is electrically connected with the source region 114. The drain region lead electrode 8 is electrically connected with the drain region 115.

[0120] The technical features of the above-described embodiments can be combined in any manner. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described, but it should be considered that any combination of the technical features is within the scope of the disclosure.

[0121] The above-described embodiments only express several implementation manners of the disclosure, and the description is relatively specific and detailed, but it should not be considered as a limitation on the patent scope. It should be noted that, for those skilled in the art, without departing from the concept of the disclosure, a number of modifications and improvements can be made, which are within the protection scope of the disclosure. Therefore, the protection scope of the patent of the disclosure should be subject to the appended claims.

Claims

1. A semiconductor structure, comprising: a substrate, the substrate comprising a well region of a first conductivity type, the well region having a trench therein; a first gate dielectric layer covering at least a sidewall of the trench, the first gate dielectric layer having a thickness at a top of the trench greater than a thickness at a bottom of the trench; a first gate covering a surface of the first gate dielectric layer away from the well region; a second gate dielectric layer on a surface of the well region; a second gate on a surface of the second gate dielectric layer away from the well region; and a gate lead electrode electrically connected to both the first gate and the second gate.

2. The semiconductor structure of claim 1, wherein, a material of the first gate comprises doped polysilicon.

3. The semiconductor structure of claim 1, wherein, further comprising: a bottom semiconductor layer; and a buried dielectric layer on the bottom semiconductor layer, wherein the substrate is on a surface of the buried dielectric layer away from the bottom semiconductor layer; a bottom of the first gate is in direct contact with the buried dielectric layer. further comprising:

4. The semiconductor structure of claim 1, wherein, a drift region of the first conductivity type within the well region and on a side of the second gate away from the first gate, the drift region of the first conductivity type having a spacing from the second gate; a body region of a second conductivity type within the well region and between the second gate and the first gate; a source region within the body region; a drain region within the drift region; a source lead electrode electrically connected to the source region; and a drain lead electrode electrically connected to the drain region. 5.The semiconductor structure of claim 4, wherein the source region comprises, in order from the second gate away from the second gate, a first source diffusion region of the first conductivity type, a second source diffusion region of the second conductivity type, and a third source diffusion region of the first conductivity type; the drain region comprises a drain region of the second conductivity type. in a direction from the top of the trench to the bottom of the trench, 6. The semiconductor structure of claim 2, wherein, the thickness of the first gate dielectric layer gradually decreases, and / or a doping concentration of the doped polysilicon gradually increases. 7.A method for manufacturing a semiconductor structure, comprising: obtaining a substrate, the substrate comprising a well region of a first conductivity type; forming a trench within the well region; forming a first gate dielectric layer covering at least a sidewall of the trench, wherein the first gate dielectric layer has a thickness at a top of the trench greater than a thickness at a bottom of the trench; forming a first gate within the trench with the first gate dielectric layer formed thereon; forming a second gate dielectric layer on a surface of the well region; forming a second gate on a surface of the second gate dielectric layer away from the well region; and forming a gate lead electrode, wherein the gate lead electrode is electrically connected to both the first gate and the second gate. the forming a first gate within the trench with the first gate dielectric layer formed thereon comprises:

8. The method of producing a semiconductor structure according to claim 7, wherein filling polysilicon within the trench, the polysilicon comprising undoped polysilicon or lightly doped polysilicon; and performing ion implantation on the polysilicon to increase a doping concentration of the polysilicon and performing high-temperature push-out to obtain the first gate. 9.The method of claim 8, wherein ​ The first gate dielectric layer formed to cover at least the sidewall of the trench comprises: using a thermal oxidation process to form the first gate dielectric layer with gradually decreasing thickness in a direction from the top of the trench to the bottom of the trench; and / or The ion implantation on the polysilicon to increase the doping concentration of the polysilicon comprises: performing ion implantation with multiple different energies, so that the doping concentration of the polysilicon of the first gate gradually increases in a direction from the top of the trench to the bottom of the trench.

10. The method of claim 7, wherein: The substrate is obtained by obtaining a wafer with a bottom semiconductor layer, a buried dielectric layer, and the substrate, wherein the buried dielectric layer is on the bottom semiconductor layer, and the substrate is on a surface of the buried dielectric layer away from the bottom semiconductor layer; The trench is formed in the well region by forming the trench extending to the buried dielectric layer.

11. The method of producing a semiconductor structure according to claim 7, wherein The method further comprises: forming a drift region of the first conductivity type in the well region, the drift region being on a side of the second gate away from the first gate and having a spacing with the second gate; forming a body region of the second conductivity type in the well region, the body region being between the second gate and the first gate; forming a drain region in the drift region and a source region in the body region.

12. The method of producing a semiconductor structure according to claim 11, wherein The gate lead electrode is formed by: forming the gate lead electrode, a source region lead electrode, and a drain region lead electrode, the source region lead electrode being electrically connected to the source region, and the drain region lead electrode being electrically connected to the drain region.

13. The method of producing a semiconductor structure according to claim 11, wherein forming a drain region in the drift region and a source region in the body region comprises: forming an ion implantation region of the first conductivity type in the body region and forming the drain region in the drift region; performing ion implantation of the second conductivity type in the ion implantation region to form a second source diffusion region of the second conductivity type, wherein the ion implantation region is divided into a first source diffusion region of the first conductivity type and a third source diffusion region of the first conductivity type; the first source diffusion region, the second source diffusion region, and the third source diffusion region collectively constitute the source region.

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