Encryption method and apparatus and decryption method and apparatus integrated with post-quantum cryptography

Abstract

The present application belongs to the field of post-quantum information security. Specifically disclosed are an encryption method and apparatus and decryption method and apparatus integrated with post-quantum cryptography. By means of the present application, a conventional block algorithm SM4 is integrated with the post-quantum cryptography algorithm Streamlined NTRU Prime, the block cipher algorithm is used to encrypt plaintext data, and the post-quantum cryptography algorithm is used to encrypt a secret key of the block cipher algorithm, so as to enhance the security of conventional block encryption and enable resistance against quantum computer attacks, thereby achieving the aim of improving encryption performance. Compared with conventional post-quantum encryption solutions, the present invention has characteristics such as fast encryption and decryption speeds and low hardware resource consumption. Using hardware to implement a cryptosystem provides relatively high parallelism, and existing hardware resources can be fully utilized to implement, in parallel, operations that can be executed in parallel in an operation process, thereby improving the computational efficiency, and providing unique advantages in terms of resource consumption, security, power consumption and speed.

Description

Encryption method and device of post-quantum cryptography, decryption method and device

[0001] The application belongs to the field of post-quantum information security, and more particularly relates to an encryption method and device of post-quantum cryptography, a decryption method and device.

[0002] In recent years, quantum technology research has made breakthrough progress, which means that quantum computing will be applied to various fields in the near future. However, the development of quantum computing will bring an unprecedented impact on traditional cryptographic systems. Quantum computers use quantum bits instead of bit positions of traditional computers, and quantum bits have two states of 0 and 1, which can realize efficient parallel computing by sharing states with other quantum bits independent of each other in space. The proposal of Shor algorithm and Grover algorithm marks that quantum computers can break traditional public key encryption algorithms in polynomial time, and the security of block encryption algorithms is also greatly weakened. Therefore, traditional cryptographic algorithms are no longer secure, and it is urgent to develop post-quantum cryptographic algorithm research to ensure the security of information in the post-quantum era.

[0003] Streamlined NTRU Prime is a post-quantum cryptographic algorithm that achieves the IND-CCA2 security level and uses a key encapsulation mechanism (KEM). The Streamlined NTRU Prime algorithm structure is similar to the original NTRU algorithm, which removes the cyclotomic ring structure to reduce the attack surface based on the classical NTRU algorithm, thereby achieving the purpose of enhancing the anti-attack ability of the algorithm and improving the security. Streamlined NTRU Prime is the first complete algorithm of the NTRU Prime algorithm family. This algorithm has smaller ciphertext and faster encapsulation and decapsulation speed, but its key generation speed is slower. The algorithm is divided into two levels, the inner layer uses an asymmetric encryption algorithm, and the outer layer uses a key encapsulation algorithm.

[0004] The above-mentioned existing post-quantum cryptographic algorithm generally has the disadvantages of slow encryption and decryption speed, large system resource consumption, and the like, and is difficult to meet the requirements of real-time secure communication.

[0005] In view of the defects of the prior art, the purpose of the present application is to provide an encryption method and device of post-quantum cryptography, a decryption method and device, which aims to solve the problems of slow encryption and decryption speed and large system resource consumption of the existing post-quantum cryptographic algorithm.

[0006] ​​​To achieve the above object, in a first aspect, the application provides an encryption method of post-quantum cryptography, which is applied to a sending end and includes the following steps:

[0007] The plaintext data is encrypted by using the SM4 algorithm to generate corresponding ciphertext data;

[0008] The SM4 key used for encryption is encrypted by using the Streamlined NTRU Prime algorithm to obtain a ciphertext key;

[0009] The ciphertext data and the ciphertext key are sent to a receiving end.

[0010] To achieve the above object, in a second aspect, the application provides a decryption method of post-quantum cryptography, which is applied to a receiving end and includes the following steps:

[0011] The ciphertext data and the ciphertext key are received;

[0012] The ciphertext key is decrypted by using a private key of the Streamlined NTRU Prime algorithm to obtain a corresponding SM4 key;

[0013] The ciphertext data is decrypted by using the SM4 key to generate original plaintext data.

[0014] To achieve the above object, in a third aspect, the application provides an encryption device of post-quantum cryptography, which is encrypted by using the encryption method of post-quantum cryptography as described in the first aspect.

[0015] Preferably, the device includes a key generation module based on the Streamlined NTRU Prime algorithm and an encapsulation module based on the Streamlined NTRU Prime algorithm; wherein,

[0016] The key generation module based on the Streamlined NTRU Prime algorithm is used to generate public keys and private keys meeting the requirements according to algorithm rules, and specifically includes the following steps:

[0017] An inner key generation module is used to generate a polynomial g in R, and the polynomial g is reversible in R / / 3, a Short polynomial f is generated and h=g / (3f) is calculated, wherein h is a polynomial in R / / q ring, and h is taken as a public key and (f, 1 / g) is taken as a private key output;

[0018] An outer key generation module is used to encode and output the public key and the private key generated by the inner module, so as to be used for encapsulation and decapsulation operations;

[0019] The Streamlined NTRU Prime algorithm-based encapsulation module is configured to generate ciphertext according to input plaintext and public key, perform HashConfirm and HashSession operations and output the results for decapsulation operation, and specifically includes:

[0020] The inner-layer encryption module is configured to calculate the product hr of the input plaintext r and the public key h, perform Round operation on the product result, and generate a Rounded polynomial as output.

[0021] The outer-layer encapsulation module is configured to implement the function of the Streamlined NTRU Prime algorithm outer-layer encapsulation algorithm.

[0022] Preferably, the inner-layer key generation module includes:

[0023] The first control module is configured to generate a Short polynomial f, input p 2-bit binary numbers as coefficients of the polynomial f, generate a polynomial g in R, and attempt to calculate the inverse of g. After the operation is completed, a judgment is made. If the polynomial g is reversible, the current calculation result is taken as the coefficient of the polynomial 1 / g. If the polynomial g is not reversible, the polynomial g needs to be regenerated and the R / / 3 polynomial inverse circuit is called until the generated polynomial g is reversible. The calculation result of 1 / 3f in R / / q is multiplied by g, and the product result is taken as the public key h. The combination of the R / / 3 polynomial f and the R / / 3 polynomial 1 / g is taken as the private key.

[0024] The R / / 3 polynomial inverse circuit is configured to calculate the inverse of the polynomial g.

[0025] The second RAM is configured to temporarily store p 2-bit binary coefficients as R / / 3 polynomials.

[0026] The outer-layer key generation module includes:

[0027] The first RAM is configured to temporarily store the public key h generated by the inner-layer key generation module.

[0028] The first R / / q encoding circuit is configured to perform encoding operation on the public key h of the R / / q polynomial to obtain the encoded public key.

[0029] The first R / / 3 encoding circuit is configured to perform encoding operation on the R / / 3 polynomial f and the R / / 3 polynomial 1 / g respectively to obtain the encoded f and the encoded 1 / g.

[0030] Preferably, the inner-layer encryption module includes:

[0031] The second control module is configured to perform a Round operation on the R / / q polynomial multiplication result to obtain a Rounded polynomial ciphertext.

[0032] The polynomial multiplication circuit is configured to calculate the product of the input R / / 3 polynomial plaintext and the R / / q polynomial public key.

[0033] The fourth RAM is configured to store the public key and the plaintext respectively.

[0034] The outer encapsulation module comprises:

[0035] The first R / / q decoding circuit is configured to decode the input encoded public key to obtain an R / / q polynomial public key, and output the R / / q polynomial public key to the inner encryption module.

[0036] The third RAM is configured to temporarily store the Rounded polynomial ciphertext generated by the inner encryption module.

[0037] The second R / / q encoding circuit is configured to encode the Rounded polynomial ciphertext to obtain an encoded ciphertext.

[0038] The polynomial generation circuit is configured to generate a Short polynomial plaintext from the input p 32-bit random polynomial coefficients, and output the Short polynomial plaintext to the inner encryption module and the second R / / 3 encoding circuit.

[0039] The second R / / 3 encoding circuit is configured to encode the generated Short polynomial plaintext to obtain an encoded plaintext.

[0040] The first SHA-512 circuit is configured to perform a HashConfirm operation on the encoded plaintext and the encoded public key as inputs, combine the calculation result with the encoded ciphertext to generate N, perform a HashSession operation on the encoded plaintext and N as inputs, and output the obtained data as the final result.

[0041] Preferably, the Round operation is implemented by a shift operation and a multiplication operation in the circuit.

[0042] To achieve the above object, in a fourth aspect, the application provides a decryption device of a post-quantum cryptography fusion, which adopts the decryption method of the post-quantum cryptography fusion as described in the second aspect.

[0043] Preferably, the decryption device comprises:

[0044] The inner layer decryption module is configured to calculate 3fc e R / / q according to the input ciphertext c and the private key (f, 1 / g), perform a modulo 3 operation on all coefficients of 3fc, obtain a new polynomial e e R / / 3, calculate ev, count the number of 1s in the product result, and output ev if the value of count is the same as w, or output {1, 1,..., 1, 0, 0,..., 0} in which the first w elements are 1 and the other elements are 0.

[0045] The outer layer decryption module is configured to perform a re-encryption operation on the output result of the inner layer decryption module using the public key to obtain a new N', and perform a HashSession operation on different input parameters and output the result by judging whether N' is equal to N.

[0046] Preferably, the inner layer decryption module comprises:

[0047] The third control unit is configured to process all coefficients of the 3fc polynomial into Z / 3 by performing a simple shift operation and a multiplication operation, obtain a polynomial e e R / / 3, calculate the product ev of the two R / / 3 polynomials e and v, and output ev or {1, 1,..., 1, 0, 0,..., 0} according to the calculation result of the weight calculation circuit.

[0048] The sixth RAM is configured to temporarily store the polynomial e.

[0049] The multiplication operation circuit is configured to calculate the product of the R / / 3 polynomial f and the R / / q ciphertext c, multiply the R / / q polynomial product result by 3, and obtain 3fc e R / / q.

[0050] The weight calculation circuit is configured to traverse all coefficients of the polynomial ev p times, perform an AND operation on the coefficients and the binary number "01", and add the obtained operation result to weight.

[0051] The outer layer decryption module comprises:

[0052] The second R / / q decoding circuit is configured to decode the encoded ciphertext to obtain the R / / q polynomial ciphertext.

[0053] The R / / 3 decoding circuit is configured to decode the encoded private key to obtain the R / / 3 polynomial private key.

[0054] The fifth RAM is configured to store the R / / q polynomial ciphertext and the R / / 3 polynomial private key, respectively.

[0055] The third R / / 3 encoding circuit is configured to encode the inner layer decryption result r' generated by the inner layer decryption module to obtain the generated encoded element r'.

[0056] A second SHA-512 circuit is configured to perform a packaging operation on the r' reusing public key to obtain a new N', and the HashSession operation is calculated with different input parameters and outputted by judging whether the N' is equal to the input N.

[0057] Compared with the prior art, the above technical solutions conceived by the present application have the following beneficial effects in general:

[0058] (1) The application provides an encryption and decryption method fusing post-quantum cryptography, which fuses a traditional block algorithm SM4 and a post-quantum cryptography algorithm Streamlined NTRU Prime, uses a block cipher algorithm to encrypt plaintext data, and uses a post-quantum cryptography algorithm to encrypt the key of the block cipher algorithm. The encryption and decryption method fusing post-quantum cryptography not only strengthens the security of block encryption, has the ability to resist quantum computer attacks, and thus achieves the purpose of improving encryption performance. Compared with traditional post-quantum encryption schemes, the encryption and decryption method fusing post-quantum cryptography has the characteristics of fast encryption and decryption speed and low hardware resource consumption.

[0059] (2) For the encryption and decryption method fusing post-quantum cryptography, the application provides an encryption and decryption device fusing post-quantum cryptography, which has high parallelism, can fully utilize existing hardware resources, and can perform parallel operations in the operation process, thereby improving the calculation efficiency. The encryption and decryption device fusing post-quantum cryptography uses hardware to implement a cryptographic system, which has unique advantages in resource consumption, security, power consumption, and speed. The encryption and decryption device fusing post-quantum cryptography can be applied to traditional high-performance devices and can also run on resource-constrained Internet of Things terminal devices.

DRAWINGS

[0060] FIG. 1 is a flowchart of an encryption and decryption method fusing post-quantum cryptography provided by an embodiment of the application.

[0061] FIG. 2 is a structural diagram of an inner-layer key generation module provided by an embodiment of the application.

[0062] FIG. 3 is a structural diagram of an outer-layer key generation module provided by an embodiment of the application.

[0063] FIG. 4 is a structural diagram of an inner-layer encryption module provided by an embodiment of the application.

[0064] FIG. 5 is a structural diagram of an outer-layer packaging module provided by an embodiment of the application.

[0065] FIG. 6 is a structural diagram of an inner-layer decryption module provided by an embodiment of the application.

[0066] FIG. 7 is a structural diagram of an outer-layer unpackaging module provided by an embodiment of the application.

DETAILED DESCRIPTION

[0067] In order to make the purposes, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and should not be used to limit the present application.

[0068] The term "and / or" used herein is used to describe an association relationship of associated objects, which means that there can be three relationships, for example, A and / or B can mean that A exists alone, A and B exist together, and B exists alone. The symbol " / " used herein means an or relationship of associated objects, for example, A / B means A or B.

[0069] The terms "first" and "second" and the like in the description and claims herein are used to distinguish different objects, rather than to describe a specific order of the objects. For example, the first RAM and the second RAM are used to distinguish different RAMs, rather than to describe a specific order of the RAMs.

[0070] In the embodiments of the present application, the words such as "exemplary" or "for example" are used to mean an example, illustration, or description. Any embodiment or design scheme described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as more preferred or more advantageous than other embodiments or design schemes. Rather, the words such as "exemplary" or "for example" are intended to present the relevant concept in a specific manner.

[0071] In the description of the embodiments of the present application, unless otherwise specified, the meaning of "a plurality of" is two or more, for example, a plurality of processing units means two or more processing units, and the like; a plurality of elements means two or more elements, and the like.

[0072] Next, the technical solutions provided in the embodiments of the present application will be introduced.

[0073] As shown in FIG. 1, the present application provides an encryption method fusing post-quantum cryptography, which is applied to a sending end and includes the following steps.

[0074] The plaintext data is encrypted using an SM4 algorithm to generate corresponding ciphertext data;

[0075] The SM4 key used for encryption is encrypted using a Streamlined NTRU Prime algorithm to obtain a ciphertext key;

[0076] The ciphertext data and the ciphertext key are sent to a receiving end.

[0077] SM4 algorithm was determined as the national cryptography industry standard by the State Cryptography Administration in 2012, and was initially mainly used in WAPI (WLAN Authentication and Privacy Infrastructure) wireless network. The emergence of SM4 algorithm provides strong support for replacing the international standard with the national standard for the cryptographic algorithm on the commercial products in China. Subsequently, SM4 algorithm is widely used in government office, public security, bank, tax, power and other information systems, and occupies a very important position in the cryptography industry in China. Similar to DES and AES algorithms, SM4 algorithm is also a block cipher algorithm.

[0078] As shown in FIG. 1, the application provides a decryption method of post-quantum cryptography fusion, which is applied to a receiving end and includes the following steps:

[0079] Receiving ciphertext data and a ciphertext key;

[0080] Decrypting the ciphertext key by using a Streamlined NTRU Prime algorithm private key to obtain a corresponding SM4 key;

[0081] Decrypting the ciphertext data by using the SM4 key to generate original plaintext data.

[0082] Correspondingly, the application provides an encryption device of post-quantum cryptography fusion, which adopts the above-mentioned encryption method of post-quantum cryptography fusion for encryption.

[0083] SM4 algorithm mainly includes XOR, shift and box operation, and S-box is the key to affect the hardware performance of SM4 algorithm. However, compared with Streamlined NTRU Prime algorithm, the resource consumption of hardware implementation of SM4 algorithm is relatively small, so the application adopts a lookup table method to realize S-box construction, and a register is used to store a substitution table of 256 data bytes.

[0084] Preferably, the application comprises a key generation module based on Streamlined NTRU Prime algorithm and an encapsulation module based on Streamlined NTRU Prime algorithm; wherein,

[0085] The key generation module based on Streamlined NTRU Prime algorithm is used to generate public keys and private keys meeting the requirements according to algorithm rules, and specifically includes the following steps:

[0086] The inner key generation module is used to generate a polynomial g in R, and the polynomial g is reversible in R / / 3, to generate a Short polynomial f and calculate h = g / (3f), wherein h is a polynomial in R / / q ring, and h is taken as a public key, and (f, 1 / g) is taken as a private key output.

[0087] An outer key generation module for encoding and outputting the public key and the private key generated by the inner layer module for encapsulation and decapsulation operations;

[0088] An encapsulation module based on the Streamlined NTRU Prime algorithm for generating ciphertext from the input plaintext and the public key, performing HashConfirm and HashSession operations and outputting for decapsulation operations, specifically comprising:

[0089] An inner encryption module for calculating the product hr∈R / / q of the input plaintext r and the public key h, performing Round operation on the product result to generate a Rounded polynomial as output;

[0090] An outer encapsulation module for implementing the function of the outer encapsulation algorithm of the Streamlined NTRU Prime algorithm.

[0091] It should be noted that the SNTRUP algorithm adopts a two-layer design, the inner layer algorithm is a public key encryption algorithm, and the outer layer is a key encapsulation algorithm. The outer layer key encapsulation algorithm takes the inner layer public key encryption algorithm as the basis, cooperates with hash algorithms, encoding / decoding algorithms, etc. to realize its function. R represents the polynomial ring Z[x] / (x p -1), and R / / 3 represents the polynomial ring (Z / 3)[x] / (x p -1).

[0092] For the inverse operation of the polynomial g, the following method is adopted: first, calculate the inverse of the polynomial g, if the polynomial g is not invertible, then generate a new polynomial g and calculate its inverse.

[0093] Preferably, as shown in FIG. 2, the inner key generation module comprises:

[0094] A first control module for generating a Short polynomial f, inputting p 2-bit binary numbers as the coefficients of the polynomial f, generating a polynomial g in R, and attempting to calculate the inverse of g. After the operation is completed, it is judged whether the polynomial g is invertible. If the polynomial g is invertible, the current calculation result is taken as the coefficient of the polynomial 1 / g. If it is not invertible, a new polynomial g needs to be generated and the R / / 3 polynomial inverse circuit is called until the generated polynomial g is invertible. Calculate 1 / 3f∈R / / q and multiply the calculation result with g. The product result is taken as the public key h output. The combination of the R / / 3 polynomial f and the R / / 3 polynomial 1 / g is taken as the private key output;

[0095] An R / / 3 polynomial inverse circuit for calculating the inverse of the polynomial g;

[0096] A second RAM is used to temporarily store p 2-bit binary coefficients of the R / / 3 polynomial.

[0097] In FIG. 2, the input end includes input data din, a clock signal clock, and a reset signal reset, and the output end includes a completion signal done, polynomial f coefficient output dour, f output valid signal f_valid, 1 / g coefficient output dour_rec_g, 1 / g output valid signal rec_g_valid, public key h output data dour_h, and h output valid signal h_valid. q is a number agreed upon by the Streamlined NTRU Prime algorithm, q > 16w + 1, and x p -x-1 is an irreducible polynomial over the polynomial ring (□ / q)[x].

[0098] As shown in FIG. 3, the outer key generation module includes:

[0099] A first RAM is used to temporarily store the public key h generated by the inner key generation module.

[0100] A first R / / q encoding circuit is used to perform encoding operation on the public key h of the R / / q polynomial, to obtain the encoded public key.

[0101] A first R / / 3 encoding circuit is used to perform encoding operation on f of the R / / 3 polynomial and 1 / g of the R / / 3 polynomial respectively, to obtain the encoded f and the encoded 1 / g.

[0102] It should be noted that, in order to improve the calculation speed, two R / / 3 polynomial encoding modules are designed in the outer key generation module to perform encoding operation on f and 1 / g respectively, so that the two polynomials can be encoded at the same time.

[0103] Since each coefficient of the polynomial h needs to be represented by a 13-bit binary number, the input port and the output port of the first RAM are both set to 13-bit wide.

[0104] In FIG. 3, the input end includes input data din, a clock signal clock, and a reset signal reset, and the output end includes encoded public key output data enc_pk, encoded public key valid signal enc_pk_valid, encoded polynomial f output data enc_f, encoded f valid signal enc_f_valid, encoded polynomial 1 / g output data enc_g_rec, encoded 1 / g valid signal enc_g_rec_valid, implicit rejection component p output data sec_key_rej, implicit rejection component p valid signal sec_key_rej_valid, and a completion signal done.

[0105] Preferably, as shown in FIG. 4, the inner layer encryption module comprises:

[0106] a second control module for performing a Round operation on the R / / q polynomial multiplication result to obtain a Rounded polynomial ciphertext;

[0107] a polynomial multiplication circuit for calculating the product of the input R / / 3 polynomial plaintext and the R / / q polynomial public key;

[0108] a fourth RAM for storing the public key and the plaintext respectively.

[0109] In FIG. 4, the input end comprises a public key input din_pk, a plaintext r input din_r, a clock signal clock and a reset signal reset, and the output end comprises a ciphertext output dout_c, a ciphertext output valid signal dout_c_valid and a completion signal done.

[0110] As shown in FIG. 5, the outer layer packaging module comprises:

[0111] a first R / / q decoding circuit for decoding the input encoded public key to obtain an R / / q polynomial public key, and outputting the R / / q polynomial public key to the inner layer encryption module;

[0112] a third RAM for temporarily storing the Rounded polynomial ciphertext generated by the inner layer encryption module;

[0113] a second R / / q encoding circuit for encoding the Rounded polynomial ciphertext to obtain an encoded ciphertext;

[0114] a polynomial generation circuit for randomly generating a Short polynomial plaintext for the input p 32-bit random polynomial coefficients, and outputting the Short polynomial plaintext to the inner layer encryption module and the second R / / 3 encoding circuit;

[0115] a second R / / 3 encoding circuit for encoding the generated Short polynomial plaintext to generate an encoded plaintext;

[0116] a first SHA-512 circuit for performing a HashConfirm operation with the encoded plaintext and the encoded public key as inputs, combining the calculation result with the encoded ciphertext to generate N, performing a HashSession operation with the encoded plaintext and N as inputs, and outputting the obtained data as the final result.

[0117] In FIG. 5, the input end includes an encoded public key input din_enc_pk, a random polynomial input din_random, a clock signal clock and a reset signal reset, and the output end includes a hash operation result output dout_hash, a hash output valid signal dout_hash_valid and a completion signal done. The encoded public key input din_enc_pk adopts an 8-bit width design, and according to the requirement of the polynomial generation algorithm, the input of the polynomial generation module is a 32-bit integer, so the din_random port adopts a 32-bit width design.

[0118] Since the public key is an R / / q polynomial and the plaintext is an R / / 3 polynomial, two second RAMs with different bit widths are designed in the inner encryption module to store the public key and the plaintext respectively. Both of the two RAMs adopt a dual-port design, and the port a and the port b both have read and write functions, and can read and write two words at the same time in one clock cycle.

[0119] The polynomial multiplication circuit adopts a combination of the Karatsuba algorithm and the Schoolbook algorithm, and the input is a 13-bit public key and a 2-bit plaintext, and the output is a 13-bit calculation result.

[0120] Preferably, the Round operation is realized by a shift operation and a multiplication operation in the circuit.

[0121] Correspondingly, the present application provides a decryption device of the post-quantum cryptography fusion, which adopts the decryption method of the post-quantum cryptography fusion.

[0122] Preferably, the decryption device comprises:

[0123] The inner decryption module is used to calculate 3fc e R / / q according to the input ciphertext c and the private key (f, 1 / g), perform a modulo 3 operation on all coefficients of 3fc, obtain a new polynomial e e R / / 3, calculate ev, calculate the number of 1s in the product result count, and if the value of count is the same as w, output ev, otherwise output {1, 1,..., 1, 0, 0,..., 0}, wherein the first w elements are 1 and the other elements are 0, i.e. p-w elements;

[0124] The outer unpacking module is used to perform an encapsulation operation on the output result of the inner decryption module using the public key to obtain a new N', and perform a HashSession operation with different input parameters and output by judging whether N' is equal to N.

[0125] Preferably, as shown in FIG. 6, the inner decryption module comprises:

[0126] The third control unit is used for processing all coefficients of the 3fc polynomial into Z / 3 by simple shift operation and multiplication operation, obtaining a polynomial e in R / / 3, calculating the product ev of the two R / / 3 polynomials e and v, and outputting ev or {1, 1, …, 1, 0, 0, …, 0} according to the calculation result of the weight calculation circuit;

[0127] The sixth RAM is used for temporarily storing the polynomial e.

[0128] The multiplication operation circuit is used for calculating the product of the R / / 3 polynomial f and the R / / q polynomial ciphertext c, multiplying the R / / q polynomial product result by 3, and obtaining 3fc in R / / q.

[0129] The weight calculation circuit is used for traversing all coefficients of the polynomial ev for p times, performing AND operation on the coefficients and the binary number “01”, and adding the obtained operation result to weight.

[0130] In FIG. 6, the input ports include an f input port din_f, a v input port din_v, a ciphertext c input port din_c, a clock signal clock and a reset signal reset, and the output ports include output data dout, output data valid signal dout_valid and completion signal done.

[0131] As shown in FIG. 7, the outer layer unpacking module includes:

[0132] The second R / / q decoding circuit is used for decoding the encoded ciphertext to obtain the ciphertext of the R / / q polynomial.

[0133] The R / / 3 decoding circuit is used for decoding the encoded private key to obtain the private key of the R / / 3 polynomial.

[0134] The fifth RAM is used for respectively storing the ciphertext of the R / / q polynomial and the private key of the R / / 3 polynomial.

[0135] The third R / / 3 encoding circuit is used for encoding the inner layer decryption result r′ generated by the inner layer decryption module to obtain the generated encoded element r′.

[0136] The second SHA-512 circuit is used for performing a re-encryption operation on r′ using the public key to obtain a new N′, and calculating the HashSession operation with different input parameters and outputting by judging whether N′ is equal to the input N.

[0137] In FIG. 7, the input end includes encoded ciphertext c input data din_enc_c, encoded f input data din_enc_f, encoded v input data din_enc_v, a connection encapsulation module port din_encap, a clock signal clock and a reset signal reset, and the output port includes a completion signal done, hash output data dout_hash and a hash output valid signal dout_hash_valid.

[0138] It should be noted that multiplying the result of fc by 3 is relatively simple to implement, but the calculation result needs to be processed to ensure that each coefficient is within the interval of -(q-1) / 2 to (q-1) / 2. When the value of the coefficient is less than -(q-1) / 2, the sum of the coefficient and q is taken as a new coefficient. When the value of the coefficient is greater than (q-1) / 2, the difference t-q of the original coefficient t is taken as a new coefficient. If the coefficient is exactly within the interval of -(q-1) / 2 to (q-1) / 2, no processing is required. All coefficients of the 3fc polynomial are processed into Z / 3 by performing a simple shift operation and multiplication operation to obtain the polynomial e∈R / / 3.

[0139] Since each coefficient of the polynomial e belongs to Z / 3, the input and output ports of the fifth RAM are designed with a 2-bit width, and the simultaneous reading and writing of 2-bit binary numbers can be completed in one clock cycle.

[0140] It can be understood that the detailed function implementation of each unit / module can be referred to the description in the foregoing method embodiments, which will not be described here.

[0141] It should be understood that the above device is used to execute the method in the above embodiments, and the corresponding program modules in the device have similar implementation principles and technical effects to those described in the above method. The working process of the device can be referred to the corresponding process in the above method, which will not be described here.

[0142] Based on the method in the above embodiments, the embodiment of the present application provides a computer readable storage medium, which stores a computer program. When the computer program runs on a processor, the processor executes the method in the above embodiments.

[0143] Based on the method in the above embodiments, the embodiment of the present application provides a computer program product. When the computer program product runs on a processor, the processor executes the method in the above embodiments.

[0144] It can be understood that the processor in the embodiments of the present application can be a central processing unit (CPU), and can also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, transistor logic devices, hardware components or any combination thereof. The general-purpose processor can be a microprocessor or any conventional processor.

[0145] The method steps in the embodiments of the present application can be implemented in the form of hardware or by a processor executing software instructions. The software instructions can be composed of corresponding software modules, and the software modules can be stored in a random access memory (RAM), a flash memory, a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically EPROM (EEPROM), a register, a hard disk, a mobile hard disk, a CD-ROM or any other form of storage medium well known in the art. An exemplary storage medium is coupled to the processor, so that the processor can read information from the storage medium and write information to the storage medium. Of course, the storage medium can also be an integral part of the processor. The processor and the storage medium can be located in an ASIC.

[0146] In the above embodiments, all or part of the embodiments can be implemented by software, hardware, firmware or any combination thereof. When implemented by software, all or part of the embodiments can be implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of the present application are generated. The computer can be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions can be stored in or transmitted by a computer readable storage medium. The computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center through a wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) manner. The computer readable storage medium can be any available medium accessible by a computer or a data storage device such as a server, data center, etc. integrated with one or more available media sets. The available media can be a magnetic medium (such as a floppy disk, a hard disk, a magnetic tape), an optical medium (such as a DVD), or a semiconductor medium (such as a solid state disk (SSD)), etc.

[0147] It can be understood that various numerical numbers involved in the embodiments of the present application are only distinguished for convenience of description, and are not used to limit the scope of the embodiments of the present application.

[0148] Those skilled in the art easily understand that the above only describes the preferred embodiments of the present application and is not used to limit the present application. Any modification, equivalent replacement and improvement made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims

1. A method of encryption of a post-quantum cryptographic fusion, characterized by, The method is applied to a sending end and includes: encrypting plaintext data using an SM4 algorithm to generate corresponding ciphertext data; encrypting an SM4 key used for encryption using a Streamlined NTRU Prime algorithm to obtain a ciphertext key; sending the ciphertext data and the ciphertext key to a receiving end.

2. A decryption method of post-quantum cryptography, characterized by, The method is applied to a receiving end and includes: receiving ciphertext data and a ciphertext key; decrypting the ciphertext key using a private key of the Streamlined NTRU Prime algorithm to obtain a corresponding SM4 key; decrypting the ciphertext data using the SM4 key to generate original plaintext data.

3. An encryption device of post-quantum cryptography, characterized by, The encryption method of the post-quantum fusion cipher is used for encryption.

4. The encryption apparatus of claim 3, wherein It includes: a key generation module based on the Streamlined NTRU Prime algorithm and an encapsulation module based on the Streamlined NTRU Prime algorithm; wherein the key generation module based on the Streamlined NTRU Prime algorithm is configured to generate a public key and a private key according to an algorithm rule, and specifically includes: an inner key generation module configured to generate a polynomial g in R, and the polynomial g is reversible in R / / 3, generate a Short polynomial f, and calculate h = g / (3f), wherein h is a polynomial in R / / q, and h is taken as the public key and (f, 1 / g) is taken as the private key and output; an outer key generation module configured to encode the public key and the private key generated by the inner module and output the public key and the private key for encapsulation and decapsulation operations; the encapsulation module based on the Streamlined NTRU Prime algorithm is configured to generate ciphertext according to input plaintext and a public key, perform HashConfirm and HashSession operations and output the ciphertext for decapsulation operations, and specifically includes: an inner encryption module configured to calculate the product hr of input plaintext r and the public key h, perform Round operation on the product result to generate a Rounded polynomial as output, and output the Rounded polynomial; an outer encapsulation module configured to implement the function of the outer encapsulation algorithm of the Streamlined NTRU Prime algorithm.

5. The encryption apparatus of claim 4, wherein, The inner key generation module includes: a first control module configured to generate a Short polynomial f, input p 2-bit binary numbers as coefficients of the polynomial f, generate a polynomial g in R, and try to calculate the inverse of the polynomial g, judge the result after the operation, if the polynomial g is reversible, take the current calculation result as the coefficient of the polynomial 1 / g, if the polynomial g is not reversible, regenerate the polynomial g and call a R / / 3 polynomial inverse circuit until the generated polynomial g is reversible; calculate 1 / 3f ∈ R / / q, multiply the calculation result with g, and output the product result as the public key h, and output the combination of the R / / 3 polynomial f and the R / / 3 polynomial 1 / g as the private key; a R / / 3 polynomial inverse circuit configured to calculate the inverse of the polynomial g. A second RAM is configured to temporarily store p 2-bit binary coefficients of the R / / 3 polynomial; The outer key generation module comprises: A first RAM is configured to temporarily store a public key h generated by the inner key generation module; A first R / / q encoding circuit is configured to perform an encoding operation on the public key h of the R / / 3 polynomial to obtain an encoded public key; A first R / / 3 encoding circuit is configured to perform an encoding operation on f of the R / / 3 polynomial and 1 / g of the R / / 3 polynomial respectively to obtain an encoded f and an encoded 1 / g.

6. The encryption apparatus of claim 4, wherein, The inner encryption module comprises: A second control module is configured to perform a Round operation on the R / / q polynomial product result to obtain a Rounded polynomial ciphertext; A polynomial multiplication circuit is configured to calculate the product of the input R / / 3 polynomial plaintext and the R / / q polynomial public key; A fourth RAM is configured to store the public key and the plaintext respectively; The outer encapsulation module comprises: A first R / / q decoding circuit is configured to perform a decoding operation on the input encoded public key to obtain an R / / q polynomial public key, which is output to the inner encryption module; A third RAM is configured to temporarily store the Rounded polynomial ciphertext generated by the inner encryption module; A second R / / q encoding circuit is configured to perform an encoding operation on the Rounded polynomial ciphertext to obtain an encoded ciphertext; A polynomial generation circuit is configured to randomly generate a Short polynomial plaintext from the input p 32-bit random polynomial coefficients, and output the Short polynomial plaintext to the inner encryption module and the second R / / 3 encoding circuit; A second R / / 3 encoding circuit is configured to encode the generated Short polynomial plaintext to generate an encoded plaintext; A first SHA-512 circuit is configured to perform a HashConfirm operation on the encoded plaintext and the encoded public key as inputs, combine the calculation result with the encoded ciphertext to generate N, and perform a HashSession operation on the encoded plaintext and N as inputs, and output the obtained data as the final result.

7. The encryption apparatus of claim 6, wherein, The Round operation is implemented by a shift operation and a multiplication operation in the circuit.

8. A post-fusion quantum cryptographic decryption apparatus, characterized by comprising: The decryption is performed by using the decryption method of the post-fusion quantum cryptography according to claim 2.

9. The decryption apparatus of claim 8, wherein, The decryption method comprises: An inner decryption module is configured to calculate 3fc∈R / / q from the input ciphertext c and the private key (f, 1 / g), perform a modulo 3 operation on all coefficients of 3fc to obtain a new polynomial e∈R / / 3, and calculate ev, count the number of 1 in the product result, and if the value of count is the same as w, output ev, otherwise output {1, 1,..., 1, 0, 0,..., 0}, wherein the first w elements are 1 and the other elements are 0; An outer decryption encapsulation module is configured to perform an encapsulation operation on the output result of the inner decryption module using the public key to obtain a new N', and perform a HashSession operation on different input parameters and output the result by judging whether N' is equal to N.

10. The decryption apparatus of claim 9 wherein, The inner decryption module comprises: The third control unit is configured to process all coefficients of the 3fc polynomial into Z / 3 by performing a simple shift operation and a multiplication operation, obtain a polynomial e in R / / 3, calculate the product ev of the two R / / 3 polynomials e and v, and output ev or {1, 1,..., 1, 0, 0,..., 0} according to the calculation result of the weight calculation circuit; The sixth RAM is configured to temporarily store the polynomial e; The multiplication operation circuit is configured to calculate the product of the R / / 3 polynomial f and the R / / q polynomial ciphertext c, multiply the R / / q polynomial product result by 3, and obtain 3fc in R / / q; The weight calculation circuit is configured to traverse all coefficients of the polynomial ev for p times, perform an AND operation on the coefficients and a binary number "01", and add the obtained operation result to weight; The outer layer unpacking module comprises: The second R / / q decoding circuit is configured to decode the encoded ciphertext to obtain the ciphertext of the R / / q polynomial; The R / / 3 decoding circuit is configured to decode the encoded private key to obtain the private key of the R / / 3 polynomial; The fifth RAM is configured to store the ciphertext of the R / / q polynomial and the private key of the R / / 3 polynomial, respectively; The third R / / 3 encoding circuit is configured to encode the inner layer decryption result r' generated by the inner layer decryption module to obtain an encoded element r'; The second SHA-512 circuit is configured to perform a packing operation on r' using the public key to obtain a new N', judge whether N' is equal to the input N, calculate the HashSession operation with different input parameters, and output.

Images