Display substrate and display apparatus

Abstract

A display substrate and a display apparatus. The display substrate comprises a display area and a peripheral area, wherein the peripheral area at least comprises a data control apparatus, the data control apparatus comprises a plurality of control circuits (80), at least one control circuit (80) comprises a plurality of switch groups (G1-G3), at least one switch group (G1-G3) comprises a plurality of switch units (Q1-Q6), and at least one switch unit (Q1-Q6) comprises a plurality of transistors (M1-M3); and in a first direction (X), there is a first distance (L1) between adjacent switch groups, and in a second direction (Y), there is a second distance (L2) between adjacent transistors, the first distance (L1) being greater than the second distance (L2).

Description

Display substrate and display device TECHNICAL FIELD

[0001] The present disclosure relates to, but is not limited to, the technical field of display, and particularly relates to a display substrate and a display device. BACKGROUND

[0002] Micro Organic Light-Emitting Diode (Micro-OLED) is a micro display developed in recent years, and silicon-based OLED is one of them. Silicon-based OLED is a new display technology that combines semiconductor process and OLED display technology to prepare OLED devices based on wafers. Because of the advantages of semiconductor process and OLED display technology, silicon-based OLED not only has high Pixels Per Inch (PPI), but also has high brightness, low power consumption, high response speed, high color gamut and high thermal stability.

[0003] SUMMARY

[0004] The following is a summary of the subject matter of the detailed description herein. This summary is not intended to limit the scope of the claims.

[0005] In one aspect, the display substrate provided by the embodiments of the present disclosure includes a display area and a peripheral area located at least one side of the display area, the display area includes at least a plurality of sub-pixels and a plurality of data signal lines, at least one sub-pixel includes a pixel driving circuit, the data signal line is configured to provide a data signal to the connected pixel driving circuit, the peripheral area includes at least a data control device, the data control device includes a plurality of control circuits, the plurality of control circuits are configured to provide a data signal to the plurality of data signal lines; at least one control circuit includes a plurality of switch groups arranged in sequence along a first direction, at least one switch group includes a plurality of switch units arranged in sequence along the first direction, at least one switch unit includes a plurality of transistors arranged in sequence along a second direction and forming a parallel structure, the first direction and the second direction intersect; in the first direction, the first distance between adjacent switch groups is greater than the second distance between adjacent transistors in the second direction.

[0006] In an exemplary embodiment, the first distance is greater than or equal to 1 μm.

[0007] In an exemplary embodiment, at least one control circuit includes three switch groups, at least one switch group includes two switch units, and at least one switch unit includes a first transistor, a second transistor and a third transistor.

[0008] In an example embodiment, the first transistor comprises at least a first active region, the second transistor comprises at least a second active region, and the third transistor comprises at least a third active region; in the at least one switch group, the first active regions of the two switch units are in an integrated structure connected to each other, the second active regions of the two switch units are in an integrated structure connected to each other, and the third active regions of the two switch units are in an integrated structure connected to each other.

[0009] In an example embodiment, the first distance is a distance between the first active regions in adjacent switch groups, or a distance between the second active regions, or a distance between the third active regions; and the second distance is a distance between the first active region and the second active region, or a distance between the second active region and the third active region.

[0010] In an example embodiment, the at least one switch unit further comprises a first connection electrode and a second connection electrode; the first connection electrode is connected to a first source region of the first active region, a second source region of the second active region, and a third source region of the third active region, respectively, and the first connection electrode serves as a first source electrode of the first transistor, a second source electrode of the second transistor, and a third source electrode of the third transistor; and the second connection electrode is connected to a first drain region of the first active region, a second drain region of the second active region, and a third drain region of the third active region, respectively, and the second connection electrode serves as a first drain electrode of the first transistor, a second drain electrode of the second transistor, and a third drain electrode of the third transistor.

[0011] In an example embodiment, in the at least one switch group, the two switch units share the first connection electrode.

[0012] In an example embodiment, the at least one control circuit further comprises an input signal line, and the input signal line is connected to the first connection electrode in the three switch groups through an input electrode, respectively.

[0013] In an example embodiment, the input electrode comprises at least a horizontal connection electrode and a vertical connection electrode; the horizontal connection electrode has a strip shape extending along the first direction, and the horizontal connection electrode is connected to the first connection electrode 51 in the three switch groups through a via, respectively; the vertical connection electrode has a strip shape extending along the second direction, a first end of the vertical connection electrode is connected to the horizontal connection electrode, and a second end of the vertical connection electrode is connected to the input signal line through a via.

[0014] In an exemplary embodiment, a projection of the lateral connection electrode on the display substrate plane at least partially overlaps with a projection of the first connection electrode on the display substrate plane, and a projection of the lateral connection electrode on the display substrate plane at least partially overlaps with a projection of the second connection electrode on the display substrate plane.

[0015] In an exemplary embodiment, in at least one of the switch units, a projection of the lateral connection electrode on the display substrate plane at least partially overlaps with a projection of a third source region of the third active region on the display substrate plane, and a projection of the lateral connection electrode on the display substrate plane at least partially overlaps with a projection of a third drain region of the third active region on the display substrate plane.

[0016] In an exemplary embodiment, in at least one of the switch units, a projection of the lateral connection electrode on the display substrate plane has a first overlapping area with a projection of a third source region of the third active region on the display substrate plane, and a projection of the lateral connection electrode on the display substrate plane has a second overlapping area with a projection of a third drain region of the third active region on the display substrate plane, and a ratio of the first overlapping area to the second overlapping area is 0.9 to 1.1.

[0017] In an exemplary embodiment, the at least one switch unit further includes an output signal line, a first end of the output signal line is connected with the second connection electrode, and a second end of the output signal line is connected with the data signal line; a projection of the output signal line on the display substrate plane does not overlap with a projection of the first gate electrode of the first transistor, a projection of the second gate electrode of the second transistor, and a projection of the third gate electrode of the third transistor on the display substrate plane.

[0018] In an exemplary embodiment, in the at least one control circuit, a ratio of a spacing between two adjacent output signal lines to a spacing between another two adjacent output signal lines is 0.95 to 1.05.

[0019] In an exemplary embodiment, in the at least one switch unit, the output signal line includes at least a first line segment, a second line segment, and a third line segment connected in sequence, a first end of the first line segment is connected with the second connection electrode, a second end of the first line segment is connected with a first end of the second line segment after extending toward a direction close to the display area, a second end of the second line segment is connected with a first end of the third line segment after extending toward a direction close to an adjacent switch unit or a direction away from the adjacent switch unit, and a second end of the third line segment is connected with the data signal line after extending toward a direction close to the display area.

[0020] In an exemplary embodiment, in the at least one switch group, the second line segments in the two switch units extend in directions approaching each other.

[0021] In an exemplary embodiment, in the at least one switch group, the second line segments in the two switch units extend in directions approaching each other.

[0022] In an exemplary embodiment, the first transistor further includes a first gate electrode, the second transistor further includes a second gate electrode, and the third transistor further includes a third gate electrode; the at least one switch unit further includes a third connection electrode connected with the first gate electrode, the second gate electrode and the third gate electrode through gate vias, and a projection of the gate vias on a display substrate plane does not overlap with projections of the first active area, the second active area and the third active area on the display substrate plane.

[0023] In an exemplary embodiment, the at least one switch unit further includes a gate connection electrode connected with the third connection electrode and a control signal line connected with the gate connection electrode through a control signal via, and a number of the control signal via is greater than or equal to 2.

[0024] In an exemplary embodiment, in the at least one control circuit, gate connection electrodes of the at least three switch units are located on a straight line.

[0025] In an exemplary embodiment, in the at least one control circuit, control signal vias of the at least three switch units are located on a straight line.

[0026] In an exemplary embodiment, the data control device further includes a substrate potential line in a ring structure surrounding the plurality of control circuits.

[0027] In an exemplary embodiment, the peripheral area further includes a display driving chip, input signal lines of the control circuit are connected with the display driving chip, and a plurality of output signal lines of the control circuit are connected with a plurality of data signal lines in correspondence.

[0028] In another aspect, the embodiments of the present disclosure provide a display device including the foregoing display substrate.

[0029] Other aspects can become apparent from a review of the drawings and detailed description. BRIEF DESCRIPTION OF DRAWINGS

[0030] The accompanying drawings are used to provide an understanding of the technical solutions of the present disclosure, and constitute a part of the specification, and are used together with embodiments of the present disclosure to explain the technical solutions of the present disclosure, and do not constitute a limitation on the technical solutions of the present disclosure. The shape and size of each component in the drawings do not reflect the true proportion, and the purpose is only to schematically illustrate the present disclosure.

[0031] FIG. 1 is a structural schematic diagram of a silicon-based OLED display device;

[0032] FIG. 2 is a plan structural schematic diagram of a display area in a silicon-based OLED display device;

[0033] FIG. 3 is a cross-sectional structural schematic diagram of a display area in a silicon-based OLED display device;

[0034] FIG. 4 is an equivalent circuit diagram of a pixel driving circuit;

[0035] FIG. 5 is a driving timing diagram of the pixel driving circuit shown in FIG. 4;

[0036] FIG. 6 is a structural schematic diagram of a display substrate according to an exemplary embodiment of the present disclosure;

[0037] FIG. 7 is a working principle diagram of a data control device according to an exemplary embodiment of the present disclosure;

[0038] FIG. 8 is an equivalent circuit diagram of a control circuit according to an exemplary embodiment of the present disclosure;

[0039] FIG. 9 is a driving timing diagram of the control circuit in normal display according to an exemplary embodiment of the present disclosure;

[0040] FIG. 10 is a driving timing diagram of the control circuit in monochrome display according to an exemplary embodiment of the present disclosure;

[0041] FIG. 11 is a driving timing diagram of the control circuit in monochrome display according to another exemplary embodiment of the present disclosure;

[0042] FIG. 12 is a driving timing diagram of the control circuit in monochrome display according to still another exemplary embodiment of the present disclosure;

[0043] FIG. 13 is a structural schematic diagram of a data control device according to an exemplary embodiment of the present disclosure;

[0044] FIG. 14 is a schematic diagram after forming an active region pattern according to an embodiment of the present disclosure;

[0045] FIGS. 15A and 15B are schematic diagrams after forming a gate conductive layer pattern according to an embodiment of the present disclosure;

[0046] FIGS. 16A and 16B are schematic diagrams after forming a P-type doped region pattern according to an embodiment of the present disclosure;

[0047] FIGS. 17A and 17B are schematic diagrams of the formation of an N-type doped region pattern according to an embodiment of the present disclosure;

[0048] FIG. 18 is a schematic diagram of the formation of a second insulating layer pattern according to an embodiment of the present disclosure;

[0049] FIGS. 19A and 19B are schematic diagrams of the formation of a first conductive layer pattern according to an embodiment of the present disclosure;

[0050] FIG. 20 is a schematic diagram of the formation of a third insulating layer pattern according to an embodiment of the present disclosure;

[0051] FIGS. 21A and 21B are schematic diagrams of the formation of a second conductive layer pattern according to an embodiment of the present disclosure;

[0052] FIG. 22 is a schematic diagram of the formation of a fourth insulating layer pattern according to an embodiment of the present disclosure;

[0053] FIGS. 23A and 23B are schematic diagrams of the formation of a third conductive layer pattern according to an embodiment of the present disclosure;

[0054] FIG. 24 is a schematic diagram of the formation of a fifth insulating layer pattern according to an embodiment of the present disclosure;

[0055] FIGS. 25A and 25B are schematic diagrams of the formation of a fourth conductive layer pattern according to an embodiment of the present disclosure;

[0056] FIG. 26 is a schematic diagram of the overall layout of a data control device according to an exemplary embodiment of the present disclosure.

[0057] Explanation of reference signs: 10—potential line active region; 11—first active region; 12—second active region; 13—third active region; 21—first gate electrode; 22—second gate electrode; 23—third gate electrode; 30—P-type doped region; 40—N-type doped region; 50—substrate potential line; 51—first connection electrode; 52—second connection electrode; 53—third connection electrode; 54—fourth connection electrode; 55—fifth connection electrode; 61—first gate connection electrode; 62—second gate connection electrode; 63—third gate connection electrode; 64—fourth gate connection electrode; 65—fifth gate connection electrode; 66—sixth gate connection electrode; 71—lateral connection electrode; 72—vertical connection electrode; 80—control circuit; 81—input signal line; 82—output signal line; 90—switching unit; 91—first control signal line; 92—second control signal line; 93—third control signal line; 94—fourth control signal line; 95—fifth control signal line; 96—sixth control signal line; 100—display area; 101—silicon substrate; 102—driving circuit layer; 103—light-emitting structure layer; 104—first encapsulation layer; 105—color film structure layer; 106—second encapsulation layer; 107—cover plate layer; 200—binding area; 300—frame area. DETAILED DESCRIPTION

[0058] For the purpose of making the objects, technical solutions and advantages of the present disclosure clearer, below, the embodiments of the present disclosure will be described in detail with reference to the drawings. Note that the embodiments can be implemented in a variety of different forms. It should be easily understood by those skilled in the art that the embodiments and contents can be changed into various forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. The embodiments in the present disclosure and the features in the embodiments can be combined with each other arbitrarily without conflict. In order to keep the following description of the embodiments of the present disclosure clear and brief, the detailed description of some known functions and known components is omitted in the present disclosure. The drawings of the embodiments of the present disclosure only involve the structures related to the embodiments of the present disclosure, and other structures can be referred to the generally designed

[0059] The scale of the drawings in the present disclosure can be used as a reference in the actual process, but is not limited thereto. For example, the width-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display device and the number of sub-pixels in each pixel are also not limited to the number shown in the drawings. The drawings described in the present disclosure are only schematic structural diagrams, and one embodiment of the present disclosure is not limited to the shapes or values shown in the drawings.

[0060] In the present specification, ordinal numbers such as "first", "second", "third", and the like are provided in order to avoid confusion of components, and are not intended to be limiting in terms of number.

[0061] In the present specification, in order to facilitate the description, the words indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like are used to describe the positional relationship of the components with reference to the drawings, and are only for the convenience of the description of the present specification and the simplification of the description, and are not intended to indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure. The positional relationship of the components is appropriately changed according to the direction of describing each component. Therefore, it is not limited to the words described in the specification, and can be appropriately changed according to the situation.

[0062] In the present specification, unless explicitly specified and limited, the terms "mount", "connect", "connection" should be understood broadly. For example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or electrically connected; it can be directly connected, or indirectly connected through an intermediate piece, or the communication inside two elements. For those skilled in the art, the specific meaning of the above terms in the present disclosure can be understood according to the specific circumstances.

[0063] In this specification, a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (a drain electrode terminal, a drain region, or a drain electrode) and the source electrode (a source electrode terminal, a source region, or a source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that, in this specification, the channel region refers to a region where current flows mainly.

[0064] In this specification, in order to distinguish between two poles of a transistor other than the gate electrode, one of the poles is directly described as a first pole and the other pole is directly described as a second pole, where the first pole can be a drain electrode and the second pole can be a source electrode, or the first pole can be a source electrode and the second pole can be a drain electrode. In the case of using a transistor with opposite polarity or in the case of a change in the direction of current in circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Thus, in this specification, the "source electrode" and the "drain electrode" can be interchanged.

[0065] In this specification, "electrically connected" includes the case where components are connected through an element having some function of electricity. The element having some function of electricity is not particularly limited as long as electric signals can be transmitted and received between the components to be connected. Examples of the element having some function of electricity include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, and another element having various functions.

[0066] In this specification, "parallel" refers to a state where an angle formed between two straight lines is greater than or equal to -10° and less than or equal to 10°, and thus includes a state where the angle is greater than or equal to -5° and less than or equal to 5°. In addition, "perpendicular" refers to a state where an angle formed between two straight lines is greater than or equal to 80° and less than or equal to 100°, and thus includes a state where the angle is greater than or equal to 85° and less than or equal to 95°.

[0067] In this specification, a "film" and a "layer" can be interchanged with each other. For example, a "conductive layer" can be replaced with a "conductive film". Similarly, a "insulating film" can be replaced with an "insulating layer".

[0068] In this specification, "formation in the same layer" refers to a structure in which two (or more) kinds of structures are formed by patterning in the same step. The materials of the two (or more) kinds of structures formed in the same layer can be the same or different. For example, the materials of precursors used for forming the two (or more) kinds of structures in the same layer are the same, and the materials of the two (or more) kinds of structures formed in the same layer can be the same or different.

[0069] In this specification, a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon is not strictly a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon, but can be an approximately triangle, a rectangle, a trapezoid, a pentagon, or a hexagon, and can have some small deformation due to a tolerance, can have a rounded corner, a rounded side, or a deformation, and the like.

[0070] In the present disclosure, "about" means not strictly limited to the boundary, allowing values within the range of process and measurement errors.

[0071] FIG. 1 is a structural schematic diagram of a silicon-based OLED display device. As shown in FIG. 1, the silicon-based OLED display device can include a display area and a peripheral area (non-display area). The display area can include a plurality of scanning signal lines, a plurality of data signal lines, and a plurality of sub-pixels Pxij forming a plurality of pixel rows and a plurality of pixel columns, the plurality of scanning signal lines are respectively arranged in the plurality of pixel rows, and the plurality of data signal lines are respectively arranged in the plurality of pixel columns. Each sub-pixel Pxij can include at least a pixel driving circuit and a light emitting device, the pixel driving circuit is configured to provide a current required for light emission to the connected light emitting device, the pixel driving circuit of each sub-pixel Pxij can be connected to the scanning signal line of the corresponding pixel row and the data signal line of the corresponding pixel column, the sub-pixel Pxij can refer to the sub-pixel of the i-th pixel row and the j-th pixel column, the pixel driving circuit of the sub-pixel Pxij is respectively connected to the i-th scanning signal line and the j-th data signal line, and i and j can be natural numbers. The peripheral area can include at least a gate driver (GD) and a source driver (SD), the gate driver is respectively connected to the plurality of scanning signal lines in the display area, and the gate driver is configured to provide a required timing signal to the connected pixel driving circuit to realize a row-by-row scanning function. The source driver is respectively connected to the plurality of data signal lines in the display area, and the source driver is configured to provide a required data signal to the connected pixel driving circuit to realize switching and control of a display picture.

[0072] In an exemplary embodiment, the silicon-based OLED display device can be a one-chip display architecture (One Chip), in which a gate driver, a source driver, a clock control circuit, an image processing unit, and a storage unit are integrated on the same chip. The chip of the One Chip architecture includes both digital and analog parts, which is a mixed signal chip.

[0073] In another exemplary embodiment, the silicon-based OLED display device can be a two-chip display architecture (Two Chip), in which a gate driver and a source driver are integrated in a display substrate, and a clock control circuit, an image processing unit, a mobile industry processor interface (MIPI), and a storage unit are integrated in a chip, which is connected to the display substrate by a COC process and bonding.

[0074] FIG. 2 is a schematic diagram of a planar structure of a display region in a silicon-based OLED display device. As shown in FIG. 2, in a direction parallel to the plane of the display device, the display region can include a plurality of pixel units P arranged in a matrix manner, at least one pixel unit P can include a first sub-pixel P1 emitting light of a first color, a second sub-pixel P2 emitting light of a second color, and a third sub-pixel P3 emitting light of a third color, each of the three sub-pixels can include a pixel driving circuit and a light-emitting device, the pixel driving circuit in each sub-pixel is connected to a scan signal line and a data signal line, respectively, and is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and output a corresponding current to the display light-emitting device. The light-emitting device in each sub-pixel is connected to the pixel driving circuit in the sub-pixel, and is configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit in the sub-pixel.

[0075] In exemplary embodiments, the first sub-pixel P1 can be a red (R) sub-pixel emitting red light, the second sub-pixel P2 can be a blue (B) sub-pixel emitting blue light, and the third sub-pixel P3 can be a green (G) sub-pixel emitting green light.

[0076] In exemplary embodiments, the shape of the sub-pixel can be any one or more of a triangle, a square, a rectangle, a diamond, a trapezoid, a parallelogram, a pentagon, a hexagon, and other polygons, and the three sub-pixels can be arranged in a horizontal side-by-side manner, a vertical side-by-side manner, a triangular shape, etc., which are not limited in the present disclosure. In other possible embodiments, the pixel unit can include four sub-pixels, which are not limited in the present disclosure.

[0077] FIG. 3 is a schematic diagram of a cross-sectional structure of a display region in a silicon-based OLED display device, illustrating a structure for realizing full color using white light + color film. As shown in FIG. 3, in a direction perpendicular to the display device, the silicon-based OLED display device can include a silicon substrate 101, a driving circuit layer 102 disposed on the silicon substrate 101, a light-emitting structure layer 103 disposed on a side of the driving circuit layer 102 away from the silicon substrate 101, a first encapsulation layer 104 disposed on a side of the light-emitting structure layer 103 away from the silicon substrate 101, a color film structure layer 105 disposed on a side of the first encapsulation layer 104 away from the silicon substrate 101, a second encapsulation layer 106 disposed on a side of the color film structure layer 105 away from the silicon substrate 101, and a cover plate layer 107 disposed on a side of the second encapsulation layer 106 away from the silicon substrate 101. In some possible implementations, the silicon-based OLED display device can include other film layers, which are not limited in the present disclosure.

[0078] In an example embodiment, the silicon substrate 101 can be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. The driving circuit layer 102 can be prepared on the silicon substrate 101 by a silicon semiconductor process, and can include a plurality of circuit units, which can at least include a pixel driving circuit, the pixel driving circuit being connected to a scan signal line and a data signal line respectively, and the pixel driving circuit including a plurality of transistors and a storage capacitor, only one transistor being taken as an example in FIG. 3. The transistor can include a gate electrode G, a source electrode S and a drain electrode D, the gate electrode G, the source electrode S and the drain electrode D being connected to corresponding connection electrodes respectively through tungsten metal filled vias (i.e., tungsten vias, W-vias), and being connected to other electrical structures (such as a trace, etc.) through the connection electrodes.

[0079] In an example embodiment, the light emitting structure layer 103 can include a plurality of light emitting devices, which can at least include an anode, an organic light emitting layer and a cathode, the anode being connected to the drain electrode D of the transistor through a connection electrode, the organic light emitting layer being connected to the anode, the cathode being connected to the organic light emitting layer, the cathode being connected to a second power supply line, and the organic light emitting layer emitting light under the driving of the anode and the cathode. In an example embodiment, the organic light emitting layer can include an emission layer (EML) and any one or more of a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL) and an electron injection layer (EIL). In an example embodiment, for a light emitting device emitting white light, the organic light emitting layers of all sub-pixels can be a common layer connected together.

[0080] In an example embodiment, the first encapsulation layer 104 and the second encapsulation layer 106 can adopt a thin film encapsulation (TFE) mode, which can ensure that external water vapor cannot enter the light emitting structure layer. The color film structure layer 105 can at least include a red filter unit, a blue filter unit and a green filter unit, the red filter unit being arranged at a red sub-pixel to filter white light emitted by the light emitting device into red light, the blue filter unit being arranged at a blue sub-pixel to filter white light emitted by the light emitting device into blue light, and the green filter unit being arranged at a green sub-pixel to filter white light emitted by the light emitting device into green light. The cover plate layer 107 can be made of glass or a plastic-based colorless polyimide having a flexible property.

[0081] FIG. 4 is an equivalent circuit diagram of a pixel driving circuit. As shown in FIG. 4, the pixel driving circuit is of a 4T2C structure, which can include four transistors (a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4) and two storage capacitors (a first capacitor C1 and a second capacitor C2), and is connected with six signal lines (a first scan signal line S1, a second scan signal line S2, a third scan signal line S3, a data signal line DATA, a first power supply line VDD, and a second power supply line VSS).

[0082] In an example embodiment, the pixel driving circuit can include a first node N1, a second node N2, and a third node N3. The first node N1 is connected with a second electrode of the first transistor T1, a gate electrode of the third transistor T3, and a first end of the first capacitor C1, respectively. The second node N2 is connected with a second electrode of the second transistor T2, a first electrode of the third transistor T3, a second end of the first capacitor C1, and a first end of the second capacitor C2, respectively. The third node N3 is connected with a second electrode of the third transistor T3 and a second electrode of the fourth transistor T4, respectively.

[0083] In an example embodiment, the first transistor T1 can be referred to as a Write Switch transistor, a gate electrode of the first transistor T1 is connected with the first scan signal line S1, a first electrode of the first transistor T1 is connected with the data signal line DATA, and a second electrode of the first transistor T1 is connected with the first node N1. In an example embodiment, the first scan signal line S1 can output a Write Switch signal.

[0084] In an example embodiment, the second transistor T2 can be referred to as a Display Switch transistor, a gate electrode of the second transistor T2 is connected with the second scan signal line S2, a first electrode of the second transistor T2 is connected with the first power supply line VDD, and a second electrode of the second transistor T2 is connected with the second node N2. In an example embodiment, the second scan signal line S2 can output a Display Switch signal.

[0085] In an example embodiment, the third transistor T3 can be referred to as a Driver transistor, a gate electrode of the third transistor T3 is connected with the first node N1, a first electrode of the third transistor T3 is connected with the second node N2, and a second electrode of the third transistor T3 is connected with the third node N3.

[0086] In an example embodiment, the fourth transistor T4 can be referred to as an Auto Zero transistor, a gate electrode of the fourth transistor T4 is connected with the third scan signal line S3, a first electrode of the fourth transistor T4 is connected with the second power supply line VSS, and a second electrode of the fourth transistor T4 is connected with the third node N3. In an example embodiment, the third scan signal line S3 can output a reset signal.

[0087] In an example embodiment, a first end of the first capacitor C1 is connected with the first node N1, and a second end of the first capacitor C1 is connected with the second node N2. A first end of the second capacitor C2 is connected with the second node N2, and a second end of the second capacitor C2 is connected with the first power supply line VDD.

[0088] In an example embodiment, the light emitting device EL can be an organic light emitting diode (OLED) including a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked. The first electrode of the light emitting device EL is connected with the third node N3, and the second electrode of the light emitting device EL is connected with the common voltage line VCOM.

[0089] In an example embodiment, the signal of the first power supply line VDD can be a high level signal continuously provided, and the signals of the second power supply line VSS and the common voltage line VCOM can be low level signals continuously provided.

[0090] In an example embodiment, the first transistor T1 to the fourth transistor T4 can be P-type transistors (PMOS) or N-type transistors (NMOS). For example, the first transistor T1 to the fourth transistor T4 are all P-type transistors, and using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display substrate, and improve the yield of the product.

[0091] In an example embodiment, the first transistor T1 to the fourth transistor T4 can include P-type transistors and N-type transistors. For example, the first transistor T1 to the third transistor T3 can be P-type transistors, and the fourth transistor T4 can be an N-type transistor, as shown in FIG. 4.

[0092] FIG. 5 is a driving timing diagram of the pixel driving circuit shown in FIG. 4. As shown in FIG. 5, in an example embodiment, the working process of the pixel driving circuit can include:

[0093] The first stage A1 can be called an initialization stage. The signals of the first scan signal line S1 and the second scan signal line S2 are low level signals, and the signal of the third scan signal line S3 is a high level signal, so that the first transistor T1, the second transistor T2 and the fourth transistor T4 are turned on. The turning on of the first transistor T1 makes the bias voltage Vofs output by the data signal line DATA written into the first capacitor C1, and the potential Vs of the first node N1 (i.e. the gate electrode of the third transistor T3) is Vofs. The turning on of the second transistor T2 makes the first power voltage ELVDD output by the first power supply line VDD written into the second node N2, and the potential Vg of the second node N2 (i.e. the first electrode of the third transistor T3) is ELVDD. At this time, the gate-source voltage Vgs of the third transistor T3 is ELVDD-Vofs, and the storage voltage V cs of the first capacitor C1 is ELVDD-Vofs, and the potential Vd of the third node N3 (i.e. the second electrode of the third transistor T3) is Vg+Vth, which is prepared for the next stage of discharging. Wherein, ELVDD-V ofs >|Vth|, and Vth is the threshold voltage of the third transistor T3.

[0094] The second stage A2 can be called a self-discharge stage. The signal of the third scan signal line S3 is a high level signal, and the fourth transistor T4 is continuously turned on. The signal of the first scan signal line S1 changes from a low level signal to a high level signal, so that the first transistor T1 is first turned off and the first node N1 is floating. Subsequently, the signal of the second scan signal line S2 changes from a low level signal to a high level signal, so that the second transistor T2 is turned off, the second node N2 forms a loop through the turned-on third transistor T3, the third node N3 and the turned-on fourth transistor T4, and the discharging is started, and the potential of the second node N2 is decreased. Because the first node N1 is floating, the voltage difference across the first capacitor C1 is unchanged, so that the potential of the first node N1 is decreased with the potential of the second node N2. Due to the back gate effect of the third transistor T3, the gate-source voltage Vgs of the third transistor T3 remains unchanged, so that the equivalent threshold voltage |V th_EF of the third transistor T3 is gradually increased with the decrease of the potential of the second node N2, and |V th_EF |=α(ELVDD-Vs)+|Vth|, and α is the back gate coefficient. When the equivalent threshold voltage |V th_EF of the third transistor T3 is increased to the gate-source voltage Vgs of the third transistor T3, the third transistor T3 is turned off, and the discharging of the second node N2 is stopped.

[0095] The third stage A3 can be referred to as a data writing stage and a threshold compensation stage. The signal of the second scan signal line S2 is a high level signal, and the second transistor T2 is continuously turned off. The signal of the third scan signal line S3 is a high level signal, and the fourth transistor T4 is continuously turned on. The signal of the first scan signal line S13 changes from a high level signal to a low level signal, so that the first transistor T1 is turned on. The turning on of the first transistor T1 causes the data voltage Vdata output by the data signal line DATA to be written to the first node N1, and the potential of the first node N1 changes from Vofs to Vdata. Since the second node N2 is floating, threshold compensation can be achieved in this stage.

[0096] The fourth stage A4 can be referred to as a light emitting stage. The signals of the second scan signal line S2 and the third scan signal line S3 are low level signals, and the signal of the first scan signal line S1 is a high level signal, so that the second transistor T2 is turned on, and the first transistor T1 and the fourth transistor T4 are turned off. The turning on of the second transistor T2 causes the power supply voltage output by the first power supply line VDD to be provided to the first electrode of the light emitting device EL through the turned-on second transistor T2 and the third transistor T3, so as to drive the light emitting device EL to emit light.

[0097] In the light emitting stage, the driving current of the third transistor T3 is not affected by the threshold voltage of the third transistor T3, so that the influence of the threshold voltage of the third transistor T3 on the driving current is eliminated, the display brightness uniformity of the display product is ensured, and the display effect of the entire display product is improved.

[0098] An example embodiment of the present disclosure provides a display substrate, comprising a display area and a peripheral area located at least one side of the display area, the display area at least comprising a plurality of sub-pixels and a plurality of data signal lines, at least one sub-pixel comprising a pixel driving circuit, the data signal line being configured to provide a data signal to the connected pixel driving circuit, the peripheral area at least comprising a data control device, the data control device comprising a plurality of control circuits, the plurality of control circuits being configured to provide a data signal to the plurality of data signal lines; at least one control circuit comprising a plurality of switch groups arranged in sequence along a first direction, at least one switch group comprising a plurality of switch units arranged in sequence along the first direction, at least one switch unit comprising a plurality of transistors arranged in sequence along a second direction and forming a parallel structure, the first direction and the second direction intersecting; in the first direction, a first distance exists between adjacent switch groups, and in the second direction, a second distance exists between adjacent transistors, the first distance being greater than the second distance.

[0099] In an example embodiment, the first distance is greater than or equal to 1 μm.

[0100] In an example embodiment, the at least one control circuit includes three switch groups, the at least one switch group includes two switch units, and the at least one switch unit includes a first transistor, a second transistor, and a third transistor.

[0101] The technical solutions of the display substrate of the present disclosure are described below by way of example embodiments.

[0102] FIG. 6 is a structural schematic diagram of a display substrate according to an example embodiment of the present disclosure. As shown in FIG. 6, the display substrate can include at least a display area 100 and a peripheral area located on at least one side of the display area 100. The peripheral area can include a binding area 200 located on one side of the display area 100 and a frame area 300 located on the other side of the display area 100. The display area 100 can include at least a plurality of sub-pixels Pxij for displaying dynamic pictures or static images, the binding area 200 can include at least a display driving chip and a data control device for providing data signals to the display area 100, and the frame area 300 can include at least a gate driving device for providing scan signals to the display area 100. In an example embodiment, the peripheral area including the binding area 200 and the frame area 300 can further include a cathode ring in a ring structure, which is not limited in the present disclosure.

[0103] In an example embodiment, the gate driving device can be arranged on one side or both sides of the display area in the pixel row direction. The gate driving device can include a plurality of cascaded gate driving circuits, at least one gate driving circuit is connected to a scan signal line in a pixel row in the display area and provides a scan signal to the connected scan signal line. When the gate driving device is arranged on both sides of the display area in the pixel row direction, the scan signal line in the pixel row is driven by two gate driving circuits, forming a double-side driving structure, which can ensure the driving capability of high pixel density and avoid distortion of the driving signal.

[0104] In an example embodiment, the display driving chip (DDIC) as the data driving device can be bound on the display substrate by a chip-on-chip (COC) binding packaging process. The display driving chip is connected to a plurality of data signal lines in the display area through the data control device, the display driving chip is configured to generate the required data signals for the display area, and the data control device is configured to provide the data signals of the display driving chip to the plurality of data signal lines of the display area respectively.

[0105] In an example embodiment, the size of the pixel density (also referred to as display resolution) of the display device determines the number of pads of the display driving chip and the number of signal lines between the display driving chip and the display area. For example, under a 4K display resolution, the number of pads of the display driving chip is 3*4K, and the number of signal lines between the display driving chip and the display area is 3*4K. In a micro display device, such a large number of pads and signal lines can cause the size of the display driving chip and the display substrate to increase, thereby increasing the product cost.

[0106] An example embodiment of the present disclosure provides a display substrate, a data control device is arranged on the display substrate, the data control device converts serial signals of a display driving chip into parallel signals and then inputs the parallel signals into data signal lines of a display area, which can effectively reduce the number of pads of the display driving chip and the number of signal lines between the display driving chip and the display area, simplify the product structure, and reduce the product cost. For example, under a 4K display resolution, a plurality of 1:n control circuits are used in the data control device, so that one signal source (one pad of the display driving chip) can provide data signals to n data signal lines, which can greatly reduce the number of pads, and the number of pads of the display driving chip can be reduced to 3*4K / n, where n can be a positive integer greater than or equal to 2.

[0107] In an example embodiment, the data control device can include a plurality of control circuits arranged in sequence, at least one control circuit is connected with one input signal line, n output signal lines, and n control signal lines, respectively, the input signal line is connected with the display driving chip, and the output signal line is connected with the data signal line of the display area. The at least one control circuit is configured to provide signals of the display driving chip to the n data signal lines in time division mode according to the control of the n control signal lines, thereby realizing a time division multiplexing function.

[0108] In an example embodiment, n can be 6.

[0109] FIG. 7 is a working principle diagram of a data control device according to an example embodiment of the present disclosure. As shown in FIG. 7, the data control device of the binding area 200 can include at least two control circuits 80, each of which can include six switch units 90, and each of the switch units 90 can include at least a control end, an input end, and an output end. In at least one control circuit 80, the control ends of the six switch units 90 are connected with six control signal lines, respectively, the input ends of the six switch units 90 are connected with one input signal line, and the output ends of the six switch units 90 are connected with six output signal lines, respectively.

[0110] In the example embodiment, in the at least one control circuit 80, the six switch units 90 can be a first switch unit 90-1, a second switch unit 90-2, a third switch unit 90-3, a fourth switch unit 90-4, a fifth switch unit 90-5, and a sixth switch unit 90-6, respectively, the six control signal lines can be a first control signal line 91, a second control signal line 92, a third control signal line 93, a fourth control signal line 94, a fifth control signal line 95, and a sixth control signal line 96, respectively, and the six output signal lines can be a first output signal line 82-1, a second output signal line 82-2, a third output signal line 82-3, a fourth output signal line 82-4, a fifth output signal line 82-5, and a sixth output signal line 82-6, respectively.

[0111] In the example embodiment, the input terminals of the first switch unit 90-1 to the sixth switch unit 90-6 in each control circuit 80 are connected to the same input signal line 81.

[0112] In the example embodiment, in the at least one control circuit 80, the control terminal of the first switch unit 90-1 is connected to the first control signal line 91, the control terminal of the second switch unit 90-2 is connected to the second control signal line 92, the control terminal of the third switch unit 90-3 is connected to the third control signal line 93, the control terminal of the fourth switch unit 90-4 is connected to the fourth control signal line 94, the control terminal of the fifth switch unit 90-5 is connected to the fifth control signal line 95, and the control terminal of the sixth switch unit 90-6 is connected to the sixth control signal line 96. The output terminal of the first switch unit 90-1 is connected to the first output signal line 82-1, the output terminal of the second switch unit 90-2 is connected to the second output signal line 82-2, the output terminal of the third switch unit 90-3 is connected to the third output signal line 82-3, the output terminal of the fourth switch unit 90-4 is connected to the fourth output signal line 82-4, the output terminal of the fifth switch unit 90-5 is connected to the fifth output signal line 82-5, and the output terminal of the sixth switch unit 90-6 is connected to the sixth output signal line 82-6.

[0113] In the example embodiment, the plurality of input signal lines 81 of the plurality of control circuits 80 are configured to be connected to a display driving chip, and the plurality of output signal lines of the plurality of control circuits 80 are configured to be connected to the plurality of data signal lines in the display area 100.

[0114] FIG. 8 is an equivalent circuit diagram of a control circuit according to an exemplary embodiment of the present disclosure. As shown in FIG. 8, the control circuit according to the present disclosure can include six switching units 90, six control signal lines 91, one input signal line 81, and six output signal lines 82. The control terminals of the six switching units 90 are respectively connected to the six control signal lines 91, the input terminals of the six switching units 90 are connected to the one input signal line 81, and the output terminals of the six switching units 90 are respectively connected to the six output signal lines 82.

[0115] In an exemplary embodiment, at least one switching unit 90 can include three transistors connected in parallel, and the three transistors can include a first transistor M1, a second transistor M2, and a third transistor M3. The gate electrodes of the three transistors are connected together as the control terminal of the switching unit 90, the source electrodes of the three transistors are connected together as the input terminal of the switching unit 90, and the drain electrodes of the three transistors are connected together as the output terminal of the switching unit 90.

[0116] In an exemplary embodiment, in the first switching unit 90-1, the gate electrodes of the three transistors are respectively connected to the first control signal line 91, the source electrodes of the three transistors are respectively connected to the input signal line 81, and the drain electrodes of the three transistors are respectively connected to the first output signal line 82-1.

[0117] In an exemplary embodiment, in the second switching unit 90-2, the gate electrodes of the three transistors are respectively connected to the second control signal line 92, the source electrodes of the three transistors are respectively connected to the input signal line 81, and the drain electrodes of the three transistors are respectively connected to the second output signal line 82-2.

[0118] In an exemplary embodiment, in the third switching unit 90-3, the gate electrodes of the three transistors are respectively connected to the third control signal line 93, the source electrodes of the three transistors are respectively connected to the input signal line 81, and the drain electrodes of the three transistors are respectively connected to the third output signal line 82-3.

[0119] In an exemplary embodiment, in the fourth switching unit 90-4, the gate electrodes of the three transistors are respectively connected to the fourth control signal line 94, the source electrodes of the three transistors are respectively connected to the input signal line 81, and the drain electrodes of the three transistors are respectively connected to the fourth output signal line 82-4.

[0120] In an exemplary embodiment, in the fifth switching unit 90-5, the gate electrodes of the three transistors are respectively connected to the fifth control signal line 95, the source electrodes of the three transistors are respectively connected to the input signal line 81, and the drain electrodes of the three transistors are respectively connected to the fifth output signal line 82-5.

[0121] In the sixth switch unit 90-6, the gate electrodes of the three transistors are connected to the sixth control signal line 96, the source electrodes of the three transistors are connected to the input signal line 81, and the drain electrodes of the three transistors are connected to the sixth output signal line 82-6.

[0122] In the exemplary embodiment, the input signal line 81 is configured to be connected to a display driving chip, the display driving chip outputs a serial signal to the switch unit through the input signal line 81, and the serial signal contains data signals of six sub-pixels in the same pixel row. The first output signal line 82-1 to the sixth output signal line 82-6 are configured to be connected to six data signal lines of a display area, and the six data signals in the serial signal are respectively output to the six data signal lines in the display area.

[0123] In the exemplary embodiment, the parallel connection of the three transistors in the switch unit can effectively increase the width-length ratio (W / L) of the transistors, thereby improving the driving capability of the transistors. In addition, the parallel connection of the three transistors can also effectively improve the driving reliability, so that even if one or two transistors fail, the transmission of the data signal can be ensured, and the normal display of multiple sub-pixels in a pixel column can be ensured.

[0124] In the exemplary embodiment, the first transistor M1, the second transistor M2, and the third transistor M3 in the switch unit can be polysilicon transistors.

[0125] In some possible embodiments, the switch unit can adopt a parallel connection of two transistors or a parallel connection of more than four transistors, and the transistors can be oxide transistors, which are not limited in the present disclosure.

[0126] FIG. 9 is a driving timing diagram of the control circuit in the normal display of the exemplary embodiment of the present disclosure. As shown in FIG. 9, in the normal display, the driving process of the control circuit includes a plurality of driving periods T, and in each driving period T, the control circuit outputs six data signals in a serial signal output by a display driving chip to six data signal lines of a display area, and the six data signal lines write the six data signals into six pixel driving circuits of a pixel row.

[0127] In the exemplary embodiment, at least one driving period T can include seven time periods arranged in sequence, and an interval can be arranged between adjacent time periods.

[0128] In the first time period t1, the signals of the six control signal lines are all low signals, and the six switch units are all turned on. The reference voltage output by the display driving chip is transmitted to the six data signal lines through the input signal line, the six switch units, and the six output signal lines.

[0129] In the second time period t2, the first control signal line 91 is a low signal, the other control signal lines are high signals, the first switch unit is turned on, the other switch units are turned off, and the first data signal output by the display driving chip is transmitted to the first data signal line through the input signal line, the first switch unit and the first output signal line. For example, the first data signal can be the data signal of the red (R) sub-pixel.

[0130] In the third time period t3, the second control signal line 92 is a low signal, the other control signal lines are high signals, the second switch unit is turned on, the other switch units are turned off, and the second data signal output by the display driving chip is transmitted to the second data signal line through the input signal line, the second switch unit and the second output signal line. For example, the second data signal can be the data signal of the green (G) sub-pixel.

[0131] In the fourth time period t4, the third control signal line 93 is a low signal, the other control signal lines are high signals, the third switch unit is turned on, the other switch units are turned off, and the third data signal output by the display driving chip is transmitted to the third data signal line through the input signal line, the third switch unit and the third output signal line. For example, the third data signal can be the data signal of the blue (B) sub-pixel.

[0132] In the fifth time period t5, the fourth control signal line 94 is a low signal, the other control signal lines are high signals, the fourth switch unit is turned on, the other switch units are turned off, and the fourth data signal output by the display driving chip is transmitted to the fourth data signal line through the input signal line, the fourth switch unit and the fourth output signal line. For example, the fourth data signal can be the data signal of the red sub-pixel.

[0133] In the sixth time period t6, the fifth control signal line 95 is a low signal, the other control signal lines are high signals, the fifth switch unit is turned on, the other switch units are turned off, and the fifth data signal output by the display driving chip is transmitted to the fifth data signal line through the input signal line, the fifth switch unit and the fifth output signal line. For example, the fifth data signal can be the data signal of the green sub-pixel.

[0134] In the seventh time period t7, the sixth control signal line 96 is a low signal, the other control signal lines are high signals, the sixth switch unit is turned on, the other switch units are turned off, and the sixth data signal output by the display driving chip is transmitted to the sixth data signal line through the input signal line, the sixth switch unit and the sixth output signal line. For example, the sixth data signal can be the data signal of the blue sub-pixel.

[0135] In the exemplary embodiments, under the orderly control of the 6 control signal lines, the control circuit can convert the serial signal output by the display driving chip, which contains 6 sub-pixel data signals in the same pixel row, into parallel signals and provide them to the 6 data signal lines respectively, realizing time division multiplexing. Through the cooperation of the scanning signals output by the gate driving device, the data signals of multiple sub-pixels in the display area can be accurately input into the pixel driving circuit of the corresponding sub-pixel, realizing image display.

[0136] During the preparation of the display substrate, multiple detections need to be performed, one of which is light-on detection. The light-on detection is performed by inputting a detection signal to the display substrate, so that the pixels thereof present colors, and whether each pixel is good is checked through automatically optical inspection (AOI) to confirm whether the display substrate has defects. In the exemplary embodiments, the display during the detection of the display substrate can be referred to as the AOI mode of the display substrate. In addition, the preparation process of the display substrate also includes an aging procedure. Since the prepared light-emitting device has interface instability and the like, the light-emitting device needs to be lit up for a period of time with a certain size of current, so as to age the interface instability and reduce the brightness attenuation of the light-emitting device, thereby increasing the service life of the light-emitting device.

[0137] In the exemplary embodiments, the light-on detection can be performed by an external device outputting control signals and data signals before the display substrate is bonded with the display driving chip and the flexible circuit board (FPC), or can be performed by the display driving chip outputting control signals and data signals after the display substrate is bonded with the display driving chip and the flexible circuit board (FPC), which is not limited in the present disclosure.

[0138] In the exemplary embodiments, the data control device provided by the exemplary embodiments of the present disclosure can realize the light-on detection and aging treatment of the display substrate, and the data control device can output the data signal required by a certain color sub-pixel to perform the light-on detection and aging treatment on the certain color sub-pixel in the display substrate. For example, the data control device can control all red sub-pixels in the display substrate to light up. For another example, the data control device can control all blue sub-pixels in the display substrate to light up. For another example, the data control device can control all green sub-pixels in the display substrate to light up.

[0139] The present disclosure realizes the light-on detection and aging treatment of the display substrate through the data control device, which not only can effectively increase the testing and analyzing means, help to locate various types of defects and improve the defect analysis efficiency, but also can make the product have better service life performance through the single-color and high-brightness aging treatment in the AOI mode of the display substrate.

[0140] FIG. 10 is a driving timing diagram of the control circuit in a monochrome display according to an exemplary embodiment of the present disclosure. As shown in FIG. 10, the first switch unit and the fourth switch unit provide the data signal of the red sub-pixel.

[0141] In the first time period t1, the signals of the first control signal line 91 and the fourth control signal line 94 are low level signals, and the signals of the other control signal lines are high level signals. The first switch unit and the fourth switch unit are turned on, and the other switch units are turned off. The reference voltage output by the display driving chip is transmitted to the first data signal line and the fourth data signal line, respectively.

[0142] In the second time period t2, the signal of the first control signal line 91 is a low level signal, and the signals of the other control signal lines are high level signals. The first switch unit is turned on, and the other switch units are turned off. The first data signal output by the display driving chip is transmitted to the first data signal line through the input signal line, the first switch unit and the first output signal line.

[0143] In the third time period t3, the signals of the six control signal lines are high level signals, and the six switch units are all turned off.

[0144] In the fourth time period t4, the signals of the six control signal lines are high level signals, and the six switch units are all turned off.

[0145] In the fifth time period t5, the signal of the fourth control signal line 94 is a low level signal, and the signals of the other control signal lines are high level signals. The fourth switch unit is turned on, and the other switch units are turned off. The fourth data signal output by the display driving chip is transmitted to the fourth data signal line through the input signal line, the fourth switch unit and the fourth output signal line.

[0146] In the sixth time period t6, the signals of the six control signal lines are high level signals, and the six switch units are all turned off.

[0147] In the seventh time period t7, the signals of the six control signal lines are high level signals, and the six switch units are all turned off.

[0148] In the example embodiment, by adjusting the control signals of the data control device, monochrome display in the AOI mode can be realized. When displaying a monochrome red picture, the first control signal line and the fourth control signal line normally output control signals, the signals of the second control signal line, the third control signal line, the fifth control signal line and the sixth control signal line are all set to high level signals, and the corresponding second switch unit, the third switch unit, the fifth switch unit and the sixth switch unit are all disconnected, so that in the serial signals output by the display driving chip, only the data signal of the red sub-pixel can normally pass through the data control device and be output to the data signal line, and then be written into the pixel driving circuit of the red sub-pixel, so that the red sub-pixel is normally displayed, the green sub-pixel and the blue sub-pixel are not displayed, and the red sub-pixel is realized.

[0149] FIG. 11 is a driving timing diagram of the control circuit in another monochrome display of the example embodiment of the present disclosure. As shown in FIG. 11, the second switch unit and the fifth switch unit provide the data signal of the green sub-pixel.

[0150] In the first period t1, the signals of the second control signal line 92 and the fifth control signal line 95 are low level signals, and the signals of the other control signal lines are high level signals, the second switch unit and the fifth switch unit are turned on, and the other switch units are disconnected, and the reference voltage output by the display driving chip is transmitted to the second data signal line and the fifth data signal line, respectively.

[0151] In the second period t2, the signals of the six control signal lines are high level signals, and the six switch units are all disconnected.

[0152] In the third period t3, the signal of the second control signal line 92 is a low level signal, and the signals of the other control signal lines are high level signals, the second switch unit is turned on, and the other switch units are disconnected, and the second data signal output by the display driving chip is transmitted to the second data signal line through the input signal line, the second switch unit and the second output signal line.

[0153] In the fourth period t4, the signals of the six control signal lines are high level signals, and the six switch units are all disconnected.

[0154] In the fifth period t5, the signals of the six control signal lines are high level signals, and the six switch units are all disconnected.

[0155] In the sixth period t6, the signal of the fifth control signal line 95 is a low level signal, and the signals of the other control signal lines are high level signals, the fifth switch unit is turned on, and the other switch units are disconnected, and the fifth data signal output by the display driving chip is transmitted to the fifth data signal line through the input signal line, the fifth switch unit and the fifth output signal line.

[0156] In the seventh time period t7, the signals of the six control signal lines are all high level signals, and the six switch units are all turned off.

[0157] In the exemplary embodiment, by adjusting the control signals of the data control device, monochrome display in the AOI mode can be realized. When displaying a monochrome green picture, the second control signal line and the fifth control signal line normally output control signals, the signals of the first control signal line, the third control signal line, the fourth control signal line and the sixth control signal line are all set to high level signals, and the corresponding first switch unit, the third switch unit, the fourth switch unit and the sixth switch unit are all turned off. Among the serial signals output by the display driving chip, only the data signal of the green sub-pixel can be normally output to the data signal line through the data control device, and then written into the pixel driving circuit of the green sub-pixel, so that the green sub-pixel is normally displayed, and the red sub-pixel and the blue sub-pixel are not displayed, thereby realizing the lighting of the green sub-pixel.

[0158] FIG. 12 is a driving timing diagram of the control circuit in another monochrome display mode according to an exemplary embodiment of the present disclosure. As shown in FIG. 12, the third switch unit and the sixth switch unit provide the data signal of the blue sub-pixel.

[0159] In the first time period t1, the signals of the third control signal line 93 and the sixth control signal line 96 are both low level signals, and the signals of the other control signal lines are all high level signals. The third switch unit and the sixth switch unit are both turned on, and the other switch units are turned off. The reference voltage output by the display driving chip is transmitted to the third data signal line and the sixth data signal line, respectively.

[0160] In the second time period t2, the signals of the six control signal lines are all high level signals, and the six switch units are all turned off.

[0161] In the third time period t3, the signals of the six control signal lines are all high level signals, and the six switch units are all turned off.

[0162] In the fourth time period t4, the signal of the third control signal line 93 is a low level signal, and the signals of the other control signal lines are all high level signals. The third switch unit is turned on, and the other switch units are turned off. The third data signal output by the display driving chip is transmitted to the third data signal line through the input signal line, the third switch unit and the third output signal line.

[0163] In the fifth time period t5, the signals of the six control signal lines are all high level signals, and the six switch units are all turned off.

[0164] In the sixth time period t6, the signals of the six control signal lines are all high level signals, and the six switch units are all turned off.

[0165] In the seventh time period t7, the signal of the sixth control signal line 96 is a low level signal, the signals of the other control signal lines are high level signals, the sixth switch unit is turned on, the other switch units are turned off, and the sixth data signal output by the display driving chip is transmitted to the sixth data signal line through the input signal line, the sixth switch unit and the sixth output signal line.

[0166] In the exemplary embodiments, by adjusting the control signals of the data control device, monochrome display in the AOI mode can be realized. When displaying a monochrome blue picture, the third control signal line and the sixth control signal line normally output control signals, the signals of the first control signal line, the second control signal line, the fourth control signal line and the fifth control signal line are all set to high level signals, and the corresponding first switch unit, the second switch unit, the fourth switch unit and the fifth switch unit are all turned off. Among the serial signals output by the display driving chip, only the data signal of the blue sub-pixel can be normally output to the data signal line through the data control device, and then written into the pixel driving circuit of the blue sub-pixel, so that the blue sub-pixel is normally displayed, the red sub-pixel and the green sub-pixel are not displayed, and the lighting of the blue sub-pixel is realized.

[0167] In the exemplary embodiments, the pixel driving circuit works in the linear conduction region in the AOI mode, which can provide greater output current, so that the light emitting device is fully aged under high brightness. In addition, for the life characteristics of red light emitting materials, green light emitting materials and blue light emitting materials, targeted aging treatment can be realized. For example, the green light emitting material is aged for a longer time than the red light emitting material and the blue light emitting material, and different aging treatment times of the red light emitting device, the green light emitting device and the blue light emitting device can be realized through the monochrome AOI mode, so that the product has better life performance.

[0168] FIG. 13 is a structural schematic diagram of a data control device according to an exemplary embodiment of the present disclosure, which illustrates the structure of a control circuit. In the exemplary embodiments, the display substrate according to the exemplary embodiments of the present disclosure can include at least a display area and a peripheral area located on at least one side of the display area. The display area can include a plurality of sub-pixels and a plurality of data signal lines forming a plurality of pixel rows and a plurality of pixel columns, at least one sub-pixel can include a pixel driving circuit, and the data signal line is configured to provide a data signal to the connected pixel driving circuit. The peripheral area can include at least a display driving chip and a data control device, the data control device can include a plurality of control circuits arranged in sequence, and the plurality of control circuits are configured to provide the data signal output by the display driving chip to the data signal line of the display area.

[0169] In an example embodiment, the at least one control circuit can include a first switch unit Q1, a second switch unit Q2, a third switch unit Q3, a fourth switch unit Q4, a fifth switch unit Q5 and a sixth switch unit Q6 arranged in sequence along a first direction X, and the six switch units form a 1:6 control structure.

[0170] In an example embodiment, the six switch units can be divided into three switch groups, each switch group including two switch units. The first switch group G1 includes the first switch unit Q1 and the second switch unit Q2, the second switch group G2 includes the third switch unit Q3 and the fourth switch unit Q4, and the third switch group G3 includes the fifth switch unit Q5 and the sixth switch unit Q6. The first switch group G1, the second switch group G2 and the third switch group G3 are arranged in sequence along the first direction X, and the two switch units in each switch group are arranged in sequence along the first direction X.

[0171] In an example embodiment, the at least one switch unit includes a first transistor M1, a second transistor M2 and a third transistor M3 arranged in sequence along a second direction Y, and the first transistor M1, the second transistor M2 and the third transistor M3 are in parallel structure, i.e. the gate electrodes of the three transistors are connected to each other, the source electrodes of the three transistors are connected to each other, and the drain electrodes of the three transistors are connected to each other. In an example embodiment, the first direction X and the second direction Y intersect.

[0172] In an example embodiment, in the first direction X, the first distance L1 between adjacent switch groups can be greater than the second distance L2 between adjacent transistors in the second direction Y.

[0173] In an example embodiment, the first distance L1 can be greater than or equal to 1 μm.

[0174] In an example embodiment, in the at least one switch unit, the first transistor M1 can include at least a first active region, a first source electrode, a first drain electrode and a first gate electrode, the second transistor M2 can include at least a second active region, a second source electrode, a second drain electrode and a second gate electrode, and the third transistor M3 can include at least a third active region, a third source electrode, a third drain electrode and a third gate electrode. The first source electrode, the second source electrode and the third source electrode are connected to each other, the first drain electrode, the second drain electrode and the third drain electrode are connected to each other, and the first gate electrode, the second gate electrode and the third gate electrode are connected to each other, so that the first transistor M1, the second transistor M2 and the third transistor M3 form a parallel structure.

[0175] In an example embodiment, in the at least one switch group, the first active regions in the two switch units can be an integral structure connected to each other, the second active regions in the two switch units can be an integral structure connected to each other, and the third active regions in the two switch units can be an integral structure connected to each other.

[0176] In an example embodiment, the first distance L1 can be a distance between two first active regions in adjacent switch groups, or a distance between two second active regions, or a distance between two third active regions.

[0177] In an example embodiment, the second distance L2 can be a distance between a first active region and a second active region, or a distance between a second active region and a third active region.

[0178] In an example embodiment, the at least one switch unit further comprises a first connection electrode 51 and a second connection electrode 52, and the first connection electrode 51 and the second connection electrode 52 can be in the shape of a broken line extending along the second direction Y. The first connection electrode 51 is connected to the first source region of the first active region, the second source region of the second active region, and the third source region of the third active region, respectively, and the first connection electrode 51 can simultaneously serve as the first source electrode of the first transistor M1, the second source electrode of the second transistor M2, and the third source electrode of the third transistor M3, i.e., the first source electrode, the second source electrode, and the third source electrode are an integral structure connected to each other. The second connection electrode 52 is connected to the first drain region of the first active region, the second drain region of the second active region, and the third drain region of the third active region, respectively, and the second connection electrode 52 can simultaneously serve as the first drain electrode of the first transistor M1, the second drain electrode of the second transistor M2, and the third drain electrode of the third transistor M3, i.e., the first drain electrode, the second drain electrode, and the third drain electrode are an integral structure connected to each other.

[0179] In an example embodiment, in the at least one switch group, the two switch units can share the same first connection electrode 51.

[0180] In an example embodiment, the at least one control circuit further comprises an input signal line 81, and the input signal line 81 can be connected to the first connection electrode 51 in the three switch groups through an input electrode, so as to realize that the input signal line 81 writes a data signal to the source electrodes of the three transistors in the six switch units. In an example embodiment, the input signal line 81 is configured to be connected to a display driving chip.

[0181] In an example embodiment, the input electrode can include at least the horizontal connection electrode 71 and the vertical connection electrode 72. The horizontal connection electrode 71 can be in the shape of a strip extending along the first direction X, and the horizontal connection electrode 71 can be connected to the first connection electrode 51 in the three switch groups through a via, respectively. The vertical connection electrode 72 can be in the shape of a strip extending along the second direction Y, and a first end of the vertical connection electrode 72 is connected to the horizontal connection electrode 71, and a second end of the vertical connection electrode 72 is connected to the input signal line 81 through a via.

[0182] In an example embodiment, in the at least one control circuit, a projection of the horizontal connection electrode 71 on the display substrate plane at least partially overlaps a projection of the first connection electrode 51 in the three switch groups on the display substrate plane, and a projection of the horizontal connection electrode 71 on the display substrate plane at least partially overlaps a projection of the second connection electrode 52 in the six switch units on the display substrate plane.

[0183] In an example embodiment, the first transistor M1 can further include a first gate electrode, the second transistor M2 can further include a second gate electrode, and the third transistor M3 can further include a third gate electrode. The third connection electrode 53 can be connected to the first gate electrode, the second gate electrode, and the third gate electrode through gate vias, respectively, and a projection of the gate vias on the display substrate plane does not overlap a projection of the first active region, the second active region, and the third active region on the display substrate plane.

[0184] In an example embodiment, the at least one switch unit further includes a gate connection electrode and a control signal line, the gate connection electrode is connected to the third connection electrode 53, and the control signal line is connected to the gate connection electrode through a control signal via K, and the number of control signal vias K can be greater than or equal to 2.

[0185] In the example embodiment, the first control signal line 91 is connected to the third connection electrode 53 in the first switch unit Q1 through the control signal via hole and the gate connection electrode, thus realizing that the first control signal line 91 controls the turn-on and turn-off of the three transistors in the first switch unit Q1. The second control signal line 92 is connected to the third connection electrode 53 in the second switch unit Q2 through the control signal via hole and the gate connection electrode, thus realizing that the second control signal line 92 controls the turn-on and turn-off of the three transistors in the second switch unit Q2. The third control signal line 93 is connected to the third connection electrode 53 in the third switch unit Q3 through the control signal via hole and the gate connection electrode, thus realizing that the third control signal line 93 controls the turn-on and turn-off of the three transistors in the third switch unit Q3. The fourth control signal line 94 is connected to the third connection electrode 53 in the fourth switch unit Q4 through the control signal via hole and the gate connection electrode, thus realizing that the fourth control signal line 94 controls the turn-on and turn-off of the three transistors in the fourth switch unit Q4. The fifth control signal line 95 is connected to the third connection electrode 53 in the fifth switch unit Q5 through the control signal via hole and the gate connection electrode, thus realizing that the fifth control signal line 95 controls the turn-on and turn-off of the three transistors in the fifth switch unit Q5. The sixth control signal line 96 is connected to the third connection electrode 53 in the sixth switch unit Q6 through the control signal via hole and the gate connection electrode, thus realizing that the sixth control signal line 96 controls the turn-on and turn-off of the three transistors in the sixth switch unit Q6.

[0186] In the example embodiment, the at least one switch unit further comprises an output signal line 82, a first end of the output signal line 82 is connected to the second connection electrode 52, and a second end of the output signal line 82 is configured to be connected to a data signal line. The orthogonal projection of the output signal line 82 on the display substrate plane does not overlap with the orthogonal projection of the first gate electrode of the first transistor M1, the second gate electrode of the second transistor M2 and the third gate electrode of the third transistor M3 on the display substrate plane.

[0187] In the example embodiment, in the at least one control circuit, the ratio of the spacing between two adjacent output signal lines 82 to the spacing between another two adjacent output signal lines 82 can be about 0.95 to 1.05.

[0188] In an exemplary embodiment, the first spacing D1 between the output signal line 82 in the first switching unit Q1 and the output signal line 82 in the second switching unit Q2, the second spacing D2 between the output signal line 82 in the second switching unit Q2 and the output signal line 82 in the third switching unit Q3, the third spacing D3 between the output signal line 82 in the third switching unit Q3 and the output signal line 82 in the fourth switching unit Q4, the fourth spacing D4 between the output signal line 82 in the fourth switching unit Q4 and the output signal line 82 in the fifth switching unit Q5, and the fifth spacing D5 between the output signal line 82 in the fifth switching unit Q5 and the output signal line 82 in the sixth switching unit Q6 can be substantially the same.

[0189] In an exemplary embodiment, the first spacing D1, the second spacing D2, the third spacing D3, the fourth spacing D4, and the fifth spacing D5 can be substantially the same.

[0190] In an exemplary embodiment, in at least one of the switching units, the output signal line 82 can include at least a first segment 82-1, a second segment 82-2, and a third segment 82-3 connected in sequence. A first end of the first segment 82-1 is connected to the second connection electrode 52, a second end of the first segment 82-1 extends toward the display area, and then is connected to a first end of the second segment 82-2. A second end of the second segment 82-2 extends toward the adjacent switching unit or away from the adjacent switching unit, and then is connected to a first end of the third segment 82-3. A second end of the third segment 82-3 extends toward the display area, and then is connected to the data signal line in the display area.

[0191] In the exemplary embodiments, in at least one switch group, the second line segments 82-2 of the two switch units extend in directions approaching each other. For example, in the first switch group G1, the second line segment 82-2 of the first switch unit Q1 extends in a direction approaching the second line segment 82-2 of the second switch unit Q2, and the second line segment 82-2 of the second switch unit Q2 extends in a direction approaching the second line segment 82-2 of the first switch unit Q1. For another example, in the second switch group G2, the second line segment 82-2 of the third switch unit Q3 extends in a direction approaching the second line segment 82-2 of the fourth switch unit Q4, and the second line segment 82-2 of the fourth switch unit Q4 extends in a direction approaching the second line segment 82-2 of the third switch unit Q3. For yet another example, in the third switch group G3, the second line segment 82-2 of the fifth switch unit Q5 extends in a direction approaching the second line segment 82-2 of the sixth switch unit Q6, and the second line segment 82-2 of the sixth switch unit Q6 extends in a direction approaching the second line segment 82-2 of the fifth switch unit Q5.

[0192] In the exemplary embodiments, in two adjacent switch units in adjacent switch groups, the second line segments 82-2 of the two switch units extend in directions moving away from each other. For example, the second switch unit Q2 in the first switch group G1 and the third switch unit Q3 in the second switch group G2 are two adjacent switch units in adjacent switch groups, the second line segment 82-2 of the second switch unit Q2 extends in a direction moving away from the second line segment 82-2 of the third switch unit Q3, and the second line segment 82-2 of the third switch unit Q3 extends in a direction moving away from the second line segment 82-2 of the second switch unit Q2. For another example, the fourth switch unit Q4 in the second switch group G2 and the fifth switch unit Q5 in the third switch group G3 are two adjacent switch units in adjacent switch groups, the second line segment 82-2 of the fourth switch unit Q4 extends in a direction moving away from the second line segment 82-2 of the fifth switch unit Q5, and the second line segment 82-2 of the fifth switch unit Q5 extends in a direction moving away from the second line segment 82-2 of the fourth switch unit Q4.

[0193] In the exemplary embodiments, the data control device further comprises a substrate potential line 50, the substrate potential line 50 being in a ring structure surrounding the plurality of control circuits.

[0194] The preparation process of the display device is exemplarily illustrated below. The "patterning process" in the present disclosure refers to the process of depositing a film layer, coating photoresist on the film layer, mask exposure, development, etching, stripping photoresist, etc. for metal materials, inorganic materials or transparent conductive materials, and refers to the process of coating organic materials, mask exposure and development, etc. for organic materials. The deposition can be any one or more of sputtering, evaporation, chemical vapor deposition, the coating can be any one or more of spraying, spin coating and inkjet printing, and the etching can be any one or more of dry etching and wet etching, which are not limited in the present disclosure. The "film" refers to a thin film of a certain material on a substrate prepared by deposition, coating or other processes. If the "film" does not need to be patterned during the entire preparation process, the "film" can also be referred to as a "layer". If the "film" needs to be patterned during the entire preparation process, it is referred to as a "film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are arranged in the same layer" in the present disclosure refers to that A and B are formed at the same time by the same patterning process. The "thickness" of the film layer refers to the size of the film layer in the direction perpendicular to the display device. In the exemplary embodiments of the present disclosure, "the orthographic projection of B is within the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0195] In the exemplary embodiments, the preparation process of the display substrate can include the following steps.

[0196] (1) Provide a silicon substrate. In the exemplary embodiments, the silicon substrate can be an N-type silicon substrate, which can serve as the channel region of a P-type transistor.

[0197] In some possible embodiments, the silicon substrate can be a P-type silicon substrate, which can serve as the channel region of an N-type transistor, which is not limited in the present disclosure.

[0198] (2) Form an active area (AA) pattern. In the exemplary embodiments, a photoresist pattern including an opening region can be formed on the N-type silicon substrate by coating photoresist, exposure and development, the photoresist in the opening region is removed to expose the surface of the N-type silicon substrate, p-type doping ions are implanted in the opening region by ion implantation, and the remaining photoresist is stripped to form an active area pattern on the N-type silicon substrate, as shown in FIG. 14.

[0199] In the exemplary embodiments, the active area pattern of each switch unit in the control circuit can include at least a potential line active area 10, a first active area 11, a second active area 12 and a third active area 13.

[0200] In the example embodiment, the shape of the potential line active region 10 can be linear or zigzag along the first direction X, can be arranged across the first to sixth switch units Q1-Q6, and two potential line active regions 10 can be arranged on both sides of the switch units in the second direction Y. The potential line active region 10 is configured to be connected with the substrate potential line formed subsequently.

[0201] In the example embodiment, the shape of the first, second, and third active regions 11, 12, and 13 in each switch unit can be a strip shape along the second direction Y, and the first, second, and third active regions 11, 12, and 13 can be arranged in sequence along the second direction Y. The first active region 11 can be used as the active region of the first transistor M1, the second active region 12 can be used as the active region of the second transistor M2, and the third active region 13 can be used as the active region of the third transistor M3.

[0202] In the example embodiment, the first active regions 11 in each switch group can be an integrated structure connected with each other, the second active regions 12 in each switch group can be an integrated structure connected with each other, and the third active regions 13 in each switch group can be an integrated structure connected with each other. The disclosure can effectively reduce the area occupied by the data control device by arranging the integrated active regions in the switch group.

[0203] In the example embodiment, in the first switch group G1, the first active regions 11 in the first and second switch units Q1 and Q2 can be an integrated structure connected with each other, the second active regions 12 in the first and second switch units Q1 and Q2 can be an integrated structure connected with each other, and the third active regions 13 in the first and second switch units Q1 and Q2 can be an integrated structure connected with each other.

[0204] In the example embodiment, in the second switch group G2, the first active regions 11 in the third and fourth switch units Q3 and Q4 can be an integrated structure connected with each other, the second active regions 12 in the third and fourth switch units Q3 and Q4 can be an integrated structure connected with each other, and the third active regions 13 in the third and fourth switch units Q3 and Q4 can be an integrated structure connected with each other.

[0205] In the example embodiment, in the third switch group G3, the first active regions 11 in the fifth and sixth switch units Q5 and Q6 can be an integrated structure connected with each other, the second active regions 12 in the fifth and sixth switch units Q5 and Q6 can be an integrated structure connected with each other, and the third active regions 13 in the fifth and sixth switch units Q5 and Q6 can be an integrated structure connected with each other.

[0206] In an example embodiment, in the first direction X, there can be a first distance L1 between the active regions of adjacent switch groups. For example, there can be a first distance L1 between the active region of the first switch group G1 and the active region of the second switch group G2. For another example, there can be a first distance L1 between the active region of the second switch group G2 and the active region of the third switch group G3, and the first distance L1 can be a dimension in the first direction X.

[0207] In an example embodiment, the first distance L1 can be a distance between the first active region 11 in the first switch group G1 and the first active region 11 in the second switch group G2, or can be a distance between the second active region 12 in the first switch group G1 and the second active region 12 in the second switch group G2, or can be a distance between the third active region 13 in the first switch group G1 and the third active region 13 in the second switch group G2, or can be a distance between the first active region 11 in the second switch group G2 and the first active region 11 in the third switch group G3, or can be a distance between the second active region 12 in the second switch group G2 and the second active region 12 in the third switch group G3, or can be a distance between the third active region 13 in the second switch group G2 and the third active region 13 in the third switch group G3.

[0208] In an example embodiment, the first distance L1 can be greater than or equal to 1 μm.

[0209] In an example embodiment, the first distance L1 can be a distance between two adjacent switch groups. By setting the distance between adjacent switch groups to be greater than or equal to 1 μm, the present disclosure can effectively reduce interference between switch groups.

[0210] In an example embodiment, in the second direction Y, there can be a second distance L2 between adjacent transistors, and the first distance L1 can be greater than the second distance L2.

[0211] In an example embodiment, in at least one switch group, the second distance L2 can be a distance between the first active region 11 and the second active region 12, or the second distance L2 can be a distance between the second active region 12 and the third active region 13.

[0212] In an example embodiment, the second distance L2 can be a distance between the first transistor M1 and the second transistor M2, or can be a distance between the second transistor M2 and the third transistor M3. By setting the distance between adjacent switch groups to be greater than the distance between adjacent transistors, the present disclosure can maximize the reduction of interference between switch groups.

[0213] In an exemplary embodiment, the distance between the A active region and the B active region can be the distance between the edge of the A active region close to the B active region and the edge of the B active region close to the A active region, can be the average distance, or can be the minimum distance, without limitation in the present disclosure.

[0214] In an exemplary embodiment, the active region of the at least one transistor can have an active length and an active width, the active length can be the size of the active region in the first direction X, and the active width can be the size of the active region in the second direction Y.

[0215] In an exemplary embodiment, in the at least one switching unit, the active length of the first active region 11, the active length of the second active region 12, and the active length of the third active region 13 can be substantially the same, and the active width of the first active region 11, the active width of the second active region 12, and the active width of the third active region 13 can be substantially the same.

[0216] In an exemplary embodiment, in the at least one control circuit, the active length of the first active region 11, the second active region 12, and the third active region 13 in the six switching units can be substantially the same, and the active width of the first active region 11, the second active region 12, and the third active region 13 in the six switching units can be substantially the same.

[0217] (3) Forming a gate conductive layer pattern. In an exemplary embodiment, forming the gate conductive layer pattern can include: sequentially depositing a first insulating film and a polysilicon film on the silicon substrate on which the aforementioned pattern is formed, first patterning the polysilicon film by a patterning process to form a first insulating layer covering the active region pattern and a polysilicon layer disposed on the first insulating layer, and then doping the polysilicon layer to form the gate conductive layer pattern, as shown in FIGS. 15A and 15B, FIG. 15B is a schematic diagram of the gate conductive layer in FIG. 15A.

[0218] In an exemplary embodiment, the gate conductive layer pattern of each switching unit in the control circuit can at least include: a first gate electrode 21, a second gate electrode 22, and a third gate electrode 23.

[0219] In the example embodiment, the shapes of the first gate electrode 21, the second gate electrode 22, and the third gate electrode 23 in each switching unit can each be a bar shape extending along the second direction Y, and can be arranged in order along the second direction Y, the orthogonal projection of the first gate electrode 21 on the silicon substrate can at least partially overlap the orthogonal projection of the first active region 11 on the silicon substrate, the first gate electrode 21 can serve as the gate electrode of the first transistor M1, the orthogonal projection of the second gate electrode 22 on the silicon substrate can at least partially overlap the orthogonal projection of the second active region 12 on the silicon substrate, the second gate electrode 22 can serve as the gate electrode of the second transistor M2, and the orthogonal projection of the third gate electrode 23 on the silicon substrate can at least partially overlap the orthogonal projection of the third active region 13 on the silicon substrate, the third gate electrode 23 can serve as the gate electrode of the third transistor M3.

[0220] In the example embodiment, the gate electrode of at least one transistor can have a gate length and a gate width, the gate length can be the dimension of the gate electrode in the second direction Y, and the gate width can be the dimension of the gate electrode in the first direction X.

[0221] In the example embodiment, in at least one switching unit, the gate length of the first gate electrode 21, the second gate electrode 22, and the third gate electrode 23 can be substantially the same, and the gate width of the first gate electrode 21, the second gate electrode 22, and the third gate electrode 23 can be substantially the same.

[0222] In the example embodiment, in at least one control circuit, the gate length of the first gate electrode 21 in the six switching units can be substantially the same, the gate length of the second gate electrode 22 in the six switching units can be substantially the same, and the gate length of the third gate electrode 23 in the six switching units can be substantially the same.

[0223] In the example embodiment, in at least one control circuit, the gate width of the first gate electrode 21 in the six switching units can be substantially the same, the gate width of the second gate electrode 22 in the six switching units can be substantially the same, and the gate width of the third gate electrode 23 in the six switching units can be substantially the same.

[0224] In the example embodiment, in at least one switching unit, the aspect ratio of the first transistor M1, the second transistor M2, and the third transistor M3 can be substantially the same, and the aspect ratio can be the ratio of the active width of the transistor to the gate width of the transistor.

[0225] In the example embodiment, in at least one control circuit, the aspect ratio of the first transistor M1 in the six switching units can be substantially the same, the aspect ratio of the second transistor M2 in the six switching units can be substantially the same, and the aspect ratio of the third transistor M3 in the six switching units can be substantially the same.

[0226] (4) Forming a P-type doped (SP) region pattern. In an exemplary embodiment, forming the P-type doped region pattern can include: coating a photoresist on the silicon substrate on which the aforementioned pattern is formed, forming a plurality of opening regions by exposure and development, the photoresist in the plurality of opening regions being removed, and forming P-type doped regions in the opening regions by a doping process. As shown in FIGS. 16A and 16B, FIG. 16B is a schematic diagram of the P-type doped region in FIG. 16A.

[0227] In an exemplary embodiment, the shape of the P-type doped region 30 in the control circuit can be rectangular, and the P-type doped region 30 can be disposed between two potential line active regions 10. The orthogonal projection of the P-type doped region 30 on the silicon substrate contains the orthogonal projection of the first active region 11, the second active region 12, and the third active region 13 of the six switch cells on the silicon substrate, so that the active regions on both sides of the gate electrode in the first direction X form source regions and drain regions, respectively.

[0228] In an exemplary embodiment, the source region and the drain region of each transistor are P-type heavily doped regions P+.

[0229] In an exemplary embodiment, in at least one switch group, the active region between two adjacent gate electrodes in the first direction X can simultaneously serve as the source region of one transistor and the source region of another transistor, that is, the source region of the two adjacent transistors in the first direction X can be shared.

[0230] In an exemplary embodiment, the orthogonal projection of the P-type doped region on the silicon substrate does not overlap the orthogonal projection of the potential line active region 10 on the silicon substrate.

[0231] (5) Forming an N-type doped (SN) region pattern. In an exemplary embodiment, forming the N-type doped region pattern can include: coating a photoresist on the silicon substrate on which the aforementioned pattern is formed, forming a plurality of opening regions by exposure and development, the photoresist in the plurality of opening regions being removed, and forming N-type doped regions in the opening regions by a doping process. As shown in FIGS. 17A and 17B, FIG. 17B is a schematic diagram of the N-type doped region in FIG. 17A.

[0232] In an exemplary embodiment, the shape of the N-type doped region 40 in the control circuit can be a polyline extending along the first direction X or a polyline, and the orthogonal projection of the N-type doped region 40 on the silicon substrate contains the orthogonal projection of the potential line active region 10 on the silicon substrate.

[0233] (6) Forming a second insulating layer pattern. In an exemplary embodiment, forming the second insulating layer pattern can include: depositing a second insulating thin film on the silicon substrate on which the aforementioned pattern is formed, and patterning the second insulating thin film by a patterning process to form a second insulating layer covering the gate conductive layer pattern, the second insulating layer being provided with a plurality of vias. As shown in FIG. 18.

[0234] In an example embodiment, the plurality of vias of each switching unit in the control circuit can include at least a first via V1 to a tenth via V10.

[0235] In an example embodiment, a footprint of the first via V1 on the silicon substrate can be within a footprint of the first source region of the first active region on the silicon substrate, the first insulating layer and the second insulating layer within the first via V1 are etched away to expose a surface of the first source region, and the first via V1 is configured to enable a subsequently formed first connecting electrode to connect with the first source region through the via.

[0236] In an example embodiment, since the first active region 11 in each switching group is an integral structure connected with each other, two switching units in each switching group can share the first via V1. For example, the first switching unit Q1 and the second switching unit Q2 can share the first via V1. For another example, the third switching unit Q3 and the fourth switching unit Q4 can share the first via V1. For yet another example, the fifth switching unit Q5 and the sixth switching unit Q6 can share the first via V1.

[0237] In an example embodiment, the first via V1 can be multiple, and the multiple first vias V1 can be arranged in sequence along the second direction Y to reduce contact resistance and increase connection reliability.

[0238] In an example embodiment, a footprint of the second via V2 on the silicon substrate can be within a footprint of the first drain region of the first active region on the silicon substrate, the first insulating layer and the second insulating layer within the second via V2 are etched away to expose a surface of the first drain region, and the second via V2 is configured to enable a subsequently formed second connecting electrode to connect with the first drain region through the via.

[0239] In an example embodiment, a footprint of the third via V3 on the silicon substrate can be within a footprint of the second source region of the second active region on the silicon substrate, the first insulating layer and the second insulating layer within the third via V3 are etched away to expose a surface of the second source region, and the third via V3 is configured to enable a subsequently formed first connecting electrode to connect with the second source region through the via.

[0240] In an example embodiment, since the second active region 12 in each switching group is an integral structure connected with each other, two switching units in each switching group can share the third via V3. For example, the first switching unit Q1 and the second switching unit Q2 can share the third via V3. For another example, the third switching unit Q3 and the fourth switching unit Q4 can share the third via V3. For yet another example, the fifth switching unit Q5 and the sixth switching unit Q6 can share the third via V3.

[0241] In an example embodiment, the third via V3 can be multiple, and the multiple third vias V3 can be sequentially arranged along the second direction Y to reduce contact resistance and increase connection reliability.

[0242] In an example embodiment, a projection on the silicon substrate of the fourth via V4 can be located within a projection on the silicon substrate of the second drain region of the second active region, the first insulating layer and the second insulating layer within the fourth via V4 are etched away to expose a surface of the second drain region, and the fourth via V4 is configured to enable a second connection electrode formed subsequently to connect with the second drain region through the via.

[0243] In an example embodiment, a projection on the silicon substrate of the fifth via V5 can be located within a projection on the silicon substrate of the third source region of the third active region, the first insulating layer and the second insulating layer within the fifth via V5 are etched away to expose a surface of the third source region, and the fifth via V5 is configured to enable a first connection electrode formed subsequently to connect with the third source region through the via.

[0244] In an example embodiment, since the third active region 13 in each switch group is an integrated structure connected with each other, two switch units in each switch group can share the fifth via V5. For example, the first switch unit Q1 and the second switch unit Q2 can share the fifth via V5. For another example, the third switch unit Q3 and the fourth switch unit Q4 can share the fifth via V5. For yet another example, the fifth switch unit Q5 and the sixth switch unit Q6 can share the fifth via V5.

[0245] In an example embodiment, the fifth via V5 can be multiple, and the multiple fifth vias V5 can be sequentially arranged along the second direction Y to reduce contact resistance and increase connection reliability.

[0246] In an example embodiment, a projection on the silicon substrate of the sixth via V6 can be located within a projection on the silicon substrate of the third drain region of the third active region, the first insulating layer and the second insulating layer within the sixth via V6 are etched away to expose a surface of the third drain region, and the sixth via V6 is configured to enable a second connection electrode formed subsequently to connect with the third drain region through the via.

[0247] In an example embodiment, a projection on the silicon substrate of the seventh via V7 can be located within a projection on the silicon substrate of the first gate electrode 21, the second insulating layer within the seventh via V7 is etched away to expose a surface of the first gate electrode 21, and the seventh via V7 is configured to enable a third connection electrode formed subsequently to connect with the first gate electrode 21 through the via.

[0248] In an example embodiment, the seventh via V7 can be multiple, and the multiple seventh vias V7 can be sequentially arranged along the first direction X to reduce contact resistance and increase connection reliability.

[0249] In an example embodiment, the eighth via V8 can be multiple, and the multiple eighth vias V8 can be sequentially arranged along the first direction X to reduce contact resistance and increase connection reliability.

[0250] In an example embodiment, the eighth via V8 can be multiple, and the multiple eighth vias V8 can be sequentially arranged along the first direction X to reduce contact resistance and increase connection reliability.

[0251] In an example embodiment, the ninth via V9 can be multiple, and the multiple ninth vias V9 can be sequentially arranged along the first direction X to reduce contact resistance and increase connection reliability.

[0252] In an example embodiment, the ninth via V9 can be multiple, and the multiple ninth vias V9 can be sequentially arranged along the first direction X to reduce contact resistance and increase connection reliability.

[0253] In an example embodiment, the seventh via V7, the eighth via V8, and the ninth via V9 can be referred to as gate vias. In the second direction Y, the seventh via V7 can be located on a side of the first active region 11 away from the second active region 12, and the projection of the seventh via V7 on the silicon substrate does not overlap the projection of the first active region 11 on the silicon substrate. The eighth via V8 can be located between the first active region 11 and the second active region 12, and the projection of the eighth via V8 on the silicon substrate does not overlap the projections of the first active region 11 and the second active region 12 on the silicon substrate. The ninth via V9 can be located between the second active region 12 and the third active region 13, and the projection of the ninth via V9 on the silicon substrate does not overlap the projections of the second active region 12 and the third active region 13 on the silicon substrate. This arrangement of gate vias in the present disclosure can facilitate the arrangement of multiple connection electrodes formed subsequently, optimize the connection structure of the gate conductive layer and the first conductive layer formed subsequently, and reduce the occupied area of the data control device.

[0254] In the example embodiment, the orthographic projection of the tenth via V10 on the silicon substrate can be located within the range of the orthographic projection of the potential line active region 10 on the silicon substrate, the first insulating layer and the second insulating layer in the tenth via V10 are etched away to expose the surface of the potential line active region 10, and the tenth via V10 is configured to connect the substrate potential line formed subsequently therethrough to the potential line active region 10.

[0255] In the example embodiment, the tenth via V10 can be multiple, and the multiple tenth vias V10 can be arranged in sequence along the first direction X to reduce the contact resistance and increase the connection reliability.

[0256] (7) Forming a first conductive layer pattern. In the example embodiment, forming the first conductive layer pattern can include: depositing a first conductive thin film on the silicon substrate on which the aforementioned pattern is formed, and patterning the first conductive thin film through a patterning process to form the first conductive layer pattern on the second insulating layer. As shown in FIGS. 19A and 19B, FIG. 19B is a schematic diagram of the first conductive layer in FIG. 19A. In the example embodiment, the first conductive layer can be referred to as a first metal (Metal 1) layer.

[0257] In the example embodiment, the first conductive layer pattern of each switching unit in the control circuit can at least include: a substrate potential line 50, a first connection electrode 51, a second connection electrode 52, and a third connection electrode 53.

[0258] In the example embodiment, the shape of the substrate potential line 50 can be a straight line or a polyline extending along the first direction X, and the substrate potential line 50 can be arranged on both sides of the second direction Y of the plurality of transistors and connected to the potential line active region 10 through the plurality of tenth vias V10.

[0259] In the example embodiment, since the potential line active region 10 is located in the N-type doped region, the substrate potential line 50 not only can achieve a relatively stable potential reference to ensure consistent and reliable performance of the control circuit under different working conditions, but also can provide a better signal isolation effect, reduce signal crosstalk and interference, and improve the circuit stability and reliability of the data control device.

[0260] In the example embodiment, the shape of the first connection electrode 51 can be a straight line or a polyline extending along the second direction Y, and the first connection electrode 51 is connected to the first source region through the first via V1, connected to the second source region through the third via V3, and connected to the third source region through the fifth via V5.

[0261] In the example embodiment, the first connection electrode 51 realizes the interconnection between the source electrodes of the three transistors, and can simultaneously serve as the first source electrode of the first transistor M1, the second source electrode of the second transistor M2, and the third source electrode of the third transistor M3. The first connection electrode 51 is configured to be connected with the subsequently formed input electrode.

[0262] In the example embodiment, the two switch units in each switch group can share the first connection electrode 51 due to the shared source region and via in each switch group. For example, the first switch unit Q1 and the second switch unit Q2 can share the first connection electrode 51. For another example, the third switch unit Q3 and the fourth switch unit Q4 can share the first connection electrode 51. For yet another example, the fifth switch unit Q5 and the sixth switch unit Q6 can share the first connection electrode 51. The present disclosure can effectively reduce the number of connection electrodes and the occupied space of the data control device by sharing the first connection electrode 51 by the two switch units in each switch group.

[0263] In the example embodiment, the second connection electrode 52 can have a linear shape or a polyline shape extending along the second direction Y. The second connection electrode 52 is connected with the first drain region through the second via V2, connected with the second drain region through the fourth via V4, and connected with the third drain region through the sixth via V6.

[0264] In the example embodiment, the second connection electrode 52 realizes the interconnection between the drain electrodes of the three transistors, and can simultaneously serve as the first drain electrode of the first transistor M1, the second drain electrode of the second transistor M2, and the third drain electrode of the third transistor M3. The second connection electrode 52 is configured to be connected with the subsequently formed fourth connection electrode.

[0265] In the example embodiment, the third connection electrode 53 can have a linear shape or a polyline shape extending along the second direction Y. The third connection electrode 53 can be provided with a first connection block 53-1, a second connection block 53-2, and a third connection block 53-3, respectively. The first connection block 53-1, the second connection block 53-2, and the third connection block 53-3 can have a strip shape extending along the first direction X, and are connected with the third connection electrode 53, respectively. The first connection block 53-1 is connected with the first gate electrode 21 through the seventh via V7, the second connection block 53-2 is connected with the second gate electrode 22 through the eighth via V8, and the third connection block 53-3 is connected with the third gate electrode 23 through the ninth via V9.

[0266] In the example embodiment, the third connection electrode 53 and the three connection blocks realize the interconnection of the first gate electrode of the first transistor M1, the second gate electrode of the second transistor M2, and the third gate electrode of the third transistor M3.

[0267] In the example embodiment, the at least one switching unit can further include a plurality of gate connection electrodes configured to be connected with a control signal line formed subsequently.

[0268] In the example embodiment, the plurality of gate connection electrodes can include at least a first gate connection electrode 61, a second gate connection electrode 62, a third gate connection electrode 63, a fourth gate connection electrode 64, a fifth gate connection electrode 65, and a sixth gate connection electrode 66.

[0269] In the example embodiment, the first gate connection electrode 61 can be in a strip shape extending along the first direction X, can be disposed in the first switching unit Q1, and can be connected with the third connection electrode 53 in the first switching unit Q1, the first gate connection electrode 61 being configured to be connected with a first control signal line formed subsequently.

[0270] In the example embodiment, the second gate connection electrode 62 can be in a strip shape extending along the first direction X, can be disposed in the second switching unit Q2, and can be connected with the third connection electrode 53 in the second switching unit Q2, the second gate connection electrode 62 being configured to be connected with a second control signal line formed subsequently.

[0271] In the example embodiment, the third gate connection electrode 63 can be in a strip shape extending along the first direction X, can be disposed in the third switching unit Q3, and can be connected with the third connection electrode 53 in the third switching unit Q3, the third gate connection electrode 63 being configured to be connected with a third control signal line formed subsequently.

[0272] In the example embodiment, the second connection block 53-2 in the third switching unit Q3 can serve as the third gate connection electrode 63, i.e., the second connection block 53-2 and the third gate connection electrode 63 in the third switching unit Q3 are in a shared structure.

[0273] In the example embodiment, the fourth gate connection electrode 64 can be in a strip shape extending along the first direction X, can be disposed in the fourth switching unit Q4, and can be connected with the third connection electrode 53 in the fourth switching unit Q4, the fourth gate connection electrode 64 being configured to be connected with a fourth control signal line formed subsequently.

[0274] In an example embodiment, the fifth gate connection electrode 65 can be in the shape of a strip extending along the first direction X, can be disposed in the fifth switch unit Q5, and can be connected with the third connection electrode 53 in the fifth switch unit Q5. The fifth gate connection electrode 65 is configured to be connected with the fifth control signal line formed subsequently.

[0275] In an example embodiment, the sixth gate connection electrode 66 can be in the shape of a strip extending along the first direction X, can be disposed in the sixth switch unit Q6, and can be connected with the third connection electrode 53 in the sixth switch unit Q6. The sixth gate connection electrode 66 is configured to be connected with the sixth control signal line formed subsequently.

[0276] In an example embodiment, in the second direction Y, the first gate connection electrode 61, the second gate connection electrode 62, the third gate connection electrode 63, the fourth gate connection electrode 64, the fifth gate connection electrode 65, and the sixth gate connection electrode 66 can be sequentially disposed along a direction away from the display area.

[0277] In an example embodiment, in at least one control circuit, the gate connection electrodes of at least three switch units are substantially located on the same straight line, that is, at least three gate connection electrodes among the first gate connection electrode 61 to the sixth gate connection electrode 66 are substantially located on the same straight line, to ensure the stability of signal transmission.

[0278] In an example embodiment, the at least three gate connection electrodes being substantially located on the same straight line can be that the orthographic projection of the at least three gate connection electrodes on the silicon substrate at least partially overlaps with the orthographic projection of the same straight line on the silicon substrate.

[0279] (8) Forming a third insulating layer pattern. In an example embodiment, forming the third insulating layer pattern can include: depositing a third insulating thin film on the silicon substrate on which the aforementioned pattern is formed, and patterning the third insulating thin film by a patterning process to form a third insulating layer covering the first conductive layer pattern, the third insulating layer being provided with a plurality of vias, as shown in FIG. 20.

[0280] In an example embodiment, the plurality of vias of each switch unit in the control circuit can include an eleventh via V11 and a twelfth via V12.

[0281] In an example embodiment, the eleventh via V11 can be located on the side of the switch unit away from the display area, the orthographic projection of the eleventh via V11 on the silicon substrate is located within the orthographic projection of the first connection electrode 51 on the silicon substrate, the third insulating layer in the eleventh via V11 is etched away to expose the surface of the first connection electrode 51, and the eleventh via V11 is configured to enable the subsequently formed transverse connection electrode to be connected with the first connection electrode 51 through the via.

[0282] In the example embodiment, since the two switch units in each switch group share the first connection electrode 51, the two switch units in each switch group can share the eleventh via V11. For example, the first switch unit Q1 and the second switch unit Q2 can share the eleventh via V11. For another example, the third switch unit Q3 and the fourth switch unit Q4 can share the eleventh via V11. For still another example, the fifth switch unit Q5 and the sixth switch unit Q6 can share the eleventh via V11.

[0283] In the example embodiment, the twelfth via V12 can be located at the side of the switch unit close to the display area, the orthographic projection of the twelfth via V12 on the silicon substrate is within the orthographic projection of the second connection electrode 52 on the silicon substrate, the third insulating layer within the twelfth via V12 is etched away to expose the surface of the second connection electrode 52, and the twelfth via V12 is configured to enable the fourth connection electrode formed subsequently to connect with the second connection electrode 52 through the via.

[0284] In the example embodiment, the eleventh via V11 and the twelfth via V12 can be multiple to reduce the contact resistance and improve the connection reliability.

[0285] In the example embodiment, at least one switch unit can further include a thirteenth via V13, a fourteenth via V14, a fifteenth via V15, a sixteenth via V16, a seventeenth via V17, and an eighteenth via V18.

[0286] In the example embodiment, the orthographic projection of the thirteenth via V13 on the silicon substrate is within the orthographic projection of the first gate connection electrode 61 on the silicon substrate, the third insulating layer within the thirteenth via V13 is etched away to expose the surface of the first gate connection electrode 61, and the thirteenth via V13 is configured to enable the first control signal line formed subsequently to connect with the first gate connection electrode 61 through the via.

[0287] In the example embodiment, the orthographic projection of the fourteenth via V14 on the silicon substrate is within the orthographic projection of the second gate connection electrode 62 on the silicon substrate, the third insulating layer within the fourteenth via V14 is etched away to expose the surface of the second gate connection electrode 62, and the fourteenth via V14 is configured to enable the second control signal line formed subsequently to connect with the second gate connection electrode 62 through the via.

[0288] In the example embodiment, the third gate connecting electrode 63 is formed on the silicon substrate 1, and the third gate connecting electrode 63 is formed on the third insulating layer 32. The third gate connecting electrode 63 is configured to be connected to the third control signal line formed later through the fifteenth via hole V15.

[0289] In the example embodiment, the fourth gate connecting electrode 64 is formed on the silicon substrate 1, and the fourth gate connecting electrode 64 is formed on the third insulating layer 32. The fourth gate connecting electrode 64 is configured to be connected to the fourth control signal line formed later through the sixteenth via hole V16.

[0290] In the example embodiment, the fifth gate connecting electrode 65 is formed on the silicon substrate 1, and the fifth gate connecting electrode 65 is formed on the third insulating layer 32. The fifth gate connecting electrode 65 is configured to be connected to the fifth control signal line formed later through the seventeenth via hole V17.

[0291] In the example embodiment, the sixth gate connecting electrode 66 is formed on the silicon substrate 1, and the sixth gate connecting electrode 66 is formed on the third insulating layer 32. The sixth gate connecting electrode 66 is configured to be connected to the sixth control signal line formed later through the eighteenth via hole V18.

[0292] In the example embodiment, the thirteenth via hole V13 to the eighteenth via hole V18 can be referred to as a control signal via hole, and the number of control signal via holes in each switch unit can be greater than or equal to 2. This not only reduces the contact resistance, but also improves the connection reliability of the control signal line and the gate connecting electrode, effectively avoiding the vertical dark line and other defects caused by the disconnection between the control signal line and the gate connecting electrode.

[0293] In the example embodiment, in at least one control circuit, the control signal via holes of at least three switch units are substantially located on the same straight line, that is, at least three of the thirteenth via hole V13 to the eighteenth via hole V18 are substantially located on the same straight line, so as to ensure the stability of signal transmission.

[0294] In the example embodiment, the at least three via holes being substantially located on the same straight line can mean that the orthographic projection of the at least three via holes on the silicon substrate at least partially overlaps with the orthographic projection of the same straight line on the silicon substrate.

[0295] (9) forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern can include: depositing a second conductive thin film on the silicon substrate on which the aforementioned pattern is formed, patterning the second conductive thin film through a patterning process, and forming the second conductive layer pattern on the third insulating layer. In an exemplary embodiment, the second conductive layer can be referred to as a second metal (Metal2) layer.

[0296] In an exemplary embodiment, the second conductive layer pattern of each switching unit in the control circuit can include at least a fourth connection electrode 54.

[0297] In an exemplary embodiment, the fourth connection electrode 54 can have a strip shape extending along the second direction Y, the fourth connection electrode 54 can be connected to the second connection electrode 52 through a twelfth via V12, and the fourth connection electrode 54 can be configured to be connected to a fifth connection electrode to be formed later.

[0298] In an exemplary embodiment, the second conductive layer pattern of at least one control circuit can further include an input electrode, and the input electrode can include a horizontal connection electrode 71 and a vertical connection electrode 72.

[0299] In an exemplary embodiment, the horizontal connection electrode 71 can have a strip shape extending along the first direction X, and the horizontal connection electrode 71 can be disposed on a side of the control circuit away from the display area. The horizontal connection electrode 71 can be connected to the first connection electrode 51 in each of the three switching groups through an eleventh via V11. In an exemplary embodiment, since the first connection electrode 51 is shared by two switching units in each switching group, the first connection electrode 51 simultaneously serves as a first source electrode of the first transistor M1, a second source electrode of the second transistor M2, and a third source electrode of the third transistor M3, and thus the horizontal connection electrode 71 achieves the mutual connection of the source electrodes of the six transistors in the six switching units.

[0300] In an exemplary embodiment, the vertical connection electrode 72 can have a strip shape extending along the second direction Y, a first end of the vertical connection electrode 72 can be connected to the horizontal connection electrode 71, and a second end of the vertical connection electrode 72 can extend away from the display area and be configured to be connected to an input signal line to be formed later.

[0301] In an exemplary embodiment, in at least one control circuit, the horizontal connection electrode 71 and the vertical connection electrode 72 can be an integrated structure connected to each other.

[0302] In the example embodiment, the orthogonal projection of the lateral connection electrode 71 on the silicon substrate at least partially overlaps the orthogonal projection of the first connection electrode 51 of the three switch groups on the silicon substrate, and the orthogonal projection of the lateral connection electrode 71 on the silicon substrate at least partially overlaps the orthogonal projection of the second connection electrode 52 of the six switch units on the silicon substrate. The present disclosure can effectively ensure the consistency of the input signal by arranging the lateral connection electrode to extend to cover the source end and the drain end of the six switch units.

[0303] In the example embodiment, the orthogonal projection of the lateral connection electrode 71 on the silicon substrate at least partially overlaps the orthogonal projection of the third active region 13 and the third gate electrode 23 of the six switch units on the silicon substrate.

[0304] In the example embodiment, in at least one switch unit, the orthogonal projection of the lateral connection electrode 71 on the silicon substrate at least partially overlaps the orthogonal projection of the third source region of the third active region on the silicon substrate, and the orthogonal projection of the lateral connection electrode 71 on the silicon substrate at least partially overlaps the orthogonal projection of the third drain region of the third active region on the silicon substrate.

[0305] In the example embodiment, in at least one switch unit, the orthogonal projection of the lateral connection electrode 71 on the silicon substrate has a first overlapping area with the orthogonal projection of the third source region of the third active region on the silicon substrate, and the orthogonal projection of the lateral connection electrode 71 on the silicon substrate has a second overlapping area with the orthogonal projection of the third drain region of the third active region on the silicon substrate. The ratio of the first overlapping area to the second overlapping area can be about 0.9 to 1.1.

[0306] In the example embodiment, the first overlapping area and the second overlapping area can be substantially the same, the first overlapping area in the plurality of switch units can be substantially the same, and the second overlapping area in the plurality of switch units can be substantially the same, which can effectively ensure the uniformity of the process, the uniformity of the electrical characteristics, and the consistency of the input signal.

[0307] In the example embodiment, the at least one control circuit can further include a first control signal line 91, a second control signal line 92, a third control signal line 93, a fourth control signal line 94, a fifth control signal line 95, and a sixth control signal line 96.

[0308] In the example embodiment, the first control signal line 91 can have a strip shape extending along the first direction X, can be provided across the first to sixth switch units Q1 to Q6, and the first control signal line 91 is connected to the first gate connection electrode 61 through the thirteenth via V13. Since the first gate connection electrode 61 is connected to the third connection electrode 53 in the first switch unit Q1, the third connection electrode 53 is connected to the first, second, and third gate electrodes 21, 22, and 23, respectively, the connection of the first control signal line 91 to the gate electrodes of the first to third transistors M1, M2, and M3 in the first switch unit Q1 is achieved, and the first control signal line 91 can control the on and off of the first to third transistors M1, M2, and M3 in the first switch unit Q1.

[0309] In the example embodiment, the second control signal line 92 can have a strip shape extending along the first direction X, can be provided across the first to sixth switch units Q1 to Q6, and the second control signal line 92 is connected to the second gate connection electrode 62 through the fourteenth via V14. Since the second gate connection electrode 62 is connected to the third connection electrode 53 in the second switch unit Q2, the third connection electrode 53 is connected to the first, second, and third gate electrodes 21, 22, and 23, respectively, the connection of the second control signal line 92 to the gate electrodes of the first to third transistors M1, M2, and M3 in the second switch unit Q2 is achieved, and the second control signal line 92 can control the on and off of the first to third transistors M1, M2, and M3 in the second switch unit Q2.

[0310] In the example embodiment, the third control signal line 93 can have a strip shape extending along the first direction X, can be provided across the first to sixth switch units Q1 to Q6, and the third control signal line 93 is connected to the third gate connection electrode 63 through the fifteenth via V15. Since the third gate connection electrode 63 is connected to the third connection electrode 53 in the third switch unit Q3, the third connection electrode 53 is connected to the first, second, and third gate electrodes 21, 22, and 23, respectively, the connection of the third control signal line 93 to the gate electrodes of the first to third transistors M1, M2, and M3 in the third switch unit Q3 is achieved, and the third control signal line 93 can control the on and off of the first to third transistors M1, M2, and M3 in the third switch unit Q3.

[0311] In the example embodiment, the fourth control signal line 94 can have a strip shape extending along the first direction X, can be provided across the first to sixth switching units Q1 to Q6, and the fourth control signal line 94 is connected to the fourth gate connection electrode 64 through the sixteenth via V16. Since the fourth gate connection electrode 64 is connected to the third connection electrode 53 in the fourth switching unit Q4, the third connection electrode 53 is connected to the first, second, and third gate electrodes 21, 22, and 23, respectively, the connection of the fourth control signal line 94 to the gate electrodes of the first to third transistors M1 to M3 in the fourth switching unit Q4 is achieved, and the fourth control signal line 94 can control the on and off of the first to third transistors M1 to M3 in the fourth switching unit Q4.

[0312] In the example embodiment, the fifth control signal line 95 can have a strip shape extending along the first direction X, can be provided across the first to sixth switching units Q1 to Q6, and the fifth control signal line 95 is connected to the fifth gate connection electrode 65 through the seventeenth via V17. Since the fifth gate connection electrode 65 is connected to the third connection electrode 53 in the fifth switching unit Q5, the third connection electrode 53 is connected to the first, second, and third gate electrodes 21, 22, and 23, respectively, the connection of the fifth control signal line 95 to the gate electrodes of the first to third transistors M1 to M3 in the fifth switching unit Q5 is achieved, and the fifth control signal line 95 can control the on and off of the first to third transistors M1 to M3 in the fifth switching unit Q5.

[0313] In the example embodiment, the sixth control signal line 96 can have a strip shape extending along the first direction X, can be provided across the first to sixth switching units Q1 to Q6, and the sixth control signal line 96 is connected to the sixth gate connection electrode 66 through the eighteenth via V18. Since the sixth gate connection electrode 66 is connected to the third connection electrode 53 in the sixth switching unit Q6, the third connection electrode 53 is connected to the first, second, and third gate electrodes 21, 22, and 23, respectively, the connection of the sixth control signal line 96 to the gate electrodes of the first to third transistors M1 to M3 in the sixth switching unit Q6 is achieved, and the sixth control signal line 96 can control the on and off of the first to third transistors M1 to M3 in the sixth switching unit Q6.

[0314] In the exemplary embodiments, in the second direction Y, the first control signal line 91, the second control signal line 92, the third control signal line 93, the fourth control signal line 94, the fifth control signal line 95, and the sixth control signal line 96 can be sequentially arranged along a direction away from the display area, and the distance between adjacent control signal lines in the second direction Y can be substantially the same.

[0315] (10) Forming a fourth insulating layer pattern. In the exemplary embodiments, forming the fourth insulating layer pattern can include: depositing a fourth insulating thin film on the silicon substrate on which the aforementioned patterns are formed, patterning the fourth insulating thin film by a patterning process, forming a fourth insulating layer covering the second conductive layer pattern, and the fourth insulating layer being provided with a plurality of vias, as shown in FIG. 22.

[0316] In the exemplary embodiments, the plurality of vias in the control circuit can include a twenty-first via V21 and a twenty-second via V22.

[0317] In the exemplary embodiments, the twenty-first via V21 is located within the range of the orthographic projection of the vertical connection electrode 72 on the silicon substrate, the fourth insulating layer in the twenty-first via V21 is etched away, exposing the surface of the vertical connection electrode 72, and the twenty-first via V21 is configured to allow the subsequently formed input signal line to pass through the via and be connected to the vertical connection electrode 72.

[0318] In the exemplary embodiments, the twenty-second via V22 can be provided in each switching unit of the control circuit, the twenty-second via V22 is located within the range of the orthographic projection of the fourth connection electrode 54 on the silicon substrate, the fourth insulating layer in the twenty-second via V22 is etched away, exposing the surface of the fourth connection electrode 54, and the twenty-second via V22 is configured to allow the subsequently formed fifth connection electrode to pass through the via and be connected to the fourth connection electrode 54.

[0319] (11) Forming a third conductive layer pattern. In the exemplary embodiments, forming the third conductive layer pattern can include: depositing a third conductive thin film on the silicon substrate on which the aforementioned patterns are formed, patterning the third conductive thin film by a patterning process, and forming the third conductive layer pattern on the fourth insulating layer, as shown in FIGS. 23A and 23B, FIG. 23B being a schematic view of the third conductive layer in FIG. 23A. In the exemplary embodiments, the third conductive layer can be referred to as a third metal (Metal 3) layer.

[0320] In the exemplary embodiments, the second conductive layer pattern of the control circuit can at least include: a fifth connection electrode 55 and an input signal line 81.

[0321] In the example embodiment, the input signal line 81 can be in the shape of a strip extending along the second direction Y, and the input signal line 81 is connected to the vertical connection electrode 72 through the twenty-first via V21. Since the vertical connection electrode 72 is connected to the horizontal connection electrode 71, the horizontal connection electrode 71 is connected to the first connection electrode 51, and the first connection electrode 51 is connected to the first source electrode, the second source electrode and the third source electrode of the first transistor M1, the second transistor M2 and the third transistor M3 respectively, the input signal line 81 is connected to the first source electrode of the first transistor M1, the second source electrode of the second transistor M2 and the third source electrode of the third transistor M3 in the six switching units simultaneously, and the input signal line 81 can input data signals to the input terminals of the six switching units simultaneously.

[0322] In the example embodiment, the fifth connection electrode 55 can be arranged in each switching unit of the control circuit, the fifth connection electrode 55 can be in the shape of a strip extending along the second direction Y, the fifth connection electrode 55 is connected to the fourth connection electrode 54 through the twenty-second via V22, and the fifth connection electrode 55 is configured to be connected to the output signal line formed subsequently.

[0323] (12) Forming the fifth insulating layer pattern. In the example embodiment, forming the fifth insulating layer pattern can include: depositing a fifth insulating thin film on the silicon substrate on which the aforementioned patterns are formed, patterning the fifth insulating thin film through a patterning process, forming a fifth insulating layer covering the third conductive layer pattern, and arranging a plurality of vias on the fifth insulating layer, as shown in FIG. 24.

[0324] In the example embodiment, the plurality of vias of each switching unit in the control circuit can include a thirty-first via V31.

[0325] In the example embodiment, the orthographic projection of the thirty-first via V31 on the silicon substrate is within the range of the orthographic projection of the fifth connection electrode 55 on the silicon substrate, the fifth insulating layer in the thirty-first via V31 is etched away, exposing the surface of the fifth connection electrode 55, and the thirty-first via V31 is configured to allow the output signal line formed subsequently to be connected to the fifth connection electrode 55 through the via.

[0326] (13) Forming the fourth conductive layer pattern. In the example embodiment, forming the fourth conductive layer pattern can include: depositing a fourth conductive thin film on the silicon substrate on which the aforementioned patterns are formed, patterning the fourth conductive thin film through a patterning process, and forming the fourth conductive layer pattern on the fifth insulating layer, as shown in FIG. 25A and FIG. 25B, and FIG. 25B is a schematic diagram of the fourth conductive layer in FIG. 25A. In the example embodiment, the fourth conductive layer can be referred to as a fourth metal (Metal4) layer.

[0327] In an example embodiment, the second conductive layer pattern of each of the switching units in the control circuit can at least include the output signal line 82.

[0328] In an example embodiment, the output signal line 82 can be in the shape of a broken line extending along the second direction Y, and the output signal line 82 is connected to the fifth connection electrode 55 through the thirty-first via V31. Since the fifth connection electrode 55 is connected to the fourth connection electrode 54, the fourth connection electrode 54 is connected to the second connection electrode 52, and the second connection electrode 52 is connected to the first drain region, the second drain region, and the third drain region respectively, the connection of the output signal line 82 to the first drain electrode of the first transistor M1, the second drain electrode of the second transistor M2, and the third drain electrode of the third transistor M3 is realized. In an example embodiment, the output signal line 82 is configured to be connected to the data signal line of the display region.

[0329] In an example embodiment, the output signal line 82 has no overlap with the orthographic projection of the first gate electrode 21, the second gate electrode 22, and the third gate electrode 23 on the silicon substrate. By setting the output signal line 82 not to overlap with the gate electrodes of the first transistor M1, the second transistor M2, and the third transistor M3, the present disclosure can effectively reduce the parasitic capacitance of the output signal line 82, and reduce the rising time delay value (tr) and the falling time delay value (tf) of the output signal.

[0330] In an example embodiment, the output signal line 82 in at least one of the switching units can at least include a first line segment 82-1, a second line segment 82-2, and a third line segment 82-3 connected in sequence, the first line segment 82-1 and the third line segment 82-3 can be in the shape of a strip extending along the second direction Y, and the second line segment 82-2 can be in the shape of a strip extending along the first direction X.

[0331] In an example embodiment, the first end of the first line segment 82-1 is connected to the fifth connection electrode 55 through the thirty-first via V31, and the second end of the first line segment 82-1 is connected to the first end of the second line segment 82-2 after extending along the opposite direction of the second direction Y (towards the direction close to the display region). The second end of the second line segment 82-2 is connected to the first end of the third line segment 82-3 after extending along the first direction X or the opposite direction of the first direction X (towards the direction close to the adjacent switching unit or the direction away from the adjacent switching unit). The second end of the third line segment 82-3 is connected to the data signal line of the display region after extending along the opposite direction of the second direction Y (towards the direction close to the display region).

[0332] In the exemplary embodiments, in at least one switch group, the second line segments 82-2 of two switch units extend in directions approaching each other. For example, in the first switch group G1, the second line segment 82-2 of the first switch unit Q1 extends in the direction of the second line segment 82-2 of the second switch unit Q2, and the second line segment 82-2 of the second switch unit Q2 extends in the direction of the second line segment 82-2 of the first switch unit Q1. For another example, in the second switch group G2, the second line segment 82-2 of the third switch unit Q3 extends in the direction of the second line segment 82-2 of the fourth switch unit Q4, and the second line segment 82-2 of the fourth switch unit Q4 extends in the direction of the second line segment 82-2 of the third switch unit Q3. For yet another example, in the third switch group G3, the second line segment 82-2 of the fifth switch unit Q5 extends in the direction of the second line segment 82-2 of the sixth switch unit Q6, and the second line segment 82-2 of the sixth switch unit Q6 extends in the direction of the second line segment 82-2 of the fifth switch unit Q5.

[0333] In the exemplary embodiments, in two adjacent switch units in adjacent switch groups, the second line segments 82-2 of the two switch units extend in directions moving away from each other. For example, the second switch unit Q2 in the first switch group G1 and the third switch unit Q3 in the second switch group G2 are two adjacent switch units in adjacent switch groups, the second line segment 82-2 of the second switch unit Q2 extends in the direction moving away from the second line segment 82-2 of the third switch unit Q3, and the second line segment 82-2 of the third switch unit Q3 extends in the direction moving away from the second line segment 82-2 of the second switch unit Q2. For another example, the fourth switch unit Q4 in the second switch group G2 and the fifth switch unit Q5 in the third switch group G3 are two adjacent switch units in adjacent switch groups, the second line segment 82-2 of the fourth switch unit Q4 extends in the direction moving away from the second line segment 82-2 of the fifth switch unit Q5, and the second line segment 82-2 of the fifth switch unit Q5 extends in the direction moving away from the second line segment 82-2 of the fourth switch unit Q4.

[0334] In the exemplary embodiments, in at least one control circuit, the ratio of the spacing between two adjacent output signal lines 82 to the spacing between another two adjacent output signal lines 82 can be 0.95 to 1.05.

[0335] In the exemplary embodiments, the spacing between adjacent output signal lines 82 refers to the spacing between adjacent third line segments 82-3.

[0336] In the exemplary embodiments, the first spacing D1 between the output signal line 82 in the first switching unit Q1 and the output signal line 82 in the second switching unit Q2, the second spacing D2 between the output signal line 82 in the second switching unit Q2 and the output signal line 82 in the third switching unit Q3, the third spacing D3 between the output signal line 82 in the third switching unit Q3 and the output signal line 82 in the fourth switching unit Q4, the fourth spacing D4 between the output signal line 82 in the fourth switching unit Q4 and the output signal line 82 in the fifth switching unit Q5, and the fifth spacing D5 between the output signal line 82 in the fifth switching unit Q5 and the output signal line 82 in the sixth switching unit Q6 can be approximately 0.95 to 1.05, the ratio of the first spacing D1 to the second spacing D2 can be approximately 0.95 to 1.05, the ratio of the second spacing D2 to the third spacing D3 can be approximately 0.95 to 1.05, the ratio of the third spacing D3 to the fourth spacing D4 can be approximately 0.95 to 1.05, and the ratio of the fourth spacing D4 to the fifth spacing D5 can be approximately 0.95 to 1.05.

[0337] In the exemplary embodiments, the first spacing D1, the second spacing D2, the third spacing D3, the fourth spacing D4, and the fifth spacing D5 can be substantially the same. By setting the spacings between the adjacent output signal lines to be substantially the same, the present disclosure can ensure that the parasitic capacitances between the plurality of output signal lines are substantially the same, and thus the coupling between the plurality of output signal lines is substantially uniform, effectively avoiding the vertical lines and other defects caused by the inconsistent coupling between the output signal lines.

[0338] Thus far, the preparation of the display substrate of the exemplary embodiments of the present disclosure is completed.

[0339] In the exemplary embodiments, the display substrate of the exemplary embodiments of the present disclosure can include a silicon substrate, and a first insulating layer, a gate conductive layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a third conductive layer, a fifth insulating layer, and a fourth conductive layer sequentially arranged on the silicon substrate. The first insulating layer to the fifth insulating layer can be made of silicon oxide SiOx, silicon nitride SiNx, or silicon oxynitride SiON, and can be a single-layer structure or a multi-layer composite structure. The first conductive layer to the fourth conductive layer can be made of a metal material such as silver (Ag), copper (Cu), aluminum (Al), or molybdenum (Mo), or can be made of an alloy material composed of a metal, such as an aluminum-neodymium alloy (AlNd) or a molybdenum-niobium alloy (MoNb), and the alloy material can be a single-layer structure or a multi-layer composite structure, such as a composite structure composed of a Mo layer, a Cu layer, and a Mo layer.

[0340] In the exemplary embodiments, the planar shape of the via hole can be rectangular, circular, or elliptical, and the sizes of the plurality of via holes can be the same or different, which is not limited in the present disclosure.

[0341] Fig. 26 is a layout diagram of a data control device according to an example embodiment of the present disclosure. As shown in Fig. 26, the data control device can be arranged in a peripheral region, and a plurality of control circuits in the data control device can be arranged in sequence along a first direction X. The input signal line 81 of each control circuit extends towards the display driving chip and is connected to the display driving chip by binding. The output signal line 82 of each control circuit extends towards the display region and is connected to the data signal line.

[0342] In the example embodiment, the substrate potential line 50 forms a ring structure around the plurality of control circuits, which can effectively shield the signal interference of other circuits on the control circuits and effectively enhance the anti-interference performance of the data control device.

[0343] The example embodiment of the present disclosure provides a display substrate. By arranging the data control device, the data control device converts the serial signals of the display driving chip into parallel signals and inputs the parallel signals into the data signal lines of the display region. The number of pads of the display driving chip and the number of signal lines between the display driving chip and the display region can be effectively reduced, the product structure is simplified, the product cost is reduced, and the display substrate can be applied to a silicon-based OLED display device with a pixel density of 4K or more.

[0344] The data control device provided by the present disclosure has the advantages of small occupied area, large driving capacity, strong anti-interference performance, and the like, can effectively avoid crosstalk of data signals, improve the accuracy of display information, and enhance the quality of a display picture.

[0345] The present disclosure sets the distance between adjacent switch groups to be greater than the distance between adjacent transistors, and the distance between adjacent switch groups is greater than or equal to 1 μm, which can minimize the interference between switch groups.

[0346] The present disclosure sets the switch unit to adopt a parallel structure of three transistors, which can effectively increase the width-length ratio of the transistor, thereby improving the driving capacity of the transistor, and can effectively improve the driving reliability and ensure the transmission of data signals.

[0347] The present disclosure sets the active region and the shared first connection electrode in the switch group to have an integrated structure, which can effectively reduce the occupied area of the data control device.

[0348] The present disclosure sets the number of control signal vias to be greater than or equal to 2, which can not only reduce the contact resistance, but also improve the connection reliability of the control signal line and the gate connection electrode, and effectively avoid vertical dark lines and other defects caused by the disconnection between the control signal line and the gate connection electrode.

[0349] The disclosure can effectively ensure the consistency of the input signal by setting the transverse connection electrode to extend to cover the source end and the drain end of 6 switch units, and can effectively reduce the parasitic capacitance of the output signal line, and reduce the rising edge delay value and the falling edge delay value of the output signal by setting the output signal line not to overlap with the gate electrode of the transistor.

[0350] The disclosure can ensure that the parasitic capacitance between the plurality of output signal lines is substantially the same by setting the spacing between adjacent output signal lines to be substantially the same, thereby ensuring that the coupling between the plurality of output signal lines is substantially uniform, effectively avoiding data signal crosstalk and vertical lines and other defects caused by inconsistent coupling between the output signal lines.

[0351] The disclosure can effectively increase the testing and analysis means, help to locate various defects, and improve the defect analysis efficiency by setting the data control device to realize the lighting detection and aging treatment of the display substrate. In addition, the single-color and high-brightness aging treatment in the AOI mode of the display substrate can make the product have better service life performance.

[0352] The preparation process of the disclosure can be realized by using mature preparation equipment, has high compatibility, is simple to implement, has high production efficiency, low production cost, and high yield.

[0353] The structure of the display substrate and the preparation process thereof in the exemplary embodiments of the disclosure are merely exemplary and can be changed, increased or reduced according to actual conditions, which are not limited in the disclosure.

[0354] In the exemplary embodiments, the display substrate of the disclosure can be applied to display devices with pixel driving circuits, such as silicon-based OLED micro display devices, silicon-based LED micro display devices, and OLED display devices, which are not limited in the disclosure.

[0355] The exemplary embodiments of the disclosure also provide a display device comprising the display substrate described above. The display device of the disclosure can be used in virtual reality (VR) devices, augmented reality (AR) devices, extended reality (XR) devices, mixed reality (MR) devices, sights, range finders, and the like.

[0356] Although the embodiments disclosed in the disclosure are as described above, it should be noted that the above embodiments are merely exemplary and not limiting. Therefore, the disclosure is not limited to the specific embodiments shown and described herein. Various modifications, substitutions or omissions can be made to the embodiments without departing from the scope of the disclosure.

Claims

1. A display substrate comprising a display area and a peripheral area located at least one side of the display area, the display area comprising at least a plurality of sub-pixels and a plurality of data signal lines, at least one sub-pixel comprising a pixel driving circuit, the data signal lines being configured to provide data signals to the connected pixel driving circuits, the peripheral area comprising at least a data control device, the data control device comprising a plurality of control circuits, the plurality of control circuits being configured to provide data signals to the plurality of data signal lines; at least one control circuit comprising a plurality of switch groups arranged in sequence along a first direction, at least one switch group comprising a plurality of switch units arranged in sequence along the first direction, at least one switch unit comprising a plurality of transistors arranged in sequence along a second direction and forming a parallel structure, the first direction and the second direction intersecting; in the first direction, a first distance is provided between adjacent switch groups, in the second direction, a second distance is provided between adjacent transistors, the first distance being greater than the second distance. 2.The display substrate of claim 1, wherein, The first distance is greater than or equal to 1 pm. 3.The display substrate of claim 1, wherein, At least one control circuit comprises three switch groups, at least one switch group comprises two switch units, and at least one switch unit comprises a first transistor, a second transistor, and a third transistor. 4.The display substrate of claim 3, wherein, The first transistor comprises at least a first active region, the second transistor comprises at least a second active region, and the third transistor comprises at least a third active region; in at least one switch group, the first active regions in the two switch units are an integral structure connected to each other, the second active regions in the two switch units are an integral structure connected to each other, and the third active regions in the two switch units are an integral structure connected to each other. 5.The display substrate of claim 4, wherein, The first distance is the distance between the first active regions, or the distance between the second active regions, or the distance between the third active regions in adjacent switch groups; the second distance is the distance between the first active region and the second active region, or the distance between the second active region and the third active region. 6.The display substrate of claim 4, wherein, At least one switch unit further comprises a first connection electrode and a second connection electrode; the first connection electrode is connected to a first source region of the first active region, a second source region of the second active region, and a third source region of the third active region, respectively, and the first connection electrode serves as a first source electrode of the first transistor, a second source electrode of the second transistor, and a third source electrode of the third transistor; The second connection electrode is connected to a first drain region of the first active region, a second drain region of the second active region, and a third drain region of the third active region, respectively, and the second connection electrode serves as a first drain electrode of the first transistor, a second drain electrode of the second transistor, and a third drain electrode of the third transistor. 7.The display substrate of claim 6, wherein, In at least one switch group, the two switch units share the first connection electrode. 8.The display substrate of claim 6, wherein, At least one control circuit further comprises an input signal line, the input signal line being connected to the first connection electrode in the three switch groups through an input electrode, respectively. 9.The display substrate of claim 8, wherein, The input electrode comprises at least a horizontal connection electrode and a vertical connection electrode, the horizontal connection electrode is in a strip shape extending along the first direction, the horizontal connection electrode is connected with the first connection electrode 51 in the three switch groups through a via, the vertical connection electrode is in a strip shape extending along the second direction, a first end of the vertical connection electrode is connected with the horizontal connection electrode, and a second end of the vertical connection electrode is connected with the input signal line through a via. 10.The display substrate of claim 9, wherein, The horizontal connection electrode is at least partially overlapped with the first connection electrode in the three switch groups in the orthographic projection on the display substrate plane, and the horizontal connection electrode is at least partially overlapped with the second connection electrode in the six switch units in the orthographic projection on the display substrate plane. 11.The display substrate of claim 9, wherein, In at least one switch unit, the horizontal connection electrode is at least partially overlapped with the third source region of the third active region in the orthographic projection on the display substrate plane, and the horizontal connection electrode is at least partially overlapped with the third drain region of the third active region in the orthographic projection on the display substrate plane. 12.The display substrate of claim 11, wherein, In at least one switch unit, the horizontal connection electrode has a first overlapping area with the third source region of the third active region in the orthographic projection on the display substrate plane, and the horizontal connection electrode has a second overlapping area with the third drain region of the third active region in the orthographic projection on the display substrate plane, and the ratio of the first overlapping area to the second overlapping area is 0.9 to 1.

1. 13.The display substrate of claim 6, wherein, The output signal line further comprises a first end connected with the second connection electrode and a second end connected with the data signal line, and the orthographic projection of the output signal line on the display substrate plane is not overlapped with the orthographic projection of the first gate electrode of the first transistor, the second gate electrode of the second transistor and the third gate electrode of the third transistor on the display substrate plane. 14.The display substrate of claim 13, wherein, In at least one control circuit, the ratio of the spacing between two adjacent output signal lines to the spacing between another two adjacent output signal lines is 0.95 to 1.

05. 15.The display substrate of claim 13, wherein, In at least one switch unit, the output signal line comprises at least a first line segment, a second line segment and a third line segment connected in sequence, a first end of the first line segment is connected with the second connection electrode, a second end of the first line segment is connected with a first end of the second line segment after extending towards the display area, a second end of the second line segment is connected with a first end of the third line segment after extending towards the adjacent switch unit or away from the adjacent switch unit, and a second end of the third line segment is connected with the data signal line after extending towards the display area. 16.The display substrate of claim 15, wherein, In at least one switch group, the second line segment in the two switch units extends towards each other. 17.The display substrate of claim 15, wherein, In two adjacent switch units in the adjacent switch group, the second line segments in the two switch units extend away from each other. 18.The display substrate of claim 4, wherein, The first transistor further includes a first gate electrode, the second transistor further includes a second gate electrode, and the third transistor further includes a third gate electrode; the at least one switch unit further includes a third connection electrode, the third connection electrode is connected with the first gate electrode, the second gate electrode and the third gate electrode through gate via holes, and a projection of the gate via holes on a display substrate plane does not overlap with projections of the first active area, the second active area and the third active area on the display substrate plane.

19. The display substrate of claim 18, wherein, The at least one switch unit further includes a gate connection electrode and a control signal line, the gate connection electrode is connected with the third connection electrode, and the control signal line is connected with the gate connection electrode through a control signal via hole, and a number of the control signal via hole is greater than or equal to 2. 20.The display substrate of claim 19, wherein, In the at least one control circuit, gate connection electrodes of the at least three switch units are located on a straight line. 21.The display substrate of claim 19, wherein, In the at least one control circuit, control signal via holes of the at least three switch units are located on a straight line.

22. The display substrate according to any one of claims 1 to 21, wherein, The data control device further includes a substrate potential line, and the substrate potential line is in a ring structure surrounding the plurality of control circuits.

23. The display substrate according to any one of claims 1 to 21, wherein, The peripheral area further includes a display driving chip, input signal lines of the control circuit are connected with the display driving chip, and a plurality of output signal lines of the control circuit are connected with a plurality of data signal lines in a corresponding manner.

24. A display device, comprising the display substrate according to any one of claims 1 to 23.

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