Qubit mapping method and apparatus, and device and storage medium

Abstract

The embodiments of the present application belong to the technical field of quantum computing. Disclosed are a qubit mapping method and apparatus, and a device and a storage medium. The method comprises: acquiring a logical qubit sequence and a gate operation sequence corresponding to a quantum computing task (201); on the basis of i candidate physical qubits corresponding to the first i logical qubits in the logical qubit sequence, determining mappable physical qubits of an (i+1)th logical qubit (202); on the basis of mapping cost evaluation results corresponding to the mappable physical qubits, performing screening to select a candidate physical qubit corresponding to the (i+1)th logical qubit (203); when mapping cost evaluation results corresponding to mappable physical qubits of an n-th logical qubit are obtained, determining a target mapping cost evaluation result (204); and on the basis of a qubit mapping combination corresponding to the target mapping cost evaluation result, mapping n logical qubits to n physical qubits (205).

Description

Quantum bit mapping method, device, equipment and storage medium

[0001] The present application claims priority to the Chinese patent application No. 202410642662.2, filed on May 22, 2024, and entitled "Quantum bit mapping method, device, equipment and storage medium", the entire content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] Embodiments of the present application relate to the technical field of quantum computing, in particular to a quantum bit mapping method, device, equipment and storage medium. BACKGROUND

[0003] In quantum hardware, quantum bits are stored in quantum bit units as the basic unit to complete quantum computing. Quantum algorithms are usually represented in the form of quantum circuits, and the given quantum circuits are generally assumed to be fully connected. However, on a real physical quantum chip, due to the limitation of the topology of the physical chip, the quantum bits are connected in a restricted manner. Therefore, in the quantum algorithm compilation process, a quantum bit mapping strategy is needed to compensate for the restricted connection of quantum bits on the physical chip, so as to realize the adaptation of the quantum program between the logical circuit and the physical circuit.

[0004] The mapping process of quantum bits can be divided into two steps, the first step is to generate an initial mapping, and the second step is to exchange the mapping states of two logical quantum bits by adding a controlled swap gate (i.e. a swap gate) in the case that the physical quantum bits corresponding to the logical quantum bits associated with the gate operation are not connected, so that the physical quantum bits corresponding to the logical quantum bits associated with the gate operation are connected, thereby compensating for the connectivity between the logical quantum bits.

[0005] In related technologies, in the process of generating an initial mapping, the logical quantum bits in the quantum circuit are directly randomly mapped to the physical quantum bits on the real physical quantum chip, resulting in randomness in the connection relationship between the physical quantum bits corresponding to the logical quantum bits associated with each gate operation, thereby requiring more swap gates in the process of executing the gate operation, causing resource waste. SUMMARY

[0006] Embodiments of the present application provide a quantum bit mapping method, device, equipment and storage medium, and the technical solution is as follows:

[0007] In one aspect, the present application provides a quantum bit mapping method, which is executed by a computer device, and the method comprises:

[0008] obtain a logical qubit sequence corresponding to a quantum computing task and a gate operation sequence, the logical qubit sequence comprising n logical qubits, n being a positive integer;

[0009] determine, based on i candidate physical qubits corresponding to the first i logical qubits in the logical qubit sequence, a mappable physical qubit of an (i+1)th logical qubit in a physical hardware resource, i being a positive integer;

[0010] select, from the mappable physical qubits of the (i+1)th logical qubit, the candidate physical qubit corresponding to the (i+1)th logical qubit based on a mapping evaluation result corresponding to the mappable physical qubits, wherein the mapping evaluation result represents a degree of influence of a quantum bit mapping combination formed by mapping the (i+1)th logical qubit to the mappable physical qubit on execution of the gate operation sequence, and the degree of influence is related to a number of newly added gate operations required for execution of the gate operation sequence;

[0011] determine a target mapping evaluation result from the mapping evaluation results, the target mapping evaluation result being better than other mapping evaluation results, in a case where the mapping evaluation result corresponding to the mappable physical qubit of the nth logical qubit is obtained;

[0012] map the n logical qubits to n physical qubits in the physical hardware resource based on the quantum bit mapping combination corresponding to the target mapping evaluation result.

[0013] In another aspect, an embodiment of the present application provides a quantum bit mapping device, the device comprising:

[0014] an obtaining module configured to obtain a logical qubit sequence corresponding to a quantum computing task and a gate operation sequence, the logical qubit sequence comprising n logical qubits, n being a positive integer;

[0015] a bit determining module configured to determine, based on i candidate physical qubits corresponding to the first i logical qubits in the logical qubit sequence, a mappable physical qubit of an (i+1)th logical qubit in a physical hardware resource, i being a positive integer;

[0016] The bit screening module is configured to screen the candidate physical quantum bit corresponding to the i+1th logical quantum bit from the mappable physical quantum bits of the i+1th logical quantum bit based on a mapping evaluation result corresponding to the mappable physical quantum bit, wherein the mapping evaluation result represents an influence degree of a quantum bit mapping combination formed by mapping the i+1th logical quantum bit to the mappable physical quantum bit on the execution of the gate operation sequence, and the influence degree is related to a number of additional gate operations required for the execution of the gate operation sequence.

[0017] The result determination module is configured to determine a target mapping evaluation result from the mapping evaluation results when the mapping evaluation result corresponding to the nth logical quantum bit is obtained, wherein the target mapping evaluation result is better than other mapping evaluation results.

[0018] The bit mapping module is configured to map the n logical quantum bits to n physical quantum bits in the physical hardware resource based on the quantum bit mapping combination corresponding to the target mapping evaluation result.

[0019] In another aspect, an embodiment of the present application provides a computer device, which comprises a processor and a memory, and the memory stores at least one instruction, and the at least one instruction is loaded and executed by the processor to implement the quantum bit mapping method according to the above aspect.

[0020] In another aspect, an embodiment of the present application provides a computer readable storage medium, which stores at least one instruction, and the at least one instruction is loaded and executed by a processor to implement the quantum bit mapping method according to the above aspect.

[0021] In another aspect, an embodiment of the present application provides a computer program product, which comprises at least one instruction stored in a computer readable storage medium. A processor of a computer device reads the at least one instruction from the computer readable storage medium, and the processor executes the at least one instruction, so that the computer device executes the quantum bit mapping method according to the above aspect.

[0022] In the embodiments of the present application, after obtaining the logical qubits corresponding to the quantum computing task and the gate operation sequence, the logical qubits are not directly mapped to the physical qubits in the physical hardware resources. Instead, based on the logical qubit sequence, the mappable physical qubits of each logical qubit are determined starting from the first logical qubit, and the mapping evaluation results corresponding to each mappable physical qubit are calculated, and the candidate physical qubits are selected from the mappable physical qubits according to the mapping evaluation results. Then, through the method of progressive selection, after the mapping evaluation results corresponding to the mappable physical qubits of the nth logical qubit are determined, the optimal mapping evaluation result is selected as the target mapping evaluation result, and the logical qubits are mapped to the physical qubits in the physical hardware resources according to the quantum bit mapping combination corresponding to the target mapping evaluation result. Compared with the direct random quantum bit mapping method, the quantum bit mapping method provided in the embodiments of the present application can reduce the number of newly added gate operations in the gate operation execution process as much as possible, thereby improving the accuracy of quantum bit mapping and optimizing the mapping quality of quantum bits. BRIEF DESCRIPTION OF DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0024] FIG. 1 shows a structural block diagram of a quantum computing system provided by an example embodiment of the present application;

[0025] FIG. 2 shows a flowchart of a quantum bit mapping method provided by an example embodiment of the present application;

[0026] FIG. 3 shows a schematic diagram of a quantum bit mapping combination provided by an example embodiment of the present application;

[0027] FIG. 4 shows a flowchart of a process of obtaining a logical qubit sequence provided by an example embodiment of the present application;

[0028] FIG. 5 shows a logical quantum circuit corresponding to a quantum computing task provided by an example embodiment of the present application;

[0029] FIG. 6 shows a gate operation dependency graph corresponding to the logical quantum circuit in FIG. 5;

[0030] FIG. 7 shows a flowchart of a process of selecting candidate quantum bits provided by an example embodiment of the present application;

[0031] FIG. 8 shows a schematic diagram of a quantum bit mapping combination according to another example embodiment of the present application;

[0032] FIG. 9 shows a flow chart of a process of calculating mapping evaluation results of each quantum bit mapping combination according to an example embodiment of the present application;

[0033] FIG. 10 shows a logical quantum circuit corresponding to a quantum computing task according to another example embodiment of the present application;

[0034] FIG. 11 shows a gate operation dependency graph corresponding to the logical quantum circuit in FIG. 10;

[0035] FIG. 12 shows a quantum bit mapping combination corresponding to the logical quantum bits in FIG. 10 according to an example embodiment of the present application;

[0036] FIG. 13 shows a schematic diagram of screening candidate quantum bits according to an example embodiment of the present application;

[0037] FIG. 14 shows a schematic diagram of screening candidate quantum bits based on a global manner according to an example embodiment of the present application;

[0038] FIG. 15 shows a schematic diagram of screening candidate quantum bits based on a partition manner according to another example embodiment of the present application;

[0039] FIG. 16 shows a schematic diagram of screening candidate quantum bits based on a global manner and a partition manner according to another example embodiment of the present application;

[0040] FIG. 17 shows a structural block diagram of a quantum bit mapping device according to an example embodiment of the present application;

[0041] FIG. 18 shows a structural schematic diagram of a computer device according to an example embodiment of the present application. DETAILED DESCRIPTION

[0042] For the purpose of making the objects, technical solutions and advantages of the present application clearer, the following will further describe the embodiments of the present application with reference to the accompanying drawings.

[0043] The example embodiments will be described in detail herein with reference to the accompanying drawings. The following description is with reference to the drawings, in which like numerals indicate like elements, unless otherwise described, in the various drawings. The following example embodiments described in the following example embodiments are not meant to represent all embodiments consistent with the present application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the present application as detailed in the appended claims.

[0044] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting thereof. As used in this application and the appended claims, the singular forms "a," "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term "and / or," as used herein, refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0045] It should be understood that although the terms first, second, etc. can be used herein to describe various information, but the information should not be limited to these terms. These terms are only used to distinguish one type of information from another type of information. For example, a first parameter can also be called a second parameter without departing from the scope of the application, and similarly, a second parameter can also be called a first parameter. Depending on the context, the word "if" as used herein can be interpreted as "when" or "upon" or "in response to determining".

[0046] First, the nouns involved in the embodiments of the present application are briefly introduced:

[0047] Qubit: is the unit of measurement in quantum information science. Traditional computers use 0 and 1, and quantum computers also use 0 and 1 to represent information, but the difference is that a qubit can be 0 and 1 at the same time. This effect is called quantum superposition, which is a unique feature of quantum computers. The superposition state of qubits greatly improves the processing speed of quantum computers.

[0048] Qubit mapping: when designing a quantum circuit, users usually design according to their own algorithm requirements. However, current quantum chips often have difficulty in realizing the coupling between all qubits, so when executing a quantum circuit on a quantum computing hardware, it is necessary to rearrange the qubits used in the quantum algorithm or add some SWAP gates to exchange states to make up for the topological limitations in the chip, so as to realize the adaptation of the quantum program between the logical circuit and the physical circuit. This rearrangement process when mapping the logical qubits in the logical circuit to the physical qubits in the physical chip is called quantum mapping.

[0049] Quantum gate: also known as gate operation, the basic unit of quantum circuit for operating qubits, which can be represented by a unitary matrix. Compared with traditional logic gates, quantum gates are reversible. According to the number of bits affected, it can be divided into single-qubit gate operation, double-qubit gate operation and multi-qubit gate operation.

[0050] Quantum circuit: is a model for performing quantum computation, including qubits and quantum gates. Quantum circuit diagram is similar to traditional circuit diagram, but quantum circuit diagram defines the conversion path of qubit state and the time sequence of events, rather than the physical connection mode.

[0051] Quantum chip: a semiconductor chip designed and manufactured based on the principles of quantum mechanics, which can utilize the superposition and entanglement of quantum states to achieve more efficient data processing and computing functions. Quantum chip is a microcircuit board composed of single or multiple quantum bits (qubits), each quantum bit has two possible states: 0 and 1, but in quantum mechanics, they can also be in a linear combination of the two states, which is the concept of "superposition" in quantum computing, and it also has the property of "coherence", that is, it will not collapse into any one definite state before measurement.

[0052] Please refer to FIG. 1, which shows the architecture diagram of the quantum computing system to which the quantum bit mapping method of an example embodiment of the present application is applied. The quantum computing system includes a browser, a client, a quantum application, a quantum operating system (Qubit Operating System, QOS), quantum hardware resources, etc.

[0053] Optionally, the browser and the client are executable programs for generating quantum computing tasks, and the browser and the client are usually run on a terminal. Optionally, the terminal can be a smartphone, a tablet computer, a notebook computer, a desktop computer, a smart television, a wearable device, or a vehicle terminal, etc.

[0054] Among them, the quantum application is deployed on the quantum operating system. The application programming interface (Application Programming Interface, API) in the quantum application is used to receive quantum computing tasks, the task distribution system in the quantum application is used to distribute quantum computing tasks to the quantum operating system, and the quantum simulator in the quantum application can simulate quantum computing tasks.

[0055] Optionally, the quantum operation system is deployed in the cloud, and a quantum operation system is generally installed on quantum hardware resources. The quantum operation system includes an intermediate representation, a quantum just-in-time (JIT) compiler, a quantum capsule, resource allocation, isolation security, and resource inspection. The intermediate representation serves as a common interface between a quantum application and the quantum operation system, and can serve as an abstract representation of a quantum computing task. The quantum JIT compiler includes a task scheduling model and a topology compilation model. The task scheduling model is used for task scheduling, and the topology compilation model is used for compiling the scheduled task to obtain a quantum bit cell topology. The quantum capsule includes an inspector and a database. The inspector is used for inspecting a quantum computing task, and the database is used for storing data of the quantum computing task, such as a quantum bit cell topology corresponding to the quantum computing task. The resource allocation is used for allocating virtualized resources for the quantum computing task. The isolation security is used for data isolation and data security between the quantum operation system and quantum hardware resources. The resource inspection is used for the quantum computing task to inspect quantum hardware resources.

[0056] The quantum hardware resources are physical spaces in which quantum computing is located. The quantum hardware resources are generally deployed in the cloud. The quantum hardware resources can include a physical QPU1 and a physical QPU2. The physical QPU1 and the physical QPU2 refer to quantum processing units (QPU).

[0057] The quantum processing unit includes a large number of physical quantum bits. Adjacent physical quantum bits are connected through the action of a radio frequency beam to form an overall quantum bit network.

[0058] When a browser or a client generates a task, and the task is a quantum computing task, the computer device first distributes the task to the task scheduling model of the quantum operation system through the task distribution system in the quantum application, and simulates the quantum computing task through the quantum simulator in the quantum application. Then, the task is scheduled by the task scheduling model in the quantum operation system, and is compiled by the topology compilation model, so that a quantum bit topology structure suitable for executing the quantum computing task can be obtained.

[0059] Referring to FIG. 2, a flowchart of a quantum bit mapping method provided by an example embodiment of the present application is shown. The method is used in a computer device, and includes the following steps:

[0060] In step 201, a logical quantum bit sequence corresponding to a quantum computing task and a gate operation sequence are obtained. The logical quantum bit sequence includes n logical quantum bits.

[0061] Optionally, the quantum computing task refers to a task that utilizes qubits instead of binary bits to perform computations through principles of quantum mechanics, such as quantum superposition, quantum entanglement, and the like. For example, quantum communication, quantum sensing, quantum imaging, and the like.

[0062] Optionally, a physical qubit is a physical unit that implements a qubit and is a physically existing object, such as a Josephson junction in a superconducting circuit, an ion energy level in an ion trap, and the like. The physical qubit has characteristics such as quantum superposition and quantum entanglement and is an information carrier in quantum computing. A logical qubit is an abstract concept in quantum computing and is introduced to achieve fault tolerance for quantum computing. The logical qubit is built on the physical qubit and is protected through encoding and error correction and the like. The goal of the logical qubit is to achieve stable and scalable quantum computing, that is, to maintain the accuracy of the computing result regardless of how many errors occur during the computation.

[0063] Optionally, a gate operation refers to a basic unit of operation on a qubit, and a gate operation sequence includes a series of gate operations that need to be executed in sequence to perform a quantum computing task. Optionally, the gate operation can be a single-qubit gate operation, a two-qubit gate operation, or a multi-qubit gate operation.

[0064] In the embodiments of the present application, the gate operation is a two-qubit gate operation, that is, each gate operation is applied to two logical qubits in a plurality of logical qubits. For example, a controlled-NOT (CNOT) gate, a SWAP gate, and the like.

[0065] In some embodiments, in the case where there is a quantum computing task, the computer device first parses the quantum computing task and generates a qubit topology structure corresponding to the quantum computing task through topology compilation. The qubit topology structure represents the connection relationship between the logical qubits. At the same time, the computer device generates a gate operation sequence corresponding to the quantum computing task according to the execution order of each gate operation involved in the quantum computing task. Further, the computer device sorts each logical qubit according to the qubit topology structure and the gate operation sequence, thereby obtaining a logical qubit sequence corresponding to the quantum computing task.

[0066] Optionally, the logical qubit sequence includes n logical qubits, where n is a positive integer. For example, the logical qubit sequence can be represented as [q1, q2, q3, …, qn]. n ]。

[0067] In a possible implementation, the quantum computing task includes a plurality of quantum computing sub-tasks, and the computer device determines quantum bit topological structures corresponding to the respective quantum computing sub-tasks, and obtains a general quantum bit topological structure capable of executing the quantum computing task by taking a union of the plurality of quantum bit topological structures.

[0068] Optionally, the gate operation sequence and the logical quantum bit are generally constructed in advance by a quantum computing platform through a quantum error correction code, and are stored in a preset storage space. When a quantum computing task needs to be executed, the computer device can directly extract the preset gate operation sequence and the logical quantum bit from the preset storage space.

[0069] In step 202, based on i candidate physical quantum bits corresponding to the first i logical quantum bits in the logical quantum bit sequence, a mappable physical quantum bit of the i+1 logical quantum bit in the physical hardware resource is determined.

[0070] Optionally, the physical hardware resource refers to a physical quantum chip, a quantum computer, or the like, and the physical hardware resource includes a large number of physical quantum bits.

[0071] Optionally, the physical quantum bit is a basic unit for storing and processing quantum information that actually exists in the physical hardware resource. For example, the physical quantum bit can be a Josephson junction in a superconducting circuit, an ion in an ion trap, or the like. The physical quantum bit has quantum superposition and quantum entanglement, and is an information carrier in quantum computing.

[0072] In some embodiments, in order to map the logical quantum bit to the physical quantum bit in the physical hardware resource, and to make the logical quantum bit and the physical quantum bit in a one-to-one mapping relationship, the computer device can determine the candidate physical quantum bit corresponding to each logical quantum bit in the logical quantum bit sequence in sequence according to the bit number of each logical quantum bit in the logical quantum bit sequence.

[0073] In a possible implementation, in a case where i candidate physical quantum bits corresponding to the first i logical quantum bits in the logical quantum bit sequence have been determined, the computer device can determine other physical quantum bits in the physical hardware resource except the i candidate physical quantum bits as mappable physical quantum bits corresponding to the i+1 logical quantum bit, i being a positive integer.

[0074] Optionally, the physical quantum bit can be represented as Q, and the physical hardware resource includes n physical quantum bits Q1-Qn. n In an illustrative quantum bit mapping combination, the logical quantum bit sequence is [q1, q2, q3, …… qn], and the physical hardware resource includes n physical quantum bits Q1-Qn. nFor example, in the case that the physical hardware resource includes 20 physical quantum bits, the first logical quantum bit corresponds to 20 quantum bit mapping manners, and in each quantum bit mapping manner of the first logical quantum bit, the second logical quantum bit corresponds to 19 quantum bit mapping manners, further, in each quantum bit mapping manner of the second logical quantum bit, the third logical quantum bit corresponds to 18 quantum bit mapping manners, and so on, and thus there are 20*19*18*...*2*1 quantum bit mapping combinations. n .

[0075] In step 203, based on the mapping evaluation result corresponding to the mappable physical quantum bit, the candidate physical quantum bit corresponding to the i+1th logical quantum bit is selected from the mappable physical quantum bits of the i+1th logical quantum bit, wherein the mapping evaluation result represents the degree of influence of the quantum bit mapping combination formed when the i+1th logical quantum bit is mapped to the mappable physical quantum bit on the execution of the gate operation sequence, and the degree of influence is related to the number of newly added gate operations required for the execution of the gate operation sequence.

[0076] In some embodiments, when the mappable physical quantum bit corresponding to each logical quantum bit in the sequence of logical quantum bits is determined in turn, each logical quantum bit corresponds to a plurality of possible quantum bit mapping combinations, so that the number of quantum bit mapping combinations increases exponentially in the process of layer-by-layer quantum bit mapping. In the case that there are a large number of physical quantum bits in the physical hardware resource, the number of quantum bit mapping combinations is even larger, resulting in high computational complexity for determining one quantum bit mapping combination from a plurality of quantum bit mapping combinations.

[0077] For example, in the case that the physical hardware resource includes 20 physical quantum bits, the first logical quantum bit corresponds to 20 quantum bit mapping manners, and in each quantum bit mapping manner of the first logical quantum bit, the second logical quantum bit corresponds to 19 quantum bit mapping manners, further, in each quantum bit mapping manner of the second logical quantum bit, the third logical quantum bit corresponds to 18 quantum bit mapping manners, and so on, and thus there are 20*19*18*...*2*1 quantum bit mapping combinations.

[0078] In the embodiments of the present application, in order to reduce the computational complexity in the quantum bit mapping process and reduce the consumption of computing resources, in the process of determining the physical quantum bit corresponding to the logical quantum bit layer by layer, the mapping evaluation result corresponding to each mappable physical quantum bit is calculated to screen the mappable physical quantum bits, so as to retain the mappable physical quantum bits with relatively optimal mapping evaluation results as the candidate physical quantum bits corresponding to the logical quantum bit at this layer, wherein the number of bits of the candidate physical quantum bits is significantly less than the number of bits of the mappable physical quantum bits.

[0079] Optionally, the mapping evaluation result represents an influence degree of a quantum bit mapping combination formed by mapping the i+1th logical quantum bit to the mappable physical quantum bit on the execution of the gate operation sequence. The influence degree is related to a number of newly added gate operations required by the execution of the gate operation sequence.

[0080] In a possible implementation, under the premise that a plurality of quantum bit mapping combinations corresponding to the first i logical quantum bits have been determined, the computer device can determine, according to i candidate physical quantum bits corresponding to the first i logical quantum bits in each quantum bit mapping combination, a next layer of the quantum bit mapping combination corresponding to the i+1th logical quantum bit, thereby updating the quantum bit mapping combination corresponding to each mappable physical quantum bit, and then the computer device calculates, for each quantum bit mapping combination corresponding to each mappable physical quantum bit, a mapping evaluation result, and determines, according to the mapping evaluation result, a mappable physical quantum bit corresponding to a relatively optimal quantum bit mapping combination as a candidate physical quantum bit corresponding to the i+1th logical quantum bit.

[0081] Optionally, the mapping evaluation result corresponding to each quantum bit mapping combination corresponding to the i+1th logical quantum bit can be represented by a specific numerical value. The larger the numerical value of the mapping evaluation result, the better the mapping evaluation result, and the better the influence of the quantum bit mapping combination formed by mapping the i+1th logical quantum bit to the mappable physical quantum bit on the execution of the gate operation sequence.

[0082] Optionally, after obtaining the mapping evaluation result of each quantum bit mapping combination corresponding to each mappable physical quantum bit by calculation, the computer device can determine, by comparing numerical values, a mappable physical quantum bit corresponding to at least one quantum bit mapping combination with a larger numerical value of the mapping evaluation result as a candidate physical quantum bit corresponding to the i+1th logical quantum bit according to the principle that the larger the numerical value, the better the mapping evaluation result.

[0083] For example, as shown in FIG. 3, in the case of a physical hardware resource including 20 physical quantum bits Q1-Q20, for a logical quantum bit sequence [q1, q2, q3, …, q20], first, the mappable physical quantum bits corresponding to the first logical quantum bit q1 are Q1-Q4, and after calculating the mapping evaluation result, three quantum bit mapping combinations of q1 corresponding to Q1, q1 corresponding to Q4, and q1 corresponding to Q20 can be screened out. 20 n 20 10 20 ​​​​19 physical qubits except Q1; under this quantum bit mapping combination in which q1 corresponds to Q4, the mappable physical qubit corresponding to the second logical qubit q2 is Q1-Q 20 19 physical qubits except Q4; under this quantum bit mapping combination in which q1 corresponds to Q 10 , the mappable physical qubit corresponding to the second logical qubit q2 is Q1-Q 20 19 physical qubits except Q 10 , that is, [q1, q2] corresponds to 57 quantum bit mapping combinations in total, so that the computer device can calculate mapping evaluation results corresponding to 57 quantum bit mapping combinations respectively, for example, the mapping evaluation results of three quantum bit mapping combinations [q1, q2] corresponds to [Q1, Q5], [q1, q2] corresponds to [Q1, Q9], and [q1, q2] corresponds to [Q 10 , Q8] are better than other mapping evaluation results, it can be determined that under this quantum bit mapping combination in which q1 corresponds to Q1, the candidate physical qubit corresponding to the second logical qubit q2 is Q5 and Q9; under this quantum bit mapping combination in which q1 corresponds to Q4, the second logical qubit q2 has no candidate physical qubit; under this quantum bit mapping combination in which q1 corresponds to Q 10 , the candidate physical qubit corresponding to the second logical qubit q2 is Q8.

[0084] Step 204, in the case of obtaining the mapping evaluation results corresponding to the mappable physical qubits of the nth logical qubit, determining the target mapping evaluation result from the mapping evaluation results, the target mapping evaluation result is better than other mapping evaluation results.

[0085] In some embodiments, after sequentially determining the candidate physical qubits corresponding to the first n-1 logical qubits in the sequence of logical qubits and obtaining a plurality of quantum bit mapping combinations, the computer device can determine the mappable physical qubits corresponding to the nth logical qubit under each quantum bit mapping combination, and calculate the mapping evaluation results corresponding to each mappable physical qubit respectively, so as to determine the optimal one from the plurality of mapping evaluation results as the target mapping evaluation result.

[0086] The target mapping evaluation result is better than other mapping evaluation results, and the target mapping evaluation result represents that when the nth logical qubit is mapped to the mappable physical qubit, the quantum bit mapping combination formed has the optimal influence on each gate operation in the sequence of gate operations.

[0087] Optionally, when the mapping evaluation results corresponding to each mappable physical qubit are represented by numerical values, the numerical value of the target mapping evaluation result is greater than the numerical values of other mapping evaluation results.

[0088] As shown in FIG. 3, in the quantum bit mapping combination in which q1 corresponds to Q1, the candidate physical quantum bits corresponding to the second logical quantum bit q2 are Q5 and Q9; in the quantum bit mapping combination in which q1 corresponds to Q1, the candidate physical quantum bits corresponding to the second logical quantum bit q2 are Q8. Thus, in the quantum bit mapping combination in which q1 corresponds to Q1 and q2 corresponds to Q5, the mappable physical quantum bits corresponding to the third logical quantum bit q3 are the 18 physical quantum bits in the quantum computer 100 except Q1 and Q5; in the quantum bit mapping combination in which q1 corresponds to Q1 and q2 corresponds to Q9, the mappable physical quantum bits corresponding to the third logical quantum bit q3 are the 18 physical quantum bits in the quantum computer 100 except Q1 and Q9; in the quantum bit mapping combination in which q1 corresponds to Q1 and q2 corresponds to Q8, the mappable physical quantum bits corresponding to the third logical quantum bit q3 are the 18 physical quantum bits in the quantum computer 100 except Q1 and Q8. 10 20 20 10 20 10 10 10

[0089] Step 205: mapping the n logical quantum bits to the n physical quantum bits in the physical hardware resource based on the quantum bit mapping combination corresponding to the target mapping evaluation result.

[0090] In some embodiments, after determining the target mapping evaluation result from the mapping evaluation results corresponding to the mappable physical quantum bits of the nth logical quantum bit, the computer device can map the n logical quantum bits to the n physical quantum bits in the physical hardware resource according to the quantum bit mapping combination corresponding to the target mapping evaluation result.

[0091] As shown in FIG. 3, after obtaining the target mapping evaluation result, the computer device can map the logical quantum bits q1, q2 and q3 to the physical quantum bits Q 10 , Q8 and Q7 in the physical hardware resource in sequence.

[0092] ​​​​​​​​To sum up, in the embodiment of the present application, after obtaining the logical qubits corresponding to the quantum computing task and the gate operation sequence, the logical qubits are not directly mapped to the physical qubits in the physical hardware resources. Instead, based on the logical qubit sequence, the mappable physical qubits of each logical qubit are determined from the first logical qubit, and the mapping evaluation results corresponding to each mappable physical qubit are calculated. Then, according to the mapping evaluation results, the corresponding candidate physical qubits are selected from the mappable physical qubits. Further, through the method of progressive screening, after determining the mapping evaluation results corresponding to the mappable physical qubits of the nth logical qubit, the optimal mapping evaluation result is selected as the target mapping evaluation result, and the logical qubits are mapped to the physical qubits in the physical hardware resources according to the quantum bit mapping combination corresponding to the target mapping evaluation result. Compared with the direct random quantum bit mapping method, the quantum bit mapping method provided in the embodiment of the present application can reduce the number of newly added gate operations in the gate operation execution process as much as possible, thereby improving the accuracy of quantum bit mapping and optimizing the mapping quality of quantum bits.

[0093] In some embodiments, considering that there is a one-to-one mapping relationship between the logical qubits and the physical qubits, when determining the mappable physical qubits corresponding to the i+1th logical qubit, the i candidate physical qubits corresponding to the first i logical qubits are taken into account. That is, if the order of determining the candidate physical qubits corresponding to each logical qubit is different, different quantum bit mapping combinations will be generated. Therefore, in order to improve the efficiency of determining the target mapping evaluation result, the computer device can first sort the logical qubits according to the bit importance of the logical qubits to obtain the logical qubit sequence.

[0094] Please refer to FIG. 4, which shows the flowchart of the process of obtaining the logical qubit sequence provided in an example embodiment of the present application. The embodiment takes the method used in the computer device as an example for illustration, and the method includes the following steps:

[0095] Step 401: Analyzing the quantum computing task to obtain the gate operation sequence and n logical qubits.

[0096] In a possible implementation, in the case of a quantum computing task, the computer device first analyzes the quantum computing task, determines the logical quantum circuit corresponding to the quantum computing task, obtains n logical qubits corresponding to the quantum computing task, and generates the gate operation sequence corresponding to the quantum computing task according to the execution order of each gate operation involved in the quantum computing task.

[0097] Illustratively, as shown in FIG. 5, a logical quantum circuit corresponding to a quantum computing task provided by an example embodiment of the present application is shown. The logical quantum circuit includes logical quantum bits q0, q1, q2, q3, q4, and gate operations g0, g1, g2, g3, g4.

[0098] At step 402, the gate operation associated with each logical quantum bit is determined, and the execution sequence number of each gate operation is determined.

[0099] In a possible implementation, considering that the earlier a gate operation is executed in a logical quantum circuit, the greater the impact on the mapping of quantum bits, therefore, in order to sort the logical quantum bits, the computer device needs to first determine the gate operation associated with each logical quantum bit according to the execution sequence of each gate operation in the logical quantum circuit and the two logical quantum bits corresponding to each gate operation, and then sequentially traverse each logical quantum bit.

[0100] Here, the gate operation associated with a logical quantum bit is the gate operation that applies to the logical quantum bit. For example, if the gate operation g1 is applied to the logical quantum bits q1 and q2, then the gate operation associated with the logical quantum bit q1 includes the gate operation g1.

[0101] Illustratively, as shown in FIG. 5, the gate operation g0 is applied to the logical quantum bits q0 and q2, the gate operation g1 is applied to the logical quantum bits q3 and q4, the gate operation g2 is applied to the logical quantum bits q0 and q1, the gate operation g3 is applied to the logical quantum bits q1 and q2, and the gate operation g4 is applied to the logical quantum bits q2 and q3, so that the gate operation associated with the logical quantum bit q0 is g0 and g2, the gate operation associated with the logical quantum bit q1 is g2 and g3, the gate operation associated with the logical quantum bit q2 is g0, g3, and g4, the gate operation associated with the logical quantum bit q3 is g1 and g4, and the gate operation associated with the logical quantum bit q4 is g1.

[0102] Optionally, the execution sequence number of each gate operation can be determined according to a gate dependency graph corresponding to the logical quantum circuit, where the gate dependency graph refers to a directed acyclic graph (DAG) used to represent the dependency relationship between each gate operation (quantum operation) in the quantum circuit, and the node of the gate dependency graph is a single gate operation in the quantum circuit, and the edge of the gate dependency graph represents the dependency relationship between two gate operations. Regarding the generation of the gate dependency graph corresponding to the logical quantum circuit, in a possible implementation, the computer device takes each gate operation as a node of the gate dependency graph, determines the directed edge between each node according to the execution sequence of each gate operation, and thus generates the gate dependency graph corresponding to the logical quantum circuit according to each node and the directed edge between the nodes.

[0103] Further, the computer device determines the execution sequence number of the node corresponding to the gate operation according to the dependency graph depth at which the node is located in the gate operation dependency graph, wherein the dependency graph depth at which the node is located refers to the length of the longest path from the source node (the node without an incoming edge) of the gate operation dependency graph to the node, that is, the layer number at which the node is located in the gate operation dependency graph. For example, if the node is located at the first layer of the gate operation dependency graph, the execution sequence number of the node corresponding to the gate operation is 0; if the node is located at the second layer of the gate operation dependency graph, the execution sequence number of the node corresponding to the gate operation is 1, and so on, thereby determining the execution sequence number of each gate operation.

[0104] Illustratively, as shown in FIG. 6, the computer device takes the gate operations g0, g1, g2, g3, and g4 as nodes, and determines the directed edges between the nodes according to the execution order of each gate operation, wherein the gate operations g0 and g1 are executed first, the gate operation g2 is executed after the gate operation g0, the gate operation g3 is executed after the gate operations g0 and g2, and the gate operation g4 is executed after the gate operations g1 and g3, thereby generating the gate operation dependency graph corresponding to the logical quantum circuit in FIG. 5. Further, according to the gate operation dependency graph, the gate operations g0 and g1 are source nodes, the longest path from the gate operation g0 to the gate operation g2 is 1, the longest path from the gate operation g0 to the gate operation g3 is 2, and the longest path from the gate operation g0 to the gate operation g4 is 3, so that the computer device can determine that the execution sequence number of the gate operations g0 and g1 is 0 (dep = 0), the execution sequence number of the gate operation g2 is 1 (dep = 1), the execution sequence number of the gate operation g3 is 2 (dep = 2), and the execution sequence number of the gate operation g4 is 3 (dep = 3).

[0105] In step 403, the bit importance of each logical quantum bit is determined based on the preset parameter and the execution sequence number of each gate operation associated with the logical quantum bit.

[0106] In a possible implementation, after determining the gate operation associated with each logical quantum bit and the execution sequence number of each gate operation, the computer device can calculate the operation importance of each gate operation on the logical quantum bit according to the execution sequence number of each gate operation associated with the logical quantum bit and the preset parameter, and then determine the bit importance of the logical quantum bit by summing up the operation importance corresponding to each gate operation associated with the logical quantum bit.

[0107] Optionally, the preset parameter is a parameter value set according to actual business needs, which is usually any value between 0 and 1. For example, the preset parameter a can take the value of 0.5.

[0108] Optionally, the operation importance of the gate operation represents a degree of influence of the gate operation on determining the bit importance of the logical quantum bit, and the higher the operation importance, the greater the influence of the gate operation on the bit importance.

[0109] Optionally, the operation importance of the gate operation can be represented as a parameter a with a preset parameter as the base and the execution sequence number of the gate operation as the exponent. dep(g) Thus, the bit importance of the logical quantum bit can be represented as wei(q) = å g∈gate[q] a dep(g) wherein wei(q) represents the bit importance of the logical quantum bit q, gate[q] represents a set of all gate operations associated with the logical quantum bit q, g represents a gate operation, dep(g) represents the execution sequence number of the gate operation, and a represents a preset parameter.

[0110] Illustratively, as shown in FIGS. 5 and 6, in the case of a = 0.5, for the logical quantum bit q0, the bit importance is wei(q0) = 0.5 0 + 0.5 1 = 1.5; for the logical quantum bit q1, the bit importance is wei(q1) = 0.5 1 + 0.5 2 = 0.75; for the logical quantum bit q2, the bit importance is wei(q2) = 0.5 0 + 0.5 2 + 0.5 3 = 1.375; for the logical quantum bit q3, the bit importance is wei(q3) = 0.5 0 + 0.5 3 = 1.125; for the logical quantum bit q4, the bit importance is wei(q4) = 0.5 0 = 1.

[0111] In step 404, the n logical quantum bits are sorted based on the bit importance, to obtain a logical quantum bit sequence.

[0112] In one possible implementation, after determining the bit importance of each logical quantum bit, the computer device can sort the n logical quantum bits in descending order according to the bit importance, to obtain a logical quantum bit sequence corresponding to the quantum computing task.

[0113] Illustratively, as shown in FIGS. 5 and 6, after calculating the bit importance of the logical quantum bits q0, q1, q2, q3, and q4, respectively, the logical quantum bit sequence [q0, q2, q3, q4, q1] can be obtained.

[0114] In the above embodiments, according to the logical quantum circuit corresponding to the quantum computing task, the gate operation associated with each logical quantum bit is determined, and the bit importance of the logical quantum bit is determined in combination with the execution sequence number of each gate operation, so as to generate a logical quantum bit sequence. The logical quantum bits in the logical quantum bit sequence are sorted in descending order of bit importance, which facilitates subsequent determination of the candidate physical quantum bit corresponding to each logical quantum bit based on the logical quantum bit sequence, and helps to improve the mapping quality of the quantum bits.

[0115] In some embodiments, after determining the logical quantum bit sequence corresponding to the quantum computing task, the computer device can sequentially traverse each logical quantum bit according to the bit sequence number of the logical quantum bit in the logical quantum bit sequence in a one-to-one mapping manner between the logical quantum bit and the physical quantum bit, so as to determine the candidate physical quantum bit corresponding to each logical quantum bit.

[0116] Optionally, for the first logical quantum bit in the logical quantum bit sequence, since the mapping relationship of other logical quantum bits has not been determined, the computer device can determine each physical quantum bit in the physical hardware resource as the mappable physical quantum bit corresponding to the first logical quantum bit. Then, by calculating the mapping evaluation result of each mappable physical quantum bit, the candidate physical quantum bit corresponding to the first logical quantum bit is selected from the mappable physical quantum bit.

[0117] Optionally, for the i+1th logical quantum bit in the logical quantum bit sequence, since the candidate physical quantum bit corresponding to the first i logical quantum bits has been determined, the computer device can only determine the remaining physical quantum bits in the physical hardware resource as the mappable physical quantum bit corresponding to the i+1th logical quantum bit, except for the i candidate physical quantum bits corresponding to the first i logical quantum bits.

[0118] Illustratively, there are physical hardware resources containing physical quantum bits Q1-Q 20 For the logical quantum bit sequence [q3, q2, q4, q0, q1, q5], first, the mappable physical quantum bits corresponding to the first logical quantum bit q3 are Q1-Q 20 After screening, it is determined that the candidate physical quantum bits corresponding to the first logical quantum bit q3 are Q6, Q7, Q 12 , Q 20 After that, for the second logical quantum bit q2, under the quantum bit mapping combination that q3 corresponds to Q6, the mappable physical quantum bits corresponding to the second logical quantum bit q2 are the 19 physical quantum bits except Q6 in Q1-Q 20 ; under the quantum bit mapping combination that q3 corresponds to Q 12In the quantum bit mapping combination, the second logical quantum bit q2 corresponds to the 19 physical quantum bits Q1 ~ Q19 except Q 20 In the quantum bit mapping combination, the second logical quantum bit q2 corresponds to the 19 physical quantum bits Q1 ~ Q19 except Q 12 In the quantum bit mapping combination, the second logical quantum bit q2 corresponds to the 19 physical quantum bits Q1 ~ Q19 except Q 20 In the quantum bit mapping combination, the second logical quantum bit q2 corresponds to the 19 physical quantum bits Q1 ~ Q19 except Q 20 In the quantum bit mapping combination, the second logical quantum bit q2 corresponds to the 19 physical quantum bits Q1 ~ Q19 except Q 20 In the quantum bit mapping combination, the second logical quantum bit q2 corresponds to the 19 physical quantum bits Q1 ~ Q19 except Q 20 and so on.

[0119] By traversing each logical quantum bit in sequence according to the bit sequence number of the logical quantum bit in the logical quantum bit sequence, the candidate physical quantum bits corresponding to each logical quantum bit can be determined, which can improve the efficiency and orderliness of determining the quantum bit mapping combination.

[0120] In order to improve the efficiency of quantum bit mapping and avoid calculating all quantum bit mapping combinations formed by logical quantum bits and physical quantum bits, for each logical quantum bit, the computer device needs to calculate the mapping evaluation results corresponding to each mappable physical quantum bit, and then screen the corresponding candidate physical quantum bit according to the mapping evaluation results. Illustratively, as shown in FIG. 7, the process can include the following steps:

[0121] Step 701, based on the i candidate physical quantum bits corresponding to the first i logical quantum bits and the mappable physical quantum bits of the i+1 logical quantum bit, determining the mapping evaluation results corresponding to each mappable physical quantum bit.

[0122] In some embodiments, after determining the i candidate physical quantum bits corresponding to the first i logical quantum bits and obtaining a plurality of quantum bit mapping combinations, the computer device needs to determine the mappable physical quantum bits of the i+1 logical quantum bit in each quantum bit mapping combination, and then determine the mapping evaluation results corresponding to each mappable physical quantum bit in combination with the i candidate physical quantum bits corresponding to the first i logical quantum bits and the mappable physical quantum bits of the i+1 logical quantum bit.

[0123] Exemplarily, as shown in FIG. 8, there are physical hardware resources including physical quantum bits Q0-Q5, and for a logical quantum bit sequence [q3, q2, q4, q0, q1, q5], firstly, the mappable physical quantum bits corresponding to the first logical quantum bit q3 are Q0-Q5, and after screening, it is determined that the candidate physical quantum bits corresponding to the first logical quantum bit q3 are Q1, Q3, and Q5, and for the second logical quantum bit q2, under the quantum bit mapping combination that q3 corresponds to Q1, the mappable physical quantum bits corresponding to the second logical quantum bit q2 are Q0, Q2, Q3, Q4, and Q5; under the quantum bit mapping combination that q3 corresponds to Q3, the mappable physical quantum bits corresponding to the second logical quantum bit q2 are Q0, Q1, Q2, Q4, and Q5; and under the quantum bit mapping combination that q3 corresponds to Q5, the mappable physical quantum bits corresponding to the second logical quantum bit q2 are Q0, Q1, Q2, Q3, and Q4. Further, the computer device needs to calculate the mapping evaluation results corresponding to fifteen quantum bit mapping combinations of Q1+Q0, Q1+Q2, Q1+Q3, Q1+Q4, Q1+Q5, Q3+Q0, Q3+Q1, Q3+Q2, Q3+Q4, Q3+Q5, Q5+Q0, Q5+Q1, Q5+Q2, Q5+Q3, and Q5+Q4, respectively.

[0124] Exemplarily, FIG. 9 shows a flowchart of a specific process of calculating the mapping evaluation result of each quantum bit mapping combination, which can include the following steps:

[0125] In step 7011, according to the quantum bit mapping combination formed when the i+1th logical quantum bit is mapped to the mappable physical quantum bit, the executable gate operation and the non-executable gate operation in the gate operation sequence are determined, wherein the executable gate operation does not need to add a new gate operation, and the non-executable gate operation needs to add a new gate operation.

[0126] In a possible implementation, the computer device firstly divides each gate operation in the gate operation sequence according to the quantum bit mapping combination formed when the i+1th logical quantum bit is mapped to the mappable physical quantum bit, and divides the gate operation into the executable gate operation and the non-executable gate operation.

[0127] The executable gate operation does not need to add a gate operation, and the non-executable gate operation needs to add a gate operation. Optionally, the executable gate operation refers to a gate operation with a bit distance of 1, and the non-executable gate operation refers to a gate operation with a bit distance greater than 1. The bit distance of the gate operation refers to the distance between the physical qubits involved in the gate operation. In the case that the two physical qubits involved in the gate operation are adjacent physical qubits, the bit distance of the gate operation is 1; in the case that there is at least one intermediate physical qubit between the two physical qubits involved in the gate operation, the bit distance of the gate operation is greater than 1.

[0128] Optionally, the computer device traverses the gate operations according to the execution order of each gate operation in the gate operation sequence based on the quantum bit mapping combination formed when the i+1th logical qubit is mapped to the mappable physical qubit, so as to determine the gate operation as an executable gate operation in the case that the bit distance of the gate operation is 1, and determine the gate operation and other gate operations executed after the gate operation as non-executable gate operations in the case that the bit distance of the gate operation is greater than 1.

[0129] Optionally, the gate operation can be represented as g=(q,q'), the process of mapping the logical qubit to the physical qubit can be represented as mapping π, and the bit distance between the candidate physical qubits corresponding to the gate operation can be represented as dist(g,π)=dist AG (π(q),π(q')) where π(q) represents mapping the logical qubit q to the physical qubit on the physical hardware resource AG, and dist AG (π(q),π(q')) represents the physical distance between the physical qubit corresponding to the logical qubit q and the physical qubit corresponding to the logical qubit q'.

[0130] In the case that the physical qubit corresponding to the logical qubit q is adjacent to the physical qubit corresponding to the logical qubit q', it is considered that the bit distance corresponding to the gate operation g=(q,q') is 1; in the case that the physical qubit corresponding to the logical qubit q is not adjacent to the physical qubit corresponding to the logical qubit q', it is considered that the bit distance corresponding to the gate operation g=(q,q') is greater than 1.

[0131] As shown in FIG. 10, the logical quantum circuit includes logical quantum bits q0, q1, q2, q3, gate operations g0, g1, g2, g3, g4, g5, and g6. The gate operation g0 corresponds to the logical quantum bits q0 and q2, the gate operation g1 corresponds to the logical quantum bits q2 and q3, the gate operation g2 corresponds to the logical quantum bits q0 and q3, the gate operation g3 corresponds to the logical quantum bits q0 and q2, the gate operation g4 corresponds to the logical quantum bits q2 and q3, the gate operation g5 corresponds to the logical quantum bits q0 and q3, and the gate operation g6 corresponds to the logical quantum bits q1 and q3.

[0132] As shown in FIG. 11, according to the execution order of the gate operations in the logical quantum circuit shown in FIG. 10, a gate operation dependency graph corresponding to the logical quantum circuit can be obtained.

[0133] As shown in FIG. 12, a quantum bit mapping combination corresponding to the logical quantum bits q0, q1, q2, and q3 is shown, in which the logical quantum bit q0 is mapped to the physical quantum bit Q0, the logical quantum bit q1 is mapped to the physical quantum bit Q1, the logical quantum bit q2 is mapped to the physical quantum bit Q2, and the logical quantum bit q3 is mapped to the physical quantum bit Q3.

[0134] Further, in combination with FIGS. 10-12, for the gate operation g0, the logical quantum bits q0 and q2 correspond to the physical quantum bits Q0 and Q2, respectively, and the physical quantum bits Q0 and Q2 are adjacent in the physical hardware resources, so the bit distance of the gate operation g0 is 1, and the gate operation g0 is an executable gate operation; for the gate operation g1, the logical quantum bits q2 and q3 correspond to the physical quantum bits Q2 and Q3, respectively, and the physical quantum bits Q2 and Q3 are adjacent in the physical hardware resources, so the bit distance of the gate operation g1 is 1, and the gate operation g1 is an executable gate operation; for the gate operation g2, the logical quantum bits q0 and q3 correspond to the physical quantum bits Q0 and Q3, respectively, and the distance between the physical quantum bits Q0 and Q3 in the physical hardware resources is 2, which is greater than 1, so the gate operation g2 is an inexecutable gate operation, and the gate operations g3, g4, g5, and g6 are executed after the gate operation g2, so the gate operations g3, g4, g5, and g6 are also inexecutable gate operations.

[0135] For the determination process of the bit distance of the inexecutable gate operation, in a possible implementation, in a case where candidate physical quantum bits exist for all the logical quantum bits corresponding to the inexecutable gate operation, the computer device can determine the distance between the two candidate physical quantum bits as the bit distance of the inexecutable gate operation; in a case where no candidate physical quantum bit exists for any of the logical quantum bits corresponding to the inexecutable gate operation, the computer device can determine the maximum distance between the physical quantum bits in the physical hardware resources as the bit distance of the inexecutable gate operation.

[0136] Among them, the maximum distance between physical qubits in physical hardware resources refers to the maximum physical distance between any two physical qubits in physical hardware resources.

[0137] Schematic illustration, referring to Figures 10-12, for the non-executable gate operation g2, logical qubits q0 and q3 correspond to physical qubits Q0 and Q3, respectively. The distance between physical qubits Q0 and Q3 in the physical hardware resources is 2. Therefore, the bit distance of the non-executable gate operation is 2. All logical qubits corresponding to the non-executable gate operations shown in Figure 10 have candidate physical qubits. If the logical quantum circuit also includes gate operation g7 corresponding to logical qubits q0 and q4, and logical qubit q4 does not have a corresponding candidate physical qubit, then for the non-executable gate operation g7, its bit distance is the maximum distance of 2 between physical qubits in the physical hardware resources.

[0138] By classifying gate operations according to the bit distance of each gate operation in the gate operation sequence, gate operations are divided into executable gate operations and non-executable gate operations. This helps to determine the number of first gate operations required to add new gate operations to the gate operation sequence for non-executable gate operations, thereby improving the efficiency of the simulated gate operation execution process. It also helps to calculate the first mapping estimator result and the second mapping estimator result for executable gate operations and non-executable gate operations respectively, thereby improving the computational efficiency of the mapping estimator result.

[0139] Step 7012: Determine the number of the first gate operations required to add gate operations to the gate operation sequence based on the qubit mapping combination.

[0140] In one possible implementation, for a qubit mapping combination formed when mapping the (i+1)th logical qubit to a mappable physical qubit, after determining the executable and non-executable gate operations, the computer device can simulate the gate operation execution process and add gate operations to the qubit mapping combination during the simulation execution process to transform the non-executable gate operations into executable gate operations, thereby counting the first gate operation number required to add gate operations based on the gate operation sequence executed based on the qubit mapping combination.

[0141] Optionally, the computer device can transform an inoperable gate operation into an executable gate operation by adding a SWAP gate to swap the mapping relationship between two logical qubits and physical qubits, thereby making the physical qubits corresponding to the two logical qubits to which the inoperable gate operation is applied adjacent.

[0142] As shown in FIGS. 10-12, for the gate operation g2, the logical qubits q0 and q3 correspond to the physical qubits Q0 and Q3 respectively, the distance between the physical qubits Q0 and Q3 in the physical hardware resource is 2, and the physical qubit Q3 is adjacent to the physical qubits Q1 and Q2 in the physical hardware resource. Therefore, the computer device can exchange the mapping relationship between the logical qubit q0 and the physical qubit Q0, and the logical qubit q2 and the physical qubit Q2 through the SWAP gate, so that the logical qubits q0 and q3 of the gate operation g2 correspond to the physical qubits Q2 and Q3 respectively, and the gate operation g2 is converted into an executable gate operation.

[0143] In step 7013, the first mapping evaluation sub-result is determined based on the second gate operation quantity of the executable gate operation and the total bit quantity of the mappable physical qubits in the physical hardware resource.

[0144] In a possible implementation, for the executable gate operation, the computer device can count the second gate operation quantity of the executable gate operation in the gate operation sequence, and then determine the first mapping evaluation sub-result according to the second gate operation quantity and the total bit quantity of the mappable physical qubits in the physical hardware resource.

[0145] Optionally, the computer device can obtain the first mapping evaluation sub-result according to the product of the second gate operation quantity and the total bit quantity of the mappable physical qubits in the physical hardware resource.

[0146] The first mapping evaluation sub-result can be expressed as cost1(π)=P×n×β, where P represents the second gate operation quantity of the executable gate operation, n represents the total bit quantity of the mappable physical qubits in the physical hardware resource, and β is an adjustable parameter value set according to actual business needs.

[0147] In step 7014, the second mapping evaluation sub-result is determined based on the total bit quantity, the bit distance of the unexecutable gate operation, and the hardware diameter of the physical hardware resource.

[0148] In a possible implementation, for the unexecutable gate operation, the computer device needs to determine the second mapping evaluation sub-result according to the bit distance of each unexecutable gate operation, the hardware diameter of the physical hardware resource, and the total bit quantity of the mappable physical qubits in the physical hardware resource.

[0149] Optionally, in order to facilitate the evaluation of each non-executable gate operation respectively, the computer device can first determine the non-executable gate operation associated with each logical qubit in the qubit mapping combination, thereby generating a non-executable gate operation sequence corresponding to each logical qubit. Further, for each non-executable gate operation, the computer device determines the gate operation evaluation result of the non-executable gate operation according to the gate operation sequence number of the non-executable gate operation in the non-executable gate operation sequence, the hardware diameter, and the bit distance of the non-executable gate operation.

[0150] Optionally, the computer device can determine the gate operation evaluation result of the non-executable gate operation according to the difference between the adjustable parameter related to the hardware diameter and the bit distance of the non-executable gate operation.

[0151] Optionally, the gate operation evaluation result represents the degree of influence of the non-executable gate operation on the sequence of gate operations. The gate operation evaluation result can be represented as α i ×(γ diam -dist(gate x [i],π)),wherein gate x represents the non-executable gate operation sequence composed of the non-executable gate operations associated with the logical qubit q x , i represents the gate operation sequence number of the non-executable gate operation in the non-executable gate operation sequence, dist(gate x [i],π) represents the bit distance of the non-executable gate operation, diam represents the hardware diameter of the physical hardware resource, γ diam is an adjustable parameter related to the hardware diameter, and α is an adjustable parameter value set according to actual business needs.

[0152] Further, the computer device sequentially adds and sums the gate operation evaluation results of each non-executable gate operation according to the bit sequence number of the logical qubit and the gate operation sequence number of the non-executable gate operation, to obtain a second mapping evaluation sub-result, according to the total bit quantity and the third gate operation quantity of the non-executable gate operation sequence.

[0153] Optionally, the second mapping evaluation sub-result can be represented as wherein len(gate x ) represents the third gate operation quantity of the non-executable gate operation included in the non-executable gate operation sequence, and n represents the total bit quantity.

[0154] It is considered that in the case where the third gate operation quantity is large enough, i.e., the value of i increases constantly, and α is valued between 0 and 1, so the value of α i also decreases exponentially, and the gate operation evaluation result α i ×(γ diam-dist(gate x As the value of α diam ×(γ 30 -dist(gate -8 [i], π)) becomes smaller and smaller, the weight of the second mapping estimation sub-result in the estimation result also becomes smaller and smaller, i.e., in the case of a large enough value of i, the influence of the gate operation estimation result on the second mapping estimation sub-result can be ignored. Therefore, in order to optimize the calculation process of the estimation result and reduce the consumption of computing resources, the computer device can increase an accumulation and summation condition for judging whether to continue to perform accumulation and summation on the gate operation estimation result in the process of accumulating and summing the gate operation estimation results of the respective non-executable gate operations.

[0155] In a possible implementation, the computer device accumulates and sums the gate operation estimation results of the respective non-executable gate operations according to the total number of bits and the third number of non-executable gate operations in the non-executable gate operation sequence, according to the bit serial number of the logical qubit and the gate operation serial number of the non-executable gate operation. Meanwhile, a truncation parameter is set, and the gate operation estimation results of the respective non-executable gate operations are compared with the truncation parameter. In the case where the gate operation estimation result of the non-executable gate operation is not less than the truncation parameter, it is indicated that the influence of the gate operation estimation result on the second mapping estimation sub-result cannot be ignored, and therefore the gate operation estimation result needs to be accumulated and summed. In the case where the gate operation estimation result of the non-executable gate operation is less than the truncation parameter, it is indicated that the influence of the gate operation estimation result on the second mapping estimation sub-result can be ignored, and therefore the accumulation and summation is stopped, and the second mapping estimation sub-result is obtained.

[0156] For example, in the case where α = 0.55, γ diam = 1, α 30 = 1.6e -8 , α 40 = 4e -11 are all very small values and can be ignored in the calculation process, the computer device can take the truncation parameter as 1e -6 , so that the computer device stops the accumulation and summation of the gate operation estimation result in the case where α i ×(γ diam -dist(gate x [i], π)) is less than 1e -6 .

[0157] By setting the truncation parameter, comparing the gate operation estimation results of the non-executable gate operations with the truncation parameter, and stopping the accumulation and summation in the case where the gate operation estimation result of the non-executable gate operation is less than the truncation parameter, the consumption of computing resources can be reduced, and the calculation process of the second mapping estimation sub-result can be optimized.

[0158] In another possible implementation, the computer device accumulates and sums the gate operation evaluation result of each non-executable gate operation according to the bit sequence number of the logical qubit and the gate operation sequence number of the non-executable gate operation based on the total bit quantity and the third gate operation quantity of the non-executable gate operation in the gate operation sequence. Meanwhile, the computer device sets a sequence number threshold, compares the gate operation sequence number of each non-executable gate operation with the sequence number threshold, and in the case that the gate operation sequence number of the non-executable gate operation is not greater than the sequence number threshold, it is indicated that the influence of the gate operation evaluation result of the non-executable gate operation on the second mapping evaluation sub-result cannot be ignored, and therefore the gate operation evaluation result needs to be accumulated and summed; in the case that the gate operation sequence number of the non-executable gate operation is greater than the sequence number threshold, it is indicated that the influence of the gate operation evaluation result of the non-executable gate operation on the second mapping evaluation sub-result can be ignored, and therefore the accumulation and summation is stopped, and the second mapping evaluation sub-result is obtained.

[0159] For example, in the case that α = 0.55, γ = 1, α = 1.6e-4, and α = 4e-4, all are very small values and can be ignored in the operation process, and therefore the computer device can take the sequence number threshold as 40, and in the case that the gate operation sequence number of the non-executable gate operation is greater than 40, the computer device stops the accumulation and summation of the gate operation evaluation result. diam 30 -8 40 -11 For example, in the case that α = 0.55, γ = 1, α = 1.6e-4, and α = 4e-4, all are very small values and can be ignored in the operation process, and therefore the computer device can take the sequence number threshold as 40, and in the case that the gate operation sequence number of the non-executable gate operation is greater than 40, the computer device stops the accumulation and summation of the gate operation evaluation result.

[0160] By setting the sequence number threshold, comparing the gate operation sequence number of the non-executable gate operation with the sequence number threshold, and stopping the accumulation and summation in the case that the gate operation sequence number of the non-executable gate operation is greater than the sequence number threshold, the calculation resource consumption can be reduced and the calculation process of the second mapping evaluation sub-result can be optimized.

[0161] In step 7015, the computer device obtains the mapping evaluation result corresponding to the mappable physical qubit based on the first mapping evaluation sub-result, the second mapping evaluation sub-result, and the first gate operation quantity.

[0162] In a possible implementation, after obtaining the first mapping evaluation sub-result corresponding to the executable gate operation and the second mapping evaluation sub-result corresponding to the non-executable gate operation, the computer device can obtain the mapping evaluation result corresponding to the mappable physical qubit based on the first mapping evaluation sub-result, the second mapping evaluation sub-result, and the first gate operation quantity.

[0163] Optionally, the computer device can first sum the first mapping evaluation sub-result and the second mapping evaluation sub-result, and divide the sum of the first mapping evaluation sub-result and the second mapping evaluation sub-result by the first gate operation quantity of the newly added gate operation in the gate operation sequence, so as to obtain the mapping evaluation result corresponding to the mappable physical qubit. ​​​​

[0164] Optionally, the mapping evaluation result is represented as wherein m represents the first number of additional gate operations required for performing the sequence of gate operations based on the quantum bit mapping combination.

[0165] In the process of determining the mapping evaluation result corresponding to the mappable physical quantum bit, each gate operation in the sequence of gate operations is first divided into executable gate operations and non-executable gate operations, and the first number of additional gate operations required for performing the sequence of gate operations is determined according to the non-executable gate operations. Meanwhile, the first mapping evaluation sub-result and the second mapping evaluation sub-result are calculated for the executable gate operations and the non-executable gate operations respectively, and then the mapping evaluation result corresponding to the mappable physical quantum bit is determined, thereby improving the calculation efficiency and accuracy of the mapping evaluation result.

[0166] Step 702: filtering out a first number of candidate mapping evaluation results from the mapping evaluation results, the candidate mapping evaluation results being better than other mapping evaluation results.

[0167] In some embodiments, after determining the mapping evaluation result corresponding to the quantum bit mapping combination generated by each mappable physical quantum bit of the i+1th logical quantum bit, in order to reduce the calculation complexity in the quantum bit mapping process and reduce the consumption of calculation resources, the computer device can filter out candidate physical quantum bits from the mappable physical quantum bits of the i+1th logical quantum bit. The computer device can compare each mapping evaluation result to filter out a first number of candidate mapping evaluation results from the mapping evaluation results, wherein the candidate mapping evaluation results are better than other mapping evaluation results.

[0168] Optionally, the first number can be a pre-set fixed value or a value dynamically adjusted based on the calculation complexity, and the embodiments of the present application do not limit this.

[0169] In a possible implementation, the computer device can take each candidate physical quantum bit corresponding to the i th logical quantum bit as a group, and filter out candidate mapping evaluation results from the mapping evaluation results corresponding to the plurality of mappable physical quantum bits of the i+1th logical quantum bit in each group.

[0170] For example, as shown in FIG. 13, taking a logical qubit sequence [q0, q1, q2, …] and physical hardware resources including physical qubits Q0, Q1, Q2, Q3, Q4, Q5 as an example, for the mappable physical qubits corresponding to the logical qubit q0, the physical qubits are Q0, Q1, Q2, Q3, Q4, Q5, and after mapping evaluation, the candidate physical qubits Q1 and Q5 are obtained. Thus, the computer device determines the mappable physical qubits corresponding to the logical qubit q1 based on the candidate physical qubits Q1 and Q5 corresponding to the logical qubit q0, and obtains the mapping evaluation results of each mappable physical qubit. Then, taking the candidate physical qubits Q1 and Q5 corresponding to the logical qubit q0 as two branches, the computer device continues to screen two candidate physical qubits in each group, and the number of candidate physical qubits screened in the third layer is 2x2x2, and the number of candidate physical qubits screened in the n th layer is 2 n .

[0171] Obviously, in the above screening manner, the number of candidate physical qubits screened in each layer is increasing, which leads to an increase in the complexity of the algorithm to the factorial level.

[0172] Therefore, in order to reduce the number of candidate physical qubits corresponding to each logical qubit while ensuring the mapping optimization quality and controlling the complexity of the algorithm, in a possible implementation, the computer device can directly screen a first number of candidate mapping evaluation results from the qubit mapping combinations generated by each mappable physical qubit of the (i+1) th logical qubit in a global screening manner.

[0173] For example, as shown in FIG. 14, taking a logical qubit sequence [q0, q1, q2, …] and physical hardware resources including physical qubits Q0, Q1, Q2, Q3, Q4, Q5 as an example, for the mappable physical qubits corresponding to the logical qubit q0, the physical qubits are Q0, Q1, Q2, Q3, Q4, Q5, and after mapping evaluation, the candidate physical qubits Q1 and Q5 are obtained. Thus, the computer device determines the mappable physical qubits corresponding to the logical qubit q1 based on the candidate physical qubits Q1 and Q5 corresponding to the logical qubit q0, and obtains the mapping evaluation results of each mappable physical qubit. Then, taking the candidate physical qubits Q1 and Q5 corresponding to the logical qubit q0 as two branches, the computer device continues to screen two candidate physical qubits in each group, and the number of candidate physical qubits screened in the third layer is 2x2x2, and the number of candidate physical qubits screened in the n th layer is 2

[0174] It can be seen that the global screening manner can keep the bit number of the candidate physical quantum bits corresponding to each layer of logical quantum bits as the first number, thereby realizing the control of the algorithm complexity.

[0175] Optionally, in order to more evenly consider the mapping evaluation results of different mappable physical quantum bits, the computer device can also group the mapping evaluation results corresponding to the mappable physical quantum bits, and screen the candidate mapping evaluation results in a partition screening manner. In a possible implementation, the computer device first sorts the mapping evaluation results corresponding to the mappable physical quantum bits according to the bit sequence numbers of the candidate physical quantum bits corresponding to the i th logical quantum bit and the bit sequence numbers of the mappable physical quantum bits of the i+1 th logical quantum bit, sorts the mapping evaluation results corresponding to the mappable physical quantum bits according to the sorting result and the first grouping number, and then groups the mapping evaluation results corresponding to the mappable physical quantum bits, and further screens the second number of candidate mapping evaluation results from each group of mapping evaluation results, wherein the candidate mapping evaluation results are better than other mapping evaluation results in the same group.

[0176] As shown in FIG. 15, for example, taking the logical quantum bit sequence as [q0, q1, q2, …] and the physical hardware resources including physical quantum bits Q0, Q1, Q2, Q3, Q4, Q5 as an example, the mappable physical quantum bits corresponding to the logical quantum bit q0 are Q0, Q1, Q2, Q3, Q4, Q5, so that the computer device divides them into two groups and screens one candidate mapping evaluation result in each group, thereby obtaining the candidate physical quantum bits Q1 and Q5 corresponding to the logical quantum bit q0. Then, the computer device determines the mappable physical quantum bits corresponding to the logical quantum bit q1 based on the candidate physical quantum bits Q1 and Q5 corresponding to the logical quantum bit q0, and obtains ten quantum bit mapping combinations Q1+Q0, Q1+Q2, Q1+Q3, Q1+Q4, Q1+Q5, Q5+Q0, Q5+Q1, Q5+Q2, Q5+Q3, Q5+Q4, so that the computer device continues to screen one candidate mapping evaluation result from each of the two groups of mapping evaluation results in a partition screening manner, and obtains two quantum bit mapping combinations Q1+Q2 and Q5+Q1, that is, the number of candidate physical quantum bits of the second layer of screening is 2×1, and the number of candidate physical quantum bits of each three layers of screening is 2×1, and the number of candidate physical quantum bits of the n th layer of screening is also 2×1.

[0177] It can be seen that the partition screening manner can keep the bit number of the candidate physical quantum bits corresponding to each layer of logical quantum bits as the first grouping number×the second number, thereby realizing the control of the algorithm complexity.

[0178] Optionally, the computer device can also screen the candidate mapping evaluation results by combining the above two screening manners. In a possible implementation, the computer device first screens out a third number of first candidate mapping evaluation results from the mapping evaluation results according to the global screening manner, and the first candidate mapping evaluation results are better than other mapping evaluation results. Meanwhile, the mapping evaluation results corresponding to the mappable physical qubits are sorted according to the bit sequence number of the candidate physical qubit corresponding to the i th logical qubit and the bit sequence number of the mappable physical qubit of the i + 1 th logical qubit, and the mapping evaluation results corresponding to the mappable physical qubits are grouped according to the sorting result and the second grouping number, and then a fourth number of second candidate mapping evaluation results are screened out from each group of mapping evaluation results according to the partition screening manner, and the second candidate mapping evaluation results are better than other mapping evaluation results in the same group except the first candidate mapping evaluation results.

[0179] As shown in FIG. 16, for example, taking the logical qubit sequence as [q0, q1, q2, …], and the physical hardware resources including physical qubits Q0, Q1, Q2, Q3, Q4, Q5, for the mappable physical qubits corresponding to the logical qubit q0, Q0, Q1, Q2, Q3, Q4, Q5, the computer device first screens out one candidate physical qubit Q2 from the six qubit mapping combinations according to the global screening manner, and then screens out candidate physical qubits Q1 and Q5 from each group according to the partition screening manner, and then the computer device determines the global screening and partition screening manners based on the candidate physical qubits Q1, Q2 and Q5 corresponding to the logical qubit q0, and screens out one candidate mapping evaluation result corresponding to the qubit mapping combination Q1+Q2 from the 15 mappable physical qubits corresponding to the logical qubit q1 in the global range, and simultaneously screens out one candidate mapping evaluation result corresponding to the qubit mapping combination Q2+Q1 and one candidate mapping evaluation result corresponding to the qubit mapping combination Q5+Q1 from the two groups, and so on. The number of candidate physical qubits of each three layers of screening is 1+2x1, and the number of candidate physical qubits of the n th layer of screening is also 1+2x1.

[0180] It can be seen that the screening manner combining global and partition can keep the bit number of the candidate physical qubit corresponding to each layer of logical qubit as the third number+the second grouping numberxthe fourth number, thereby realizing the control of the algorithm complexity.

[0181] In step 703, the mappable physical qubit corresponding to the candidate mapping evaluation result is determined as the candidate physical qubit corresponding to the i + 1 th logical qubit.

[0182] In a possible implementation, the computer device can determine the mappable physical qubits corresponding to each candidate mapping evaluation result as the candidate physical qubits corresponding to the i+1th logical qubit, so as to obtain a plurality of qubit mapping combinations corresponding to the first i+1 logical qubits in the logical qubit sequence.

[0183] Further, for each qubit mapping combination, the computer device can continue to determine the mappable physical qubits of the i+2th logical qubit in the physical hardware resource according to the i+1 candidate physical qubits corresponding to the first i+1 logical qubits, so as to continue to repeat the above steps until the mappable physical qubits of the nth logical qubit in the physical hardware resource are determined, and the qubit mapping combination corresponding to the target mapping evaluation result is determined by evaluating and screening the qubit mapping combinations corresponding to each mappable physical qubit respectively.

[0184] In the above embodiment, in the process of screening the candidate physical qubits corresponding to the i+1th logical qubit, the bit number of the candidate physical qubits corresponding to each layer of logical qubits is effectively controlled by using the two screening methods of global screening and partition screening, the algorithm complexity is reduced, and the efficiency of performing qubit mapping in a large-scale physical quantum chip is improved.

[0185] Further, in the process of screening the physical qubits, the mappable physical qubits corresponding to the relatively optimal mapping evaluation result are screened out as the candidate physical qubits corresponding to the i+1th logical qubit by evaluating the qubit mapping combinations corresponding to each mappable physical qubit, so as to improve the screening quality of the candidate physical qubits.

[0186] In addition, in the process of calculating the mapping evaluation result, in the case of a large number of gate operations, in order to avoid the calculation complexity increasing infinitely with the increase of the number of gate operations, by setting the truncation parameter or the sequence number threshold, the accumulation calculation is stopped in the case that the influence of the gate operation evaluation result on the overall mapping evaluation result is negligible, so as to effectively reduce the calculation complexity and reduce the consumption of calculation resources.

[0187] Please refer to FIG. 17, which shows the structure block diagram of the qubit mapping device provided by an example embodiment of the present application, which includes:

[0188] The acquisition module 1701 is configured to acquire a logical qubit sequence and a gate operation sequence corresponding to a quantum computing task, wherein the logical qubit sequence includes n logical qubits, and n is a positive integer.

[0189] The bit determining module 1702 is configured to determine, based on i candidate physical qubits corresponding to the first i logical qubits in the sequence of logical qubits, a mappable physical qubit of an (i+1)th logical qubit in the physical hardware resource, where i is a positive integer;

[0190] The bit screening module 1703 is configured to screen, based on a mapping evaluation result corresponding to the mappable physical qubit, the candidate physical qubit corresponding to the (i+1)th logical qubit from the mappable physical qubit of the (i+1)th logical qubit, where the mapping evaluation result represents a degree of advantage or disadvantage of a quantum bit mapping combination formed by mapping the (i+1)th logical qubit to the mappable physical qubit on execution of the sequence of gate operations, and the degree of advantage or disadvantage is related to a number of newly added gate operations required for execution of the sequence of gate operations.

[0191] The result determining module 1704 is configured to determine, in a case where the mapping evaluation result corresponding to the mappable physical qubit of the nth logical qubit is obtained, a target mapping evaluation result from the mapping evaluation results, where the target mapping evaluation result is better than other mapping evaluation results.

[0192] The bit mapping module 1705 is configured to map the n logical qubits to n physical qubits in the physical hardware resource based on the quantum bit mapping combination corresponding to the target mapping evaluation result.

[0193] Optionally, the bit screening module 1703 includes:

[0194] The result determining unit is configured to determine, based on the i candidate physical qubits corresponding to the first i logical qubits and the mappable physical qubit of the (i+1)th logical qubit, the mapping evaluation result corresponding to each mappable physical qubit.

[0195] The result screening unit is configured to screen, from the mapping evaluation results, a first number of candidate mapping evaluation results, where the candidate mapping evaluation results are better than other mapping evaluation results.

[0196] The bit determining unit is configured to determine, as the candidate physical qubit corresponding to the (i+1)th logical qubit, the mappable physical qubit corresponding to the candidate mapping evaluation result.

[0197] Optionally, the result screening unit is configured to:

[0198] sort the mapping estimation results corresponding to the mappable physical qubits based on the bit sequence number of the candidate physical qubit corresponding to the i th logical qubit and the bit sequence number of the mappable physical qubit of the i + 1 th logical qubit;

[0199] group the mapping estimation results corresponding to the mappable physical qubits based on the sorting result and the first grouping number;

[0200] select a second number of candidate mapping estimation results from each group of mapping estimation results, the candidate mapping estimation results being superior to other mapping estimation results in the same group.

[0201] Optionally, the result screening unit is further configured to:

[0202] select a third number of first candidate mapping estimation results from the mapping estimation results, the first candidate mapping estimation results being superior to other mapping estimation results;

[0203] sort the mapping estimation results corresponding to the mappable physical qubits based on the bit sequence number of the candidate physical qubit corresponding to the i th logical qubit and the bit sequence number of the mappable physical qubit of the i + 1 th logical qubit;

[0204] group the mapping estimation results corresponding to the mappable physical qubits based on the sorting result and the second grouping number;

[0205] select a fourth number of second candidate mapping estimation results from each group of mapping estimation results, the second candidate mapping estimation results being superior to other mapping estimation results in the same group except the first candidate mapping estimation results.

[0206] Optionally, the result determination unit is configured to:

[0207] determine executable gate operations and unexecutable gate operations in the gate operation sequence according to the quantum bit mapping combination formed when the i + 1 th logical qubit is mapped to the mappable physical qubit, wherein the executable gate operations do not require the addition of the gate operation, and the unexecutable gate operations require the addition of the gate operation;

[0208] determine a first gate operation number of the gate operation required to be added based on the quantum bit mapping combination for executing the gate operation sequence;

[0209] determine a first mapping estimation sub-result based on a second gate operation number of the executable gate operation and a total bit number of the mappable physical qubits in the physical hardware resource;

[0210] determine a second mapping evaluation sub-result based on the total bit quantity, the bit distance of the non-executable gate operation, and a hardware diameter of the physical hardware resource;

[0211] obtain the mapping evaluation result corresponding to the mappable physical qubit pair based on the first mapping evaluation sub-result, the second mapping evaluation sub-result, and the first gate operation quantity.

[0212] Optionally, the result determination unit is further configured to:

[0213] generate a non-executable gate operation sequence corresponding to each logical qubit based on the non-executable gate operation associated with each logical qubit in the quantum bit mapping combination;

[0214] determine a gate operation evaluation result of the non-executable gate operation based on the gate operation sequence number of the non-executable gate operation in the non-executable gate operation sequence, the hardware diameter, and the bit distance of the non-executable gate operation, the gate operation evaluation result representing a degree of influence of the non-executable gate operation on the gate operation sequence;

[0215] add and sum the gate operation evaluation result of each non-executable gate operation according to the bit sequence number of the logical qubit and the gate operation sequence number of the non-executable gate operation based on the total bit quantity and a third gate operation quantity of the non-executable gate operation in the non-executable gate operation sequence, to obtain the second mapping evaluation sub-result.

[0216] Optionally, the result determination unit is configured to:

[0217] add and sum the gate operation evaluation result of each non-executable gate operation according to the bit sequence number of the logical qubit and the gate operation sequence number of the non-executable gate operation based on the total bit quantity and the third gate operation quantity of the non-executable gate operation in the non-executable gate operation sequence;

[0218] stop the addition and summation when the gate operation evaluation result of the non-executable gate operation is less than a truncation parameter, to obtain the second mapping evaluation sub-result.

[0219] Optionally, the result determination unit is configured to:

[0220] add and sum the gate operation evaluation result of each non-executable gate operation according to the bit sequence number of the logical qubit and the gate operation sequence number of the non-executable gate operation based on the total bit quantity and the third gate operation quantity of the non-executable gate operation in the non-executable gate operation sequence;

[0221] In a case where the gate operation sequence number of the non-executable gate operation is greater than a sequence number threshold, accumulation summation is stopped, and the second mapping estimation sub-result is obtained.

[0222] Optionally, the result determination unit is configured to:

[0223] According to the quantum bit mapping combination formed when the i+1th logical quantum bit is mapped to the mappable physical quantum bit, each gate operation is sequentially traversed according to an execution order of the gate operation in the gate operation sequence.

[0224] In a case where the bit distance of the gate operation is 1, the gate operation is determined as the executable gate operation.

[0225] In a case where the bit distance of the gate operation is greater than 1, the gate operation and other gate operations executed after the gate operation are determined as the non-executable gate operation.

[0226] Optionally, the apparatus further includes:

[0227] The first bit distance determination module is configured to, in a case where the candidate physical quantum bit exists between the logical quantum bits corresponding to the non-executable gate operation, determine a distance between the candidate physical quantum bits as the bit distance of the non-executable gate operation.

[0228] The second bit distance determination module is configured to, in a case where the candidate physical quantum bit does not exist between the logical quantum bits corresponding to the non-executable gate operation, determine a maximum distance between the physical quantum bits in the physical hardware resource as the bit distance of the non-executable gate operation.

[0229] Optionally, the acquisition module 1701 is configured to:

[0230] The quantum computing task is parsed to obtain the gate operation sequence and the n logical quantum bits.

[0231] Each logical quantum bit is associated with the gate operation, and the execution sequence number of each gate operation is determined.

[0232] Based on a preset parameter and the execution sequence number of each gate operation associated with the logical quantum bit, a bit importance of each logical quantum bit is determined.

[0233] Based on the bit importance, the n logical quantum bits are sorted to obtain the logical quantum bit sequence.

[0234] Optionally, the bit determination module 1702 is configured to:

[0235] For a first logical qubit in the sequence of logical qubits, each physical qubit in the physical hardware resources is determined as the mappable physical qubit corresponding to the first logical qubit;

[0236] For an i+1th logical qubit in the sequence of logical qubits, the remaining physical qubits in the physical hardware resources, except for the i candidate physical qubits corresponding to the first i logical qubits, are determined as the mappable physical qubits corresponding to the i+1th logical qubit.

[0237] In summary, in the embodiments of the present application, after obtaining the logical qubits corresponding to the quantum computing task and the gate operation sequence, the logical qubits are not directly mapped to the physical qubits in the physical hardware resources. Instead, based on the sequence of logical qubits, the mappable physical qubits of each logical qubit are determined starting from the first logical qubit, and the mapping evaluation results corresponding to each mappable physical qubit are calculated, and the candidate physical qubits are selected from the mappable physical qubits according to the mapping evaluation results. Then, through the method of progressive selection, after determining the mapping evaluation results corresponding to the mappable physical qubits of the nth logical qubit, the optimal mapping evaluation result is selected as the target mapping evaluation result, and the logical qubits are mapped to the physical qubits in the physical hardware resources according to the quantum qubit mapping combination corresponding to the target mapping evaluation result. Compared with the direct random qubit mapping method, the qubit mapping method provided in the embodiments of the present application can reduce the number of newly added gate operations in the gate operation execution process as much as possible, thereby improving the accuracy of qubit mapping and optimizing the mapping quality of qubits.

[0238] It should be noted that the apparatus provided in the above embodiments is only used as an example for the division of the above functional modules. In actual applications, the above functions can be completed by different functional modules according to needs, i.e., the internal structure of the apparatus is divided into different functional modules to complete all or part of the above described functions. In addition, the apparatus and method embodiments provided in the above embodiments belong to the same concept, and the implementation process is detailed in the method embodiments, which will not be described here.

[0239] It should be noted that, before and during the acquisition of the relevant user data, the application can display a prompt interface, a pop-up window or output voice prompt information, which is used to prompt the user that the relevant data of the user is currently being collected, so that the application only starts to perform the relevant steps of acquiring the relevant data of the user after obtaining the confirmation operation of the user to the prompt interface or the pop-up window, otherwise (i.e. without obtaining the confirmation operation of the user to the prompt interface or the pop-up window), ending the relevant steps of acquiring the relevant data of the user, that is, not acquiring the relevant data of the user. In other words, the information (including but not limited to user device information, user personal information, and user corresponding operation data), data (including but not limited to data for analysis, stored data, and displayed data) and signals involved in the application are authorized by the user or authorized by all parties, and the collection, use and processing of the relevant data need to comply with the relevant laws, regulations and standards of the country and region.

[0240] Please refer to FIG. 18, which shows a structural schematic diagram of a computer device provided by an exemplary embodiment of the application. Specifically, the computer device 1800 includes a central processing unit (CPU) 1801, a system memory 1804 including a random access memory 1802 and a read-only memory 1803, and a system bus 1805 connecting the system memory 1804 and the central processing unit 1801. The computer device 1800 can also include a basic input / output system (I / O system) 1806 to help transfer information between various devices in the computer, and a mass storage device 1807 for storing an operating system 1813, application programs 1814 and other program modules 1815.

[0241] In some embodiments, the basic input / output system 1806 includes a display 1808 for displaying information and an input device 1809 such as a mouse, keyboard, etc. for user input information. The display 1808 and the input device 1809 are both connected to the central processing unit 1801 through the input / output controller 1810 connected to the system bus 1805. The basic input / output system 1806 can also include an input / output controller 1810 for receiving and processing input from a keyboard, mouse, or electronic stylus, and other devices. Similarly, the input / output controller 1810 also provides output to the display screen, printer or other types of output devices.

[0242] The mass storage device 1807 is connected to the central processing unit 1801 through a mass storage controller (not shown) connected to the system bus 1805. The mass storage device 1807 and its associated computer readable media provide nonvolatile storage for the computer device 1800, that is, storage of information

[0243] Without loss of generality, the computer readable media can include computer storage media and communication media. Computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. Computer storage media includes Random Access Memory (RAM), Read Only Memory (ROM), flash memory or other solid state memory technology, Compact Disc Read Only Memory (CD-ROM), Digital Versatile Disc (DVD), or other optical storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices. It should be understood by those skilled in the art that computer storage media does not limit to the above-mentioned several types. The system memory 1804 and the mass storage device 1807 mentioned above can be collectively referred to as memory.

[0244] The memory stores one or more programs configured to be executed by the one or more central processing units 1801, and the one or more programs contain instructions for implementing the above-mentioned method. The central processing unit 1801 executes the one or more programs to implement the qubit mapping method provided by each method embodiment.

[0245] According to various embodiments of the present application, the computer device 1800 can also be connected to a remote computer operating on a network, such as the Internet, through a network connection. That is, the computer device 1800 can be connected to the network 1811 through the network interface unit 1812 connected to the system bus 1805, or in other words, the network interface unit 1812 can be used to connect to other types of networks or remote computer systems (not shown).

[0246] The embodiments of the present application also provide a computer readable storage medium, which stores at least one instruction loaded and executed by a processor to implement the qubit mapping method described in the above embodiments.

[0247] Optionally, the computer readable storage medium can include ROM, RAM, solid state disk (SSD, Solid State Drives) or optical disk, etc. Wherein, the RAM can include resistance random access memory (ReRAM, Resistance Random Access Memory) and dynamic random access memory (DRAM, Dynamic Random Access Memory).

[0248] The embodiment of the present application provides a computer program product, which comprises at least one instruction stored in a computer readable storage medium. The processor of the computer device reads the at least one instruction from the computer readable storage medium, and the processor executes the at least one instruction, so that the computer device executes the quantum bit mapping method described in the above embodiment.

[0249] Those skilled in the art can understand that all or part of the steps of the above-mentioned embodiments can be completed by hardware, or by program instructing relevant hardware to complete, and the program can be stored in a computer readable storage medium. The storage medium mentioned above can be a read-only memory, a magnetic disk or an optical disk.

[0250] The above is only optional embodiments of the present application, and is not used to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A quantum bit mapping method, the method being performed by a computer device, the method comprising: obtaining a logical quantum bit sequence corresponding to a quantum computing task and a gate operation sequence, the logical quantum bit sequence comprising n logical quantum bits, n being a positive integer; determining, based on i candidate physical quantum bits corresponding to the first i logical quantum bits in the logical quantum bit sequence, a mappable physical quantum bit in a physical hardware resource for an (i+1) th logical quantum bit, i being a positive integer; selecting, based on a mapping evaluation result corresponding to the mappable physical quantum bit, the candidate physical quantum bit corresponding to the (i+1) th logical quantum bit from the mappable physical quantum bit of the (i+1) th logical quantum bit, wherein the mapping evaluation result represents a degree of influence of a quantum bit mapping combination formed by mapping the (i+1) th logical quantum bit to the mappable physical quantum bit on execution of the gate operation sequence, and the degree of influence is related to a number of newly added gate operations required for execution of the gate operation sequence; determining a target mapping evaluation result from the mapping evaluation results of the mappable physical quantum bit of the n th logical quantum bit, the target mapping evaluation result being better than other mapping evaluation results; and mapping the n logical quantum bits to n physical quantum bits in the physical hardware resource based on a quantum bit mapping combination corresponding to the target mapping evaluation result. The selecting, based on a mapping evaluation result corresponding to the mappable physical quantum bit, the candidate physical quantum bit corresponding to the (i+1) th logical quantum bit from the mappable physical quantum bit of the (i+1) th logical quantum bit, comprises: determining the mapping evaluation result corresponding to each mappable physical quantum bit based on the i candidate physical quantum bits corresponding to the first i logical quantum bits and the mappable physical quantum bit of the (i+1) th logical quantum bit; selecting a first number of candidate mapping evaluation results from the mapping evaluation results, the candidate mapping evaluation results being better than other mapping evaluation results; and determining the mappable physical quantum bit corresponding to the candidate mapping evaluation result as the candidate physical quantum bit corresponding to the (i+1) th logical quantum bit. The selecting a first number of candidate mapping evaluation results from the mapping evaluation results comprises: sorting the mapping evaluation results corresponding to the mappable physical quantum bits based on bit sequence numbers of the candidate physical quantum bits corresponding to the i th logical quantum bit and the bit sequence numbers of the mappable physical quantum bits of the (i+1) th logical quantum bit; grouping the mapping evaluation results corresponding to the mappable physical quantum bits based on a sorting result and a first grouping number; and selecting a second number of the candidate mapping evaluation results from each group of mapping evaluation results, the candidate mapping evaluation results being better than other mapping evaluation results in the same group. ​ ​ ​ 2. The method of claim 1, wherein, ​ ​ ​ ​ 3. The method of claim 2, wherein, ​ ​ ​ ​ 4. The method of claim 2, wherein, The screening of the first quantity of candidate mapping evaluation results from the mapping evaluation results further includes: Screening a third quantity of first candidate mapping evaluation results from the mapping evaluation results, the first candidate mapping evaluation results being better than other mapping evaluation results; sequencing the mapping evaluation results corresponding to the mappable physical qubits based on the bit sequence number of the candidate physical qubits corresponding to the i-th logical qubit and the bit sequence number of the mappable physical qubits of the i+1-th logical qubit; grouping the mapping evaluation results corresponding to the mappable physical qubits based on the sequencing result and the second grouping quantity; screening a fourth quantity of second candidate mapping evaluation results from each group of mapping evaluation results, the second candidate mapping evaluation results being better than other mapping evaluation results in the same group except the first candidate mapping evaluation results.

5. The method according to any one of claims 2 to 4, wherein, The determining of the mapping evaluation results corresponding to each mappable physical qubit based on the i candidate physical qubits corresponding to the first i logical qubits and the mappable physical qubits of the i+1-th logical qubit includes: determining executable gate operations and non-executable gate operations in the gate operation sequence according to the quantum bit mapping combination formed when the i+1-th logical qubit is mapped to the mappable physical qubits, wherein the executable gate operations do not require new gate operations, and the non-executable gate operations require new gate operations; determining a first gate operation quantity of the new gate operations required for executing the gate operation sequence based on the quantum bit mapping combination; determining a first mapping evaluation sub-result based on a second gate operation quantity of the executable gate operations and a total bit quantity of the mappable physical qubits in the physical hardware resources; determining a second mapping evaluation sub-result based on the total bit quantity, a bit distance of the non-executable gate operations, and a hardware diameter of the physical hardware resources; obtaining the mapping evaluation result corresponding to the mappable physical qubit based on the first mapping evaluation sub-result, the second mapping evaluation sub-result, and the first gate operation quantity.

6. The method of claim 5, wherein, The determining of the second mapping evaluation sub-result based on the total bit quantity, the bit distance of the non-executable gate operations, and the hardware diameter of the physical hardware resources includes: generating a non-executable gate operation sequence corresponding to each logical qubit based on the non-executable gate operations associated with each logical qubit in the quantum bit mapping combination; determining a gate operation evaluation result of the non-executable gate operations based on a gate operation sequence number of the non-executable gate operations in the non-executable gate operation sequence, the hardware diameter, and the bit distance of the non-executable gate operations, the gate operation evaluation result representing a degree of influence of the non-executable gate operations on the gate operation sequence. According to the total bit quantity and the third gate operation quantity of the non-executable gate operation in the non-executable gate operation sequence, the gate operation evaluation result of each non-executable gate operation is accumulated and summed according to the bit serial number of the logical quantum bit and the gate operation serial number of the non-executable gate operation, to obtain the second mapping evaluation sub-result.

7. The method of claim 6, wherein, The step of accumulating and summing the gate operation evaluation result of each non-executable gate operation according to the total bit quantity and the third gate operation quantity of the non-executable gate operation in the non-executable gate operation sequence, and according to the bit serial number of the logical quantum bit and the gate operation serial number of the non-executable gate operation, to obtain the second mapping evaluation sub-result, comprises: According to the total bit quantity and the third gate operation quantity of the non-executable gate operation in the non-executable gate operation sequence, the gate operation evaluation result of each non-executable gate operation is accumulated and summed according to the bit serial number of the logical quantum bit and the gate operation serial number of the non-executable gate operation; In the case that the gate operation evaluation result of the non-executable gate operation is less than a truncation parameter, the accumulation and summation is stopped, and the second mapping evaluation sub-result is obtained.

8. The method of claim 6, wherein, The step of accumulating and summing the gate operation evaluation result of each non-executable gate operation according to the total bit quantity and the third gate operation quantity of the non-executable gate operation in the non-executable gate operation sequence, and according to the bit serial number of the logical quantum bit and the gate operation serial number of the non-executable gate operation, to obtain the second mapping evaluation sub-result, comprises: According to the total bit quantity and the third gate operation quantity of the non-executable gate operation in the non-executable gate operation sequence, the gate operation evaluation result of each non-executable gate operation is accumulated and summed according to the bit serial number of the logical quantum bit and the gate operation serial number of the non-executable gate operation; In the case that the gate operation serial number of the non-executable gate operation is greater than a serial number threshold, the accumulation and summation is stopped, and the second mapping evaluation sub-result is obtained.

9. The method of claim 5, wherein, The step of determining the executable gate operation and the non-executable gate operation in the gate operation sequence according to the quantum bit mapping combination formed when the i+1th logical quantum bit is mapped to the mappable physical quantum bit, comprises: According to the quantum bit mapping combination formed when the i+1th logical quantum bit is mapped to the mappable physical quantum bit, each gate operation is traversed in the execution order of the gate operation in the gate operation sequence; In the case that the bit distance of the gate operation is 1, the gate operation is determined as the executable gate operation; In the case that the bit distance of the gate operation is greater than 1, the gate operation and other gate operations executed after the gate operation are determined as the non-executable gate operation.

10. The method of claim 9, wherein, The method further comprises: In the case that the candidate physical quantum bit exists between the logical quantum bits corresponding to the non-executable gate operation, the distance between the candidate physical quantum bits is determined as the bit distance of the non-executable gate operation; In a case where the candidate physical quantum bit does not exist in the logical quantum bit corresponding to the unexecutable gate operation, a maximum distance between the physical quantum bits in the physical hardware resource is determined as the bit distance of the unexecutable gate operation.

11. The method of any one of claims 1 to 10, wherein, The obtaining the sequence of logical quantum bits and the sequence of gate operations corresponding to the quantum computing task comprises: parsing the quantum computing task to obtain the sequence of gate operations and the n logical quantum bits; determining the gate operation associated with each logical quantum bit and the execution sequence number of each gate operation; determining the bit importance of each logical quantum bit based on a preset parameter and the execution sequence number of each gate operation associated with the logical quantum bit; sequencing the n logical quantum bits based on the bit importance to obtain the sequence of logical quantum bits.

12. The method of any one of claims 1 to 11, wherein, The determining the mappable physical quantum bit of the i+1th logical quantum bit in the physical hardware resource based on the i candidate physical quantum bits corresponding to the first i logical quantum bits in the sequence of logical quantum bits comprises: for the first logical quantum bit in the sequence of logical quantum bits, determining each physical quantum bit in the physical hardware resource as the mappable physical quantum bit corresponding to the first logical quantum bit; for the i+1th logical quantum bit in the sequence of logical quantum bits, determining the remaining physical quantum bits in the physical hardware resource other than the i candidate physical quantum bits corresponding to the first i logical quantum bits as the mappable physical quantum bits corresponding to the i+1th logical quantum bit.

13. A quantum bit mapping device, the device comprising: an obtaining module configured to obtain a sequence of logical quantum bits and a sequence of gate operations corresponding to a quantum computing task, the sequence of logical quantum bits comprising n logical quantum bits, n being a positive integer; a bit determining module configured to determine a mappable physical quantum bit of an i+1th logical quantum bit in a physical hardware resource based on i candidate physical quantum bits corresponding to the first i logical quantum bits in the sequence of logical quantum bits, i being a positive integer; a bit screening module configured to screen, from the mappable physical quantum bits of the i+1th logical quantum bit, the candidate physical quantum bit corresponding to the i+1th logical quantum bit based on a mapping evaluation result corresponding to the mappable physical quantum bit, wherein the mapping evaluation result represents a degree of influence of a quantum bit mapping combination formed by mapping the i+1th logical quantum bit to the mappable physical quantum bit on the execution of the sequence of gate operations, and the degree of influence is related to a number of newly added gate operations required for executing the sequence of gate operations; a result determining module configured to determine a target mapping evaluation result from the mapping evaluation results in a case where the mapping evaluation result corresponding to the mappable physical quantum bit of the nth logical quantum bit is obtained, the target mapping evaluation result being better than other mapping evaluation results. A bit mapping module is configured to map the n logical qubits to n physical qubits in the physical hardware resources based on the target mapping estimation result corresponding to the combination of the quantum bit mapping.

14. A computer device, comprising a processor and a memory; the memory stores at least one instruction for being executed by the processor to implement the quantum bit mapping method according to any one of claims 1 to 12.

15. A computer readable storage medium, storing at least one instruction for being executed by a processor to implement the quantum bit mapping method according to any one of claims 1 to 12.

16. A computer program product, comprising at least one instruction stored in a computer readable storage medium; a processor of a computer device reads the at least one instruction from the computer readable storage medium, and executes the at least one instruction, so that the computer device implements the quantum bit mapping method according to any one of claims 1 to 12.

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