Display panel and display apparatus

Abstract

The present application relates to the technical field of display. Provided are a display panel and a display apparatus. In the display panel, at least one first connecting line and at least one third connecting line are connected to a power signal line, and at least one second connecting line and at least one fourth connecting line are connected to an initialization signal line. Thus, the present application not only reduces the resistance of a transmission path of power signals, so as to reduce the voltage drop of the power signals during transmission, but also reduces the resistance of a transmission path of initialization signals, so as to reduce the voltage drop of the initialization signals during transmission, thereby improving the uniformity of the power signals of all regions in a display region, and improving the uniformity of the initialization signals of all the regions, and further ensuring that sub-pixels in each region of the display panel emit light normally, and solving the problem of non-uniform display brightness of display panels.

Description

Display panel and display device

[0001] The present disclosure claims priority to the Chinese patent application No. 202410659334.3, filed on May 24, 2024, and entitled "Display panel and display device", the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0003] With the development of organic light emitting diode (OLED) display technology, high PPI (Pixels Per Inch) and full screen have become one of the mainstream development directions of OLED display panels. SUMMARY

[0004] The present application provides a display panel and a preparation method thereof, and a display device. The embodiments of the present application provide the following technical solutions.

[0005] In one aspect, a display panel is provided, which includes a display area and a peripheral area surrounding the display area. The display panel includes a power signal line disposed in the peripheral area, and a plurality of initialization signal lines, a plurality of first wires and a plurality of second wires disposed in the display area. Each initialization signal line extends along a first direction, and the plurality of initialization signal lines are arranged along a second direction intersecting the first direction. Each first wire extends along the first direction, and the plurality of first wires are arranged along the second direction. Each second wire extends along the second direction, and the plurality of second wires are arranged along the first direction. The plurality of first wires includes at least one first connection line and at least one second connection line, and the plurality of second wires includes at least one third connection line and at least one fourth connection line. The first connection line and the third connection line are connected to the power signal line, and the second connection line and the fourth connection line are connected to the initialization signal line.

[0006] In the above embodiments of the present application, at least one first connection line and at least one third connection line are connected to the power signal line, and at least one second connection line and at least one fourth connection line are connected to the initialization signal line. This not only reduces the resistance of the transmission path of the power signal and reduces the voltage drop of the power signal in the transmission process, but also reduces the resistance of the transmission path of the initialization signal and reduces the voltage drop of the initialization signal in the transmission process. The uniformity of the power signal in each region of the display area and the uniformity of the initialization signal in each region can be improved, thereby ensuring the normal light emission of the sub-pixels in each region of the display panel and improving the display mura (display panel brightness unevenness, causing various trace phenomena) of the display panel.

[0007] In some embodiments, the plurality of first wires includes a plurality of first connection lines and a plurality of second connection lines, each of the plurality of first connection lines includes at least one first connection line, each of the plurality of second connection lines includes at least one second connection line, and in the second direction, one of the first connection lines and one of the second connection lines are arranged alternately.

[0008] The plurality of second wires includes a plurality of third connection lines and a plurality of fourth connection lines, each of the plurality of third connection lines includes at least one third connection line, each of the plurality of fourth connection lines includes at least one fourth connection line, and in the first direction, one of the third connection lines and one of the fourth connection lines are arranged alternately.

[0009] Each of the first connection lines in each of the plurality of first connection lines is connected to at least one of the third connection lines in at least one of the plurality of third connection lines and the power signal line, and each of the second connection lines in each of the plurality of second connection lines is connected to at least one of the fourth connection lines in at least one of the plurality of fourth connection lines and the initialization signal line.

[0010] In some embodiments, each of the plurality of first connection lines includes one first connection line, each of the plurality of second connection lines includes one second connection line, each of the plurality of third connection lines includes one third connection line, and each of the plurality of fourth connection lines includes one fourth connection line.

[0011] In some embodiments, each of the plurality of first connection lines includes a plurality of adjacent first connection lines, each of the plurality of second connection lines includes a plurality of adjacent second connection lines, each of the plurality of third connection lines includes a plurality of adjacent third connection lines, and each of the plurality of fourth connection lines includes a plurality of adjacent fourth connection lines.

[0012] In some embodiments, the number of the first connection lines in each of the plurality of first connection lines is greater than the number of the second connection lines in each of the plurality of second connection lines, and / or the number of the third connection lines in each of the plurality of third connection lines is greater than the number of the fourth connection lines in each of the plurality of fourth connection lines.

[0013] In some embodiments, the display region includes a cutout region and a regular display region, the plurality of initialization signal lines includes a first initialization signal line passing through the cutout region and a second initialization signal line located in the regular display region, the plurality of first wires includes a plurality of second connection lines, the plurality of second wires includes a plurality of fourth connection lines, the plurality of second connection lines are connected to the plurality of fourth connection lines to form a mesh structure, the first initialization signal line is connected to one of the second connection lines in the mesh structure, and the second initialization signal line is connected to another one of the second connection lines in the mesh structure.

[0014] In some embodiments, the regular display area includes a display fan-out area, the plurality of first traces further include a plurality of first data connection lines, at least part of the first data connection lines are arranged in the display fan-out area. The plurality of second traces further include a plurality of second data connection lines, at least part of the second data connection lines are arranged in the display fan-out area, and one first data connection line is connected to one second data connection line.

[0015] In the first direction, at least one first data connection line is co-linear with and disconnected from one first connection line, and / or at least one first data connection line is co-linear with and disconnected from one second connection line. In the second direction, at least one second data connection line is co-linear with and disconnected from one third connection line, and / or at least one second data connection line is co-linear with and disconnected from one fourth connection line.

[0016] In some embodiments, the display panel includes a substrate, and a first conductive layer, a dielectric layer and a second conductive layer arranged in layers on the substrate. The first conductive layer includes an initialization signal line, a second connection line and a connection pattern, and the second conductive layer includes a fourth connection line. The initialization signal line is connected to the second connection line through the connection pattern, and the fourth connection line is connected to the connection pattern through the dielectric layer.

[0017] In some embodiments, the display panel further includes a plurality of sub-pixels arranged in an array in the display area, the plurality of sub-pixels include a plurality of rows and a plurality of columns, each row of sub-pixels extends along the first direction, and each column of sub-pixels extends along the second direction. Each sub-pixel includes a pixel driving circuit and a light emitting device connected thereto, the light emitting devices of the plurality of sub-pixels arranged in the array are electrically connected to the power signal line, and each initialization signal line is electrically connected to the pixel driving circuit of one row of sub-pixels.

[0018] In another aspect, a method for manufacturing a display panel is provided, the method including: forming a first conductive layer, a dielectric layer and a second conductive layer arranged in layers on a substrate, the first conductive layer including an initialization signal line, a first connection line and a second connection line, the initialization signal line, the first connection line and the second connection line all extend along a first direction, and the initialization signal line, the first connection line and the second connection line are arranged along a second direction intersecting the first direction. The second conductive layer includes a third connection line and a fourth connection line, the third connection line and the fourth connection line both extend along the second direction, and the third connection line and the fourth connection line are arranged along the first direction.

[0019] The third connection line is connected to the first connection line through the dielectric layer, the initialization signal line is connected to the second connection line, and the fourth connection line is connected to the second connection line through the dielectric layer.

[0020] The preparation method provided by the above embodiments of the present application forms a laminated first conductive layer, a dielectric layer and a second conductive layer on a substrate, the first conductive layer comprises an initialization signal line, a first connecting line and a second connecting line, and the second conductive layer comprises a third connecting line and a fourth connecting line.

[0021] The initialization signal line and the second connecting line are located in the same conductive layer, the initialization signal line can be directly connected with the second connecting line, and the fourth connecting line is connected with the second connecting line through the dielectric layer. By connecting the second connecting line and the fourth connecting line to the initialization signal line, the resistance of the transmission path of the initialization signal is reduced, the voltage drop of the initialization signal in the transmission process is reduced, the uniformity of the initialization signal of each area of the display panel is improved, the normal light emission of each area of the sub-pixel is ensured, and the display mura of the display panel is improved.

[0022] In some embodiments, a first mask plate is used, and the first connecting line and the second connecting line are formed synchronously in the process of forming the initialization signal line. A second mask plate is used, and the third connecting line and the fourth connecting line are formed synchronously.

[0023] In another aspect, a display device is provided, which comprises a controller and a display panel as in any of the above embodiments, and the controller is electrically connected with the display panel.

[0024] The display device has the same structure and beneficial technical effects as the display panel provided in some of the above embodiments, and will not be described here. BRIEF DESCRIPTION OF DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the present application, the following will briefly introduce the drawings needed to be used in some embodiments of the present application. Obviously, the drawings in the following description are only the drawings of some embodiments of the present application, and other drawings can also be obtained by those skilled in the art according to these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and not the actual size of the product involved in the embodiments of the present application, and the actual process of the method.

[0026] Fig. 1 is a structural diagram of a mobile phone provided by an embodiment of the present application;

[0027] Fig. 2 is a top view of a display panel provided by an embodiment of the present application;

[0028] Fig. 3 is a partial sectional view of a sub-pixel of the display panel in Fig. 2;

[0029] Fig. 4 is another top view of a display panel provided by an embodiment of the present application;

[0030] Fig. 5 is a partial enlarged view of the display panel in Fig. 4 at M;

[0031] FIG. 6 is another top view of the display panel according to an embodiment of the present application;

[0032] FIG. 7 is a partial enlarged view of the display panel at N in FIG. 6;

[0033] FIG. 8 is another top view of the display panel according to an embodiment of the present application;

[0034] FIG. 9 is another top view of the display panel according to an embodiment of the present application;

[0035] FIG. 10A and FIG. 10B are step diagrams for preparing the first conductive layer according to an embodiment of the present application;

[0036] FIG. 11 is a step diagram for preparing the medium layer according to an embodiment of the present application;

[0037] FIG. 12A and FIG. 12B are step diagrams for preparing the second conductive layer according to an embodiment of the present application;

[0038] FIG. 13A and FIG. 13B are step diagrams for preparing the third conductive layer according to an embodiment of the present application. DETAILED DESCRIPTION

[0039] In the related art, in the OLED display panel, the working environment of each region is different, which can cause the voltage signal for light emission to be different, and further cause the light emission brightness of different regions of the display panel to be uneven, and the display panel to have a display defect problem.

[0040] The technical solutions in some embodiments of the present application will be clearly and completely described below with reference to the drawings. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments provided by the present application, all other embodiments obtained by a person of ordinary skill in the art belong to the scope of protection of the present application.

[0041] Unless otherwise required by the context, throughout the specification and claims, the term "comprising" is to be interpreted as open, inclusive meaning, i.e. "including, but not limited to".

[0042] Hereinafter, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first" and "second" can explicitly or implicitly include one or more features. In the description of the embodiments of the present application, unless otherwise stated, the meaning of "a plurality of" is two or more.

[0043] In describing some embodiments, it will be understood that the terms "connected," "coupled," and "in communication with" are not limited to direct connection, coupling, or communication, but rather can be interpreted also to include indirect connection, coupling, or communication via another component or intervening components. For example, in describing some embodiments, the term "connected" can be used to indicate that two or more components are in direct physical or electrical contact with each other, or that they are in direct communication with each other.

[0044] Additionally, use of "based on" means "based, at least in part, on," and thereby admits alternatives.

[0045] Exemplary embodiments are described herein with reference to cross-sectional illustrations that are idealized examples. In the drawings, the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region illustrated as a rectangle will typically have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.

[0046] Embodiments of the present application provide a display device, which can be any device that displays images whether in motion (e.g., video) or stationary (e.g., a still image), and whether textual or pictorial. More particularly, it is contemplated that the embodiments can be implemented in or in association with a variety of electronic devices such as, but not limited to, mobile telephones, wireless devices, personal data assistants, handheld or portable computers, GPS receivers / navigators, cameras, MP4 players, camcorders, game consoles, wrist watches, clocks, calculators, television monitors, flat panel displays, computer monitors, auto displays (e.g., odometer display, etc.), cockpit controls and / or displays, camera view displays (e.g., display of a rear view camera in a vehicle), electronic photographs, electronic billboards or signs, projections, architectural structures, packaging, and aesthetic structures (e.g., display of images on a piece of jewelry) and the like.

[0047] Taking a mobile phone as an example of the display device, Fig. 1 is a structural diagram of a mobile phone according to an embodiment of the present application.

[0048] Referring to Fig. 1, the mobile phone 1 includes a display panel 10, which can be an organic light emitting diode (OLED) display panel.

[0049] The display panel 10 has a display side and a non-display side. The display device 100 further comprises a circuit board 11 disposed on the non-display side of the display panel 10, and a controller 12 disposed on the circuit board 11 and electrically connected with the display panel 10. The controller 12 is configured to output a timing control signal to control the display panel 10 to display an image.

[0050] FIG. 2 is a top view of the display panel according to an embodiment of the present application.

[0051] Referring to FIG. 2, the display panel 10 comprises a display area A1 and a peripheral area A2 surrounding the display area A1.

[0052] The display panel 10 comprises a plurality of sub-pixels 2 disposed on the display area A1, each of which comprises a pixel driving circuit 3. The plurality of sub-pixels 2 are arranged in an array, and the arrayed plurality of sub-pixels 2 comprise a plurality of rows and a plurality of columns. Each row of sub-pixels 2 extends along a first direction X, and each column of sub-pixels 2 extends along a second direction Y intersecting the first direction X.

[0053] For example, the second direction Y can be perpendicular to the first direction X.

[0054] FIG. 3 is a partial sectional view of a sub-pixel of the display panel in FIG. 2.

[0055] Referring to FIG. 3, the display panel 10 comprises a substrate 21, and the pixel driving circuit 3 is disposed on the substrate 21. The pixel driving circuit 3 comprises a plurality of thin film transistors T, each of which comprises an active layer T1, a gate G, a source S and a drain D. Each sub-pixel 2 further comprises a light emitting device L connected with the pixel driving circuit 3. The light emitting device L comprises an anode 22, a light emitting functional layer 23 and a cathode 24 stacked in sequence. The anode 22 is electrically connected with the drain D of a driving transistor T of the plurality of thin film transistors T, and the driving transistor T is configured to transmit a voltage signal to the anode 22. The cathode 24 also receives the voltage signal, and an electric field is generated between the anode 22 and the cathode 24. The light emitting functional layer 23 can emit light under the driving of the electric field.

[0056] In some examples, the plurality of thin film transistors T of the pixel driving circuit 3 can all be low temperature poly-silicon (LTPS) thin film transistors, and the material of the active layer T1 of the low temperature poly-silicon thin film transistor includes low temperature poly-silicon. In other examples, the plurality of thin film transistors T of the pixel driving circuit 3 can all be oxide thin film transistors, and the material of the active layer T1 of the oxide thin film transistor includes oxide semiconductor. In yet other examples, some of the plurality of thin film transistors T of the pixel driving circuit 3 can be low temperature poly-silicon thin film transistors, and the others can be oxide thin film transistors, which is also known as LTPO (LTPS+Oxide) technology.

[0057] Exemplarily, the display panel 10 further includes an anode transfer structure 25, and the anode 22 is electrically connected to the drain D of the thin film transistor T through the anode transfer structure 25.

[0058] Further, the display panel 10 further includes a passivation layer 26 and a first planarization layer 27, and the passivation layer 26 and the first planarization layer 27 are sequentially arranged on the thin film transistor T. The anode transfer structure 25 is electrically connected to the drain D of the thin film transistor T through the first planarization layer 27 and the passivation layer 26. Alternatively, it can be understood that the first planarization layer 27 and the passivation layer 26 have a via for the anode transfer structure 25 to be connected to the drain D of the thin film transistor T.

[0059] Further, the display panel 10 further includes a second planarization layer 28, and the second planarization layer 28 covers the anode transfer structure 25. The anode 22 is electrically connected to the anode transfer structure 25 through the second planarization layer 28. Alternatively, it can be understood that the second planarization layer 28 has a via for the anode 22 to be connected to the anode transfer structure 25.

[0060] Continuing to refer to FIG. 3, the display panel 10 further includes a pixel defining layer 29, and the pixel defining layer 29 includes a plurality of openings, each of which exposes at least part of the anode 22 of each sub-pixel 2. The light-emitting functional layer 23 of each sub-pixel 2 is arranged in one of the openings, and the light-emitting functional layer 23 is in electrical contact with the anode 22 through the opening of the pixel defining layer 29.

[0061] FIG. 4 is another top view of the display panel according to an embodiment of the present application; and FIG. 5 is a partial enlarged view of the display panel of FIG. 4 at M.

[0062] Referring to FIG. 4, the display area A1 includes a notch area A3 and a regular display area A4. The notch area A3 can be used to place a camera and an infrared sensing device. In addition, the area of the notch area A3 except the notch is also provided with a sub-pixel 2 to increase the number of pixels per inch (PPI) of the display panel 10, that is, to increase the pixel density of the display panel 10.

[0063] The regular display area A4 is an area of the display area A1 except the notch area A3, and the regular display area A4 is used to display a picture.

[0064] Referring to FIG. 4 and FIG. 5, the display panel 10 further includes a plurality of data signal lines 4 arranged in the display area A1. Each data signal line 4 extends along the second direction Y, and the plurality of data signal lines 4 are arranged along the first direction X.

[0065] In the display area A1, each data signal line 4 is electrically connected to the pixel driving circuit 3 of a column of sub-pixels 2. The data signal line 4 can transmit a data signal to the pixel driving circuit 3 of the column of sub-pixels 2, so as to drive the light emitting device L to emit light through the pixel driving circuit 3.

[0066] Generally, a fanout area is arranged in the peripheral area of the display panel close to the lower frame. The plurality of data signal lines are designed as fan-shaped oblique lines in the fanout area, so as to lead out the plurality of data signal lines. The arrangement of the fanout area makes the width of the lower frame larger, which is not conducive to the narrow frame of the display device.

[0067] Based on this, the embodiment of the present application provides a technology of fanout in active area (FIAA) of a data signal line.

[0068] Referring to FIG. 4 and FIG. 5, the regular display area A4 includes a display fanout area A5, and the display fanout area A5 is close to a corner area A6 of the display panel 10.

[0069] The display panel 10 further includes a plurality of first wires 51 and a plurality of second wires 52 arranged in the display area A1. Each first wire 51 extends along the first direction X, and the plurality of first wires 51 are arranged along the second direction Y. Each second wire 52 extends along the second direction Y, and the plurality of second wires 52 are arranged along the first direction X.

[0070] The plurality of first wires 51 includes a plurality of first data connection lines 53 and a plurality of first dummy connection lines 54, at least part of the first data connection lines 53 is arranged in the display fan-out area A5. In the first direction X, the first data connection lines 53 are collinear with the first dummy connection lines 54 (including the first connection lines 541 or the second connection lines 542 hereinafter), that is, the first data connection lines 53 and the first dummy connection lines 54 extend along the same straight line and are disconnected between them.

[0071] And the plurality of second wires 52 includes a plurality of second data connection lines 55 and a plurality of second dummy connection lines 56. At least part of the second data connection lines 55 is arranged in the display fan-out area A5, in the second direction Y, the second data connection lines 55 are collinear with the second dummy connection lines 56 (including the third connection lines 561 or the fourth connection lines 562 hereinafter), that is, the second data connection lines 55 and the second dummy connection lines 56 extend along the same straight line and are disconnected between them.

[0072] The data signal line 4 passing through the corner area A6 is connected to the first data connection line 53 in the display fan-out area A5, and the first data connection line 53 is connected to the second data connection line 55 in the display fan-out area A5. That is, the data signal line 4 passing through the corner area A6 is led out through the first data connection line 53 and the second data connection line 55, and the data signal line 4 is realized in the display area A1, which is beneficial to reduce the width of the peripheral area A2 of the display panel 10 close to the lower frame, improve the screen-to-body ratio of the display panel 10, realize the full-screen display, and is beneficial to realize the narrow frame of the display device 1.

[0073] Referring to FIGS. 4 and 5, the display panel 10 further includes a first power signal line 61 arranged in the peripheral area A2, and the light emitting device L of the plurality of sub-pixels 2 located in the display area A1 is electrically connected to the first power signal line 61.

[0074] For example, in combination with FIGS. 3 and 4, the cathode 24 of the light emitting device L can extend from the display area A1 to the peripheral area A2 and be electrically connected to the first power signal line 61 located in the peripheral area A2, and the first power signal line 61 can be used to transmit a first power voltage signal (for example, a VSS signal) to the cathode 24.

[0075] Referring to FIGS. 4 and 5, the plurality of first dummy connection lines 54 and the plurality of second dummy connection lines 56 are connected to form a first mesh structure, which is connected to the first power signal line 61, can reduce the resistance of the transmission path of the VSS signal, reduce the IR-drop of the VSS signal in the transmission process, thereby improve the uniformity of the VSS signal received by the cathode 24 in each region of the display area A1, and ensure the normal light emission of the light emitting device L.

[0076] Exemplarily, the black solid dots shown in FIG. 4 are positions where the first dummy connection line 54 is connected with the second dummy connection line 56, and positions where the first mesh structure accesses the first power signal line 61. The positions of the black solid dots can be adjusted according to the needs of the layout design, which is not limited in the present application.

[0077] For example, in the thin film transistor T of the pixel driving circuit 3, the conductive layer where the source S and the drain D are located can be referred to as a first source-drain conductive layer (SD1), and the conductive layer where the anode adapter structure 25 is located can be referred to as a second source-drain conductive layer (SD2). Referring to FIG. 5, the first source-drain conductive layer further includes the first dummy connection line 54, and the second source-drain conductive layer further includes the second dummy connection line 56. At the black solid dots in FIG. 4, the second dummy connection line 56 penetrates the dielectric layer (the first planarization layer 27 and the passivation layer 26) and is electrically connected with the first dummy connection line 54.

[0078] Further, the conductive layer where the anode 22 of the light emitting device L is located can be referred to as an anode layer, and the first power signal line 61 can be disposed in the anode layer. At the black solid dots in FIG. 4, the first power signal line 61 penetrates the dielectric layer (the second planarization layer 28, the first planarization layer 27 and the passivation layer 26) and is electrically connected with the first dummy connection line 54, and the first power signal line 61 penetrates the dielectric layer (the second planarization layer 28) and is electrically connected with the second dummy connection line 56.

[0079] It can be understood that the conductive layers where the first dummy connection line 54, the second dummy connection line 56 and the first power signal line 61 are located are only exemplary, which is not limited in the present application.

[0080] FIG. 6 is another top view of the display panel provided by the embodiment of the present application; and FIG. 7 is a partial enlarged view of the display panel in N in FIG. 6.

[0081] Referring to FIGS. 6 and 7, the display panel 10 further includes a plurality of second power signal lines 62 disposed in the display area A1, each of the second power signal lines 62 extends along the second direction Y, and the plurality of second power signal lines 62 are arranged along the first direction X.

[0082] It can be understood that, referring to FIG. 7, in the process of pattern design, in order to make the second power signal line 62 avoid other conductive patterns, the shape of the pattern of the second power signal line 62 can be designed as a non-straight line. Here, “each of the second power signal lines 62 extends along the second direction Y” means that the whole of the second power signal line 62 extends along the second direction Y, and the local part of the second power signal line 62 can extend deviating from the second direction Y.

[0083] In the display area A1, each second power supply signal line 62 is electrically connected with the pixel driving circuit 3 of a column of the sub-pixels 2, and the second power supply signal line 62 can transmit a second power supply voltage signal (for example, a VDD signal) to the pixel driving circuit 3 of a column of the sub-pixels 2, so as to drive the light emitting device L to emit light through the pixel driving circuit 3.

[0084] Referring to FIGS. 6 and 7, the display panel 10 further comprises an initialization signal bus 71, which is arranged in the peripheral area A2.

[0085] Exemplarily, the display panel 10 comprises two initialization signal buses 71. Along the first direction X, the two initialization signal buses 71 are arranged on opposite sides of the display area A1.

[0086] Referring to FIGS. 6 and 7, the display panel 10 further comprises a plurality of initialization signal lines 72 arranged in the display area A1, each of which extends along the first direction X, and the plurality of initialization signal lines 72 are arranged along the second direction Y.

[0087] It can be understood that, referring to FIG. 7, in the process of pattern design, in order to enable the initialization signal line 72 to avoid other conductive patterns, the shape of the pattern of the initialization signal line 72 can be designed as a non-straight line, and here, “each initialization signal line 72 extends along the first direction X” means that the whole of the initialization signal line 72 extends along the first direction X, and the local part of the initialization signal line 72 can extend deviating from the first direction X.

[0088] Each initialization signal line 72 can extend from the display area A1 to the peripheral area A2 on both sides and be electrically connected with the two initialization signal buses 71. Moreover, in the display area A1, each initialization signal line 72 is further electrically connected with the pixel driving circuit 3 of a row of the sub-pixels 2.

[0089] In the initial stage of driving the light emitting device L by the pixel driving circuit 3, the initialization signal line 72 can receive an anode initialization voltage signal (VAR signal) from the initialization signal bus 71 and transmit the anode initialization voltage signal to the pixel driving circuit 3. The pixel driving circuit 3 transmits the anode initialization voltage signal to the anode 22, so as to reset the potential of the anode 22, thereby ensuring that the light emitting device L can normally emit light in the subsequent light emitting stage.

[0090] Referring to FIGS. 6 and 7, the plurality of first dummy connection lines 54 comprises at least one first connection line 541 and at least one second connection line 542, the first connection line 541 and the second connection line 542 both extend along the first direction X and are arranged along the second direction Y.

[0091] The plurality of second dummy connection lines 56 include at least one third connection line 561 and at least one fourth connection line 562, the third connection line 561 and the fourth connection line 562 both extend along the second direction Y and are arranged along the first direction X.

[0092] The first connection line 541, the third connection line 561 and the first power signal line 61 are connected, i.e. the first connection line 541 and the third connection line 561 are connected to the first power signal line 61. Also, the second connection line 542, the fourth connection line 562 and the initialization signal line 72 are connected, i.e. the second connection line 542 and the fourth connection line 562 are connected to the initialization signal line 72.

[0093] Exemplarily, the black solid point in FIG. 6 is the position where the first connection line 541 and the third connection line 561 are connected, and the position where the first connection line 541 and the third connection line 561 are connected to the first power signal line 61. The white hollow point in FIG. 6 is the position where the second connection line 542 and the fourth connection line 562 are connected, and the position where the second connection line 542 and the fourth connection line 562 are connected to the initialization signal bus 71 and the initialization signal line 72. The positions of the black solid point and the white hollow point can be adjusted according to the needs of layout design, which is not limited in the present application.

[0094] For example, referring to FIG. 7, the first source-drain conductive layer (SD1) further includes the initialization signal line 72, the first connection line 541, the second connection line 542 and the connection pattern 8. The second source-drain conductive layer (SD2) further includes the third connection line 561 and the fourth connection line 562.

[0095] At the black solid point in FIG. 6, the third connection line 561 penetrates through the dielectric layer (the first planarization layer 27 and the passivation layer 26) to electrically connect with the first connection line 541. Also, at the white hollow point in FIG. 6, the initialization signal line 72 is connected with the second connection line 542 through the connection pattern 8, and the fourth connection line 562 is connected with the connection pattern 8 through the via hole H penetrating through the dielectric layer (the first planarization layer 27 and the passivation layer 26).

[0096] It can be understood that the conductive layer where the initialization signal line 72, the first connection line 541, the second connection line 542, the third connection line 561 and the fourth connection line 562 and the connection pattern 8 are located is only exemplary, which is not limited in the present application.

[0097] Compared with the case where all the first dummy connection lines 54 and the second dummy connection lines 56 in FIGS. 4 and 5 are connected to the first power signal line 61, in the case shown in FIGS. 6 and 7, part of the first dummy connection lines 54 (the first connection lines 541) and part of the second dummy connection lines 56 (the third connection lines 561) are connected to the first power signal line 61, and the other part of the first dummy connection lines 54 (the second connection lines 542) and the other part of the second dummy connection lines 56 (the fourth connection lines 562) are connected to the initialization signal line 72. In this way, the resistance of the transmission path of the VSS signal is reduced, the voltage drop of the VSS signal during transmission is reduced, the resistance of the transmission path of the VAR signal is reduced, the voltage drop of the VAR signal during transmission is reduced, the uniformity of the VSS signal received by the cathode 24 of each region in the display area A1 is improved, and the uniformity of the VAR signal received by the anode 22 of each region is improved, so that the light-emitting device L in each region can emit light normally, and the display mura problem of the display panel 10 is improved.

[0098] In some embodiments, referring to FIGS. 6 and 7, the plurality of initialization signal lines 72 include a first initialization signal line 721 passing through the hollowed-out area A3 and a second initialization signal line 722 located in the regular display area A4. The first initialization signal line 721 passing through the hollowed-out area A3 can mean that the first initialization signal line 721 overlaps the hollowed-out area A3 in the second direction Y.

[0099] The plurality of second connection lines 542 and the plurality of fourth connection lines 562 are connected to form a second mesh structure, the first initialization signal line 721 is connected to one of the second connection lines 542 in the second mesh structure, and the second initialization signal line 722 is connected to another of the second connection lines 542 in the second mesh structure.

[0100] It can be understood that the sub-pixel 2 in the hollowed-out area A3 is in a different environment from the sub-pixel 2 in the regular display area A4, and the VAR signal received by the anode 22 of the sub-pixel 2 will be different.

[0101] The first initialization signal line 721 passing through the cut-out area A3 is connected to one second connection line 542 in the second mesh structure, and the second initialization signal line 722 located in the regular display area A4 is connected to another second connection line 542 in the second mesh structure, so that the first initialization signal line 721 and the second initialization signal line 722 are connected to the same second mesh structure. Thus, the difference between the VAR signals transmitted by the first initialization signal line 721 and the second initialization signal line 722 can be reduced, thereby reducing the difference between the VAR signals received by the anode 22 of the cut-out area A3 and the anode 22 of the regular display area A4, improving the display brightness difference between the cut-out area A3 and the regular display area A4, and thus improving the display mura problem of the cut-out area A3.

[0102] In some embodiments, referring to FIGS. 6 and 7, the plurality of first dummy connection lines 54 includes a plurality of groups of first connection lines 541 and a plurality of groups of second connection lines 542. Each group of first connection lines 541 includes at least one first connection line 541, and each group of second connection lines 542 includes at least one second connection line 542. In the second direction Y, a group of first connection lines 541 and a group of second connection lines 542 are arranged alternately.

[0103] The plurality of second dummy connection lines 56 includes a plurality of groups of third connection lines 561 and a plurality of groups of fourth connection lines 562. Each group of third connection lines 561 includes at least one third connection line 561, and each group of fourth connection lines 562 includes at least one fourth connection line 562. In the first direction X, a group of third connection lines 561 and a group of fourth connection lines 562 are arranged alternately.

[0104] In each group of first connection lines 541, each first connection line 541 is connected to at least one third connection line 561 in at least one group of third connection lines 561 and the first power signal line 61. In each group of second connection lines 542, each second connection line 542 is connected to at least one fourth connection line 562 in at least one group of fourth connection lines 562 and one initialization signal line 72.

[0105] The above embodiments of the present application divide the plurality of first dummy connection lines 54 into a plurality of groups of first connection lines 541 and a plurality of groups of second connection lines 542, each group of first connection lines 541 includes at least one first connection line 541, and each group of second connection lines 542 includes at least one second connection line 542. The plurality of second dummy connection lines 56 is divided into a plurality of groups of third connection lines 561 and a plurality of groups of fourth connection lines 562, each group of third connection lines 561 includes at least one third connection line 561, and each group of fourth connection lines 562 includes at least one fourth connection line 562.

[0106] In the second direction Y, a group of the first connection lines 541 and a group of the second connection lines 542 are arranged alternately, so that the groups of the first connection lines 541 and the groups of the second connection lines 542 are evenly distributed in the display area A1. In the first direction X, a group of the third connection lines 561 and a group of the fourth connection lines 562 are arranged alternately, so that the groups of the third connection lines 561 and the groups of the fourth connection lines 562 are evenly distributed in the display area A1. Thus, the number of the groups of the first connection lines 541 and the third connection lines 561 connected to the first power signal line 61 is close to the number of the groups of the second connection lines 542 and the fourth connection lines 562 connected to the initialization signal line 72, so that the resistance of the transmission path of the VSS signal and the resistance of the transmission path of the VAR signal can be reduced more, thereby ensuring the normal light emission of the light emitting devices L in each region.

[0107] In some embodiments, referring to FIGS. 6 and 7, each group of the first connection lines 541 includes one first connection line 541, and each group of the second connection lines 542 includes one second connection line 542. That is, in the second direction Y, one first connection line 541 and one second connection line 542 are arranged alternately.

[0108] In addition, each group of the third connection lines 561 includes one third connection line 561, and each group of the fourth connection lines 562 includes one fourth connection line 562, that is, in the first direction X, one third connection line 561 and one fourth connection line 562 are arranged alternately.

[0109] In the second direction Y, a group of the first connection lines 541 and a group of the second connection lines 542 are arranged alternately, so that the groups of the first connection lines 541 and the groups of the second connection lines 542 are evenly distributed in the display area A1. In the first direction X, a group of the third connection lines 561 and a group of the fourth connection lines 562 are arranged alternately, so that the groups of the third connection lines 561 and the groups of the fourth connection lines 562 are evenly distributed in the display area A1.

[0110] Therefore, half of the first dummy connection lines 54 (the first connection lines 541) are connected to the first power signal line 61, and the other half of the first dummy connection lines 54 (the second connection lines 542) are connected to the initialization signal line 72. Half of the second dummy connection lines 56 (the third connection lines 561) are connected to the first power signal line 61, and the other half of the second dummy connection lines 56 (the fourth connection lines 562) are connected to the initialization signal line 72. Thus, the ratio of the number of the first connection lines 541 and the third connection lines 561 connected to the first power signal line 61 to the number of the second connection lines 542 and the fourth connection lines 562 connected to the initialization signal line 72 is 1:1, which can further reduce the resistance of the transmission path of the VSS signal and the resistance of the transmission path of the VAR signal, thereby ensuring the normal light emission of the light emitting devices L in each region.

[0111] FIG. 8 is another top view of the display panel according to an embodiment of the present application.

[0112] Referring to FIG. 8, each group of the first connection lines 541 includes a plurality of adjacent first connection lines 541, and each group of the second connection lines 542 includes a plurality of adjacent second connection lines 542. The plurality of first connection lines 541 and the plurality of second connection lines 542 are arranged alternately along the second direction Y.

[0113] In other words, the access VSS regions and the access VAR regions are divided alternately along the second direction Y. The plurality of first dummy connection lines 54 located in the access VSS regions serve as the plurality of first connection lines 541, so that the plurality of first connection lines 541 access the first power signal line 61 in the same region. The plurality of first dummy connection lines 54 located in the access VAR regions serve as the plurality of second connection lines 542, so that the plurality of second connection lines 542 access the initialization signal line 72 in the same region.

[0114] In some examples, along the second direction Y in FIG. 8, the access VAR regions, the access VSS regions, and the access VAR regions are divided in turn from top to bottom. In other examples, along the second direction Y, the access VSS regions, the access VAR regions, and the access VSS regions are divided in turn from top to bottom. In yet other examples, along the second direction Y, the access VAR regions, the access VSS regions, the access VAR regions, and the access VSS regions are divided in turn from top to bottom. The present application does not limit this.

[0115] Continuing to refer to FIG. 8, each group of the third connection lines 561 includes a plurality of adjacent third connection lines 561, and each group of the fourth connection lines 562 includes a plurality of adjacent fourth connection lines 562. The plurality of third connection lines 561 and the plurality of fourth connection lines 562 are arranged alternately along the first direction X.

[0116] In other words, the access VSS regions and the access VAR regions are divided alternately along the first direction X. The plurality of second dummy connection lines 56 located in the access VSS regions serve as the plurality of third connection lines 561, so that the plurality of third connection lines 561 access the first power signal line 61 in the same region. The plurality of second dummy connection lines 56 located in the access VAR regions serve as the plurality of fourth connection lines 562, so that the plurality of fourth connection lines 562 access the initialization signal line 72 in the same region.

[0117] In some examples, along the first direction X in FIG. 8, the access VAR region, the access VSS region and the access VAR region are sequentially divided from left to right. In other examples, along the first direction X, the access VSS region, the access VAR region and the access VSS region are sequentially divided from left to right. In yet other examples, along the first direction X, the access VAR region, the access VSS region, the access VAR region and the access VSS region are sequentially divided from left to right, and the present application does not limit this.

[0118] FIG. 9 is another top view of a display panel according to an embodiment of the present application.

[0119] Referring to FIG. 9, the number of the first connection lines 541 in each group of the first connection lines 541 is greater than the number of the second connection lines 542 in each group of the second connection lines 542. That is, the majority of the first dummy connection lines 54 (the first connection lines 541) are connected to the first power signal line 61, and the minority of the first dummy connection lines 54 (the second connection lines 542) are connected to the initialization signal line 72.

[0120] Alternatively, the number of the third connection lines 561 in each group of the third connection lines 561 is greater than the number of the fourth connection lines 562 in each group of the fourth connection lines 562. That is, the majority of the second dummy connection lines 56 (the third connection lines 561) are connected to the first power signal line 61, and the minority of the second dummy connection lines 56 (the fourth connection lines 562) are connected to the initialization signal line 72.

[0121] Alternatively, the number of the third connection lines 561 in each group of the third connection lines 561 is greater than the number of the fourth connection lines 562 in each group of the fourth connection lines 562. That is, the majority of the second dummy connection lines 56 (the third connection lines 561) are connected to the first power signal line 61, and the minority of the second dummy connection lines 56 (the fourth connection lines 562) are connected to the initialization signal line 72.

[0122] It can be understood that the sum of the number of the first connection lines 541 and the third connection lines 561 connected to the first power signal line 61 is greater than the sum of the number of the second connection lines 542 and the fourth connection lines 562 connected to the initialization signal line 72, so that the decrease of the resistance of the transmission path of the VSS signal is greater than the decrease of the resistance of the transmission path of the VAR signal. In turn, the resistance of the transmission path of the VSS signal is smaller, and the voltage drop generated in the transmission process of the VSS signal is smaller, and in the case that the influence of the VSS signal on the operation of the light emitting device L is greater than the influence of the VAR signal, the influence on the operation of the light emitting device L can be better reduced.

[0123] Exemplarily, referring to FIG. 9, each group of the first connection lines 541 includes two adjacent first connection lines 541, and each group of the second connection lines 542 includes one second connection line 542, i.e., along the second direction Y, two first connection lines 541 and one second connection line 542 are arranged alternately.

[0124] In addition, each group of the third connection lines 561 includes two adjacent third connection lines 561, and each group of the fourth connection lines includes one fourth connection line, i.e., along the first direction X, two third connection lines 561 and one fourth connection line 562 are arranged alternately.

[0125] Based on this, the number of the first connection lines 541 is twice the number of the second connection lines 542, and the number of the third connection lines 561 is twice the number of the fourth connection lines 562. The ratio of the sum of the number of the first connection lines 541 and the third connection lines 561 connected to the first power signal line 61 to the sum of the number of the second connection lines 542 and the fourth connection lines 562 connected to the initialization signal line 72 is 2:1.

[0126] In other examples, each group of the first connection lines 541 can include three adjacent first connection lines 541, and each group of the second connection lines 542 includes one second connection line 542. That is, along the second direction Y, three first connection lines 541 and one second connection line 542 are arranged alternately.

[0127] In addition, each group of the third connection lines 561 includes three adjacent third connection lines 561, and each group of the fourth connection lines includes one fourth connection line. That is, along the first direction X, three third connection lines 561 and one fourth connection line 562 are arranged alternately.

[0128] Based on this, the number of the first connection lines 541 is three times the number of the second connection lines 542, and the number of the third connection lines 561 is three times the number of the fourth connection lines 562. The ratio of the sum of the number of the first connection lines 541 and the third connection lines 561 connected to the first power signal line 61 to the sum of the number of the second connection lines 542 and the fourth connection lines 562 connected to the initialization signal line 72 is 3:1.

[0129] In yet other examples, each group of the first connection lines 541 can include four adjacent first connection lines 541, and each group of the second connection lines 542 includes one second connection line 542. That is, along the second direction Y, four first connection lines 541 and one second connection line 542 are arranged alternately.

[0130] In addition, each group of the third connection lines 561 includes four adjacent third connection lines 561, and each group of the fourth connection lines includes one fourth connection line. That is, along the first direction X, four third connection lines 561 and one fourth connection line 562 are arranged alternately. In yet other examples, each group of the first connection lines 541 can include four adjacent first connection lines 541, and each group of the second connection lines 542 includes one second connection line 542. That is, along the second direction Y, four first connection lines 541 and one second connection line 542 are arranged alternately.

[0130] In addition, each group of the third connection lines 561 includes four adjacent third connection lines 561, and each group of the fourth connection lines includes one fourth connection line. That is, along the first direction X, four third connection lines 561 and one fourth connection line 562 are arranged alternately. In yet other examples, each group of the first connection lines 541 can include four adjacent first connection lines 541, and each group of the second connection lines 542 includes one second connection line 542. That is, along the second direction Y, four first connection lines 541 and one second connection line 542 are arranged alternately.

[0130] In addition, each group of the third connection lines 561 includes four adjacent third connection lines 561, and each group of the fourth connection lines includes one fourth connection line. That is, along the first direction X, four third connection lines 561 and one fourth connection line 562 are arranged alternately. In yet other examples, each group of the first connection lines 541 can include four adjacent first connection lines 541, and each group of the second connection lines 542 includes one second connection line 542. That is, along the second direction Y, four first connection lines 541 and one second connection line 542 are arranged alternately.

[0130] In addition, each group of the third connection lines 561 includes four adjacent third connection lines 561, and each group of the fourth connection lines includes one fourth connection line. That is, along the first direction X, four third connection lines 561 and one fourth connection line 562 are arranged alternately. In yet other examples, each group of the first connection lines 541 can include four adjacent first connection lines 541, and each group of the second connection lines 542 includes one second connection line 542. That is, along the second direction Y, four first connection lines 541 and one second connection line 542 are arranged alternately.

[0130] In addition, each group of the third connection lines 561 includes four adjacent third connection lines 561, and each group of the fourth connection lines includes one fourth connection line. That is, along the first direction X, four third connection lines 561 and one fourth connection line 562 are arranged alternately. In yet other examples, each group of the first connection lines 541 can include four adjacent first connection lines 541, and each group of the second connection lines 542 includes one second connection line 542. That is, along the second direction Y, four first connection lines 541 and one second connection line 542 are arranged alternately.

[0130] In addition, each group of the third connection lines 561 includes four adjacent third connection lines 561, and each group of the fourth connection lines includes one fourth connection line. That is, along the first direction X, four third connection lines 561 and one fourth connection line 562 are arranged alternately. In yet other examples, each group of the first connection lines 541 can include four adjacent first connection lines 541, and each group of the second connection lines 542 includes one second connection line 542. That is, along the second direction Y, four first connection lines 541 and one second connection line 542 are arranged alternately.

[0130] In addition, each group of the third connection lines 561 includes four adjacent third connection lines 561, and each group of the fourth connection lines includes one fourth connection line. That is, along the first direction X, four third connection lines 561 and one fourth connection line 562 are arranged alternately. In yet other examples, each group of the first connection lines 541 can include four adjacent first connection lines 541, and each group of the second connection lines 542 includes one second connection line 542. That is, along the second direction Y, four first connection lines 541 and one second connection line 542 are arranged alternately.

[0130] In addition, each group of the third connection lines 561 includes four adjacent third connection lines 561, and each group of the fourth connection lines includes one fourth connection line. That is, along the first direction X, four third connection lines 561 and one fourth connection line 562 are arranged alternately. In yet other examples, each group of the first connection lines 541 can include four adjacent first connection lines 541, and each group of the second connection lines 542 includes one second connection line 542. That is, along the second direction Y, four first connection lines 541 and one second connection line 542 are arranged alternately.

[0130] In addition, each group of the third connection lines 561 includes four adjacent third connection lines 561, and each group of the fourth connection lines includes one fourth connection line. That is, along the first direction X, four third connection lines 561 and one fourth connection line 562 are arranged alternately. In yet other examples, each group of the first connection lines 541 can include four adjacent first connection lines 541, and each group of the second connection lines 542 includes one second connection line 542. That is, along the second direction Y, four first connection lines 541 and one second connection line 542 are arranged alternately.

[0130] In addition, each group of the third connection lines 561 includes four adjacent third connection lines 561, and each group of the fourth connection lines includes one fourth connection line. That is, along the first direction X, four third connection lines 561 and one fourth connection line 562 are arranged alternately. In yet other examples, each group of the first connection lines 541 can include four adjacent first connection lines 541, and each group of the second connection lines 542 includes one

[0131] Therefore, the number of the first connection lines 541 is four times the number of the second connection lines 542, and the number of the third connection lines 561 is four times the number of the fourth connection lines 562. The ratio of the sum of the number of the first connection lines 541 and the third connection lines 561 connected to the first power signal line 61 to the sum of the number of the second connection lines 542 and the fourth connection lines 562 connected to the initialization signal line 72 is 4:1.

[0132] In the embodiments of the present application, the ratio of the sum of the number of the first connection lines 541 and the third connection lines 561 connected to the first power signal line 61 to the sum of the number of the second connection lines 542 and the fourth connection lines 562 connected to the initialization signal line 72 is not limited to the aforementioned 1:1, 2:1, 3:1 or 4:1, etc.

[0133] In addition, in the case where the influence of the VAR signal on the operation of the light emitting device L is greater than that of the VSS signal, the number of the second connection lines 542 in each group of the second connection lines 542 can be greater than the number of the first connection lines 541 in each group of the first connection lines 541. In addition, the number of the fourth connection lines 562 in each group of the fourth connection lines 562 can be greater than the number of the third connection lines 561 in each group of the third connection lines 561, so that the sum of the number of the second connection lines 542 and the fourth connection lines 562 connected to the initialization signal line 72 is greater than the sum of the number of the first connection lines 541 and the third connection lines 561 connected to the first power signal line 61.

[0134] For example, the ratio of the sum of the number of the first connection lines 541 and the third connection lines 561 connected to the first power signal line 61 to the sum of the number of the second connection lines 542 and the fourth connection lines 562 connected to the initialization signal line 72 can be 1:2, 1:3, 1:4, etc. In this way, the reduction of the resistance of the transmission path of the VAR signal is greater than that of the VSS signal, the resistance of the transmission path of the VAR signal is smaller, the voltage drop generated in the transmission process of the VAR signal is smaller, and the influence on the operation of the light emitting device L can be better reduced.

[0135] The embodiments of the present application also provide a preparation method of the display panel. FIG. 10A and FIG. 10B are step diagrams of preparing the first conductive layer according to the embodiments of the present application. FIG. 10B is a sectional view of the structure along the section line A-A' in FIG. 10A. FIG. 11 is a step diagram of preparing the medium layer according to the embodiments of the present application. FIG. 12A and FIG. 12B are step diagrams of preparing the second conductive layer according to the embodiments of the present application. FIG. 12B is a sectional view of the structure along the section line B-B' in FIG. 12A. FIG. 13A and FIG. 13B are step diagrams of preparing the third conductive layer according to the embodiments of the present application. FIG. 13B is a sectional view of the structure along the section line C-C' in FIG. 13A.

[0136] The manufacturing method of the display panel 10 includes the following steps:

[0137] Referring to FIGS. 10A and 10B, a first conductive layer K1 is formed on the substrate 21, which may, for example, include the source S and the drain D of the thin film transistor T, and is also referred to as a first source-drain conductive layer (SD1).

[0138] The first conductive layer K1 further includes an initialization signal line 72, a first connection line 541, and a second connection line 542. The initialization signal line 72, the first connection line 541, and the second connection line 542 all extend along the first direction X, and the initialization signal line 72, the first connection line 541, and the second connection line 542 are arranged along the second direction Y.

[0139] The initialization signal line 72 is connected to the second connection line 542, for example, the first conductive layer K1 further includes a connection pattern 8, and the initialization signal line 72 is connected to the second connection line 542 through the connection pattern 8.

[0140] For example, referring to FIG. 10B, a first mask plate 91 can be used to form the first connection line 541 and the second connection line 542 synchronously in the process of forming the initialization signal line 72. That is, the initialization signal line 72, the first connection line 541, and the second connection line 542 can be formed synchronously by using the same mask plate, and no additional mask plate is needed to manufacture the first connection line 541 and the second connection line 542, which is conducive to reducing the manufacturing cost.

[0141] Referring to FIG. 11, a dielectric layer (for example, the dielectric layer can include a passivation layer 26 and a first planarization layer 27) is formed on the side of the first conductive layer K1 away from the substrate 21, and the passivation layer 26 and the first planarization layer 27 cover the thin film transistor T in sequence.

[0142] Referring to FIGS. 12A and 12B, a second conductive layer K2 is formed on the side of the first planarization layer 27 away from the substrate 21, which may, for example, include the anode adapter structure 25, and the second conductive layer K2 can be referred to as a second source-drain conductive layer (SD2).

[0143] The second conductive layer K2 further includes a third connection line 561 and a fourth connection line 562. The third connection line 561 and the fourth connection line 562 both extend along the second direction Y, and the third connection line 561 and the fourth connection line 562 are arranged along the first direction X.

[0144] At the black solid points in FIG. 12A, the third connection line 561 penetrates the passivation layer 26 and the first planarization layer 27 to be connected to the first connection line 541. At the white hollow points in FIG. 12A, the fourth connection line 562 penetrates the passivation layer 26 and the first planarization layer 27 to be connected to the connection pattern 8 (the second connection line 542).

[0145] Exemplarily, referring to FIG. 12B, the second mask plate 92 can be used to form the third connection line 561 and the fourth connection line 562 simultaneously in the process of forming the anode transfer structure 25. That is, the anode transfer structure 25, the third connection line 561 and the fourth connection line 562 can be formed simultaneously by using the same mask plate, and the third connection line 561 and the fourth connection line 562 do not need to be prepared by using additional mask plates, which is conducive to reducing the preparation cost.

[0146] Exemplarily, referring to FIGS. 13A and 13B, after the second conductive layer K2 is formed, the second planarization layer 28 and the third conductive layer K3 are formed on the side of the second conductive layer K2 away from the substrate 21. The third conductive layer K3 can include the anode 22, for example, and the third conductive layer K3 can be referred to as an anode layer.

[0147] The third conductive layer K3 further includes the first power signal line 61, which is arranged in the peripheral area A2. At the black solid point in FIG. 13A, the first power signal line 61 is connected to the first connection line 541 by penetrating the passivation layer 26, the first planarization layer 27 and the second planarization layer 28, and the first power signal line 61 is connected to the third connection line 561 by penetrating the second planarization layer 28.

[0148] The preparation method provided by the above embodiments of the present application forms the laminated first conductive layer K1, the dielectric layer (for example, the dielectric layer can include the passivation layer 26 and the first planarization layer 27) and the second conductive layer K2 on the substrate 21. The first conductive layer K1 includes the initialization signal line 72, the first connection line 541 and the second connection line 542, and the second conductive layer K2 includes the third connection line 561 and the fourth connection line 562.

[0149] The initialization signal line 72 and the second connection line 542 are located in the same conductive layer, the initialization signal line 72 can be directly connected to the second connection line 542, the fourth connection line 562 is connected to the second connection line 542 by penetrating the passivation layer 26 and the first planarization layer 27, and by connecting the second connection line 542 and the fourth connection line 562 to the initialization signal line 72, the resistance of the transmission path of the VAR signal is reduced, the voltage drop of the VAR signal in the transmission process is reduced, the uniformity of the VAR signal received by the anode 22 of each area is improved, the normal light emission of the light emitting device L of each area is ensured, and the display mura problem of the display panel 10 is improved.

[0150] Furthermore, the third connecting line 561 is connected with the first connecting line 541 through the passivation layer 26 and the first planarization layer 27. The first power signal line 61 is connected with the first connecting line 541 through the passivation layer 26, the first planarization layer 27 and the second planarization layer 28, and the first power signal line 61 is connected with the third connecting line 561 through the second planarization layer 28. By connecting the first connecting line 541 and the third connecting line 561 to the first power signal line 61, the resistance of the transmission path of the VSS signal is reduced, the voltage drop of the VSS signal in the transmission process is reduced, the uniformity of the VSS signal received by the cathode 24 in each region of the display area A1 is improved, and thus the normal light emission of the light emitting device L in each region is ensured, and the display mura problem of the display panel 10 is improved.

[0151] The above merely provides the specific implementation of the present application, but the protection scope of the present application is not limited to this. Any person skilled in the art can think of the changes or replacements within the technical range disclosed by the present application, and all the changes or replacements should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A display panel, characterized by, The display panel comprises a display area and a peripheral area surrounding the display area; the display panel comprises: a power signal line arranged in the peripheral area; a plurality of initialization signal lines arranged in the display area; the initialization signal lines extend along a first direction, and the plurality of initialization signal lines are arranged along a second direction intersecting the first direction; a plurality of first wires and a plurality of second wires arranged in the display area; the first wires extend along the first direction, and the plurality of first wires are arranged along the second direction; the second wires extend along the second direction, and the plurality of second wires are arranged along the first direction; wherein the plurality of first wires comprises at least one first connection line and at least one second connection line, and the plurality of second wires comprises at least one third connection line and at least one fourth connection line; the first connection line and the third connection line are connected to the power signal line, and the second connection line and the fourth connection line are connected to the initialization signal line.

2. The display panel of claim 1, wherein, The plurality of first wires comprises a plurality of groups of first connection lines and a plurality of groups of second connection lines; each group of first connection lines comprises at least one first connection line, and each group of second connection lines comprises at least one second connection line; along the second direction, a group of first connection lines and a group of second connection lines are arranged alternately; The plurality of second wires comprises a plurality of groups of third connection lines and a plurality of groups of fourth connection lines; each group of third connection lines comprises at least one third connection line, and each group of fourth connection lines comprises at least one fourth connection line; along the first direction, a group of third connection lines and a group of fourth connection lines are arranged alternately; one first connection line in each group of first connection lines is connected to at least one third connection line in at least one group of third connection lines and the power signal line; and one second connection line in each group of second connection lines is connected to at least one fourth connection line in at least one group of fourth connection lines and one initialization signal line.

3. The display panel of claim 2, wherein, Each group of first connection lines comprises one first connection line, and each group of second connection lines comprises one second connection line. Each group of third connection lines comprises one third connection line, and each group of fourth connection lines comprises one fourth connection line.

4. The display panel of claim 2, wherein, Each group of first connection lines comprises a plurality of adjacent first connection lines, and each group of second connection lines comprises a plurality of adjacent second connection lines; Each group of third connection lines comprises a plurality of adjacent third connection lines, and each group of fourth connection lines comprises a plurality of adjacent fourth connection lines.

5. The display panel of claim 2, wherein, The number of first connection lines in each group of first connection lines is greater than the number of second connection lines in each group of second connection lines; and / or The number of third connection lines in each group of third connection lines is greater than the number of fourth connection lines in each group of fourth connection lines.

6. The display panel of any one of claims 1-5, wherein, The display area comprises a hole area and a regular display area, the plurality of initialization signal lines comprises a first initialization signal line passing through the hole area and a second initialization signal line located in the regular display area; The plurality of first wires comprises a plurality of second connection lines, the plurality of second wires comprises a plurality of fourth connection lines, and the plurality of second connection lines and the plurality of fourth connection lines are connected to form a mesh structure. The first initialization signal line is connected with a second connection line in the mesh structure, and the second initialization signal line is connected with another second connection line in the mesh structure.

7. The display panel of claim 6, wherein, The regular display area includes a display fan-out area, the plurality of first wires further include a plurality of first data connection lines, at least part of the first data connection lines are arranged in the display fan-out area; the plurality of second wires further include a plurality of second data connection lines, at least part of the second data connection lines are arranged in the display fan-out area, and one first data connection line is connected with one second data connection line; In the first direction, at least one first data connection line is co-linear with and disconnected from one first connection line, and / or at least one first data connection line is co-linear with and disconnected from one second connection line; In the second direction, at least one second data connection line is co-linear with and disconnected from one third connection line, and / or at least one second data connection line is co-linear with and disconnected from one fourth connection line.

8. The display panel of any one of claims 1-7, wherein, The display panel includes a substrate, a first conductive layer, a dielectric layer and a second conductive layer which are arranged in layers on the substrate; The first conductive layer includes the initialization signal line, the second connection line and a connection pattern, and the second conductive layer includes the fourth connection line; The initialization signal line is connected with the second connection line through the connection pattern, and the fourth connection line is connected with the connection pattern through the dielectric layer.

9. The display panel of any one of claims 1-8, wherein, The display panel further includes a plurality of array-arranged sub-pixels arranged in the display area, the plurality of sub-pixels include a plurality of rows and a plurality of columns, each row of sub-pixels extends along the first direction, and each column of sub-pixels extends along the second direction; Each sub-pixel includes a pixel driving circuit and a light emitting device connected with each other, the light emitting devices of the plurality of array-arranged sub-pixels are electrically connected with the power signal line; One initialization signal line is electrically connected with the pixel driving circuits of one row of sub-pixels.

10. A display device, characterized by comprising: The display panel includes: The display panel according to any one of claims 1-9; A controller which is electrically connected with the display panel.

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