Display panel and display apparatus

Abstract

The present disclosure relates to the technical field of display. Provided are a display panel and a display apparatus. The display panel comprises a plurality of panel partitions sequentially arranged in a first direction, and the display panel comprises at least one gate driving circuit, wherein the gate driving circuit comprises gate driving sub-circuits respectively located in the panel partitions; the gate driving circuit comprises parallel gate driving circuits; and in two adjacent gate driving sub-circuits of the same parallel gate driving circuit, an output end of a last-stage shift register of the previous gate driving sub-circuit is electrically connected to an input end of a first-stage shift register of the next gate driving sub-circuit by means of a first control sub-circuit. The present disclosure can improve the display quality of the display panel.

Description

Display panel and display device

[0001] Cross-reference to related applications

[0002] The present disclosure claims priority to Chinese Patent Application No. 202410658512.0, filed May 24, 2024, entitled “Display panel and display device,” the entire contents of which are incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present disclosure relates to the technical field of display, and in particular, to a display panel and a display device. BACKGROUND

[0004] The flexible folding product has two forms of full-screen display and half-screen display, and can realize free switching of mobile phone and tablet computer forms. At present, the gate drive circuit of the folding product adopts a mode of driving the front surface and the back surface respectively, so that the gate drive circuits of the front surface and the back surface are independent of each other.

[0005] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present disclosure, and therefore can include information that does not constitute prior art known to those of ordinary skill in the art. SUMMARY

[0006] The purpose of the present disclosure is to overcome the shortcomings of the prior art, and to provide a display panel and a display device.

[0007] According to one aspect of the present disclosure, a display panel is provided, comprising a plurality of panel partitions arranged in a first direction in sequence; the display panel comprises at least one gate drive circuit, and the gate drive circuit comprises a sub-gate drive circuit located in each of the panel partitions respectively.

[0008] The gate drive circuit comprises a parallel gate drive circuit; in adjacent two sub-gate drive circuits of the same parallel gate drive circuit, the output end of the last stage shift register of the previous sub-gate drive circuit is electrically connected to the input end of the first stage shift register of the next sub-gate drive circuit through a first control sub-circuit.

[0009] In an embodiment of the present disclosure, the first control sub-circuit comprises one P-type transistor, or a plurality of P-type transistors connected in series, or one N-type transistor, or a plurality of N-type transistors connected in series.

[0010] In an embodiment of the present disclosure, the input end of the first stage shift register of the xth sub-gate drive circuit is electrically connected to the xth start signal through a second control sub-circuit; wherein x is an integer greater than 1.

[0011] In an embodiment of the present disclosure, the second control sub-circuit comprises a P-type transistor, or comprises a plurality of P-type transistors connected in series, or comprises an N-type transistor, or comprises a plurality of N-type transistors connected in series.

[0012] In an embodiment of the present disclosure, the display panel is provided with a control wire group corresponding to the parallel gate driving circuit, the control wire group comprising a first control wire for controlling the first control sub-circuit of the corresponding parallel gate driving circuit and a second control wire for controlling the second control sub-circuit of the corresponding parallel gate driving circuit.

[0013] The first control sub-circuit and the second control sub-circuit are of the same type of transistor.

[0014] The first control wire is electrically connected to the control end of the first control sub-circuit, and the second control wire is electrically connected to the control end of the second control sub-circuit.

[0015] In an embodiment of the present disclosure, the first control sub-circuit and the second control sub-circuit are of opposite types of transistor.

[0016] The display panel is provided with a common control wire corresponding to the parallel gate driving circuit, the common control wire being used for controlling the first control sub-circuit and the second control sub-circuit of the corresponding parallel gate driving circuit.

[0017] The common control wire, the control end of the first control sub-circuit, and the control end of the second control sub-circuit are electrically connected to each other.

[0018] In an embodiment of the present disclosure, the display panel is provided with a plurality of parallel gate driving circuits.

[0019] The first control wire corresponding to each parallel gate driving circuit is the same wire; or the second control wire corresponding to each parallel gate driving circuit is the same wire; or the first control wire and the second control wire of each parallel gate driving circuit are the same wire.

[0020] In an embodiment of the present disclosure, the display panel is provided with a plurality of parallel gate driving circuits.

[0021] The common control wire of each parallel gate driving circuit is the same wire.

[0022] In one embodiment of the present disclosure, in the same parallel gate drive circuit, the input end of the first stage shift register of the xth sub gate drive circuit is electrically connected with the output end of the last stage shift register of the x-1th sub gate drive circuit only through the first control sub circuit; wherein x is an integer greater than 1.

[0023] In one embodiment of the present disclosure, the input end of the first stage shift register of the xth sub gate drive circuit is electrically connected with the first power voltage through the second control sub circuit; the level of the first power voltage is opposite to the effective level of the scanning signal output by the parallel gate drive circuit; wherein x is an integer greater than 1.

[0024] In one embodiment of the present disclosure, the display panel is a flexible panel.

[0025] In one embodiment of the present disclosure, the display panel comprises at least two parallel gate drive circuits, and the number of shift registers of the two parallel gate drive circuits is different.

[0026] In one embodiment of the present disclosure, the parallel gate drive circuit comprises a scanning gate drive circuit for outputting a scanning control signal, and the scanning output end of each shift register of the scanning gate drive circuit is used for electrical connection with a scanning control signal line.

[0027] In one embodiment of the present disclosure, the parallel gate drive circuit comprises a light-emitting gate drive circuit for outputting a light-emitting control signal, and the light-emitting output end of each shift register of the light-emitting gate drive circuit is used for electrical connection with a light-emitting control signal line.

[0028] According to another aspect of the present disclosure, there is also provided a display device comprising the above-mentioned display panel.

[0029] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0030] The drawings herein are incorporated into the specification and form a part of the specification, show embodiments consistent with the present disclosure, and together with the specification serve to explain the principles of the present disclosure. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained according to these drawings without creative labor for those skilled in the art.

[0031] FIG. 1 is a schematic diagram of a display panel in one embodiment of the present disclosure.

[0032] FIG. 2 is a schematic diagram of a display panel in one embodiment of the present disclosure.

[0033] FIG. 3 is a schematic diagram of a display panel, according to an embodiment of the present disclosure.

[0034] FIG. 4 is a schematic diagram of a pixel driving circuit, according to an embodiment of the present disclosure.

[0035] FIG. 5 is a schematic diagram of a gate driving circuit, according to an embodiment of the present disclosure.

[0036] FIG. 6 is a schematic diagram of a gate driving circuit, according to an embodiment of the present disclosure.

[0037] FIG. 7 is a schematic diagram of a display panel, according to an embodiment of the present disclosure.

[0038] FIG. 8 is a schematic diagram of a display panel, according to the related art.

[0039] FIG. 9 is a schematic diagram of a display panel, according to an embodiment of the present disclosure.

[0040] FIG. 10 is a schematic diagram of a P-type transistor, according to an embodiment of the present disclosure.

[0041] FIG. 11 is a schematic diagram of a P-type transistor, according to an embodiment of the present disclosure.

[0042] FIG. 12 is a schematic diagram of a P-type transistor, according to an embodiment of the present disclosure.

[0043] FIG. 13 is a schematic diagram of a P-type transistor, according to an embodiment of the present disclosure.

[0044] FIG. 14 is a schematic diagram of a display panel, according to an embodiment of the present disclosure.

[0045] FIG. 15 is a driving timing diagram of a display panel, according to an embodiment of the present disclosure.

[0046] FIG. 16 is a driving timing diagram of a display panel, according to an embodiment of the present disclosure.

[0047] FIG. 17 is a schematic diagram of a display panel, according to an embodiment of the present disclosure.

[0048] FIG. 18 is a driving timing diagram of a display panel, according to an embodiment of the present disclosure.

[0049] FIG. 19 is a schematic diagram of a display panel, according to an embodiment of the present disclosure.

[0050] FIG. 20 is a driving timing diagram of a display panel, according to an embodiment of the present disclosure.

[0051] FIG. 21 is a schematic diagram of a display panel, according to an embodiment of the present disclosure.

[0052] FIG. 22 is a driving timing diagram of a display panel in one embodiment of the present disclosure.

[0053] FIG. 23 is a driving timing diagram of a display panel in one embodiment of the present disclosure.

[0054] FIG. 24 is a schematic diagram of a display panel in one embodiment of the present disclosure.

[0055] FIG. 25 is a driving timing diagram of a display panel in one embodiment of the present disclosure.

[0056] FIG. 26 is a schematic diagram of a display panel in one embodiment of the present disclosure.

[0057] FIG. 27 is a driving timing diagram of a display panel in one embodiment of the present disclosure.

[0058] FIG. 28 is a schematic diagram of a display panel in one embodiment of the present disclosure.

[0059] FIG. 29 is a driving timing diagram of a display panel in one embodiment of the present disclosure.

[0060] FIG. 30 is a driving timing diagram of a display panel in one embodiment of the present disclosure.

[0061] FIG. 31 is a schematic diagram of a display panel in one embodiment of the present disclosure.

[0062] FIG. 32 is a driving timing diagram of a display panel in one embodiment of the present disclosure.

[0063] FIG. 33 is a schematic diagram of a display panel in one embodiment of the present disclosure.

[0064] FIG. 34 is a driving timing diagram of a display panel in one embodiment of the present disclosure.

[0065] FIG. 35 is a schematic diagram of a display panel in one embodiment of the present disclosure.

[0066] FIG. 36 is a driving timing diagram of a display panel in one embodiment of the present disclosure.

[0067] FIG. 37 is a driving timing diagram of a display panel in one embodiment of the present disclosure.

[0068] FIG. 38 is a schematic diagram of a display panel in one embodiment of the present disclosure.

[0069] FIG. 39 is a driving timing diagram of a display panel in one embodiment of the present disclosure.

[0070] FIG. 40 is a schematic diagram of a display panel in one embodiment of the present disclosure.

[0071] FIG. 41 is a driving timing diagram of a display panel in one embodiment of the present disclosure. DETAILED DESCRIPTION

[0072] Example embodiments now will be described more fully hereinafter with reference to the accompanying drawings. Example embodiments, may, however, be implemented in many different forms and should not be construed as limited to the implementations set forth herein; rather, these implementations are provided as non-limiting examples so that this disclosure will fully convey the scope of the example embodiments to those skilled in the art. Like reference numerals refer to like elements throughout the figures, and description of the same or similar elements can be omitted. In addition, the drawings are to be used only as a general guide of the present disclosure, and are not necessarily to scale.

[0073] Although relative terms are used herein, such as "upper", "lower", to describe one component's relationship to another component of the icon, these terms are used herein for convenience only and are not to be construed as limiting the scope of the example embodiments. It is to be understood that if the icon were turned over, such that the "upper" component were now a "lower" component, then such terminology would, of course, apply. When a structure is on another structure, it can mean that the structure is formed integrally with the other structure, or that the structure is "directly" on the other structure, or that the structure is "indirectly" on the other structure via another structure.

[0074] The terms "one", "a", "an", "the", and "at least one" are used to mean that "one or more" of something is present; the term "includes" and its variations are used synonymously with "comprising"; the term "first", "second", and "third" are used to distinguish elements with like reference numerals and are not used to limit a quantity of elements to only three elements unless expressly stated as such; and the term "another" is used to mean "at least a second" or "at least a third".

[0075] In the embodiments of the present disclosure, a transistor refers to an element including at least three terminals of a gate, a source and a drain. The transistor has a channel region between the drain (drain electrode terminal, drain region or drain electrode) and the source (source electrode terminal, source region or source electrode), and current can flow through the source, the channel region and the drain. The channel region refers to a region through which current mainly flows. In the embodiments of the present disclosure, in the case of using a transistor with opposite polarity or in the case of changing the current direction in the circuit operation, the functions of the "source" and the "drain" are sometimes exchanged with each other, that is, the "source" and the "drain" can be exchanged with each other. In the embodiments of the present disclosure, for any one transistor, one of the "source" and the "drain" is referred to as a first electrode of the transistor, and the other is referred to as a second electrode of the transistor, and the gate is referred to as a control terminal of the transistor. In the embodiments of the present disclosure, at least part of a signal has a high level and a low level; one of the high level and the low level can be a gate-on level of the signal, which can make a controlled transistor turn on; the other of the high level and the low level can be a gate-off level of the signal, which can make the controlled transistor turn off. For example, for a signal for controlling a P-type transistor (which can be loaded to the control terminal of the P-type transistor), the gate-on level thereof is the low level, and the gate-off level thereof is the high level. For another example, for a signal for controlling an N-type transistor (which can be loaded to the control terminal of the N-type transistor), the gate-on level thereof is the high level, and the gate-off level thereof is the low level.

[0076] The structure layer A is located on the side of the structure layer B away from the substrate, which can be understood as that the structure layer A is formed on the side of the structure layer B away from the substrate. When the structure layer B is a patterned structure, part of the structure of the structure layer A can also be located at the same physical height as the structure layer B or below the physical height of the structure layer B, wherein the substrate is the height reference.

[0077] In the present disclosure, when the C structure and the D structure are described as overlapping each other, it means that the C structure and the D structure are located in different film layers, and the orthographic projection of the C structure on the display panel and the orthographic projection of the D structure on the display panel have a part overlapping each other.

[0078] The present disclosure provides a display device including a display panel PNL. The display device can be any product or component with display function, such as a mobile phone, a tablet computer, etc. The display panel PNL is a flexible panel. In one example, the display panel PNL is a folding panel; for example, the folding panel is used in a foldable mobile phone or a tablet computer, so that the display panel PNL has a front surface and a back surface, and the display mode has two modes of full-screen display and half-screen display. The full-screen display is simultaneous display on the front surface and the back surface, and the half-screen display is display on only the front surface or only the back surface. In another example, the display panel PNL is a rollable panel, so that the display panel can be rolled.

[0079] In an embodiment of the present disclosure, the display panel PNL includes a plurality of panel sub-regions SPNL arranged in sequence along a first direction DV. For example, referring to FIG. 1, the display panel PNL includes two panel sub-regions SPNL arranged in sequence along the first direction DV, and the display panel PNL can be foldable at the junction of the two panel sub-regions SPNL so that one of the panel sub-regions SPNL is a front surface and the other panel sub-region SPNL is a back surface. When the two panel sub-regions SPNL are in a folded state, a half-screen display can be achieved. When the two panel sub-regions SPNL are in an unfolded state or the two panel sub-regions SPNL are located in the same plane, a full-screen display can be achieved.

[0080] In an embodiment of the present disclosure, referring to FIG. 1, the display panel PNL includes a display region AA and a peripheral region BB located at least one side of the display region AA. In the display region AA, the display panel PNL is provided with display units UU arranged in an array, and the display units UU include sub-pixels Pixel and pixel driving circuits PDC driving the sub-pixels Pixel. The display panel PNL is not provided with display units in the peripheral region BB, or the display units provided are not used for displaying a picture. Referring to FIG. 1, the display panel PNL is provided with a plurality of scan lines GL extending along a second direction DH in the display region AA, and each scan line GL is provided in one-to-one correspondence with each display unit row. The pixel driving circuit PDC of each display unit in the display unit row is electrically connected to the corresponding scan line GL. The display panel PNL is further provided with a plurality of data lines DL extending along the first direction DV in the display region AA, and each data line DL is provided in one-to-one correspondence with each display unit column. The pixel driving circuit PDC of each display unit in the display unit column is electrically connected to the corresponding data line DL. In this way, the pixel driving circuit PDC of each display unit is connected to the scan line GL and the data line DL. A scan signal is loaded on the scan line GL to control the state of the pixel driving circuit PDC. It can be understood that in the example of FIG. 1, only one kind of scan line GL corresponding to the display unit row is shown; according to needs, the display panel PNL can be provided with a plurality of different scan lines GL corresponding to the display unit row. The data line DL can be loaded with a data voltage Vdata for driving the pixel driving circuit PDC, and the pixel driving circuit PDC can drive the sub-pixel Pixel according to the written data voltage Vdata, thereby controlling the brightness of the sub-pixel Pixel. It can be understood that the pixel driving circuit PDC can also control the brightness of the sub-pixel Pixel according to other signals.

[0081] It should be noted that, referring to FIG. 1, the display panel PNL has a first direction DV and a second direction DH. The first direction DV and the second direction DH are perpendicular to each other. For example, the first direction DV is a column direction, i.e., the overall extension direction of the data lines DL; and the second direction DH is a row direction, i.e., the overall extension direction of the scan lines GL.

[0082] Optionally, the pixel driving circuit PDC at least includes a data writing transistor, a driving transistor and a storage capacitor, and the gate of the driving transistor can be electrically connected with one of the electrode plates of the storage capacitor. The source of the data writing transistor can be electrically connected with the data line DL, and the gate of the data writing transistor can be electrically connected with a writing control wire for loading a data writing signal (a kind of scan signal). The pixel driving circuit PDC is configured such that when the gating level of the data writing signal is loaded on the writing control wire, the data writing transistor is turned on, thereby causing the driving voltage on the data line DL to be written to the gate of the driving transistor and the storage capacitor. When the data writing transistor is turned off, the driving voltage can be maintained by the storage capacitor. The driving transistor can output a driving current to drive the sub-pixel Pixel to emit light under the control of the voltage on its gate. It can be understood that the pixel driving circuit PDC of the embodiments of the present disclosure can also include other transistors or capacitors to make the pixel driving circuit PDC have better driving performance. For example, the pixel driving circuit PDC can be a 7T1C (7 thin film transistors and one storage capacitor), 8T1C (8 thin film transistors and one storage capacitor) or other architecture of pixel driving circuit.

[0083] Optionally, the sub-pixel Pixel can be a current-driven self-luminous element, for example, can be any one of OLED, PLED, QLED, Micro LED, MiNi LED and the like. In this embodiment, the sub-pixel Pixel can include sub-pixels Pixel of multiple different colors, for example, including red sub-pixels for emitting red light, blue sub-pixels for emitting green light and green sub-pixels for emitting green light. It can be understood that in other embodiments of the present disclosure, the sub-pixels Pixel in the display area AA can also have sub-pixels Pixel of other colors (for example, yellow sub-pixels for emitting yellow light, cyan sub-pixels for emitting cyan light, white sub-pixels for emitting white light, etc.).

[0084] In one embodiment of the present disclosure, referring to FIG. 2, the display panel PNL can include a substrate SBT, a driving layer DRL and a pixel layer PIXL which are sequentially stacked. The pixel layer PIXL is provided with sub-pixels Pixel, and the driving layer DRL is provided with pixel driving circuits PDC for driving the sub-pixels Pixel; each sub-pixel Pixel can emit light under the driving of the pixel driving circuit PDC to display a picture. Further, the display panel PNL also includes a thin film encapsulation layer TFE on the side of the pixel layer PIXL away from the driving backplane DBP, and the thin film encapsulation layer TFE can encapsulate and protect the pixel layer PIXL.

[0085] Optionally, the substrate SBT can be a substrate of inorganic material, a substrate of organic material, or a composite substrate formed by stacking a substrate of inorganic material and a substrate of organic material. For example, in some embodiments of the present disclosure, the material of the substrate SBT can be a glass material such as soda lime glass, quartz glass or sapphire glass. In some other embodiments of the present disclosure, the material of the substrate SBT can be polymethyl methacrylate, polyvinyl alcohol, polyvinyl phenol, polyether sulfone, polyimide, polyamide, polyacetal, polycarbonate, polyethylene terephthalate, polyethylene naphthalate or a combination thereof. In some other embodiments of the present disclosure, the substrate SBT can also be a flexible substrate, for example, the material of the substrate SBT can include polyimide.

[0086] Optionally, in the driving layer DRL, any one of the pixel driving circuits PDC can include a thin film transistor TFT and a storage capacitor. Further, the thin film transistor TFT can be selected from a top-gate thin film transistor, a bottom-gate thin film transistor or a dual-gate thin film transistor; the material of the active layer of the thin film transistor can be amorphous silicon semiconductor material, low-temperature polysilicon semiconductor material, metal oxide semiconductor material, organic semiconductor material, carbon nanotube semiconductor material or other types of semiconductor material; the thin film transistor can be an N-type thin film transistor or a P-type thin film transistor.

[0087] It can be understood that the types of any two transistors among the transistors in the pixel driving circuit can be the same or different. For example, in some embodiments, in a pixel driving circuit, some transistors can be N-type transistors and some transistors can be P-type transistors. For another example, in some other embodiments, in a pixel driving circuit, the active layer of some transistors can be made of low-temperature polysilicon semiconductor material and the active layer of some transistors can be made of metal oxide semiconductor material. In some embodiments of the present disclosure, the thin film transistor is a low-temperature polysilicon transistor. In some other embodiments of the present disclosure, some thin film transistors are low-temperature polysilicon transistors and some thin film transistors are metal oxide transistors.

[0088] Optionally, the driving layer DRL can include a semiconductor layer SCL, a gate insulating layer GI, a gate layer GT, an interlayer dielectric layer ILD, a source-drain metal layer SD, a planarization layer PLN, etc. stacked between the substrate SBT and the pixel layer PIXL. Each thin film transistor and storage capacitor can be formed by the semiconductor layer SCL, the gate insulating layer GI, the gate layer GT, the interlayer dielectric layer ILD, the source-drain metal layer SD, etc. The positional relationship of each film layer can be determined according to the film layer structure of the thin film transistor. Further, the semiconductor layer SCL can be used to form the channel region of the transistor, and can also be used to form part of the wiring or conductive structure by being made conductive when necessary. The gate layer can be used to form one or more scan wirings, such as one or more of a write control wiring, a reset control wiring, a light-emitting control wiring, etc., and can also be used to form the gate of the transistor and can also be used to form part or all of the electrode plate of the storage capacitor. The source-drain metal layer can be used to form the data line DL, the driving power supply voltage wiring, etc., and can also be used to form part of the electrode plate of the storage capacitor. Of course, in other embodiments of the present disclosure, the driving layer DRL can also include other film layers as needed, such as a light shielding layer between the semiconductor layer SCL and the substrate SBT, etc. Any one of the above-mentioned semiconductor layer SCL, gate layer GT, source-drain metal layer SD, etc. can also be multi-layered as needed, such as two different semiconductor layers SCL in the driving layer DRL, or two or three source-drain metal layers SD, or two or three gate layers GT; accordingly, the insulating film layers in the driving layer DRL (such as the gate insulating layer GI, the interlayer dielectric layer ILD, the planarization layer PLN, etc.) can be adaptively increased or decreased, or new insulating film layers can be added as needed.

[0089] Optionally, the driving layer DRL can also include a passivation layer, which can be arranged on the surface of the source-drain metal layer SD away from the substrate SBT to protect the source-drain metal layer SD.

[0090] As an example, referring to FIG. 2, the driving layer DRL can include, in sequence, an inorganic buffer layer BUF, a semiconductor layer SCL, a gate insulating layer GI, a gate layer GT, an interlayer dielectric layer ILD, a source-drain metal layer SD, and a planarization layer PLN. The thin film transistor thus formed is a top-gate thin film transistor.

[0091] In an embodiment of the present disclosure, referring to FIG. 2, the sub-pixel Pixel in the pixel layer PIXL is a thin film light emitting element, which can include two electrodes and a light emitting functional layer interposed between the two electrodes. As an example, referring to FIG. 2, the pixel layer PIXL can include, in sequence, a pixel electrode layer PEL, a light emitting functional layer EFL, and a common electrode layer COML. The pixel electrode layer PEL has a plurality of pixel electrodes PE in the display area of the display panel; the light emitting functional layer EFL has a part connected with the pixel electrode PE as a light emitting functional unit of the sub-pixel Pixel; and the common electrode layer COML is electrically connected with the light emitting functional unit of each sub-pixel Pixel as a common electrode.

[0092] Further, the pixel layer PIXL can further include a pixel definition layer PDL between the pixel electrode layer PEL and the light emitting functional layer EFL. The pixel definition layer PDL has a plurality of through pixel openings corresponding to the plurality of pixel electrodes PE one by one, and any one pixel opening exposes at least a part of the corresponding pixel electrode. For example, the pixel definition layer PDL covers the edges of the pixel electrode PE and exposes at least a part of the internal area of the pixel electrode PE, so that the pixel definition layer PDL can effectively define the actual effective area (the area directly connected with the light emitting functional layer EFL) of the pixel electrode PE, and further define the light emitting area and light emitting area of the sub-pixel Pixel. The light emitting functional layer EFL at least covers the pixel electrode PE exposed by the pixel definition layer PDL. The common electrode layer COML can cover the light emitting functional layer EFL in the display area. The pixel electrode PE and the common electrode layer COML provide carriers such as electrons and holes to the light emitting functional layer EFL, so that the light emitting functional layer EFL emits light. The part of the light emitting functional layer EFL between the pixel electrode PE and the common electrode layer COML can serve as a light emitting functional unit. The pixel electrode PE, the common electrode layer COML, and the light emitting functional unit form a light emitting element LD as a sub-pixel. One of the pixel electrode PE and the common electrode layer COML serves as an anode of the sub-pixel Pixel, and the other serves as a cathode of the sub-pixel Pixel.

[0093] In an example, the pixel electrode PE serves as an anode of the sub-pixel Pixel, and the common electrode layer COML serves as a cathode of the sub-pixel Pixel.

[0094] It can be understood that the type of light emitting element is different, and the material and film layer of the light emitting functional layer EFL are different.

[0095] For example, when the light emitting element is an OLED, the light emitting functional layer EFL can include an organic light emitting layer EML, and can include one or more of a hole injection layer HIL, a hole transport layer HTL, an electron blocking layer EBL, a hole blocking layer HBL, an electron transport layer ETL, and an electron injection layer EIL. Further, the organic light emitting layer EML can include a light emitting layer host material and a light emitting layer guest material, which can be a fluorescent dopant or a phosphorescent dopant, and in particular, can be a thermally activated delayed fluorescence material. It can be understood that when the OLED adopts a stacked structure, a charge generation layer CGL can also be provided in the light emitting functional layer EFL.

[0096] For example, when the light emitting element is a QLED, the light emitting functional layer EFL can include a quantum dot layer QDL, and can include one or more of a hole injection layer HIL, an electron transport layer ETL, an electron blocking layer EBL, a hole blocking layer HBL, an electron transport layer ETL, and an electron injection layer EIL. Further, the quantum dot layer QDL can have quantum dot particles, and the quantum dot particles can be connected to each other by surface modification groups. It can be understood that when the QLED adopts a stacked structure, a charge generation layer CGL can also be provided in the light emitting functional layer EFL.

[0097] Referring to FIG. 3, in the display panel PNL, a gate drive circuit GOA is provided in the peripheral region BB to provide a scan signal to the pixel drive circuit PDC, and the gate drive circuit includes a plurality of shift registers SR cascaded in sequence. According to the needs of the pixel drive circuit PDC, a plurality of gate drive circuits GOA can be provided in the peripheral region BB to provide different scan signals, respectively. Of course, some scan signals can also share one gate drive circuit GOA.

[0098] Optionally, according to the needs of the pixel drive circuit PDC, the scan signal can include one or more of, but not limited to, a write control signal for controlling the writing of a data voltage to the pixel drive circuit PDC, a light emitting control signal for controlling the output of a drive current by the pixel drive circuit PDC, a reset control signal for controlling the reset of the pixel drive circuit PDC, and the like. It can be understood that the scan line GL can be a write control signal line for loading the write control signal to the pixel drive circuit PDC, can be a light emitting control signal line for loading the light emitting control signal to the pixel drive circuit PDC, can be a reset control signal line for loading the reset control signal to the pixel drive circuit PDC, and the like.

[0099] Taking the pixel driving circuit PDC shown in FIG. 4 as an example, referring to FIG. 4, the pixel driving circuit PDC includes first to seventh transistors T1-T7, and a first capacitor C1, a second capacitor C2, and a light emitting element. The first transistor T1 has a first electrode electrically connected to a first initialization voltage terminal, a second electrode electrically connected to a first node N1, and a control electrode electrically connected to a first scan control signal terminal. The first transistor T1 is configured to load the first initialization voltage Vinit1 to the first node N1 in response to a gating level of the first scan control signal SC(n-1). The second transistor T2 has a first electrode electrically connected to a third node N3, a second electrode electrically connected to the first node N1, and a control electrode electrically connected to a second scan control signal terminal. The second transistor T2 is configured to make the third node N3 and the first node N1 communicate with each other in response to a gating level of the second scan control signal SC(n). The third transistor T3 has a first electrode electrically connected to a second node N2, a second electrode electrically connected to the third node N3, and a control electrode electrically connected to the first node N1. The third transistor T3 is configured to make the second node N2 and the third node N3 communicate with each other in response to a gating level of the first node N1, and the third transistor T3 is capable of generating a driving current. The fourth transistor T4 has a first electrode electrically connected to a data voltage terminal, a second electrode electrically connected to the second node N2, and a control electrode electrically connected to the second scan control signal terminal. The fourth transistor T4 is configured to load the data voltage Data to the second node N2 in response to a gating level of the second scan control signal SC(n). The fifth transistor T5 has a first electrode electrically connected to a first driving power voltage terminal, a second electrode electrically connected to the second node N2, and a control electrode electrically connected to a light emitting control signal terminal. The fifth transistor T5 is configured to load the first driving power voltage VDD to the second node N2 in response to a gating level of the light emitting control signal EM. The sixth transistor T6 has a first electrode electrically connected to the third node N3, a second electrode electrically connected to a fourth node N4 and a pixel electrode of the light emitting element, and a control electrode electrically connected to the light emitting control signal terminal. The sixth transistor T6 is configured to make the third node N3 and the fourth node N4 communicate with each other in response to a gating level of the light emitting control signal EM. The seventh transistor T7 has a first electrode electrically connected to a second initialization voltage terminal, a second electrode electrically connected to the fourth node N4, and a control electrode electrically connected to the second scan control signal terminal. The seventh transistor T7 is configured to load the second initialization voltage Vinit2 to the fourth node N4 in response to a gating level of the second scan control signal SC(n). The first capacitor C1 has one end electrically connected to the first driving power voltage terminal and the other end electrically connected to the first node N1. The second capacitor C2 is a parasitic capacitor of a data line DL. In this example, all the transistors are P-type transistors, and the gating levels of various signals are low levels.

[0100] It should be noted that in FIG. 4, the scan control signal SC includes a first scan control signal SC(n-1) and a second scan control signal SC(n). The first scan control signal SC(n-1) is provided by the (n-1)th row scan line GL, and the second scan control signal SC(n) is provided by the nth row scan line GL; wherein n is an integer greater than 0. In this way, the first scan control signal SC(n-1) and the second scan control signal SC(n) can share one gate drive circuit GOA, which is conducive to the narrow frame of the display panel. It should also be noted that in the pixel driving circuit PDC of this example, the scan control signal SC is used as a write control signal and a reset control signal.

[0101] Taking the scan shift register Pgate of the scan gate driving circuit PGOA shown in FIG. 5 as an example, referring to FIG. 5, the scan shift register Pgate includes first to eighth transistors T1-T8, and a first capacitor C1 and a second capacitor C2, to provide a scan control signal SC to the pixel driving circuit PDC shown in FIG. 4. The first electrode of the first transistor T1 is electrically connected to a scan input signal terminal PIN, the second electrode of the first transistor T1, the control electrode of the second transistor T2, the second electrode of the seventh transistor T7, and the first electrode of the eighth transistor T8 are mutually electrically connected, the control electrode of the first transistor T1, the first electrode of the second transistor T2, the control electrode of the third transistor T3, and a first scan clock signal terminal are mutually electrically connected; the first transistor T1 is used to be turned on in response to the gating level of the first scan clock signal PCK. The second electrode of the second transistor T2, the second electrode of the third transistor T3, the control electrode of the fourth transistor T4, the control electrode of the sixth transistor T6, and one end of the first capacitor C1 are mutually electrically connected; the second transistor T2 is used to be turned on in response to the gating level on the second electrode of the first transistor T1. The first electrode of the third transistor T3, the control electrode of the eighth transistor T8, and a low-level power supply voltage terminal are mutually electrically connected; the third transistor T3 is used to be turned on in response to the gating level of the first scan clock signal PCK. The first electrode of the fourth transistor T4, the other end of the first capacitor C1, the first electrode of the sixth transistor T6, and a high-level power supply voltage terminal are mutually electrically connected, the second electrode of the fourth transistor T4, the second electrode of the fifth transistor T5, one end of the second capacitor C2, and a scan output terminal POUT are mutually electrically connected; the fourth transistor T4 is used to be turned on in response to the gating level of the second electrode of the third transistor T3. The first electrode of the fifth transistor T5, the control electrode of the seventh transistor T7, and a second scan clock signal terminal are mutually electrically connected, the control electrode of the fifth transistor T5, the second electrode of the eighth transistor T8, and the other end of the second capacitor C2 are mutually electrically connected; the fifth transistor T5 is used to be turned on in response to the gating level of the second electrode of the eighth transistor T8. The second electrode of the sixth transistor T6 is electrically connected to the first electrode of the seventh transistor T7; the sixth transistor T6 is used to be turned on in response to the gating level of the second electrode of the third transistor T3. The seventh transistor T7 is used to be turned on in response to the gating level of the second scan clock signal PCB. The eighth transistor T8 is used to be turned on in response to the low-level power supply voltage VGL. In this example, all the transistors are P-type transistors, and the gating levels of various signals are low levels.

[0102] It should be noted that in the zeroth-level scan shift register Pgate0 of the scan gate driving circuit PGOA, the scan input signal terminal PIN is loaded with a scan start signal PSTV (not shown in FIG. 5).

[0103] Taking the light emitting shift register ESR of the light emitting gate driving circuit EGOA shown in FIG. 6 as an example, referring to FIG. 6, the light emitting shift register ESR includes first to thirteenth transistors T1-T13 and first to third capacitors C1-C3 to provide a light emitting control signal EM to the pixel driving circuit PDC shown in FIG. 4. The first electrode of the first transistor T1 is electrically connected with the light emitting input signal terminal EIN, the second electrode of the first transistor T1, the control electrode of the second transistor T2, the control electrode of the eighth transistor T8, the first electrode of the twelfth transistor T12, the second electrode of the thirteenth transistor T13, and the first node N1 are mutually electrically connected, the control electrode of the first transistor T1, the first electrode of the second transistor T2, the control electrode of the third transistor T3, and the first light emitting clock signal terminal are mutually electrically connected; the first transistor T1 is used to be turned on in response to the gating level of the first light emitting clock signal ECK. The second electrode of the second transistor T2, the second electrode of the third transistor T3, the control electrode of the fifth transistor T5, the first electrode of the eleventh transistor T11, and the second node N2 are mutually electrically connected; the second transistor T2 is used to be turned on in response to the gating level on the second electrode of the first transistor T1. The first electrode of the third transistor T3, the first electrode of the tenth transistor T10, the control electrode of the eleventh transistor T11, the control electrode of the twelfth transistor T12, and the low-level power supply voltage terminal are mutually electrically connected; the third transistor T3 is used to be turned on in response to the gating level of the first light emitting clock signal ECK. The first electrode of the fourth transistor T4, the first electrode of the sixth transistor T6, the control electrode of the seventh transistor T7, and the second light emitting clock signal terminal are mutually electrically connected, the second electrode of the fourth transistor T4, the second electrode of the fifth transistor T5, one end of the third capacitor C3, and the fifth node N5 are mutually electrically connected, the control electrode of the fourth transistor T4, the other end of the third capacitor C3, the control electrode of the tenth transistor T10, the second electrode of the twelfth transistor T12, and the seventh node N7 are electrically connected; the fourth transistor T4 is used to be turned on in response to the gating level of the seventh node N7. The first electrode of the fifth transistor T5, the first electrode of the eighth transistor T8, the first electrode of the ninth transistor T9, the first electrode of the thirteenth transistor T13, one end of the second capacitor C2, and the high-level power supply voltage terminal are mutually electrically connected; the fifth transistor T5 is used to be turned on in response to the gating level of the second node N2. The second electrode of the sixth transistor T6, the first electrode of the seventh transistor T7, one end of the first capacitor C1, and the third node N3 are mutually electrically connected, the control electrode of the sixth transistor T6, the second electrode of the eleventh transistor T11, the other end of the first capacitor C1, and the sixth node N6 are mutually electrically connected; the sixth transistor T6 is used to be turned on in response to the gating level of the sixth node N6. The second electrode of the seventh transistor T7, the second electrode of the eighth transistor T8, the control electrode of the ninth transistor T9, the other end of the second capacitor C2, and the fourth node N4 are mutually electrically connected; the seventh transistor T7 is used to be turned on in response to the gating level of the second light emitting clock signal ECB.The eighth transistor T8 is used for turning on in response to the gating level of the first node N1. The second pole of the ninth transistor T9, the second pole of the tenth transistor T10, and the light emitting output end EOUT are electrically connected with each other; the ninth transistor T9 is used for turning on in response to the gating level of the fourth node N4. The tenth transistor T10 is used for turning on in response to the gating level of the seventh node N7. The eleventh transistor T11 is used for turning on in response to the low-level power supply voltage VGL. The twelfth transistor T12 is used for turning on in response to the low-level power supply voltage VGL. The control pole of the thirteenth transistor T13 is electrically connected with the enable signal end; the thirteenth transistor T13 is used for turning on in response to the enable signal VEL, so that the high-level power supply voltage VGH is loaded to the seventh node N7 to turn off the tenth transistor T10, thereby making the light emitting shift register ESR stop working. In this example, all the transistors are P-type transistors, and the gating levels of various signals are low levels.

[0104] It should be noted that in the first light emitting shift register ESR1 of the light emitting gate driving circuit EGOA, the light emitting input signal end EIN loads a light emitting start signal ESTV (not shown in FIG. 6).

[0105] Referring to FIGS. 7 and 8, the display panel PNL includes a first panel subregion SPNL1 and a second panel subregion SPNL2 arranged in sequence along a first direction DV. The display panel PNL can be foldable at the junction of the first panel subregion SPNL1 and the second panel subregion SPNL2, so that the first panel subregion SPNL1 is a front surface and the second panel subregion SPNL2 is a back surface. The front surface and the back surface are respectively provided with 1000 rows of subpixels Pixel arrayed along the first direction DV. In other words, the display area AA of the first panel subregion SPNL1 is provided with a first row of subpixels Pixel1 to a first thousandth row of subpixels Pixel1000; and the display area AA of the second panel subregion SPNL2 is provided with a first thousand and first row of subpixels Pixel1001 to a second thousandth row of subpixels Pixel2000.

[0106] Referring to FIG. 5 and FIG. 8, the scanning gate driving circuit PGOA and the light-emitting gate driving circuit EGOA are arranged side by side in the peripheral area BB of the display panel PNL. The scanning gate driving circuit PGOA includes a first scanning gate driving circuit PGOA1 for providing the first panel partition SPNL1 with the scanning control signal SC and a second scanning gate driving circuit PGOA2 for providing the second panel partition SPNL2 with the scanning control signal SC. The first scanning gate driving circuit PGOA1 includes the zeroth-stage scanning shift register Pgate0 to the one-thousandth-stage scanning shift register Pgate1000 connected in sequence; the second scanning gate driving circuit PGOA2 includes the one-thousand-and-first-stage scanning shift register Pgate1001 to the two-thousandth-stage scanning shift register Pgate2000 connected in sequence; the zeroth-stage scanning shift register Pgate0 to the one-thousandth-stage scanning shift register Pgate1000 are used to drive the first row of sub-pixels Pixel1 to the one-thousandth row of sub-pixels Pixel1000 of the first panel partition SPNL1; the one-thousand-and-first-stage scanning shift register Pgate1001 to the two-thousandth-stage scanning shift register Pgate2000 are used to drive the one-thousand-and-first row of sub-pixels Pixel1001 to the two-thousandth row of sub-pixels Pixel2000 of the second panel partition SPNL2. Each scanning shift register Pgate corresponds to a row of sub-pixels Pixel one-to-one, and a scanning shift register Pgate and the pixel driving circuit PDC of the corresponding row of sub-pixels Pixel are electrically connected through the scanning control signal line SL, and are electrically connected with the pixel driving circuit PDC of the next row of sub-pixels Pixel through the scanning control signal line SL. In the adjacent two-stage scanning shift registers Pgate of the first scanning gate driving circuit PGOA1, the scanning output terminal POUT of the upper-stage scanning shift register Pgate is electrically connected with the scanning input signal terminal PIN of the lower-stage scanning shift register Pgate. In the adjacent two-stage scanning shift registers Pgate of the second scanning gate driving circuit PGOA2, the scanning output terminal POUT of the upper-stage scanning shift register Pgate is electrically connected with the scanning input signal terminal PIN of the lower-stage scanning shift register Pgate. The one-thousandth-stage scanning shift register Pgate1000 and the one-thousand-and-first-stage scanning shift register Pgate1001 do not constitute a cascaded relationship.

[0107] Referring to FIGS. 6 and 8, the light-emitting gate drive circuit EGOA includes a first light-emitting gate drive circuit EGOA1 for providing the light-emitting control signal EM to the first panel section SPNL1 and a second light-emitting gate drive circuit EGOA2 for providing the light-emitting control signal EM to the second panel section SPNL2. The first light-emitting gate drive circuit EGOA1 includes first to 500th light-emitting shift registers ESR1-ESR500 cascaded in sequence; the second light-emitting gate drive circuit EGOA2 includes 500th to 1,000th light-emitting shift registers ESR501-ESR1000 cascaded in sequence; the first to 500th light-emitting shift registers ESR1-ESR500 are used to drive first to 1,000th rows of sub-pixels Pixel1-Pixel1000 of the first panel section SPNL1; and the 500th to 1,000th light-emitting shift registers ESR501-ESR1000 are used to drive 1,001st to 2,000th rows of sub-pixels Pixel1001-Pixel2000 of the second panel section SPNL2. One light-emitting shift register ESR is electrically connected to the pixel driving circuit PDC of the corresponding adjacent two rows of sub-pixels Pixel through the light-emitting control signal line EMS. In the adjacent two light-emitting shift registers ESR of the first light-emitting gate drive circuit EGOA1, the light-emitting output terminal EOUT of the upper light-emitting shift register ESR is electrically connected to the light-emitting input signal terminal EIN of the lower light-emitting shift register ESR. In the adjacent two light-emitting shift registers ESR of the second light-emitting gate drive circuit EGOA2, the light-emitting output terminal EOUT of the upper light-emitting shift register ESR is electrically connected to the light-emitting input signal terminal EIN of the lower light-emitting shift register ESR. The 500th light-emitting shift register ESR500 and the 500th light-emitting shift register ESR501 do not constitute a cascaded relationship.

[0108] It should be noted that the scan shift register Pgate outputs the first scan control signal SC(n-1) and the second scan control signal SC(n) in the pixel driving circuit PDC shown in FIG. 4, and therefore the zeroth scan shift register Pgate0 is needed to output the first scan control signal SC(n-1) of the pixel driving circuit PDC of the first row of sub-pixels Pixel1. The scan line GL includes the scan control signal line SL for loading the scan control signal SC to the sub-pixel Pixel and the light-emitting control signal line EMS for loading the light-emitting control signal EM to the sub-pixel Pixel.

[0109] Referring to FIG. 5, FIG. 6 and FIG. 8, the peripheral region BB of the display panel PNL is further provided with a first scan start signal wire PSTV1L, a second scan start signal wire PSTV2L, a first scan clock wire PCKL, a second scan clock wire PCBL, a first emission start signal wire ESTV1L, a second emission start signal wire ESTV2L, a first emission clock wire ECKL and a second emission clock wire ECBL extending along the first direction DV. The first scan start signal wire PSTV1L is configured to provide the first scan start signal PSTV1 to the scan input signal end PIN of the zeroth stage scan shift register Pgate0. The second scan start signal wire PSTV2L is configured to provide the second scan start signal PSTV2 to the scan input signal end PIN of the first thousand and first stage scan shift register Pgate1001. The first scan clock wire PCKL and the second scan clock wire PCBL are configured to provide the first scan clock signal PCK and the second scan clock signal PCB to the scan shift register Pgate. The first emission start signal wire ESTV1L is configured to provide the first emission start signal ESTV1 to the emission input signal end EIN of the first stage emission shift register ESR1. The second emission start signal wire ESTV2L is configured to provide the second emission start signal ESTV2 to the emission input signal end EIN of the fifth hundred and first stage emission shift register ESR501. The first emission clock wire ECKL and the second emission clock wire ECBL are configured to provide the first emission clock signal ECK and the second emission clock signal ECB to the emission shift register ESR.

[0110] In this way, the second scan control signal SC(n) can be provided to the pixel driving circuit PDC of the corresponding row of sub-pixels Pixel by the scan shift register Pgate, and the first scan control signal SC(n-1) can be provided to the pixel driving circuit PDC of the next row of sub-pixels Pixel. The emission control signal EM can be provided to the pixel driving circuit PDC of the adjacent two rows of sub-pixels Pixel by the emission shift register ESR, so as to drive the sub-pixels Pixel to emit light. However, in the related art, in the full-screen display mode, the first scan gate driving circuit PGOA1 and the second scan gate driving circuit PGOA2 are independently driven, and the first emission gate driving circuit EGOA1 and the second emission gate driving circuit EGOA2 are independently driven, so that there is no cascading relationship between the first scan gate driving circuit PGOA1 and the second scan gate driving circuit PGOA2, and there is no cascading relationship between the first emission gate driving circuit EGOA1 and the second emission gate driving circuit EGOA2. Therefore, some stubborn defects, such as low gray scale black lines, are prone to occur at the junction of the first panel partition SPNL1 and the second panel partition SPNL2, thereby affecting the display quality of the display panel PNL.

[0111] To solve the above problems, in one embodiment of the present disclosure, referring to FIG. 9, the display panel PNL includes a plurality of panel sub-zones SPNL arranged in sequence along a first direction DV. The display panel PNL includes at least one gate drive circuit GOA, and the gate drive circuit GOA includes a plurality of sub-gate drive circuits SGOA respectively located in the panel sub-zones SPNL. The gate drive circuit GOA includes a parallel gate drive circuit AGOA, which can be a scan gate drive circuit PGOA, an emission gate drive circuit EGOA, a reset gate drive circuit, etc. In adjacent two sub-gate drive circuits SGOA of the same parallel gate drive circuit AGOA, the output end of the last stage shift register SR of the previous sub-gate drive circuit SGOA is electrically connected to the input end of the first stage shift register SR of the next sub-gate drive circuit SGOA through a first control sub-circuit CC1; when the first control sub-circuit CC1 is turned on, the output end of the last stage shift register SR of the previous sub-gate drive circuit SGOA is electrically connected to the input end of the first stage shift register SR of the next sub-gate drive circuit SGOA through the first control sub-circuit CC1. In this way, the adjacent two sub-gate drive circuits SGOA are electrically connected through the first control sub-circuit CC1, and when full-screen display is needed, the first control sub-circuit CC1 is turned on, so that the last stage shift register SR of the previous sub-gate drive circuit SGOA and the first stage shift register SR of the next sub-gate drive circuit SGOA form a cascade relationship, so as to facilitate the normal output of the gate drive circuit GOA, and the possibility of low gray scale black lines at the junction of the adjacent two panel sub-zones SPNL can be reduced, and the display quality of the display panel PNL can be improved.

[0112] In the embodiment of the present disclosure, one gate drive circuit GOA includes a plurality of shift registers SR connected in sequence. Between adjacent two shift registers SR of the same gate drive circuit GOA, no shift register SR of other gate drive circuit GOA can be arranged, or shift registers SR of other gate drive circuits GOA can be arranged as needed.

[0113] In one example, the shift registers SR of the at least one gate drive circuit GOA are arranged linearly along the first direction DV and connected in sequence; and between adjacent two shift registers SR of the gate drive circuit GOA, no shift register SR of other gate drive circuit GOA is arranged.

[0114] In another example, the shift registers SR of the at least one gate drive circuit GOA are arranged linearly along the first direction DV, and the shift registers SR of other gate drive circuits GOA are arranged between any two adjacent shift registers SR of the at least one gate drive circuit GOA. In other words, the shift registers SR arranged linearly along the first direction DV can belong to different gate drive circuits GOA, and the shift registers SR of the gate drive circuits GOA can be arranged alternately.

[0115] For example, the shift registers SR of four gate drive circuits GOA are arranged linearly along the first direction DV and alternately. The kth shift register SR of the mth gate drive circuit GOA is denoted as GOA(m)-SR(k). The arrangement order of the shift registers SR of the four gate drive circuits GOA is GOA(1)-SR(1), GOA(2)-SR(1), GOA(3)-SR(1), GOA(4)-SR(1), GOA(1)-SR(2), GOA(2)-SR(2), GOA(3)-SR(2), GOA(4)-SR(2), …, GOA(1)-SR(i), GOA(2)-SR(i), GOA(3)-SR(i), GOA(4)-SR(i), GOA(1)-SR(i+1), GOA(2)-SR(i+1), GOA(3)-SR(i+1), GOA(4)-SR(i+1), where m, k, i are integers greater than 0. For example, m, k, i can be 1, 2, 3, 4, 5, 6, etc. GOA(1)-SR(1), GOA(1)-SR(2), …, GOA(1)-SR(i), GOA(1)-SR(i+1), etc. are cascaded in turn until the last shift register SR of the first gate drive circuit GOA, forming the first gate drive circuit GOA; similarly, GOA(2)-SR(1), GOA(2)-SR(2), …, GOA(2)-SR(i), GOA(2)-SR(i+1), etc. are cascaded in turn until the last shift register SR of the second gate drive circuit GOA, forming the second gate drive circuit GOA; GOA(3)-SR(1), GOA(3)-SR(2), …, GOA(3)-SR(i), GOA(3)-SR(i+1), etc. are cascaded in turn until the last shift register SR of the third gate drive circuit GOA, forming the third gate drive circuit GOA; GOA(4)-SR(1), GOA(4)-SR(2), …, GOA(4)-SR(i), GOA(4)-SR(i+1), etc. are cascaded in turn until the last shift register SR of the fourth gate drive circuit GOA, forming the fourth gate drive circuit GOA.

[0116] In this example, four gate drive circuits GOA are formed by the same shift register column. It can be understood that the same shift register column can form other numbers of gate drive circuits GOA, for example, 2 gate drive circuits GOA, 3 gate drive circuits GOA, 5 gate drive circuits GOA, or 6 gate drive circuits GOA, etc.

[0117] In an embodiment of the present disclosure, the first control sub-circuit CC1 includes one P-type transistor; or includes a plurality of P-type transistors connected in series; or includes one N-type transistor; or includes a plurality of N-type transistors connected in series. In one example, the first control sub-circuit CC1 includes two or three P-type transistors connected in series. In another example, the first control sub-circuit CC1 includes two or three N-type transistors connected in series. In this way, by turning on and off one or more transistors, the cascade relationship between the last stage shift register SR of the previous sub-gate drive circuit SGOA and the first stage shift register SR of the next sub-gate drive circuit SGOA can be maintained or cut off in the adjacent two panel partitions SPNL, to adapt to different display modes.

[0118] In an embodiment of the present disclosure, the input end of the first stage shift register SR of the xthsub-gate drive circuit SGOA is electrically connected with the xthstart signal STV through the second control sub-circuit CC2; wherein x is an integer greater than 1, for example, x is 2, 3, 4, etc. The maximum value of x is y, and y is the number of panel partitions SPNL. In this way, by turning on the second control sub-circuit CC2, the xthstart signal STV can be loaded to the first stage shift register SR of the sub-gate drive circuit SGOA, to adapt to the mode of displaying only the xthpanel partition SPNL.

[0119] In an embodiment of the present disclosure, the second control sub-circuit CC2 includes one P-type transistor; or includes a plurality of P-type transistors connected in series; or includes one N-type transistor; or includes a plurality of N-type transistors connected in series. In one example, the second control sub-circuit CC2 includes two or three P-type transistors connected in series. In another example, the second control sub-circuit CC2 includes two or three N-type transistors connected in series. In this way, by turning on one or more transistors, the start signal STV is loaded to the first stage shift register SR of the corresponding sub-gate drive circuit SGOA, to adapt to different display modes.

[0120] In an embodiment of the present disclosure, referring to FIG. 9, the display panel PNL is provided with a control wire set LS corresponding to the parallel gate driving circuit AGOA. The control wire set LS includes a first control wire L1 for controlling the first control sub-circuit CC1 of the corresponding parallel gate driving circuit AGOA and a second control wire L2 for controlling the second control sub-circuit CC2 of the corresponding parallel gate driving circuit AGOA. The transistors of the first control sub-circuit CC1 and the second control sub-circuit CC2 are of the same type; for example, the transistors of the first control sub-circuit CC1 and the second control sub-circuit CC2 are all P-type transistors or N-type transistors. The first control wire L1 is electrically connected to the control end of the first control sub-circuit CC1; the second control wire L2 is electrically connected to the control end of the second control sub-circuit CC2. In this way, the first control sub-circuit CC1 can be controlled to be turned on or turned off by loading the first control sub-circuit CC1 with a gating level or an off level on the first control wire L1, and the second control sub-circuit CC2 can be controlled to be turned on or turned off by loading the second control sub-circuit CC2 with a gating level or an off level on the second control wire L2.

[0121] In an embodiment of the present disclosure, referring to FIG. 9, the transistors of the first control sub-circuit CC1 and the second control sub-circuit CC2 are of opposite types; for example, the transistors of the first control sub-circuit CC1 are P-type transistors, and the transistors of the second control sub-circuit CC2 are N-type transistors; or the transistors of the first control sub-circuit CC1 are N-type transistors, and the transistors of the second control sub-circuit CC2 are P-type transistors. The display panel PNL is provided with a common control wire LL corresponding to the parallel gate driving circuit AGOA, which is used to control the first control sub-circuit CC1 and the second control sub-circuit CC2 of the corresponding parallel gate driving circuit AGOA. The common control wire LL, the control end of the first control sub-circuit CC1, and the control end of the second control sub-circuit CC2 are electrically connected to each other. In this way, the transistors of the first control sub-circuit CC1 and the second control sub-circuit CC2 are of opposite types, and the common control wire LL can be used to control the turn-on and turn-off of the first control sub-circuit CC1 and the second control sub-circuit CC2, so as to reduce the number of wires and facilitate the narrow-frame design of the display panel PNL.

[0122] In an embodiment of the present disclosure, the display panel PNL is provided with a plurality of parallel gate driving circuits AGOA. The first control wires L1 corresponding to each parallel gate driving circuit AGOA are the same wire, and the second control wires L2 corresponding to each parallel gate driving circuit AGOA can not be the same wire; or the second control wires L2 corresponding to each parallel gate driving circuit AGOA are the same wire, and the first control wires L1 corresponding to each parallel gate driving circuit AGOA can not be the same wire; or the first control wires L1 and the second control wires L2 of each parallel gate driving circuit AGOA are the same wire. In this way, the number of wires can be further reduced, and the narrow frame design of the display panel PNL is facilitated.

[0123] In an embodiment of the present disclosure, the display panel PNL is provided with a plurality of parallel gate driving circuits AGOA. The common control wires LL of each parallel gate driving circuit AGOA are the same wire. In this way, the number of wires of the display panel PNL is further reduced.

[0124] In an embodiment of the present disclosure, in the same parallel gate driving circuit AGOA, the input end of the first-stage shift register SR of the xth sub-gate driving circuit SGOA is only electrically connected to the output end of the last-stage shift register SR of the (x-1)th sub-gate driving circuit SGOA through the first control sub-circuit CC1; wherein x is an integer greater than 1, for example, x can be 2, 3, 4, and the like. The maximum value of x is y, and y is the number of panel partitions SPNL.

[0125] In an embodiment of the present disclosure, referring to FIG. 9, the input end of the first-stage shift register SR of the xth sub-gate driving circuit SGOA is electrically connected to the first power voltage V1 through the second control sub-circuit CC2. The level of the first power voltage V1 is opposite to the effective level of the scan signal output by the parallel gate driving circuit AGOA. In one example, when the effective level of the scan signal output by the parallel gate driving circuit AGOA is high, the first power voltage V1 is low. In another example, when the effective level of the scan signal output by the parallel gate driving circuit AGOA is low, the first power voltage V1 is high. Wherein x is an integer greater than 1, for example, x can be 2, 3, 4, and the like. The maximum value of x is y, and y is the number of panel partitions SPNL. In this way, electrically connecting the input end of the first-stage shift register SR of the xth sub-gate driving circuit SGOA to the first power voltage V1 can reduce the number of start signal wires, which is conducive to the narrow frame design of the display panel PNL.

[0126] It can be understood that the effective level of the scanning signal refers to a level capable of turning on the transistor in the pixel driving circuit PDC. In an example, when the transistor of the pixel driving circuit PDC is a P-type transistor, the effective level of the scanning signal is a low level. In another example, when the transistor of the pixel driving circuit PDC is an N-type transistor, the effective level of the scanning signal is a high level.

[0127] In an embodiment of the present disclosure, the display panel PNL includes at least two parallel gate driving circuits AGOA, and the number of shift registers SR of the two parallel gate driving circuits AGOA is different. For example, the number of parallel gate driving circuits AGOA can be two, three, four, and the like. Among them, the number of shift registers SR of any two parallel gate driving circuits AGOA can be the same or different. For example, one level of shift register SR can drive two rows of adjacent sub-pixels Pixel; one level of shift register SR can drive two rows of sub-pixels Pixel apart; or one level of shift register SR can drive one row of sub-pixels Pixel.

[0128] In an embodiment of the present disclosure, the parallel gate driving circuit AGOA includes a scanning gate driving circuit PGOA for outputting a scanning control signal SC, and the scanning output end POUT of each shift register SR of the scanning gate driving circuit PGOA is used for electrical connection with the scanning control signal line SL.

[0129] In an embodiment of the present disclosure, the parallel gate driving circuit AGOA includes a light-emitting gate driving circuit EGOA for outputting a light-emitting control signal EM, and the light-emitting output end EOUT of each shift register SR of the light-emitting gate driving circuit EGOA is used for electrical connection with the light-emitting control signal line EMS.

[0130] In an embodiment of the present disclosure, the first control sub-circuit CC1 and the second control sub-circuit CC2 each include two or three series-connected transistors. In an example, the first control sub-circuit CC1 and the second control sub-circuit CC2 each include two or three series-connected P-type transistors. In another example, the first control sub-circuit CC1 and the second control sub-circuit CC2 each include two or three series-connected N-type transistors. In other examples, the first control sub-circuit CC1 includes two or three series-connected P-type transistors; the second control sub-circuit CC2 includes two or three series-connected N-type transistors. Alternatively, the first control sub-circuit CC1 includes two or three series-connected N-type transistors; the second control sub-circuit CC2 includes two or three series-connected P-type transistors. By increasing the number of transistors, when the first control sub-circuit CC1 or the second control sub-circuit CC2 needs to be turned off, the first control sub-circuit CC1 and the second control sub-circuit CC2 can be completely turned off to reduce the influence of the leakage current.

[0131] It should be noted that in the present disclosure, two P-type transistors in series refer to that the control electrodes of the two P-type transistors are electrically connected. Similarly, two N-type transistors in series refer to that the control electrodes of the two N-type transistors are electrically connected. Referring to FIG. 10, the orthogonal projection of the gate layer GT and the orthogonal projection of the semiconductor layer SCL have two overlapping regions, and one overlapping region corresponds to the orthogonal projection of one P-type transistor. FIG. 11 is a sectional view along AA' in FIG. 10, and referring to FIG. 11, the P-type transistor includes the semiconductor layer SCL, the gate insulating layer GI and the gate layer GT which are sequentially stacked and arranged adjacent to each other. Similarly, two N-type transistors in series (not shown in the figure) are similar to this.

[0132] It should be further noted that in the present disclosure, three P-type transistors in series refer to that the control electrodes of the three P-type transistors are electrically connected to each other. Similarly, three N-type transistors in series refer to that the control electrodes of the three N-type transistors are electrically connected to each other. Referring to FIG. 12, the orthogonal projection of the gate layer GT and the orthogonal projection of the semiconductor layer SCL have three overlapping regions, and one overlapping region corresponds to the orthogonal projection of one P-type transistor. FIG. 13 is a sectional view along BB' in FIG. 12, and referring to FIG. 13, the P-type transistor includes the semiconductor layer SCL, the gate insulating layer GI and the gate layer GT which are sequentially stacked and arranged adjacent to each other. Similarly, three N-type transistors in series (not shown in the figure) are similar to this.

[0133] The display panel PNL of the present disclosure will be described in detail below in combination with four examples.

[0134] In the first example, referring to FIG. 14, the display panel PNL includes the first panel sub-region SPNL1 and the second panel sub-region SPNL2 which are arranged in the first direction DV in sequence, and the display panel PNL can be foldable at the junction of the first panel sub-region SPNL1 and the second panel sub-region SPNL2 so that the first panel sub-region SPNL1 is the front surface and the second panel sub-region SPNL2 is the back surface. The display area AA of the first panel sub-region SPNL1 is provided with the first row of sub-pixels Pixel1 to the first thousandth row of sub-pixels Pixel1000; and the display area AA of the second panel sub-region SPNL2 is provided with the first thousandth and first row of sub-pixels Pixel1001 to the second thousandth row of sub-pixels Pixel2000.

[0135] The scan gate driving circuit PGOA and the emission gate driving circuit EGOA are arranged side by side in the peripheral area BB of the display panel PNL. The scan gate driving circuit PGOA includes the first scan gate driving circuit PGOA1 for providing the scan control signal SC to the first panel sub-region SPNL1 and the second scan gate driving circuit PGOA2 for providing the scan control signal SC to the second panel sub-region SPNL2.

[0136] The first scan gate drive circuit PGOA1 includes the zeroth stage scan shift register Pgate0 to the first thousand stage scan shift register Pgate1000 which are cascaded in sequence; the second scan gate drive circuit PGOA2 includes the first thousand and one stage scan shift register Pgate1001 to the second thousand stage scan shift register Pgate2000 which are cascaded in sequence; the zeroth stage scan shift register Pgate0 to the first thousand stage scan shift register Pgate1000 are used to drive the first row of sub-pixels Pixel1 to the first thousand row of sub-pixels Pixel1000 of the first panel partition SPNL1; the first thousand and one stage scan shift register Pgate1001 to the second thousand stage scan shift register Pgate2000 are used to drive the first thousand and one row of sub-pixels Pixel1001 to the second thousand row of sub-pixels Pixel2000 of the second panel partition SPNL2. Each scan shift register Pgate corresponds to each row of sub-pixels Pixel one by one, one scan shift register Pgate and the pixel driving circuit PDC of the corresponding row of sub-pixels Pixel are electrically connected through the scan control signal line SL, and are electrically connected with the pixel driving circuit PDC of the next row of sub-pixels Pixel through the scan control signal line SL. In the adjacent two stage scan shift registers Pgate of the first scan gate drive circuit PGOA1, the scan output end POUT of the upper stage scan shift register Pgate is electrically connected with the scan input signal end PIN of the lower stage scan shift register Pgate. In the adjacent two stage scan shift registers Pgate of the second scan gate drive circuit PGOA2, the scan output end POUT of the upper stage scan shift register Pgate is electrically connected with the scan input signal end PIN of the lower stage scan shift register Pgate. The scan output end POUT of the first thousand stage scan shift register Pgate1000 is electrically connected with the IN of the first thousand and one stage scan shift register Pgate1001 through two series first transistors T1.

[0137] The light-emitting gate drive circuit EGOA includes a first light-emitting gate drive circuit EGOA1 for providing the light-emitting control signal EM to the first panel partition SPNL1 and a second light-emitting gate drive circuit EGOA2 for providing the light-emitting control signal EM to the second panel partition SPNL2. The first light-emitting gate drive circuit EGOA1 includes a first-stage light-emitting shift register ESR1 to a 500th-stage light-emitting shift register ESR500 cascaded in sequence; the second light-emitting gate drive circuit EGOA2 includes a 500th-stage light-emitting shift register ESR501 to a 1000th-stage light-emitting shift register ESR1000 cascaded in sequence; the first-stage light-emitting shift register ESR1 to the 500th-stage light-emitting shift register ESR500 are used to drive the first row of sub-pixels Pixel1 to the 1000th row of sub-pixels Pixel1000 of the first panel partition SPNL1; the 500th-stage light-emitting shift register ESR501 to the 1000th-stage light-emitting shift register ESR1000 are used to drive the 1001st row of sub-pixels Pixel1001 to the 2000th row of sub-pixels Pixel2000 of the second panel partition SPNL2. One light-emitting shift register ESR is electrically connected to the pixel driving circuit PDC of the corresponding adjacent two rows of sub-pixels Pixel through the light-emitting control signal line EMS. In the adjacent two-stage light-emitting shift registers ESR of the first light-emitting gate drive circuit EGOA1, the light-emitting output end EOUT of the upper-stage light-emitting shift register ESR is electrically connected to the light-emitting input signal end EIN of the lower-stage light-emitting shift register ESR. In the adjacent two-stage light-emitting shift registers ESR of the second light-emitting gate drive circuit EGOA2, the light-emitting output end EOUT of the upper-stage light-emitting shift register ESR is electrically connected to the light-emitting input signal end EIN of the lower-stage light-emitting shift register ESR. The light-emitting output end EOUT of the 500th-stage light-emitting shift register ESR500 is electrically connected to the light-emitting input signal end EIN of the 500th-stage light-emitting shift register ESR501 through two series-connected third transistors T3.

[0138] It should be noted that the scan shift register Pgate outputs the first scan control signal SC(n-1) and the second scan control signal SC(n) in the pixel driving circuit PDC shown in FIG. 4, so the zeroth-stage scan shift register Pgate0 is needed to output the first scan control signal SC(n-1) of the pixel driving circuit PDC of the first row of sub-pixels Pixel1; the scan line GL includes the scan control signal line SL and the light-emitting control signal line EMS.

[0139] Referring to FIG. 14, the peripheral area BB of the display panel PNL is also provided with a first scan start signal wire PSTV1L, a second scan start signal wire PSTV2L, a first scan clock wire PCKL, a second scan clock wire PCBL, a first scan control wire L11, a second scan control wire L21, a first emission start signal wire ESTV1L, a second emission start signal wire ESTV2L, a first emission clock wire ECKL, a second emission clock wire ECBL, a first emission control wire L12, and a second emission control wire L22 extending along the first direction DV. The first scan start signal wire PSTV1L is electrically connected to the scan input signal end PIN of the zeroth-stage scan shift register Pgate0; the second scan start signal wire PSTV2L is electrically connected to the scan input signal end PIN of the first thousand and first-stage scan shift register Pgate1001 through two series-connected second transistors T2; the first scan clock wire PCKL and the second scan clock wire PCBL are used to provide the first scan clock signal PCK and the second scan clock signal PCB to the scan shift register Pgate. The first scan control wire L11 is electrically connected to the control electrode of the two series-connected first transistors T1; the second scan control wire L21 is electrically connected to the control electrode of the two series-connected second transistors T2.

[0140] The first emission start signal wire ESTV1L is used to provide the first emission start signal ESTV1 to the emission input signal end EIN of the first-stage emission shift register ESR1; the second emission start signal wire ESTV2L is electrically connected to the emission input signal end EIN of the fifth thousand and first-stage emission shift register ESR501 through two series-connected fourth transistors T4; the first emission clock wire ECKL and the second emission clock wire ECBL are used to provide the first emission clock signal ECK and the second emission clock signal ECB to the emission shift register ESR; the first emission control wire L12 is electrically connected to the control electrode of the two series-connected third transistors T3; the second emission control wire L22 is electrically connected to the control electrode of the two series-connected fourth transistors T4.

[0141] FIGS. 15 and 16 are driving timing diagrams of the signals loaded on the control wires of the display panel PNL shown in FIG. 14. The signals loaded on the first scan control wire L11, the first emission control wire L12, the second scan control wire L21, and the second emission control wire L22 have a turn-on voltage of -10 V and a turn-off voltage of 10 V. The first scan start signal PSTV1, the second scan start signal PSTV2, the first emission start signal ESTV1, and the second emission start signal ESTV2 have a turn-on voltage of -7 V and a turn-off voltage of 7 V.

[0142] Referring to FIGS. 14-16, when full screen display, the first scan start signal PSTV1 is loaded to the zeroth stage scan shift register Pgate0, the gating level of the signal of the first scan control line L11 is loaded to the control electrode of the two first transistors T1, the two first transistors T1 are turned on, the signal of the second scan control line L21 is loaded to the control electrode of the two second transistors T2, the two second transistors T2 are turned off, the first thousand stage scan shift register Pgate1000 is cascaded with the first thousand and one stage scan shift register Pgate1001, the second scan gate drive circuit PGOA2 starts to work. The first light-emitting start signal ESTV1 is loaded to the first stage light-emitting shift register ESR1, the gating level of the signal of the first light-emitting control line L12 is loaded to the control electrode of the two third transistors T3, the two third transistors T3 are turned on, the signal of the second light-emitting control line L22 is loaded to the control electrode of the two fourth transistors T4, the two fourth transistors T4 are turned off, the fifth hundred stage light-emitting shift register ESR500 is cascaded with the fifth hundred and one stage light-emitting shift register ESR501, the second light-emitting gate drive circuit EGOA2 starts to work, and the full screen display of the display panel PNL is facilitated.

[0143] Referring to FIGS. 14-16, in the front-only display mode, the first scan start signal PSTV1 is loaded to the gating level of the zeroth scan shift register Pgate0, so that the first scan gate drive circuit PGOA1 starts to work; the signal of the first scan control line L11 is loaded to the off level of the control electrode of the two first transistors T1, so that the two first transistors T1 are turned off, the signal of the second scan control line L21 is loaded to the gating level of the control electrode of the two second transistors T2, so that the two second transistors T2 are turned on, thereby cutting off the cascade relationship between the first thousandth scan shift register Pgate1000 and the first thousandth scan shift register Pgate1001, so that the off level of the second scan start signal PSTV2 is loaded to the scan input signal end PIN of the first thousandth scan shift register Pgate1001, and then the second scan gate drive circuit PGOA2 stops to work. The first light-emitting start signal ESTV1 is loaded to the gating level of the first light-emitting shift register ESR1, so that the first light-emitting gate drive circuit EGOA1 starts to work; the signal of the first light-emitting control line L12 is loaded to the off level of the control electrode of the two third transistors T3, so that the two third transistors T3 are turned off, the signal of the second light-emitting control line L22 is loaded to the on level of the control electrode of the two fourth transistors T4, so that the two fourth transistors T4 are turned on, thereby cutting off the cascade relationship between the fifth thousandth light-emitting shift register ESR500 and the fifth thousandth light-emitting shift register ESR501, so that the off level of the second light-emitting start signal ESTV2 is loaded to the light-emitting input signal end EIN of the fifth thousandth light-emitting shift register ESR501, and then the second light-emitting gate drive circuit EGOA2 stops to work, so as to realize the front-only display mode of the display panel PNL.

[0144] Referring to FIGS. 14-16, when only back display, the first scan start signal PSTV1 is loaded to the zeroth level scan shift register Pgate0 to make the first scan gate drive circuit PGOA1 stop working; the signal of the first scan control line L11 is loaded to the control electrode of the two first transistors T1 to make the two first transistors T1 cut off, the signal of the second scan control line L21 is loaded to the control electrode of the two second transistors T2 to make the two second transistors T2 conduct, thereby cutting off the cascade relationship between the first thousand level scan shift register Pgate1000 and the first thousand zero level scan shift register Pgate1001, making the second scan start signal PSTV2 be loaded to the scan input signal end PIN of the first thousand zero level scan shift register Pgate1001, and then making the second scan gate drive circuit PGOA2 start working. The first emitting start signal ESTV1 is loaded to the first level emitting shift register ESR1 to make the first emitting gate drive circuit EGOA1 stop working; the signal of the first emitting control line L12 is loaded to the control electrode of the two third transistors T3 to make the two third transistors T3 cut off, the signal of the second emitting control line L22 is loaded to the control electrode of the two fourth transistors T4 to make the two fourth transistors T4 conduct, thereby cutting off the cascade relationship between the fifth hundred level emitting shift register ESR500 and the fifth hundred zero level emitting shift register ESR501, making the second emitting start signal ESTV2 be loaded to the emitting input signal end EIN of the fifth hundred zero level emitting shift register ESR501, and then making the second emitting gate drive circuit EGOA2 start working, to realize the only back display mode of the display panel PNL.

[0145] In this example, each transistor is a P-type transistor. The gate-on signal of each signal is low. The gate-off signal of each signal is high. The scan level output by the B-gate drive circuit GOA and the light-emitting gate drive circuit EGOA is low. In another example, referring to FIGS. 17 and 18, the difference between this example and the first example is that, for the display panel PNL in full-screen display and front-only display, the second scan start signal PSTV2 and the second light-emitting start signal ESTV2 can be replaced by the first power voltage V1, so that even if the second transistor T2 and the fourth transistor T4 are turned on, the first thousandth-level scan shift register Pgate1001 and the fifth hundredth-level light-emitting shift register ESR501 will not be started, so that the back surface is always in a non-display state, so as to realize front-only display of the display panel PNL. Among them, the first power voltage V1 is a high-level power voltage VGH, and the high-level power voltage VGH = 7V. In other examples, referring to FIGS. 19 and 20, the difference between this example and the first example is that, for the display panel PNL in full-screen display and front-only display, the second scan start signal line PSTV2L, the second light-emitting start signal line ESTV2L, the second transistor T2 and the fourth transistor T4 can be cancelled, so that the first light-emitting control line L12 and the second light-emitting control line L22 are also cancelled, so as to reduce the number of lines and transistors, and facilitate the narrow frame design of the display panel PNL. In still other examples, the difference between this example and the first example is that the number of the first transistor T1, the second transistor T2, the third transistor T3 and the fourth transistor T4 can each be three.

[0146] In a second example, referring to FIGS. 21-23, the difference between this example and the first example is that each transistor (except for the transistors in the gate driving circuit GOA and the pixel driving circuit PDC) is an N-type transistor. The enablement of each signal (except for the signals in the gate driving circuit GOA and the pixel driving circuit PDC) is a high level. The disablement of each signal (except for the signals in the gate driving circuit GOA and the pixel driving circuit PDC) is a low level. The enablement of the signals loaded on the first scan control wire L11, the first light-emitting control wire L12, the second scan control wire L21, and the second light-emitting control wire L22 is 10 V, and the disablement is -10 V. In another example, referring to FIGS. 24 and 25, the difference between this example and the second example is that, for the display panel PNL in full-screen display and front-only display, the second scan start signal PSTV2 and the second light-emitting start signal ESTV2 can be replaced by the first power voltage V1, so that the first thousand and one-stage scan shift register Pgate1001 and the fifth hundred and one-stage light-emitting shift register ESR501 are not started even if the second transistor T2 and the fourth transistor T4 are turned on, so that the back is always in a non-display state, so as to realize front-only display of the display panel PNL. Among them, the first power voltage V1 is a high-level power voltage VGH, and the high-level power voltage VGH = 7 V. In other examples, referring to FIGS. 26 and 27, the difference between this example and the second example is that, for the display panel PNL in full-screen display and front-only display, the second scan start signal wire PSTV2L, the second light-emitting start signal wire ESTV2L, the second transistor T2, and the fourth transistor T4 can be cancelled, so that the first light-emitting control wire L12 and the second light-emitting control wire L22 are also cancelled, so as to reduce the number of wires and transistors, and facilitate the narrow frame design of the display panel PNL. In still other examples, the difference between this example and the second example is that the number of the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 can each be three.

[0147] In a third example, referring to FIGS. 28-30, the difference between this example and the first example is that the first transistor T1 and the third transistor T3 (except for the transistors in the gate drive circuit GOA and the pixel drive circuit PDC) are P-type transistors, and the second transistor T2 and the fourth transistor T4 (except for the transistors in the gate drive circuit GOA and the pixel drive circuit PDC) are N-type transistors. For the N-type transistor, the gating level of the control electrode is 10V, and the cutoff level is -10V; for the P-type transistor, the gating level of the control electrode is -10V, and the cutoff level is 10V. The control electrodes of the two first transistors T1 and the two second transistors T2 are electrically connected to the first common control wire LL1, and the control electrodes of the two third transistors T3 and the two fourth transistors T4 are electrically connected to the second common control wire LL2. The signals loaded on the first common control wire LL1 and the second common control wire LL2 are ±10V. In another example, referring to FIGS. 31 and 32, the difference between this example and the third example is that for the full-screen display and the front-only display display panel PNL, the second scan start signal PSTV2 and the second light-emitting start signal ESTV2 can be replaced by the first power voltage V1, so that even if the second transistor T2 and the fourth transistor T4 are turned on, the first thousandth-level scan shift register Pgate1001 and the fifth hundredth-level light-emitting shift register ESR501 will not be started, so that the back is always in a non-display state, so as to realize the front-only display of the display panel PNL. Among them, the first power voltage V1 is the high-level power voltage VGH, and the high-level power voltage VGH = 7V. In other examples, referring to FIGS. 33 and 34, the difference between this example and the third example is that for the full-screen display and the front-only display display panel PNL, the second scan start signal wire PSTV2L, the second light-emitting start signal wire ESTV2L, the second transistor T2 and the fourth transistor T4 can be cancelled, and thus the first light-emitting control wire L12 and the second light-emitting control wire L22 are also cancelled, so as to reduce the number of wires and transistors, and facilitate the narrow frame design of the display panel PNL. In still other examples, the difference between this example and the third example is that the number of the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 can be three.

[0148] In a fourth example, referring to FIGS. 35-37, the difference between this example and the first example is that the first transistor T1 and the third transistor T3 (except for the transistors in the gate drive circuit GOA and the pixel drive circuit PDC) are both P-type transistors, and the second transistor T2 and the fourth transistor T4 (except for the transistors in the gate drive circuit GOA and the pixel drive circuit PDC) are both N-type transistors. For the N-type transistor, the gating level of the control electrode is 10V, and the cutoff level is -10V; for the P-type transistor, the gating level of the control electrode is -10V, and the cutoff level is 10V. The control electrodes of the two first transistors T1, the two second transistors T2, the two third transistors T3, and the two fourth transistors T4 are all electrically connected to the common control wire LL. The signal loaded on the common control wire LL is ±10V. In another example, referring to FIGS. 38 and 39, the difference between this example and the fourth example is that for the display panel PNL in full-screen display and front-only display, the second scan start signal PSTV2 and the second light-emitting start signal ESTV2 can be replaced by the first power voltage V1, so that even if the second transistor T2 and the fourth transistor T4 are turned on, the first thousandth-level scan shift register Pgate1001 and the fifth hundredth-level light-emitting shift register ESR501 will not be started, so that the back surface is always in a non-display state, so as to realize the front-only display of the display panel PNL. Among them, the first power voltage V1 is the high-level power voltage VGH, and the high-level power voltage VGH = 7V. In other examples, referring to FIGS. 40 and 41, the difference between this example and the fourth example is that for the display panel PNL in full-screen display and front-only display, the second scan start signal wire PSTV2L, the second light-emitting start signal wire ESTV2L, the second transistor T2, and the fourth transistor T4 can be cancelled, so that the first light-emitting control wire L12 and the second light-emitting control wire L22 are also cancelled, so as to reduce the number of wires and transistors, and facilitate the narrow frame design of the display panel PNL. In still other examples, the difference between this example and the fourth example is that the number of the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 can all be three.

[0149] Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the features disclosed herein. It is intended that the specification and examples be considered as exemplary only, with the true scope and spirit of the disclosure being indicated by the following claims.

Claims

1. A display panel, wherein, The display panel comprises a plurality of panel partitions arranged in sequence along a first direction; the display panel comprises at least one gate drive circuit, and the gate drive circuit comprises a sub-gate drive circuit in each of the panel partitions; The gate drive circuit comprises a parallel gate drive circuit; in two adjacent sub-gate drive circuits of the same parallel gate drive circuit, the output end of the last stage shift register of the previous sub-gate drive circuit is electrically connected to the input end of the first stage shift register of the next sub-gate drive circuit through a first control sub-circuit.

2. The display panel of claim 1, wherein, The first control sub-circuit comprises a P-type transistor, or a plurality of series-connected P-type transistors, or a N-type transistor, or a plurality of series-connected N-type transistors.

3. The display panel of claim 1, wherein, The input end of the first stage shift register of the xth sub-gate drive circuit is electrically connected to the xth start signal through a second control sub-circuit; wherein x is an integer greater than 1.

4. The display panel of claim 3, wherein, The second control sub-circuit comprises a P-type transistor, or a plurality of series-connected P-type transistors, or a N-type transistor, or a plurality of series-connected N-type transistors.

5. The display panel of claim 3, wherein, The display panel is provided with a control wire group corresponding to the parallel gate drive circuit, the control wire group comprising a first control wire for controlling the first control sub-circuit of the corresponding parallel gate drive circuit and a second control wire for controlling the second control sub-circuit of the corresponding parallel gate drive circuit; The transistor types of the first control sub-circuit and the second control sub-circuit are the same; The first control wire is electrically connected to the control end of the first control sub-circuit; and the second control wire is electrically connected to the control end of the second control sub-circuit.

6. The display panel of claim 3, wherein, The transistor types of the first control sub-circuit and the second control sub-circuit are opposite; The display panel is provided with a common control wire corresponding to the parallel gate drive circuit, the common control wire being used for controlling the first control sub-circuit and the second control sub-circuit of the corresponding parallel gate drive circuit; The common control wire, the control end of the first control sub-circuit, and the control end of the second control sub-circuit are electrically connected to each other.

7. The display panel of claim 5, wherein, The display panel is provided with a plurality of parallel gate drive circuits; The first control wire corresponding to each parallel gate drive circuit is the same wire; or the second control wire corresponding to each parallel gate drive circuit is the same wire; or the first control wire and the second control wire of each parallel gate drive circuit are the same wire.

8. The display panel of claim 6, wherein, The display panel is provided with a plurality of parallel gate drive circuits; The common control wire corresponding to each parallel gate drive circuit is the same wire.

9. The display panel of claim 1, wherein, In the same parallel gate drive circuit, the input end of the first stage shift register of the xth sub-gate drive circuit is electrically connected to the output end of the last stage shift register of the x-1th sub-gate drive circuit only through the first control sub-circuit; wherein x is an integer greater than 1.

10. The display panel of claim 1, wherein, An input end of a first stage shift register of the xth sub-gate drive circuit is electrically connected with a first power voltage through a second control sub-circuit; a level of the first power voltage is opposite to an effective level of a scanning signal output by the parallel gate drive circuit; wherein x is an integer greater than 1.

11. The display panel according to any one of claims 1 to 10, wherein The display panel is a flexible panel.

12. The display panel according to any one of claims 1 to 10, wherein The display panel comprises at least two parallel gate drive circuits, and the number of shift registers of the two parallel gate drive circuits is different.

13. The display panel according to any one of claims 1 to 10, wherein The parallel gate drive circuit comprises a scanning gate drive circuit for outputting a scanning control signal, and a scanning output end of each shift register of the scanning gate drive circuit is electrically connected with a scanning control signal line.

14. The display panel according to any one of claims 1 to 10, wherein The parallel gate drive circuit comprises a light-emitting gate drive circuit for outputting a light-emitting control signal, and a light-emitting output end of each shift register of the light-emitting gate drive circuit is electrically connected with a light-emitting control signal line.

15. A display device, wherein, A display panel comprising any one of the display panels according to claims 1-14.

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