Display device and outdoor type signage device

Abstract

A display device (1) comprises: a first power supply line (P1) and a second power supply line (P2); a pixel circuit (4) connected to the first power supply line and the second power supply line; and a light-emitting element (5). The pixel circuit has a first current control unit (X1) connected to the first power supply line and the light-emitting element, and a second current control unit (X2) connected to the second power supply line and the light-emitting element. In a first mode, the light-emitting element is connected to the first power supply line via the first current control unit; in a second mode in which the number of display gradations is smaller than in the first mode, the light-emitting element is connected to the second power supply line via the second current control unit.

Description

Display device and outdoor signage device

[0001] The present invention relates to a display device.

[0002] A display device including a memory circuit in each pixel circuit is known (see Patent Document 1).

[0003] JP 2011-39514 A

[0004] 2. Description of the Related Art Display devices are required to reduce power consumption while maintaining display quality.

[0005] The display device of the present disclosure includes a first power supply line and a second power supply line, a pixel circuit connected to the first power supply line and the second power supply line, and a light-emitting element, the pixel circuit having a first current control unit connected to the first power supply line and the light-emitting element, and a second current control unit connected to the second power supply line and the light-emitting element, and in a first mode, the light-emitting element is connected to the first power supply line via the first current control unit, and in a second mode having a smaller number of display gradations than the first mode, the light-emitting element is connected to the second power supply line via the second current control unit.

[0006] It is possible to reduce power consumption while maintaining display quality.

[0007] FIG. 1 is a circuit diagram showing the configuration of a display device according to this embodiment. FIG. 2 is a circuit diagram showing the configuration of a latch circuit. FIG. 3 is a table showing an example of setting values ​​of each part corresponding to first to third modes. FIG. 4 is a timing chart showing the operation of the display device in a first mode. FIG. 5 is a timing chart showing the operation of the display device in a second mode. FIG. 6 is a table showing memory gradations in the second mode. FIG. 7 is a timing chart showing the operation of the display device in a third mode. FIG. 8 is a table showing compensation gradations in the third mode. FIG. 9 is a block diagram of an outdoor signage device according to this embodiment.

[0008] 1 is a circuit diagram showing the configuration of a display device according to this embodiment. As shown in FIG. 1, the display device 1 includes a first power supply line P1 and a second power supply line P2, a pixel circuit 4 connected to the first power supply line P1 and the second power supply line P2, and a light-emitting element 5. The display device 1 may include a pixel circuit group including the pixel circuit 4. The light-emitting element 5 may be a light-emitting diode (e.g., an organic light-emitting diode, a quantum dot light-emitting diode, or an inorganic semiconductor light-emitting diode). The light-emitting element 5 may emit red, blue, or green light, or may emit white light.

[0009] The pixel circuit 4 has a first current control unit X1 connected to the first power supply line P1 and the light emitting element 5, and a second current control unit X2 connected to the second power supply line L2 and the light emitting element 5.

[0010] In the display device, in a first mode, the light-emitting element 5 is connected to a first power supply line P1 via a first current control unit X1, and in a second mode in which the number of display gradations is smaller than in the first mode, the light-emitting element 5 is connected to a second power supply line P2 via a second current control unit X2. In the second mode, a memory display with a rewrite frequency lower than in the first mode may be performed.

[0011] The display device 1 is capable of multiple display modes, and in the second mode, memory display is possible by receiving power from the second power line P2, which makes it possible to reduce power consumption while maintaining display quality.

[0012] In the third mode, the light-emitting element 5 is connected to the first power supply line P1 via the first current control unit X1 and to the second power supply line P2 via the second current control unit X2. In the third mode, the number of display gradations in the first mode may be maintained while performing degradation compensation (addition of compensation gradations) for the light-emitting element 5. The degradation compensation can be performed using a stress value of the light-emitting element 5. The stress value can be calculated from the previous emission luminance, emission time, environmental temperature, etc.

[0013] The pixel circuit 4 has a first setting transistor T1 connected to a first power supply line P1 and a second setting transistor T2 connected to a second power supply line P2. In a first mode (e.g., an analog display mode), the first setting transistor T1 is ON and the second setting transistor T2 is OFF. In a second mode (e.g., a memory display mode), the first setting transistor T1 is OFF and the second setting transistor T2 is ON.

[0014] The first current control unit X1 includes a drive transistor TD connected to the light emitting element 5 and the first setting transistor T1. Since the pixel circuit 4 includes a drive transistor TD for analog data, the display device 1 can display normal moving images in addition to the memory display mode.

[0015] The display device 1 includes a data line DL connected to a first current controller X1 and a second current controller X2. The first current controller X1 includes a write transistor S0 connected to the data line DL.

[0016] The second current control unit X2 includes a first input transistor S1 connected to the data line DL, a first output transistor Y1 connected to the light-emitting element 5, and a first latch circuit L1 connected to the first input transistor S1 and the first output transistor Y1. The second power supply line P2 is connected to the light-emitting element 5 via the first output transistor Y1.

[0017] In the first mode, the write transistor S0 is ON and the first input transistor S1 is OFF (S2 and S3 are also OFF), and an analog grayscale voltage (video signal) is written from the data line DL to the first current control unit X1. The current of the light-emitting element 5 has a value corresponding to the analog grayscale voltage.

[0018] In the second mode, the write transistor TD is turned OFF, and the first input transistor S1 is turned ON, and one of two voltages (high voltage or low voltage) is written from the data line DL to the first latch circuit L1. For example, when a high voltage is written (latched), the output transistor Y1 is turned ON, and a current is generated from the second power line P2.

[0019] In a third mode (e.g., a degradation-compensated analog display mode), the write transistor TD and the first input transistor S1 are sequentially turned on, an analog grayscale voltage (video signal) is written from the data line DL to the first current control unit X1, and either a binary voltage (high voltage or low voltage) is written to the first latch circuit L1. For example, when a high voltage is written (latched), the output transistor Y1 is turned on, and a current is generated from the second power supply line P2.

[0020] The second current control unit X2 includes a second input transistor S2 connected to the data line DL, a second output transistor Y2 connected to the light-emitting element 5, and a second latch circuit L2 connected to the second input transistor S2 and the second output transistor Y2. The second power supply line P2 is connected to the light-emitting element 5 via the second output transistor Y2.

[0021] The second current control unit X2 includes a third input transistor S3 connected to the data line DL, a third output transistor Y3 connected to the light-emitting element 5, and a third latch circuit L3 connected to the third input transistor S3 and the third output transistor Y3. The second power supply line P2 is connected to the light-emitting element 5 via the third output transistor Y3. The first output transistor Y1, the second output transistor Y2, and the third output transistor Y3 are connected in parallel to the second power supply line P2.

[0022] In the second mode, a memory display of four gradations can be performed by combining the ON / OFF states of the first to third output transistors Y1 to Y3 (described later). In the second mode, the light-emitting element 5 may be constantly lit to display a still image.

[0023] In the third mode, four stages of deterioration compensation can be performed by combining the ON / OFF states of the first to third output transistors Y1 to Y3 (described later).

[0024] The display device 1 may include a scanning line G0 connected to the gate terminal of the write transistor S0, a scanning line G1 connected to the gate terminal of the first input transistor S1, a scanning line G2 connected to the gate terminal of the second input transistor S2, and a scanning line G3 connected to the gate terminal of the third input transistor S3. The scanning lines G0 to G3 may be driven by a single driver system that drives the scanning lines G0 to G3, or by a dual driver system that includes a drive system for the scanning line G0 and a drive system for the scanning lines G1 to G3. While three scanning lines G1 to G3 are provided in FIG. 1, only one scanning line G1 may be provided, or scanning lines G4 and onward may also be provided.

[0025] The first current controller X1 may include a capacitive element C inserted between the gate terminal and the source terminal of the driving transistor TD, and the gate terminal of the driving transistor TD may be connected to the data line DL via the write transistor S0. The source terminal of the driving transistor TD may be connected to the first power supply line P1 via the first setting transistor T1.

[0026] 2 is a circuit diagram showing the configuration of a latch circuit. Each of the first latch circuit L1, the second latch circuit L2, and the third latch circuit L3 includes inverters I1 and I2 connected in parallel in the opposite directions, as shown in FIG. 2 . The inverter I1 is a CMOS circuit and includes a P-type transistor T11 supplied with a VDD power supply (e.g., 5 V) and an N-type transistor T12 supplied with a VSS power supply (e.g., 0 V). The inverter I2 is a CMOS circuit and includes a P-type transistor T13 supplied with a VDD power supply (e.g., 5 V) and an N-type transistor T14 supplied with a VSS power supply (e.g., 0 V). The gate terminal of the inverter I1 is connected to the drain terminal of the inverter I2, and the drain terminal of the inverter I1 is connected to the gate terminal of the inverter I2.

[0027] In the display device 1, the refresh rate can be reduced to 0 Hz to 1.0 Hz in the second mode (memory display mode), and when driven at 0 Hz (when refreshing once per second, minute, or hour), the drive of the data line DL can also be stopped, thereby achieving further reduction in power consumption.

[0028] FIG. 3 is a table showing an example of setting values ​​of each component corresponding to the first to third modes. As shown in FIG. 3, the latch output (High side) may be 5.0 V in all modes, and the latch output (Low side) may be 0 V in all modes. The control voltage (High side) of transistors T1 and T2 may be 5.0 V in all modes, and the control voltage (Low voltage side) of transistors T1 and T2 may be −5.0 V in all modes. The voltage of the first power line P1 may be 3.5 V in the first and second modes, and 2.0 V in the third mode. The voltage of the second power line P2 may be 3.5 V in all modes. The cathode voltage of the light-emitting element 5 may be −3.5 V in all modes. The video signal (signal on the data line DL) in the first and third modes may be 0 to 5.0 V.

[0029] 4 is a timing chart showing the operation of the display device in the first mode. In the first mode (analog display mode), the first setting transistor T1 is ON and the second setting transistor T2 is OFF. When the write transistor S0 is ON, an analog video signal (0 to 5 V) is written from the data line DL to the capacitive element C. As a result, a current corresponding to the video signal flows from the first power line P1 to the light-emitting element 5 via the first setting transistor T1 and the drive transistor TD.

[0030] 4, during the period K0, the scanning line G0 is active (low), which turns on the write transistor S0, causing a video signal (an analog grayscale voltage of 0 to 5 V) to be written from the data line DL, and the light-emitting element 5 is controlled to have a brightness according to the video signal.

[0031] During period K1 following period K0, the scanning line G1 becomes active (low). This turns on the first input transistor S1, and the low potential (0 V) of the data line DL is latched by the first latch circuit L1. That is, during period K1, the output of the first latch circuit L1 is maintained at high potential (5 V), and the first output transistor Y1 is turned off.

[0032] During period K2 following period K1, the scanning line G2 becomes active (low). This turns on the second input transistor S2, and the low potential (0 V) of the data line DL is latched by the second latch circuit L2. That is, during period K2, the output of the second latch circuit L2 is maintained at high potential (5 V), and the second output transistor Y2 is turned off.

[0033] During period K3 following period K2, the scanning line G3 becomes active (low). This turns on the third input transistor S3, and the low potential (0 V) of the data line DL is latched by the third latch circuit L3. That is, during period K3, the output of the third latch circuit L3 is maintained at high potential (5 V), and the third output transistor Y3 is turned off.

[0034] 5 is a timing chart showing the operation of the display device in the second mode. In the second mode (memory display mode), the first setting transistor T1 is OFF and the second setting transistor T2 is ON. The first to third input transistors (S1 to S3) are sequentially turned ON, causing a memory gradation to be written from the data line DL to the second current control unit X2. As a result, a current corresponding to the memory gradation flows from the second power line P2 to the light-emitting element 5.

[0035] 5, during a period K0, the scanning line G0 is active (low), which turns on the write transistor S0, supplying the high potential (5 V) of the data line DL to the control terminal of the drive transistor TD, and turning off the drive transistor TD.

[0036] During period K1 following period K0, the scanning line G1 becomes active (low). This turns on the first input transistor S1, and the high potential (5 V) of the data line DL is latched by the first latch circuit L1. That is, during period K1, the output of the first latch circuit L1 is maintained at low potential (0 V), and the first output transistor Y1 is turned on.

[0037] During period K2 following period K1, the scanning line G2 becomes active (low). This turns on the second input transistor S2, and the low potential (0 V) of the data line DL is latched by the second latch circuit L2. That is, during period K2, the output of the second latch circuit L2 is maintained at high potential (5 V), and the second output transistor Y2 is turned off.

[0038] During period K3 following period K2, the scanning line G3 becomes active (low). This turns on the third input transistor S3, and the low potential (0 V) of the data line DL is latched by the third latch circuit L3. That is, during period K3, the output of the third latch circuit L3 is maintained at high potential (5 V), and the third output transistor Y3 is turned off.

[0039] As a result, the light-emitting element 5 is maintained at a luminance according to a memory gradation (gradation 1 described later) corresponding to Y1 being ON, Y2 being OFF, and Y3 being OFF.

[0040] FIG. 6 is a table showing the memory gradations in the second mode. As shown in FIG. 6, there are four memory gradations. Gradation 0 (black gradation) corresponds to a combination of Y1 OFF, Y2 OFF, and Y3 OFF. Gradation 1 corresponds to a combination of Y1 ON, Y2 OFF, and Y3 OFF. Gradation 2 corresponds to a combination of Y1 ON, Y2 ON, and Y3 OFF. Gradation 3 (white gradation) corresponds to a combination of Y1 ON, Y2 ON, and Y3 ON. Since four gradations can be displayed per subpixel (including the pixel circuit 4 and the light-emitting element 5), when RGB color display is performed, 64 gradation memory display levels are possible per pixel (RGB subpixel).

[0041] 7 is a timing chart showing the operation of the display device in the third mode. In the third mode (deterioration compensation analog display mode), the first setting transistor T1 is ON and the second setting transistor T2 is ON. The write transistor S0 and the first to third input transistors S1 to S3 are sequentially turned ON, so that a video signal is written from the data line DL to the first current control unit X1, and then a compensation gray scale is written from the data line DL to the second current control unit X2. This causes currents corresponding to the video signal and the compensation gray scale to flow from the first and second power supply lines P1 and P2 to the light-emitting element 5.

[0042] 7, during a period K0, the scanning line G0 is active (low), which turns on the writing transistor S0 and writes a video signal (analog gray scale voltage of 0 to 5 V) from the data line DL.

[0043] During period K1 following period K0, the scanning line G1 becomes active (low). This turns on the first input transistor S1, and the high potential (5 V) of the data line DL is latched by the first latch circuit L1. That is, during period K1, the output of the first latch circuit L1 is maintained at low potential (0 V), and the first output transistor Y1 is turned on.

[0044] During period K2 following period K1, the scanning line G2 becomes active (low). This turns on the second input transistor S2, and the high potential (5 V) of the data line DL is latched by the second latch circuit L2. That is, during period K2, the output of the second latch circuit L2 is maintained at low potential (0 V), and the second output transistor Y2 is turned on.

[0045] During period K3 following period K2, the scanning line G3 becomes active (low). This turns on the third input transistor S3, and the low potential (0 V) of the data line DL is latched by the third latch circuit L3. That is, during period K3, the output of the third latch circuit L3 is maintained at high potential (5 V), and the third output transistor Y3 is turned off.

[0046] As a result of the above, a compensation gray scale (gray scale C described below) corresponding to Y1 being ON, Y2 being ON, and Y3 being OFF is written to the second current control unit X2, and the light-emitting element 5 is controlled to a brightness according to the video signal and the compensation gray scale.

[0047] FIG. 8 is a table showing compensation gradations in the third mode. As shown in FIG. 8, there are four compensation gradations. Gradation A (when degradation is negligible) corresponds to a combination of Y1 OFF, Y2 OFF, and Y3 OFF. Gradation B (when the degree of degradation is small) corresponds to a combination of Y1 ON, Y2 OFF, and Y3 OFF. Gradation C (when the degree of degradation is medium) corresponds to a combination of Y1 ON, Y2 ON, and Y3 OFF. Gradation D (when the degree of degradation is large) corresponds to a combination of Y1 ON, Y2 ON, and Y3 ON.

[0048] 9 is a block diagram of an outdoor signage device according to this embodiment. The outdoor signage device 20 includes a display device 1 and a solar battery 10 that supplies power to the display device 1. The outdoor signage device 20 generates power from sunlight during the day and is capable of displaying video advertisements that consume a lot of power. At night, the outdoor signage device 20 is powered by a battery charged during the day, and may display still image advertisements in an AOD (Always On Display) mode in a low-power memory display mode.

[0049] The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope of the claims. Embodiments obtained by appropriately combining the technical means disclosed in different embodiments are also included in the technical scope of the present invention. Furthermore, new technical features can be formed by combining the technical means disclosed in each embodiment.

[0050] 1 Display device P1 First power supply line P2 Second power supply line 4 Pixel circuit 5 Light emitting element DL Data line X1 First current control section X2 Second current control section L1 First latch circuit L2 Second latch circuit L3 Third latch circuit T1 First setting transistor T2 Second setting transistor TD Drive transistor S0 Write transistor S1 First input transistor Y1 First output transistor S2 Second input transistor Y2 Second output transistor S3 Third input transistor Y3 Third output transistor

Claims

1. A display device comprising: a first power supply line and a second power supply line; a pixel circuit connected to the first power supply line and the second power supply line; and a light-emitting element; wherein the pixel circuit has a first current control unit connected to the first power supply line and the light-emitting element, and a second current control unit connected to the second power supply line and the light-emitting element; in a first mode, the light-emitting element is connected to the first power supply line via the first current control unit; and in a second mode which has fewer display gradations than the first mode, the light-emitting element is connected to the second power supply line via the second current control unit.

2. The display device according to claim 1, wherein in said second mode, memory display is performed with a rewrite frequency lower than that in said first mode.

3. A display device according to claim 1 or 2, wherein in a third mode, the light-emitting element is connected to the first power supply line via the first current control section and to the second power supply line via the second current control section.

4. The display device according to claim 3, wherein in the third mode, the number of display gradations in the first mode is maintained while compensation for deterioration of the light-emitting elements is performed.

5. The display device according to any one of claims 1 to 4, wherein the pixel circuit has a first setting transistor connected to the first power supply line and a second setting transistor connected to the second power supply line, wherein in the first mode the first setting transistor is ON and the second setting transistor is OFF, and in the second mode the first setting transistor is OFF and the second setting transistor is ON.

6. A display device according to any one of claims 1 to 5, comprising a data line connected to the first current control section and the second current control section, the first current control section including a write transistor connected to the data line.

7. The display device according to claim 6, wherein the second current control section includes a first input transistor connected to the data line, a first output transistor connected to the light-emitting element, and a first latch circuit connected to the first input transistor and the first output transistor.

8. The display device according to claim 7, wherein the second power supply line is connected to the light-emitting element via the first output transistor.

9. The display device according to claim 7, wherein in the first mode, the write transistor is turned ON and the first input transistor is turned OFF, and a grayscale voltage is written from the data line to the first current control section.

10. The display device according to claim 7, wherein in the second mode, the write transistor is turned OFF and the first input transistor is turned ON, and one of two voltage levels is written from the data line to the first latch circuit.

11. The display device according to claim 7, wherein in a third mode, the write transistor and the first input transistor are sequentially turned ON, a gradation voltage is written from the data line to the first current control section, and one of the two-value voltages is written to the first latch circuit.

12. The display device according to claim 5, wherein the first current control section includes a drive transistor connected to the light emitting element and the first setting transistor.

13. The display device according to claim 7, wherein the second current control section includes a second input transistor connected to the data line, a second output transistor connected to the light-emitting element, and a second latch circuit connected to the second input transistor and the second output transistor, and the second power supply line is connected to the light-emitting element via the second output transistor.

14. The display device according to claim 13, wherein the second current control section includes a third input transistor connected to the data line, a third output transistor connected to the light-emitting element, and a third latch circuit connected to the third input transistor and the third output transistor, and the second power supply line is connected to the light-emitting element via the third output transistor.

15. The display device according to claim 14, wherein in the second mode, a four-level gradation memory display is performed.

16. The display device according to any one of claims 1 to 15, wherein in the second mode, the light emitting elements are constantly lit to display a still image.

17. An outdoor signage device comprising the display device according to any one of claims 1 to 16 and a solar battery.

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