Transistor structure, gate drive circuit, and display panel

Abstract

The present disclosure provides a transistor structure, a gate drive circuit, and a display panel. A transistor group in the transistor structure comprises at least two control parts, at least two first electrode parts, and at least two second electrode parts. The second electrode parts and the first electrode parts are alternately arranged in the channel length direction. The orthographic projection of a control part on a base substrate is located between the orthographic projections of adjacent second electrode parts on the base substrate and the orthographic projections of the first electrode parts on the base substrate. The at least two first electrode parts include a non-edge first electrode part, and the non-edge first electrode part is located between the two adjacent second electrode parts. The two adjacent second electrode parts include at least one non-edge second electrode part. The non-edge first electrode part comprises a main body part and at least one protruding part; the protruding part is located between the main body part and the non-edge second electrode part; and the width of at least part of the protruding part is less than that of the main body part in the channel width direction.

Description

Transistor structure, gate driving circuit and display panel TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular to a transistor structure, a gate driving circuit and a display panel. BACKGROUND

[0002] With the continuous development of display technology, the application field of display products is becoming more and more extensive, and the requirements for display products are becoming more and more numerous. In order to reduce the manufacturing cost, simplify the manufacturing process flow, and reduce the width of the non-display area, more and more display products adopt GOA (English: Gate On Array) technology, which is a technology of integrating a gate driving circuit on an array substrate to save a traditional gate driving chip. When driving a display product to display by using the GOA technology, the gate driving circuit needs to have strong driving capability to improve its control capability, and therefore some transistors in the gate driving circuit need to meet a large output current and good characteristic uniformity.

[0003] SUMMARY

[0004] The present disclosure aims to provide a transistor structure, a gate driving circuit and a display panel.

[0005] In order to achieve the above-mentioned purpose, the present disclosure provides the following technical solutions:

[0006] A first aspect of the present disclosure provides a transistor structure, comprising: at least one group of transistor groups arranged along a channel width direction; at least one of the transistor groups comprises: at least two control parts, at least two first electrode parts, and at least two second electrode parts; the second electrode parts and the first electrode parts are alternately arranged along a channel length direction, and a normal projection of the control part on a substrate of the transistor structure is located between a normal projection of the adjacent second electrode part on the substrate and a normal projection of the first electrode part on the substrate;

[0007] The at least two first electrode parts include a non-edge first electrode part, the non-edge first electrode part is located between two adjacent second electrode parts, the two adjacent second electrode parts include at least one non-edge second electrode part, and the non-edge second electrode part is located between two adjacent first electrode parts.

[0008] The non-edge first electrode part comprises a main body part and at least one protruding part, the protruding part is located between the main body part and a non-edge second electrode part, along the channel width direction, at least part of the width of the protruding part is smaller than the width of the main body part.

[0009] Optionally, the transistor group includes an active pattern, the orthographic projection of the active pattern on the substrate and the orthographic projection of the at least two control portions on the substrate respectively forming an overlapping region; along the channel width direction, at least a portion of the width of the protrusion is smaller than the width of the overlapping region.

[0010] Optionally, along the width direction of the channel, the width of the main body is greater than or equal to the width of the overlapping region.

[0011] Optionally, the non-edge first electrode portion includes at least two protrusions, a portion of which is located on a first side of the main body portion and another portion of which is located on a second side of the main body portion, with the first side and the second side facing each other along the length of the channel.

[0012] Optionally, on the same side of the main body, at least two protrusions are provided, arranged along the width direction of the channel, wherein the sum of the minimum widths of the at least two protrusions along the width direction of the channel is less than the width of the overlapping area.

[0013] Optionally, the transistor structure includes at least two sets of transistor groups arranged along the channel width direction. In adjacent sets of transistors, adjacent main body portions along the channel width direction are coupled together by a first connecting portion. Along the channel length direction, the width of the first connecting portion is greater than or equal to the width of the main body portion.

[0014] Optionally, along the length of the channel, the width of the first connecting portion is greater than or equal to the sum of the widths of the main body portion and the protrusion portion.

[0015] Optionally, the protrusion includes at least two sub-parts arranged sequentially along the length of the channel, with adjacent sub-parts having different widths along the width of the channel; at least one of the at least two sub-parts has a width along the width of the channel that is smaller than the width of the overlapping region.

[0016] Optionally, the at least two sub-parts include at least one first sub-part, the first sub-part having a first width along the channel width direction, the first width gradually increasing or decreasing in a direction away from the main body.

[0017] Optionally, the at least two sub-parts include at least one second sub-part, the second sub-part having a second width along the channel width direction, the second width being equal to the minimum value of the first width, and the second sub-part being coupled to the end of the first sub-part having the minimum first width.

[0018] Optionally, the at least two sub-parts include a first sub-part and a second sub-part; the first sub-part is located between the second sub-part and the main body, or the second sub-part is located between the first sub-part and the main body.

[0019] Optionally, the maximum value of the first width is less than or equal to the width of the overlapping region.

[0020] Optionally, the at least two sub-parts include: a third sub-part, a fourth sub-part, and a fifth sub-part arranged sequentially along the length direction of the channel; along the width direction of the channel, the width of the third sub-part and the width of the fifth sub-part are both greater than the width of the fourth sub-part, and the width of the fourth sub-part is less than the width of the overlapping region.

[0021] Optionally, the width of the third sub-part along the channel width direction is less than or equal to the width of the overlapping region; and / or, the width of the fifth sub-part along the channel width direction is less than or equal to the width of the overlapping region.

[0022] Optionally, along the width direction of the channel, the width of the third sub-part is equal to the width of the fifth sub-part.

[0023] Optionally, the fourth sub-part includes at least two sub-patterns spaced apart along the width direction of the channel, wherein the sum of the widths of the at least two sub-patterns along the width direction of the channel is less than the width of the overlapping region.

[0024] Optionally, the transistor structure includes at least two groups of transistors arranged along the channel width direction, wherein adjacent second electrode portions along the channel width direction are coupled to each other via a second connection portion, and adjacent control portions along the channel width direction are coupled to each other via a third connection portion.

[0025] Along the channel width direction, on one side of the at least two sets of transistors, each of the second electrode portions is coupled to each other, and on the other side of the at least two sets of transistors, each of the first electrode portions is coupled to each other, and each of the control portions is coupled to each other.

[0026] Optionally, the control unit includes a bottom gate pattern and a top gate pattern, wherein the bottom gate pattern, the active pattern, and the top gate pattern are arranged sequentially along a direction away from the substrate.

[0027] Along the width direction of the channel, adjacent bottom grid patterns are coupled together by bottom grid connecting parts, and adjacent top grid patterns are coupled together by top grid connecting parts.

[0028] Optionally, the at least two first electrode portions include an edge first electrode portion, which is located at the outermost edge of the transistor structure along the channel length direction;

[0029] The first edge electrode portion includes an edge body portion and at least one edge protrusion portion, the edge protrusion portion being located between the edge body portion and the second edge electrode portion, and along the channel width direction, at least a portion of the width of the edge protrusion portion is smaller than the width of the edge body portion.

[0030] Based on the above-described transistor structure, a second aspect of this disclosure provides a gate driving circuit, including a shift register unit, wherein the shift register unit includes the above-described transistor structure.

[0031] Based on the above-described gate driving circuit, a third aspect of this disclosure provides a display panel including the aforementioned gate driving circuit. Attached Figure Description

[0032] The accompanying drawings, which are included to provide a further understanding of this disclosure and form part of this disclosure, illustrate exemplary embodiments of the present disclosure and are used to explain the disclosure, but do not constitute an undue limitation of the disclosure. In the drawings:

[0033] Figure 1 is a schematic diagram of a transistor structure provided in an embodiment of this disclosure;

[0034] Figure 2 is a schematic diagram of the layout of the control electrodes in Figure 1;

[0035] Figure 3 is a schematic diagram of the layout of the first electrode in Figure 1;

[0036] Figure 4 is a schematic diagram of the layout of the control electrode, the first electrode, and the second electrode in Figure 1;

[0037] Figure 5 is a schematic diagram of the layout of the second electrode in Figure 1;

[0038] Figure 6 is a schematic diagram showing the poor uniformity of characteristics in the transistor structure provided in the embodiment of this disclosure;

[0039] Figure 7 is a schematic diagram of an input current density provided in an embodiment of this disclosure;

[0040] Figure 8 is a schematic diagram of another input current density provided in an embodiment of this disclosure;

[0041] Figure 9 is a cross-sectional schematic diagram of the display product provided in an embodiment of this disclosure;

[0042] Figure 10 is a schematic diagram of a second layout of the first electrode provided in an embodiment of this disclosure;

[0043] Figure 11 is a schematic diagram of a third layout of the first electrode provided in an embodiment of this disclosure;

[0044] Figure 12 is a schematic diagram of a layout of a protrusion provided in an embodiment of this disclosure;

[0045] Figure 13 is a schematic diagram of a fourth layout of the first electrode provided in an embodiment of this disclosure;

[0046] Figure 14 is a schematic diagram of another layout of the protrusion provided in an embodiment of this disclosure;

[0047] Figure 15 is a schematic diagram of a fifth layout of the first electrode provided in an embodiment of this disclosure;

[0048] Figure 16 is a schematic diagram of another layout of the protrusion provided in an embodiment of this disclosure;

[0049] Figure 17 is a schematic diagram of the characteristic curves under the condition of poor characteristic uniformity provided in the embodiments of this disclosure;

[0050] Figure 18 is a schematic diagram of the characteristic curves under the condition of good characteristic uniformity provided by the embodiments of this disclosure;

[0051] Figure 19 is a circuit schematic diagram of the shift register unit provided in an embodiment of this disclosure;

[0052] Figure 20 is a schematic diagram of another layout of the protrusion provided in an embodiment of this disclosure;

[0053] Figure 21 is a schematic diagram of another layout of the protrusion provided in an embodiment of this disclosure;

[0054] Figure 22 is a schematic diagram of the binding principle of H when the H content is low, according to an embodiment of this disclosure;

[0055] Figure 23 is a schematic diagram of the binding principle of H as the H content increases, provided in an embodiment of this disclosure. Detailed Implementation

[0056] To further illustrate the transistor structure, gate driving circuit, and display panel provided in the embodiments of this disclosure, a detailed description is provided below with reference to the accompanying drawings.

[0057] Taking Organic Light-Emitting Diode (OLED) display products as an example, these products can specifically include: Low Temperature Poly-Silicon (LTPS) OLED display products, Low Temperature Polycrystalline Oxide (LTPO) OLED display products, etc. In OLED display products, the gate driving circuit needs to have strong driving capability to improve its control capability. Therefore, some transistors in the gate driving circuit need to meet the requirements of large output current Ion and good characteristic uniformity, such as the characteristic uniformity of the threshold voltage Vth.

[0058] For OLED display products, especially those including high-mobility oxide transistors, the mobility of the material itself is limited (typically Mob < 30cm). 2 To ensure the driving capability of the gate drive circuit, the output capability of the output transistor (buffer TFT) coupled to the drive signal output terminal needs to be guaranteed. This requires a significant increase in the channel width of the buffer TFT, such as a channel width-to-length ratio (W / L) of 400 / 6, but it is not limited to this. In some cases, due to layout space constraints, multiple TFTs can be arranged in series in the design to achieve a larger channel width. However, this method of significantly increasing the channel width of the buffer TFT has the problem of poor characteristic uniformity. The characteristics at some positions are severely negatively biased, causing fluctuations in the threshold voltage Vth of the output transistor, which in turn leads to a reduction in the display quality of the display product due to the signal output by the gate drive circuit.

[0059] Therefore, how to ensure that transistors with a large aspect ratio in the gate drive circuit can meet the requirements of large output current and good characteristic uniformity has become an urgent technical problem to be solved.

[0060] Please refer to Figures 1 to 5, 7 and 8. This disclosure provides a transistor structure including: at least one group of transistors 40 arranged along the channel width direction; at least one of the transistor groups 40 includes: at least two control portions 301, at least two first electrode portions 101, and at least two second electrode portions 201; the second electrode portions 201 and the first electrode portions 101 are alternately arranged along the channel length direction, and the orthographic projection of the control portion 301 on the substrate of the transistor structure is located between the orthographic projections of adjacent second electrode portions 201 on the substrate and the orthographic projections of the first electrode portions 101 on the substrate.

[0061] The at least two first electrode portions 101 include non-edge first electrode portions (as shown in Figure 3), which are located between two adjacent second electrode portions 201. The two adjacent second electrode portions 201 include at least one non-edge second electrode portion (as shown in Figure 5, the second electrode portion 201 located in the middle along the channel length direction), which is located between two adjacent first electrode portions 101. It is worth noting that the non-edge electrode portion is not located at the outermost edge of the transistor structure along the channel length direction, that is, a second electrode portion is also provided on the side of the non-edge electrode portion facing the outermost edge.

[0062] As shown in FIG4, the non-edge first electrode portion includes a main body portion 1011 and at least one protrusion 1012. The protrusion 1012 is located between the main body portion 1011 and the non-edge second electrode portion. Along the channel width direction, at least a portion of the width b1 of the protrusion 1012 is smaller than the width b2 of the main body portion 1011.

[0063] For example, the transistor structure includes at least two sets of transistor groups 40 arranged along the channel width direction.

[0064] For example, the transistor structure includes three groups of transistors 40 arranged along the channel width direction, but is not limited thereto. It should be noted that the channel width direction and the channel length direction correspond to the channel width-to-length ratio of the transistor structure, that is, the length of the channel of the transistor structure is the length of the channel in the channel length direction, and the channel width of the transistor structure is the width of the channel in the channel width direction.

[0065] For example, the control unit 301 includes a gate portion, the first electrode portion 101 includes a source portion, and the second electrode portion 201 includes a drain portion, but is not limited thereto.

[0066] For example, the second electrode portion 201 and the first electrode portion 101 are arranged alternately along the channel length direction. For example, the number of second electrode portions 201 is one more than the number of first electrode portions 101, or the number of first electrode portions 101 is one more than the number of second electrode portions 201. Taking at least one transistor group 40 as an example, which includes four control portions 301, two first electrode portions 101, and three second electrode portions 201; along the channel length direction, the first second electrode portion 201, the first first electrode portion 101, the second second electrode portion 201, the second first electrode portion 101, and the third second electrode portion 201 are arranged sequentially, and the four control portions 301 are arranged sequentially along the channel length direction, with the orthographic projection of the control portion 301 on the substrate located between the orthographic projection of the adjacent second electrode portion 201 on the substrate and the orthographic projection of the first electrode portion 101 on the substrate.

[0067] For example, the at least two first electrode portions 101 include at least one non-edge first electrode portion, which is located between two adjacent second electrode portions 201, meaning that the non-edge first electrode portion is not located on the outermost side of the transistor structure along the channel length direction. The at least two first electrode portions 101 may be configured to include an edge first electrode portion 101 as needed. An edge first electrode portion 101 refers to a portion located on the outermost side of the transistor structure along the channel length direction, meaning it is not located between two adjacent second electrode portions 201. For example, the non-edge first electrode portion includes the first first electrode portion 101 and the second first electrode portion 101.

[0068] For example, one of the two adjacent second electrode portions 201 includes a non-edge second electrode portion located between two adjacent first electrode portions 101, meaning that the non-edge second electrode portion is not located on the outermost side of the transistor structure along the channel length direction. For example, the non-edge second electrode portion includes the second second electrode portion 201.

[0069] For example, the non-edge first electrode portion includes a main body portion 1011 and at least one protrusion portion 1012, wherein the main body portion 1011 and the protrusion portion 1012 are formed as an integral structure.

[0070] For example, adjacent first electrode portions 101 and second electrode portions 201, and a control portion 301 whose orthogonal projection on the substrate is located between the orthogonal projections of the first electrode portion 101 and the second electrode portion 201, together form a sub-transistor in its respective transistor group 40. It should be noted that a transistor group 40 includes a plurality of sub-transistors arranged along the channel length direction. Adjacent sub-transistors may reuse one first electrode portion 101 or one second electrode portion 201. The plurality of sub-transistors includes a starting sub-transistor 401, at least one intermediate sub-transistor 402, and a ending sub-transistor 403 arranged sequentially along the channel length direction. The starting sub-transistor 401 and the ending sub-transistor 403 are both located on the outermost side of the transistor structure along the channel length direction, and the intermediate sub-transistor 402 is located in the middle region of the transistor structure along the channel length direction.

[0071] As shown in Figure 6, the control unit 301 (including the top gate pattern TG and the bottom gate pattern BG) is generally made of metal Mo. The insulating layer (such as GI) between the control unit 301 and the active layer 60 contains H. When the buffer TFT includes the transistor structure, the Mo density is relatively high. Since Mo is a columnar grain, it has a hydrogen absorption effect. Therefore, the Mo density affects the H content around the active layer. H near the edge of the active layer easily diffuses to the outermost part of the active layer, resulting in a lower H content near the edge and a higher H content at the outermost part. However, H near the middle part of the active layer is difficult to diffuse, resulting in a higher H content near the middle part of the active layer. This causes a characteristic shift in the transistor structure, causing the intermediate sub-transistor 402 in the transistor structure to turn on prematurely. It should be noted that the arrows in Figure 6 represent the H diffusion direction and the direction of absorption by Mo.

[0072] More specifically, as shown in Figure 22, when the H content is low, it mainly binds to metallic bonds (M) or oxygen bonds (O) to passivate defects, reducing carrier concentration and causing a positive shift in Vth. As shown in Figure 23, with increasing H content, it acts as a donor defect, forming -OH bonds or H+ ions, increasing carrier concentration and inducing a negative shift in Vth. It should be noted that Figure 23 illustrates the bonding between H and indium gallium zinc oxide (IGZO) as the H content increases.

[0073] Based on the above principle, as shown in Figure 23, the intermediate sub-transistor 402 has a high H content near the active layer, which causes the transistor structure to shift, resulting in the transistor structure turning on prematurely.

[0074] As can be seen from the specific structure of the transistor structure described above, in the transistor structure provided in this embodiment, by providing the non-edge first electrode portion including a main body portion 1011 and at least one protrusion 1012, the protrusion 1012 being located between the main body portion 1011 and the non-edge second electrode portion, such that the non-edge first electrode portion, the non-edge second electrode portion, and a control portion 301 whose orthogonal projection on the substrate is located between the orthogonal projections of the non-edge first electrode portion and the non-edge second electrode portion, can jointly form an intermediate sub-transistor 402; by providing the protrusion along the channel width direction... At least a portion of the width of the output portion 1012 is smaller than the width of the main body portion 1011, causing the width of the non-edge first electrode portion to narrow along the direction close to the channel region of the intermediate sub-transistor 402. This effectively reduces the concentration of transport carriers in the intermediate sub-transistor 402 when it is working, thereby reducing the input current density of the intermediate sub-transistor 402 and better balancing the overall current density of the transistor structure. This effectively overcomes the problem of premature turn-on of the intermediate sub-transistor 402 caused by the characteristic deviation of the transistor structure, and greatly improves the uniformity of the transistor structure characteristics.

[0075] Therefore, when the transistor structure provided in the embodiments of this disclosure is applied to the gate driving circuit, the gate driving circuit can achieve a strong driving capability, thereby greatly improving the control capability of the gate driving circuit and ensuring the display effect of the display product under the drive of the gate driving circuit.

[0076] It should be noted that, as shown in Figures 7 and 8, the solid arrows represent the input current density of the peripheral sub-transistor, and the dashed arrows represent the input current density of the intermediate sub-transistor 402.

[0077] For example, the fluctuation parameter 3δ, which measures the threshold voltage fluctuation of a transistor structure, can be improved from 1.6 to 0.5. Specifically, as shown in Figures 17 and 18, Figure 17 is the Id-Vg curve in related technologies, and Figure 18 is the Id-Vg curve in the embodiment of this disclosure. In both figures, the horizontal axis represents Vg in V, and the vertical axis represents Id in A. Vg represents the voltage of the control unit 301 of the transistor structure, and Id represents the drain current of the transistor structure.

[0078] As shown in Figures 1 and 4, in some embodiments, the transistor group 40 includes an active pattern 60, the orthographic projection of the active pattern 60 on the substrate and the orthographic projection of the at least two control units 301 on the substrate respectively forming an overlapping region 80; along the channel width direction, at least a portion of the width b1 of the protrusion 1012 is smaller than the width b3 of the overlapping region 80.

[0079] For example, the active pattern 60 extends along the length direction of the channel, but is not limited thereto.

[0080] For example, the orthographic projection of the active pattern 60 on the substrate and the orthographic projection of the at least two control units 301 on the substrate respectively form an overlapping region 80, and the portion of the active pattern 60 located in the overlapping region 80 is the channel portion of each sub-transistor.

[0081] In the above configuration, at least a portion of the width of the protrusion 1012 is smaller than the width of the overlapping region 80 along the channel width direction, so that the width of the non-edge first electrode portion is narrowed along the direction close to the channel portion of its corresponding intermediate sub-transistor 402. In this way, when the intermediate sub-transistor 402 is working, the input current density of the intermediate sub-transistor 402 can be effectively reduced to achieve the effect of balancing the overall current density of the transistor structure. This effectively overcomes the problem of premature turn-on of the intermediate sub-transistor 402 caused by the characteristic offset of the transistor structure, and greatly improves the characteristic uniformity of the transistor structure.

[0082] As shown in Figure 4, in some embodiments, along the width direction of the channel, the width b2 of the main body portion 1011 is greater than or equal to the width b3 of the overlapping region 80.

[0083] The above configuration ensures that when the current flows through the main body 1011, it can be well transmitted by the large area of ​​the main body 1011, thereby reducing the input current density of the intermediate sub-transistor 402 while ensuring the transmission performance of the non-edge first electrode portion included in the intermediate sub-transistor 402.

[0084] As shown in FIG20, in some embodiments, the non-edge first electrode portion includes at least two protrusions 1012, a portion of the protrusions 1012 being located on a first side of the main body portion 1011, and another portion of the protrusions 1012 being located on a second side of the main body portion 1011, with the first side and the second side facing each other along the length of the channel.

[0085] For example, a portion of the protrusion 1012 is located on the first side of the main body 1011, and the non-edge first electrode portion, the control portion 301 adjacent to the first side, and the non-edge second electrode portion form a sub-transistor; another portion of the protrusion 1012 is located on the second side of the main body 1011, and the non-edge first electrode portion, the control portion 301 adjacent to the second side, and the non-edge second electrode portion form another sub-transistor; these two sub-transistors reuse the non-edge first electrode portion.

[0086] The above configuration helps to further reduce the input current density of the intermediate sub-transistor 402, thereby achieving the effect of balancing the overall current density of the transistor structure. This effectively overcomes the problem of the intermediate sub-transistor 402 turning on prematurely due to the characteristic offset of the transistor structure, and greatly improves the characteristic uniformity of the transistor structure.

[0087] Moreover, the above configuration reduces the input current density of the intermediate sub-transistor 402 without increasing the complexity of the transistor structure, which helps to simplify the layout space occupied by the transistor structure and reduce the layout difficulty of the transistor structure in a limited layout space.

[0088] As shown in FIG21, in some embodiments, at least two protrusions 1012 arranged along the width direction of the channel are provided on the same side of the main body 1011. The sum of the minimum widths of the at least two protrusions 1012 along the width direction of the channel (e.g., b4+b5) is less than the width of the overlapping region 80.

[0089] The above-mentioned arrangement of at least two protrusions 1012 arranged along the channel width direction on the same side of the main body 1011 makes the input current distribution more uniform, which is beneficial to improving the characteristic stability of the sub-transistor.

[0090] The above-mentioned setting ensures that the sum of the minimum widths of the at least two protrusions 1012 along the channel width direction is less than the width of the overlapping region 80. This effectively reduces the input current density of the intermediate sub-transistor 402, thereby achieving the effect of balancing the overall current density of the transistor structure. This effectively overcomes the problem of the intermediate sub-transistor 402 turning on prematurely due to the characteristic offset of the transistor structure, and greatly improves the uniformity of the transistor structure characteristics.

[0091] As shown in FIG3, in some embodiments, the transistor structure includes at least two groups of transistors arranged along the channel width direction. In adjacent groups of transistors 40, adjacent main body portions 1011 along the channel width direction are coupled together by a first connection portion 102. Along the channel length direction, the width b6 of the first connection portion 102 is greater than or equal to the width b7 of the main body portion 1011.

[0092] For example, along the length of the channel, the width of the first connecting portion 102 is greater than or equal to the sum of the widths of the main body portion 1011 and the protrusion portion 1012.

[0093] For example, the first connecting portion 102 and the main body portion 1011 coupled thereto are formed as an integral structure.

[0094] As shown in Figures 2 and 5, exemplarily, the transistor structure includes at least two groups of transistors arranged along the channel width direction. In adjacent transistor groups 40, the second electrode portions 201 adjacent along the channel width direction are coupled together by a second connection portion 202, and the control portions 301 adjacent along the channel width direction are coupled together by a third connection portion 302. As shown in Figure 1, along the channel width direction, on one side of the at least two groups of transistors 40, each second electrode portion 201 is coupled together, and on the other side of the at least two groups of transistors 40, each first electrode portion 101 is coupled together, and each control portion 301 is coupled together.

[0095] For example, along the channel width direction, each of the second electrode portions 201 is coupled to one side of the at least two sets of transistor groups 40, thereby connecting all the second electrode portions 201 included in the transistor structure together to form the second electrode 20 of the transistor structure.

[0096] For example, along the channel width direction, on the other side of the at least two sets of transistor groups 40, each of the first electrode portions 101 is coupled together, thereby connecting all the first electrode portions 101 included in the transistor structure together to form the first electrode 10 of the transistor structure.

[0097] For example, along the channel width direction, on the other side of the at least two sets of transistor groups 40, each of the control units 301 is coupled together, thereby connecting all the control units 301 included in the transistor structure together to form the control electrode 30 of the transistor structure. The control electrode 30 may include a first control layer 30a and a second control layer 30b, the first control layer 30a including a bottom gate pattern BG, and the second control layer 30b including a top gate pattern TG.

[0098] When the transistor structure is connected to the shift register unit, it can be coupled to other structures in the shift register unit through the first electrode, the second electrode and the control electrode 30.

[0099] The above-described configuration, where the width of the first connecting portion 102 is greater than or equal to the width of the main body portion 1011 along the channel length direction, and where the width of the first connecting portion 102 is greater than or equal to the sum of the widths of the main body portion 1011 and the protrusion 1012 along the channel length direction, ensures that when current flows through the first connecting portion 102, it can be well transmitted by the larger area of ​​the first connecting portion 102. This achieves the goal of reducing the input current density of the intermediate sub-transistor 402 while ensuring the current transmission performance between adjacent main body portions 1011.

[0100] The above configuration also enables the transistor structure to include at least two sets of transistor groups 40 arranged sequentially along the channel width direction, ensuring that the transistor structure has a large channel width-to-length ratio.

[0101] As shown in Figures 1 to 5, in some embodiments, the control unit 301 includes a bottom gate pattern BG and a top gate pattern TG. Along the direction away from the substrate, the bottom gate pattern BG, the active pattern 60, and the top gate pattern TG are arranged sequentially. Along the channel width direction, adjacent bottom gate patterns BG are coupled to each other through a bottom gate connection portion, and adjacent top gate patterns TG are coupled to each other through a top gate connection portion.

[0102] As shown in Figure 9, exemplarily, SiO is used. x The material is deposited using plasma-enhanced chemical vapor deposition (PECVD) at 380°C to form a 100 nm thick buffer layer (BUF), which serves as an insulating dielectric layer. A 300 nm thick molybdenum metal layer is then deposited using sputter magnetron sputtering. This molybdenum metal layer is patterned using exposure, development, and etching processes to form the bottom gate pattern (BG) and bottom gate interconnects. Finally, SiO2 is deposited... x The material was prepared by forming a 300 nm thick first insulating layer GI1 using PECVD at 380 °C; then, using Sputter magnetron sputtering, a 25 nm thick indium gallium oxide (IGO) thin film was deposited at room temperature using an indium gallium oxide target (In2O3:Ga2O3 = 1:1 wt%), and the IGO thin film was patterned to form an active pattern 60; then, SiO2 was used... x The material is first deposited using PECVD to form a second insulating layer GI2. Then, a 300nm thick molybdenum metal layer is deposited using a sputtering deposition apparatus. This molybdenum layer is then patterned using exposure, development, and etching processes to form the top gate pattern TG and the top gate connection portion. Next, an interlayer insulating layer ILD is formed. Finally, a 700nm thick source / drain metal layer is deposited using sputter magnetron sputtering, comprising sequentially stacked Ti, Al, and Ti thin films. This source / drain metal layer is then patterned to form the first electrode portion 101 and the second electrode portion 201. The first electrode portion 101 and the second electrode portion 201 are coupled to corresponding portions of the active pattern 60 (coupling can be achieved through vias Via1 and Via2 as shown in Figure 1), serving as the source and drain of the transistor structure. Figure 9 also illustrates a passivation layer PVX and a multilayer film 70, which may include, but is not limited to, a planarization layer, a second source / drain metal layer, an anode layer, and a pixel delimiting layer.

[0103] In the transistor structure provided in the above embodiments, the transistor structure is configured as a dual-gate structure including a top gate pattern TG and a bottom gate pattern BG. Of course, the transistor structure can also be configured as a single-gate structure including only the top gate pattern TG or the bottom gate pattern BG.

[0104] As shown in Figures 10 to 16, in some embodiments, the protrusion 1012 includes at least two sub-parts (e.g., first sub-part 1012a, second sub-part 1012b, third sub-part 1012c, fourth sub-part 1012d, and fifth sub-part 1012e) arranged sequentially along the length of the channel, and adjacent sub-parts have different widths along the width of the channel; at least one of the at least two sub-parts has a width along the width of the channel that is smaller than the width of the overlapping region 80.

[0105] For example, the protrusion 1012 includes at least two sub-parts arranged sequentially along the length of the channel, the at least two sub-parts being formed as an integral structure.

[0106] By setting adjacent sub-parts to have different widths along the channel width direction, when the protrusion 1012 of the first electrode part 101 is narrowed, the protrusion 1012 can be narrowed to different widths at different positions, thereby enabling better adjustment of the current density.

[0107] By setting at least one of the at least two sub-parts to have a width along the channel width direction that is smaller than the width of the overlapping region 80, the input current density of the intermediate sub-transistor 402 can be effectively reduced, thereby achieving the effect of balancing the overall current density of the transistor structure. This effectively overcomes the problem of the intermediate sub-transistor 402 turning on prematurely due to the characteristic offset of the transistor structure, and greatly improves the characteristic uniformity of the transistor structure.

[0108] As shown in Figures 10 to 12, in some embodiments, the at least two sub-parts include at least one first sub-part 1012a, the first sub-part 1012a having a first width along the channel width direction, the first width gradually increasing or decreasing in the direction away from the main body 1011.

[0109] For example, the first sub-part 1012a is formed as a regular trapezoid or an inverted trapezoidal structure, but is not limited to this.

[0110] The above-described configuration allows the protrusion 1012 of the first electrode portion 101 to be narrowed at different positions with varying widths, thereby enabling better adjustment of the current density. Furthermore, by providing a first width along the channel width direction for the first sub-part 1012a, which gradually increases or decreases in the direction away from the main body portion 1011, a better transition from high to low current density can be achieved while simultaneously adjusting the current density.

[0111] As shown in Figures 10 to 12, in some embodiments, the at least two sub-parts include at least one second sub-part 1012b, the second sub-part 1012b having a second width along the channel width direction, the second width being equal to the minimum value of the first width, and the second sub-part 1012b being coupled to the end of the first sub-part 1012a having the minimum first width.

[0112] For example, the at least two sub-parts include a first sub-part 1012a and a second sub-part 1012b; the first sub-part 1012a is located between the second sub-part 1012b and the main body 1011, or the second sub-part 1012b is located between the first sub-part 1012a and the main body 1011.

[0113] The above arrangement allows the protrusion 1012 of the first electrode portion 101 to be narrowed at different widths at different locations when the protrusion 1012 is narrowed, thereby enabling better adjustment of the current density. Furthermore, by including at least one second sub-part 1012b in the at least two sub-parts, it is beneficial to achieve lower current densities.

[0114] In some embodiments, the maximum value of the first width is set to be less than or equal to the width of the overlapping region 80. This setting can effectively reduce the input current density of the intermediate sub-transistor 402, thereby achieving the effect of balancing the overall current density of the transistor structure. This effectively overcomes the problem of premature turn-on of the intermediate sub-transistor 402 caused by the characteristic offset of the transistor structure, and greatly improves the characteristic uniformity of the transistor structure.

[0115] As shown in Figures 13 to 16, in some embodiments, the at least two sub-parts include: a third sub-part 1012c, a fourth sub-part 1012d, and a fifth sub-part 1012e arranged sequentially along the length direction of the channel; along the width direction of the channel, the width of the third sub-part 1012c and the width of the fifth sub-part 1012e are both greater than the width of the fourth sub-part 1012d, and the width of the fourth sub-part 1012d is less than the width of the overlapping region 80.

[0116] For example, the width of the third sub-part 1012c along the channel width direction is less than or equal to the width of the overlapping region 80; and / or, the width of the fifth sub-part 1012e along the channel width direction is less than or equal to the width of the overlapping region 80.

[0117] For example, along the width direction of the channel, the width of the third sub-part 1012c is equal to the width of the fifth sub-part 1012e.

[0118] By setting the widths of the third sub-part 1012c and the fifth sub-part 1012e to be greater than the width of the fourth sub-part 1012d, and the width of the fourth sub-part 1012d to be less than the width of the overlapping region 80, the protrusion 1012 of the first electrode part 101 can be narrowed to different widths at different positions when the protrusion 1012 is narrowed, thereby enabling better adjustment of the current density.

[0119] By setting the width of the fourth sub-part 1012d to be smaller than the width of the overlapping region 80, the input current density of the intermediate sub-transistor 402 can be effectively reduced, thereby achieving the effect of balancing the overall current density of the transistor structure. This effectively overcomes the problem of the intermediate sub-transistor 402 turning on prematurely due to the characteristic offset of the transistor structure, and greatly improves the characteristic uniformity of the transistor structure.

[0120] In some embodiments, the fourth sub-part 1012d includes at least two sub-patterns spaced apart along the channel width direction, the sum of the widths of the at least two sub-patterns along the channel width direction being less than the width of the overlapping region 80.

[0121] The above configuration effectively reduces the input current density of the intermediate sub-transistor 402, thereby balancing the overall current density of the transistor structure. This effectively overcomes the problem of premature turn-on of the intermediate sub-transistor 402 caused by the characteristic offset of the transistor structure, greatly improving the uniformity of the transistor structure characteristics. Simultaneously, when the protrusion 1012 of the first electrode portion 101 is narrowed, the protrusion 1012 can be narrowed to different widths at different positions, thus enabling better adjustment of the current density.

[0122] In some embodiments, the at least two first electrode portions include an edge first electrode portion, which is located at the outermost edge of the transistor structure along the channel length direction;

[0123] The first edge electrode portion includes an edge body portion and at least one edge protrusion portion, the edge protrusion portion being located between the edge body portion and the second edge electrode portion, and along the channel width direction, at least a portion of the width of the edge protrusion portion is smaller than the width of the edge body portion.

[0124] For example, one of the at least two first electrode portions includes an edge first electrode portion, which is located on the outermost side of the transistor structure along the length of the channel.

[0125] For example, the edge protrusion is located between the edge main body and the non-edge second electrode, and the non-edge second electrode is located between two adjacent first electrode portions 101, that is, the edge protrusion is located on the side of the edge main body facing the interior of the transistor structure.

[0126] The above configuration allows for adjustment of the turn-on time of the edge sub-transistors, which helps improve the uniformity of transistor structure characteristics. Furthermore, this configuration helps reduce the overall layout space occupied by the transistor structure, thus simplifying its layout.

[0127] This disclosure also provides a gate driving circuit, including a shift register unit, wherein the shift register unit includes the transistor structure provided in the above embodiments.

[0128] Figure 19 illustrates the circuit structure of one shift register unit included in the gate drive circuit, but is not limited to this.

[0129] The shift register unit includes:

[0130] The first transistor M1 has its gate coupled to the frame start signal input terminal STV or the output terminal G_out(n-1) of the cascaded previous level shift register unit, its first terminal coupled to the power supply signal input terminal VDD, and its second terminal coupled to the pull-up node PU.

[0131] The second transistor M2 has its gate coupled to the output terminal G_out(n+1) of the cascaded next-stage shift register unit, its first terminal coupled to the second level signal input terminal VSD, and its second terminal coupled to the pull-up node PU.

[0132] The third transistor M3 has its gate coupled to the pull-up node PU, its first terminal coupled to , and its second terminal coupled to the output terminal G_out of its corresponding shift register unit.

[0133] The fourth transistor M4 has its gate coupled to the reset signal output terminal STV0, its first terminal coupled to the pull-up node PU, and its second terminal coupled to the third level signal input terminal VGL.

[0134] The fifth transistor M5 has its gate coupled to the second terminal of the ninth transistor M9, its first terminal coupled to the fourth level signal input terminal GCH, and its second terminal coupled to the pull-down node PD.

[0135] The sixth transistor M6 has its gate coupled to the pull-up node PU, its first terminal coupled to the pull-down node PD, and its second terminal coupled to the third level signal input terminal VGL.

[0136] The seventh transistor M7 has its gate coupled to the reset signal output terminal STV0, its first terminal coupled to the output terminal G_out of its corresponding shift register unit, and its second terminal coupled to the third-level signal input terminal VGL.

[0137] The eighth transistor M8 has its gate coupled to the pull-up node PU, its first terminal coupled to the second terminal of the ninth transistor M9, and its second terminal coupled to the third level signal input terminal VGL.

[0138] The ninth transistor M9 has its gate and first electrode coupled together and is coupled to the fourth level signal input terminal GCH.

[0139] The tenth transistor M10 has its gate coupled to the pull-down node PD, its first terminal coupled to the pull-up node PU, and its second terminal coupled to the third level signal input terminal VGL.

[0140] The eleventh transistor M11 has its gate coupled to the pull-down node PD, its first terminal coupled to the output terminal G_out of its corresponding shift register unit, and its second terminal coupled to the third level signal input terminal VGL.

[0141] Capacitor C1, the first end of which is coupled to the pull-up node PU, and the second end of which is coupled to the output terminal G_out of the shift register unit to which it belongs.

[0142] For example, the third transistor M3 includes the transistor structure described above, but is not limited to it.

[0143] In the transistor structure provided in the above embodiments, by providing the non-edge first electrode portion including a main body portion 1011 and at least one protrusion 1012, the protrusion 1012 being located between the main body portion 1011 and the non-edge second electrode portion, the non-edge first electrode portion, the non-edge second electrode portion, and the control portion 301 whose orthogonal projection on the substrate is located between the orthogonal projections of the non-edge first electrode portion and the non-edge second electrode portion, can jointly form an intermediate sub-transistor 402. By providing that at least a portion of the width of the protrusion 1012 is smaller than the width of the main body portion 1011 along the channel width direction, the width of the non-edge first electrode portion is narrowed along the direction close to the channel region of the intermediate sub-transistor 402. In this way, when the intermediate sub-transistor 402 is working, the input current density of the intermediate sub-transistor 402 can be effectively reduced to achieve the effect of balancing the overall current density of the transistor structure. This effectively overcomes the problem of premature turn-on of the intermediate sub-transistor 402 caused by the characteristic offset of the transistor structure, and greatly improves the characteristic uniformity of the transistor structure.

[0144] Therefore, when the gate driving circuit provided in this embodiment includes the above-described transistor structure, it can achieve a strong driving capability, thereby greatly improving the control capability of the gate driving circuit and ensuring the display effect of the display product under the drive of the gate driving circuit.

[0145] This disclosure also provides a display panel, including the gate driving circuit provided in the above embodiments.

[0146] It should be noted that the display panel is applied to a display device, which can be any product or component with display function, such as a television, monitor, digital photo frame, mobile phone, or tablet computer. The display device also includes flexible circuit boards, printed circuit boards, and back panels.

[0147] Since the gate driving circuit described above has a strong driving capability, it greatly improves the control capability of the gate driving circuit. Therefore, when the display panel provided in this embodiment includes the gate driving circuit provided in the above embodiment, the display panel can be driven by the gate driving circuit to better ensure the display effect of the display panel.

[0148] It should be noted that the signal line extending along the X direction means that the signal line includes a main part and a secondary part connected to the main part. The main part is a line, line segment, or strip-shaped body. The main part extends along the X direction, and the length of the main part extending along the X direction is greater than the length of the secondary part extending in other directions.

[0149] It should be noted that, in the embodiments of this disclosure, "same layer" can refer to film layers located on the same structural layer. Alternatively, for example, film layers located on the same layer can be layer structures formed by using the same film deposition process to form a specific pattern, and then patterning the film layer using the same photomask through a single patterning process. Depending on the specific pattern, the single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure can be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0150] In the various method embodiments of this disclosure, the sequence numbers of each step are not intended to limit the order of the steps. For those skilled in the art, any changes in the order of the steps are within the scope of protection of this disclosure without any creative effort.

[0151] It should be noted that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the method embodiments are basically similar to the product embodiments, so the description is relatively simple, and the relevant parts can be referred to the description of the product embodiments.

[0152] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connection,” “coupled,” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0153] It is understandable that when a component such as a layer, film, region, or substrate is referred to as being "above" or "below" another component, the component may be "directly" located "above" or "below" the other component, or there may be intermediate components present.

[0154] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples. The above descriptions are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A transistor structure, comprising: at least one group of transistor groups arranged along a channel width direction; at least one group of transistor groups includes at least two control portions, at least two first electrode portions, and at least two second electrode portions; the second electrode portions and the first electrode portions are alternately arranged along a channel length direction, and a normal projection of the control portion on a substrate of the transistor structure is located between a normal projection of the adjacent second electrode portion on the substrate and a normal projection of the first electrode portion on the substrate; a non-edge first electrode portion is included in the at least two first electrode portions, and the non-edge first electrode portion is located between two adjacent second electrode portions; at least one non-edge second electrode portion is included in the two adjacent second electrode portions, and the non-edge second electrode portion is located between two adjacent first electrode portions; the non-edge first electrode portion includes a main portion and at least one protruding portion, and the protruding portion is located between the main portion and a non-edge second electrode portion; along the channel width direction, at least part of the protruding portion has a width smaller than a width of the main portion.

2. The transistor structure of claim 1, wherein, the transistor group includes an active pattern, and a normal projection of the active pattern on the substrate forms an overlapping region with a normal projection of the at least two control portions on the substrate; along the channel width direction, at least part of the protruding portion has a width smaller than a width of the overlapping region.

3. The transistor structure of claim 2, wherein, along the channel width direction, the main portion has a width greater than or equal to the width of the overlapping region.

4. The transistor structure of claim 2, wherein, the non-edge first electrode portion includes at least two protruding portions, and a part of the protruding portions is located on a first side of the main portion, and another part of the protruding portions is located on a second side of the main portion; the first side and the second side are opposite along the channel length direction.

5. The transistor structure of claim 2, wherein, on the same side of the main portion, at least two protruding portions arranged along the channel width direction are arranged, and a sum of minimum widths of the at least two protruding portions along the channel width direction is smaller than the width of the overlapping region.

6. The transistor structure of claim 2, wherein, the transistor structure includes at least two groups of transistor groups arranged along a channel width direction, and between the main portions of the adjacent transistor groups along the channel width direction, a first connecting portion is coupled; along the channel length direction, the first connecting portion has a width greater than or equal to a width of the main portion.

7. The transistor structure of claim 6, wherein, along the channel length direction, the first connecting portion has a width greater than or equal to a sum of widths of the main portion and the protruding portion.

8. The transistor structure according to any one of claims 2 to 7, wherein the protruding portion includes at least two sub-portions arranged along the channel length direction in sequence, and adjacent sub-portions have different widths along the channel width direction; at least one sub-portion of the at least two sub-portions has a width along the channel width direction smaller than the width of the overlapping region.

9. The transistor structure of claim 8, wherein, at least one first sub-portion is included in the at least two sub-portions, and the first sub-portion has a first width along the channel width direction; the first width gradually increases or gradually decreases in a direction away from the main portion.

10. The transistor structure of claim 9, wherein, The at least two sub-portions include at least a second sub-portion, the second sub-portion has a second width along the channel width direction, the second width is equal to the minimum of the first width, and the second sub-portion is coupled to the first sub-portion at the end with the minimum first width.

11. The transistor structure of claim 10, wherein, The at least two sub-portions include a first sub-portion and a second sub-portion; the first sub-portion is located between the second sub-portion and the main body portion, or the second sub-portion is located between the first sub-portion and the main body portion.

12. The transistor structure of claim 9, wherein, The maximum of the first width is less than or equal to the width of the overlap region.

13. The transistor structure of claim 8, wherein, The at least two sub-portions include a third sub-portion, a fourth sub-portion, and a fifth sub-portion arranged in sequence along the channel length direction; along the channel width direction, the width of the third sub-portion and the width of the fifth sub-portion are both greater than the width of the fourth sub-portion, and the width of the fourth sub-portion is less than the width of the overlap region.

14. The transistor structure of claim 13, wherein, The width of the third sub-portion along the channel width direction is less than or equal to the width of the overlap region; and / or, the width of the fifth sub-portion along the channel width direction is less than or equal to the width of the overlap region.

15. The transistor structure of claim 13, wherein, Along the channel width direction, the width of the third sub-portion and the width of the fifth sub-portion are equal.

16. The transistor structure of claim 13, wherein, The fourth sub-portion includes at least two sub-patterns arranged in sequence along the channel width direction, and the sum of the widths of the at least two sub-patterns along the channel width direction is less than the width of the overlap region.

17. The transistor structure of claim 6, wherein, The transistor structure includes at least two groups of transistor groups arranged along the channel width direction, and in adjacent transistor groups, the second electrode portions adjacent along the channel width direction are coupled through second connection portions, and the control portions adjacent along the channel width direction are coupled through third connection portions. Along the channel width direction, on one side of the at least two groups of transistor groups, the second electrode portions are coupled, on the other side of the at least two groups of transistor groups, the first electrode portions are coupled, and the control portions are coupled.

18. The transistor structure of claim 17, wherein, The control portion includes a bottom gate pattern and a top gate pattern, and along the direction away from the substrate, the bottom gate pattern, the active pattern, and the top gate pattern are arranged in sequence. Along the channel width direction, adjacent bottom gate patterns are coupled through bottom gate connection portions, and adjacent top gate patterns are coupled through top gate connection portions.

19. The transistor structure of claim 1, wherein, The at least two first electrode portions include an edge first electrode portion, and the edge first electrode portion is located at the edge of the transistor structure along the channel length direction. The edge first electrode portion includes an edge main body portion and at least one edge protruding portion, the edge protruding portion is located between the edge main body portion and a non-edge second electrode portion, and along the channel width direction, the width of at least part of the edge protruding portion is less than the width of the edge main body portion.

20. A gate drive circuit including a shift register unit, the shift register unit including the transistor structure according to any one of claims 1 to 19.

21. A display panel comprising the gate drive circuit of claim 20.

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