Display panel and display apparatus

Abstract

A display panel and a display apparatus. When the display panel is in a first drive mode, display partitions perform display at the same refresh rate, and when the display panel is in a second drive mode, the display partitions perform display at a plurality of different refresh rates. Data voltage amplitudes corresponding to low-grayscale patterns in the first drive mode are greater than data voltage amplitudes corresponding to the same grayscale patterns in the second drive mode; and in the second drive mode, the data voltage amplitudes corresponding to the low-grayscale patterns in the display partitions increase as the refresh rates of the display partitions increase, such that residual images caused by frequency-division display are ameliorated.

Description

Display panel and display device TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0002] With the continuous development of display products in the consumer market, people have higher and higher requirements on power consumption. In order to reduce power consumption, frequency division (different refresh rates) display is adopted, and frequency division display will cause residual image.

[0003] Among them, frequency division display can be divided into high frequency display and low frequency display, and with the introduction of low frequency display, residual image becomes more and more serious. SUMMARY

[0004] The present application provides a display panel and a display device to alleviate the technical problem of residual image caused by frequency division display.

[0005] In a first aspect, the present application provides a display panel, which comprises at least two display partitions and a plurality of data lines for transmitting data voltage, each display partition comprises at least one pixel circuit, and each pixel circuit is connected with a corresponding data line; the display panel further comprises a first driving mode and a second driving mode, in the first driving mode, each display partition displays at a same refresh rate; in the second driving mode, each display partition displays at a plurality of different refresh rates; wherein the data voltage amplitude corresponding to a low gray scale pattern in the first driving mode is greater than the data voltage amplitude corresponding to the same gray scale pattern in the second driving mode.

[0006] In a second aspect, the present application provides a display device, which comprises the above-mentioned display panel.

[0007] In a third aspect, the present application provides a display device, which comprises the above-mentioned display panel, and the display panel comprises at least one pixel circuit, the pixel circuit comprises a light emitting device, and the light emitting device is an organic light emitting diode, a mini light emitting diode, a micro light emitting diode or a quantum dot light emitting diode. ADVANTAGEOUS EFFECTS

[0008] The display panel and display device provided in this application, by displaying each display partition at the same refresh rate in a first driving mode and displaying each display partition at multiple different refresh rates in a second driving mode, wherein the data voltage amplitude corresponding to the low grayscale pattern in the first driving mode is greater than the data voltage amplitude corresponding to the same grayscale pattern in the second driving mode, can adjust the on-state stress of the driving transistors of the pixel circuits in each display partition in the second driving mode, thereby reducing the difference in on-state stress caused by the data voltage amplitude at different refresh rates, thus reducing the brightness difference between each low grayscale pattern in different display partitions, and thereby improving the afterimage caused by frequency division display. Attached Figure Description

[0009] Figure 1 is a schematic diagram of the pixel circuit in the related technology.

[0010] Figure 2 is a timing diagram of the pixel circuit shown in Figure 1.

[0011] Figure 3 is a schematic diagram of the afterimage generated under the timing-driven operation shown in Figure 2.

[0012] Figure 4 is a schematic diagram illustrating the principle of image afterimage generation shown in Figure 3.

[0013] Figure 5 is a schematic diagram of the first type of driving of the display panel provided in the embodiment of this application in the test screen.

[0014] Figure 6 is a schematic diagram of the second type of driving of the display panel provided in the embodiment of this application in the test screen.

[0015] Figure 7 is a schematic diagram of the third type of driving of the display panel provided in the embodiment of this application in the test screen.

[0016] Figure 8 is a schematic diagram of the first type of driving of the display panel provided in various screens according to the embodiments of this application.

[0017] Figure 9 is a schematic diagram of the second type of driving of the display panel provided in the embodiments of this application in various screens.

[0018] Figure 10 is a schematic diagram of the third type of driving of the display panel provided in the embodiments of this application in various screens. Embodiments of the present invention

[0019] To make the objectives, technical solutions, and effects of this application clearer and more explicit, the following detailed description of this application is provided with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only for explaining this application and are not intended to limit this application.

[0020] Image retention is an important indicator for evaluating the optical performance of mobile phones, and its specifications are becoming increasingly stringent; moreover, with the introduction of low-frequency displays, image retention has become increasingly serious.

[0021] In this application, high-frequency display refers to the display panel's highest refresh rate, while low-frequency display refers to a display at a lower refresh rate. To achieve different refresh rates, a gate drive circuit is typically required in conjunction with corresponding pixel circuits. Pixel circuits capable of frequency division display include 7T1C, 7T2C, 8T1C, or 8T2C pixel circuits, etc.

[0022] The 8T2C pixel circuit, as shown in Figure 1, includes a driving transistor T1, a writing transistor T2, a compensation transistor T3, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a first initialization transistor T4, a second initialization transistor T7, a third initialization transistor T8, a bootstrap capacitor Cboost, a storage capacitor Cst, and a light-emitting device D1.

[0023] The first power line is connected to the first terminal of the first light-emitting control transistor T5 and one end of the storage capacitor Cst. The second terminal of the first light-emitting control transistor T5 is connected to the first terminal of the driving transistor T1, the first terminal of the writing transistor T2, and the first terminal of the third initialization transistor T8. The gate of the driving transistor T1 is connected to the other end of the storage capacitor Cst, the first terminal of the compensation transistor T3, the first terminal of the first initialization transistor T4, and one end of the bootstrap capacitor Cboost. The second terminal of the driving transistor T1 is connected to the second terminal of the compensation transistor T3 and the first terminal of the second light-emitting control transistor T6. The second terminal of the second light-emitting control transistor T6 is connected to the anode of the light-emitting device D1 and the first terminal of the second initialization transistor T7. The cathode of the light-emitting device D1 is connected to the second power line. The connections are as follows: the second terminal of the write transistor T2 is connected to the data line; the gate of the write transistor T2 is connected to the second gate drive line and the other end of the bootstrap capacitor Cboost; the second terminal of the third initialization transistor T8 is connected to the third initialization line; the gate of the third initialization transistor T8 is connected to the third gate drive line; the light emission control line is connected to the gate of the first light emission control transistor T5 and the gate of the second light emission control transistor T6; the gate of the compensation transistor T3 is connected to the first gate drive line; the second terminal of the first initialization transistor T4 is connected to the first initialization line; the gate of the first initialization transistor T4 is connected to the fourth gate drive line; the second terminal of the second initialization transistor T7 is connected to the second initialization line; and the gate of the second initialization transistor T7 is connected to the third gate drive line.

[0024] Among them, the light-emitting device D1 can be an organic light-emitting diode, a mini light-emitting diode, a micro light-emitting diode, or a quantum dot light-emitting diode.

[0025] Each of the above transistors can be an N-channel transistor or a P-channel transistor.

[0026] In this configuration, the first electrode can be either the source or the drain, and the second electrode can be either the source or the drain. For example, if the first electrode is the source, the second electrode is the drain; or if the first electrode is the drain, the second electrode is the source.

[0027] In this design, the first electrode of the driving transistor T1 is at the first node A. The second electrode of the driving transistor T1 is at the second node B. The anode of the light-emitting device D1 is at the third node C. The gate of the driving transistor T1 is at the fourth node Q.

[0028] The system includes the following power lines: First power line for transmitting the positive power signal VDD; second power line for transmitting the negative power signal VSS; and a data line for transmitting the data signal DS. A light-emitting control line for transmitting the light-emitting control signal EM. A first initialization line for transmitting the first initialization signal Vi_G. A second initialization line for transmitting the second initialization signal Vi_Ano. A third initialization line for transmitting the third initialization signal Vi3. A first gate drive line for transmitting the first gate drive signal Nscan1. A second gate drive line for transmitting the second gate drive signal Pscan1. A third gate drive line for transmitting the third gate drive signal Pscan2. A fourth gate drive line for transmitting the fourth gate drive signal Nscan2.

[0029] It should be noted that the 7T1C pixel circuit is the 8T2C pixel circuit shown in Figure 1, excluding the third initialization transistor T8 and the bootstrap capacitor Cboost. The 7T2C pixel circuit is the 8T2C pixel circuit shown in Figure 1, excluding the third initialization transistor T8. The 8T1C pixel circuit is the 8T2C pixel circuit shown in Figure 1, excluding the bootstrap capacitor Cboost.

[0030] Figure 2 is a timing diagram of the pixel circuit shown in Figure 1. The following explanation uses an example where compensation transistor T3 and the first initialization transistor T4 are both N-channel transistors, and all other transistors are P-channel transistors:

[0031] When the pixel circuit operates at the highest refresh rate, each frame is a write frame as shown in Figure 2. When the pixel circuit operates at a lower refresh rate, it operates according to a continuous write frame and at least one hold frame as shown in Figure 2. For example, when the highest refresh rate is 120Hz, the pixel circuit operates as a write frame for each frame at a refresh rate of 120Hz.

[0032] Specifically, when the pixel circuit operates at 10Hz, it operates sequentially with one write frame and eleven hold frames. When the pixel circuit operates at 30Hz, it operates sequentially with one write frame and three hold frames. When the pixel circuit operates at 60Hz, it operates sequentially with one write frame and one hold frame. The same logic applies to other refresh rates.

[0033] The write frame operation phase, as shown in Figure 2, includes the following stages:

[0034] Phase 1: The first gate drive signal Nscan1 and the third gate drive signal Pscan2 both output corresponding pulses. Under these conditions, the compensation transistor T3, the second initialization transistor T7, and the third initialization transistor T8 are all turned on to reset the potential of the first node A, the potential of the second node B, the potential of the third node C, and the potential of the fourth node Q.

[0035] In some other embodiments, the first gate drive signal Nscan1 may omit the first pulse during the write frame or hold.

[0036] Stage 2: The fourth gate drive signal Nscan2 outputs the corresponding pulse, and the first initialization transistor T4 turns on; the potential of the first gate drive signal Nscan1 jumps from low potential to high potential, and the compensation transistor T3 turns off first and then on; so as to reset the fourth node Q again, and write the data signal DS to the fourth node Q in the subsequent third stage M3.

[0037] Stage 3: The second gate drive signal Pscan1 outputs the corresponding pulse, the write transistor T2 is turned on, and the data signal DS is written to the fourth node Q through the write transistor T2, the drive transistor T1 and the compensation transistor T3.

[0038] Stage 4: The third gate drive signal Pscan2 outputs the corresponding pulse, and the second initialization transistor T7 and the third initialization transistor T8 are both turned on to reset the first electrode of the drive transistor T1 and the anode of the light-emitting device D1.

[0039] Holding phase: Drive transistor T1 is turned on, and other transistors are turned off. In order to achieve low brightness (such as 10 nits), the light emission time of phase 5 needs to be reduced. The total time of phases 1 to 5 is a fixed frame time, and the total duration of phases 1 to 4 is also fixed. Therefore, the duration of the holding phase varies with the duration of phase 5.

[0040] Stage 5: The light-emitting control signal EM switches from a high potential to a low potential, and both the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on. The light-emitting current flows through the light-emitting device D1, and the light begins to shine.

[0041] The working stages of the holding frame, as shown in Figure 2, include the aforementioned stages 1, 4, Holding, and 5, but do not include stages 2 and 3.

[0042] Because of the different working phases of the write frame and the hold frame, the switching between different refresh rates is achieved by using a skip frame method. This results in differences in the working phases between the write frame and the hold frame, which in turn leads to differences in the on-balance stress (OBS) of the driving transistor T1, thus worsening the image retention.

[0043] Figure 3 is a schematic diagram of image retention generated under the timing-driven process shown in Figure 2. The initial image, stress image, and recovery image are all test images. The initial image is a display panel illuminated at a specific grayscale level according to the corresponding refresh rate of each display zone. The specific grayscale level can be, for example, 48 grayscale (L48) or other grayscale levels. For example, the refresh rate of the first display zone can be 10Hz, the refresh rate of the second display zone can be 60Hz, and the refresh rate of the third display zone can be 120Hz. Each display zone includes a first display sub-zone and a second display sub-zone.

[0044] The stress display is based on the initial display, with each first display sub-area set to display the brightness corresponding to 0 grayscale (L0), and each second display sub-area set to display the brightness corresponding to 255 grayscale (L255), and maintained for a certain duration. The data signal transmitted to each first display sub-area is a first data signal DS1, and the data signal transmitted to each second display sub-area is a second data signal DS2. The pulse amplitudes of both the first data signal DS1 and the second data signal DS2 remain constant.

[0045] The restored image is a display based on the refresh rate of each display zone in the initial image, plus the grayscale of each first display sub-zone and each second display sub-zone in the stressed image. As shown in Figure 3, in the restored image, there are differences in brightness between the first display sub-zone of the first display zone, the first display sub-zone of the second display zone, the first display sub-zone of the third display zone, and the brightness of each second display sub-zone. This manifests as ghosting.

[0046] Figure 4 is a schematic diagram illustrating the principle of image retention as shown in Figure 3. The black areas represent combinations of the first display sub-regions, and the white areas represent combinations of the second display sub-regions. The schematic diagram of the driving transistor T1 shows the distribution of positive charges, holes, and negative charges in the active layer, gate insulating layer, and gate of the driving transistor T1 depending on the image. This distribution leads to changes in the gate-source voltage difference (Vgs) of the driving transistor T1, which in turn causes changes in the luminous current (Ids) flowing through the driving transistor T1. As can be seen from the figure, there is a difference between the Ids in the black areas and the Ids in the white areas.

[0047] Where OBS1-OBS4 represent the on-state stresses of the driving transistor T1 under different conditions, VI3 represents the potential of the third initialization signal Vi3, and V th1 -V th4 V represents the different threshold voltages of the driving transistor T1. data V represents the potential of the second data signal DS2 in the white area; GMP V data1 Both represent the potential of the first data signal DS1 in the black area. In other words, the potential of the first data signal DS1 can be set to various different values; K1 and K2 represent different constants.

[0048] In the initial display, the refresh rate of the first display area is 10Hz, the refresh rate of the second display area is 60Hz, and the refresh rate of the third display area is 120Hz. During the emission phase, the stress voltage experienced by each driving transistor T1 in the white and black areas is V. data1 +V th -VI3, therefore, no brightness difference was observed between display zones.

[0049] In the stress diagram, the stress voltage experienced by the driving transistor T1 in the black area is V. GMP +V th3 -VDD, the stress voltage experienced by the driving transistor T1 in the white region is V. data +V th1 -VDD, where VDD represents the potential of the positive power supply signal VDD. Since all display zones in the stress image are displayed at the same refresh rate, although the stress voltages on the driving transistors T1 in the white and black areas are different, no brightness difference is shown between the display zones.

[0050] When switching to the recovery screen, in the write frame, during stage 1, the stress voltages experienced by the driving transistor T1 in the white and black areas are respectively K1×(V) data +Vth1-VI3), K1×(V GMP+Vth3-VI3); In stage 2, the stress voltage experienced by the driving transistor T1 in both the white and black regions is K2×(VIgate-V). data1 In stage 3, the stress voltages experienced by the driving transistor T1 in the white and black regions are Vth2 and Vth4, respectively; in stage 4, the stress voltages experienced by the driving transistor T1 in the white and black regions are V... data1 +Vth2-VI3、V data1 +Vth4-VI3; In Holding, the stress voltages experienced by the driving transistor T1 in the white and black regions are V, respectively. data1 +Vth2-VI3、V data1 +Vth4-VI3.

[0051] During the hold frame, in stage 1, the stress voltages experienced by the driving transistor T1 in the white and black regions are V, respectively. data1 +Vth2-VI3、V data1 +Vth4-VI3; In stages 2 and 3, the stress voltage experienced by driving transistor T1 in the white and black regions does not have specific numerical values; in stage 4, the stress voltage experienced by driving transistor T1 in the white and black regions are respectively V data1 +Vth2-VI3、V data1 +Vth4-VI3; In Holding, the stress voltages experienced by the driving transistor T1 in the white and black regions are V, respectively. data1 +Vth2-VI3、V data1 +Vth4-VI3.

[0052] Therefore, in stages 1 and 2, the stress voltage experienced by the driving transistor T1 in the recovery screen is different in both the write frame and the hold frame in the white area and the black area. Furthermore, since the refresh rate of the first display partition in the recovery screen is 10Hz, the refresh rate of the second display partition is 60Hz, and the refresh rate of the third display partition is 120Hz, there is a difference in screen brightness between the black area and the white area.

[0053] In view of this, the test screens of different application scenarios shown in Figures 5, 6 and 7 show that when each display partition is displayed at multiple different refresh rates, the difference in open-state stress caused by the data voltage amplitude at different refresh rates can be reduced by decreasing the data voltage amplitude connected to the pixel circuit corresponding to the low grayscale pattern shown in the black area. This reduces the brightness difference between the low grayscale patterns in different display partitions, thereby improving the afterimage caused by frequency division display.

[0054] For example, as shown in Figure 5, the multiple display zones include a first display zone and a second display zone. In the initial screen, the first display zone and the second display zone display the same grayscale pattern. Therefore, even if the first display zone is displayed at a refresh rate of 10Hz and the second display zone is displayed at a refresh rate of 120Hz, there is no image retention caused by frequency division.

[0055] In the stress display, the first sub-area of ​​the first display zone and the first sub-area of ​​the second display zone display the same low-grayscale pattern, while the second sub-area of ​​the first display zone and the second sub-area of ​​the second display zone display the same high-grayscale pattern. The first display zone displays at a refresh rate of 10Hz, and the second display zone displays at a refresh rate of 120Hz. Since the stress display provides a first data signal DS1 for the first sub-area of ​​the first display zone and a second data signal DS2 for the first and second sub-areas, and provides a first data signal DS1 with a first voltage amplitude V1 for the first sub-area of ​​the first display zone and a first data signal DS1 with a second voltage amplitude V2 for the first sub-area of ​​the second display zone, and provides a second data signal DS2 with the same voltage amplitude for the second sub-area of ​​the first and second display zones, where the first voltage amplitude V1 is less than the second voltage amplitude V2, no afterimage due to frequency division occurs in the stress display.

[0056] The restored screen shows the same grayscale pattern in the first and second display zones, but with different refresh rates, and there is no ghosting caused by frequency division.

[0057] For example, as shown in Figure 6, the multiple display zones include a first display zone, a second display zone, and a third display zone. In the initial screen, the first display zone, the second display zone, and the third display zone display the same grayscale pattern. Therefore, even if the first display zone is displayed at a refresh rate of 10Hz, the second display zone at a refresh rate of 60Hz, and the third display zone at a refresh rate of 120Hz, there is no image retention caused by frequency division.

[0058] In the stress display, the first display sub-area of ​​the first display zone, the first display sub-area of ​​the second display zone, and the first display sub-area of ​​the third display zone all display the same low grayscale pattern, while the second display sub-area of ​​the first display zone, the second display sub-area of ​​the second display zone, and the second display sub-area of ​​the third display zone all display the same high grayscale pattern. The first display zone displays at a refresh rate of 10Hz, the second display zone displays at a refresh rate of 60Hz, and the third display zone displays at a refresh rate of 120Hz.

[0059] Because the stress display provides a first data signal DS1 for the first display sub-area of ​​the first display zone, the first display sub-area of ​​the second display zone, and the first display sub-area of ​​the third display zone; and a second data signal DS2 for the second display sub-area of ​​the first display zone, the second display sub-area of ​​the second display zone, and the second display sub-area of ​​the third display zone; the first display sub-area of ​​the first display zone provides a first data signal DS1 with a first voltage amplitude V1; the first display sub-area of ​​the second display zone provides a first data signal DS1 with a second voltage amplitude V2; the first display sub-area of ​​the third display zone provides a first data signal DS1 with a third voltage amplitude V3; and the second display sub-area of ​​the first display zone, the second display sub-area of ​​the second display zone, and the second display sub-area of ​​the third display zone provide a second data signal DS2 with the same voltage amplitude, where the first voltage amplitude V1 is less than the second voltage amplitude V2, and the second voltage amplitude V2 is less than the third voltage amplitude V3, no afterimage due to frequency division occurs in the stress display.

[0060] The restored screen shows the same grayscale pattern in the first, second, and third display zones, but with different refresh rates, and there is no ghosting caused by frequency division.

[0061] For example, as shown in Figure 7, the multiple display zones include a first display zone, a second display zone, and a third display zone. In the initial screen, the first display zone, the second display zone, and the third display zone display the same grayscale pattern. Therefore, even if the first display zone is displayed at a refresh rate of 60Hz, the second display zone at a refresh rate of 120Hz, and the third display zone at a refresh rate of 60Hz, there is no image retention caused by frequency division.

[0062] In the stress display, the first display sub-area of ​​the first display zone, the first display sub-area of ​​the second display zone, and the first display sub-area of ​​the third display zone all display the same low grayscale pattern, while the second display sub-area of ​​the first display zone, the second display sub-area of ​​the second display zone, and the second display sub-area of ​​the third display zone all display the same high grayscale pattern. The first display zone displays at a refresh rate of 60Hz, the second display zone displays at a refresh rate of 120Hz, and the third display zone displays at a refresh rate of 60Hz.

[0063] Because the stress display provides a first data signal DS1 for the first display sub-area of ​​the first display zone, the first display sub-area of ​​the second display zone, and the first display sub-area of ​​the third display zone; a second data signal DS2 for the second display sub-area of ​​the first display zone, the second display sub-area of ​​the second display zone, and the second display sub-area of ​​the third display zone; a first data signal DS1 with a first voltage amplitude V1 for the first display sub-area of ​​the first display zone; a first data signal DS1 with a second voltage amplitude V2 for the first display sub-area of ​​the second display zone; a first data signal DS1 with a third voltage amplitude V3 for the first display sub-area of ​​the third display zone; and a second data signal DS2 with the same voltage amplitude for the second display sub-area of ​​the first display zone, the second display sub-area of ​​the second display zone, and the second display sub-area of ​​the third display zone, respectively. Where the first voltage amplitude V1 is equal to the third voltage amplitude V3, and the second voltage amplitude V2 is greater than either the first voltage amplitude V1 or the third voltage amplitude V3, no afterimage due to frequency division occurs in the stress display.

[0064] The restored screen displays the same grayscale pattern in the first, second, and third display zones at the corresponding refresh rates, and there is no ghosting caused by frequency division.

[0065] The low grayscale pattern corresponds to the pattern displayed in the black area mentioned above. The high grayscale pattern corresponds to the pattern displayed in the white area mentioned above.

[0066] Based on the research and verification of the causes of image retention caused by the above frequency division and the test screens shown in Figures 5 to 7, the inventors of this application found that the following embodiments can effectively improve the image retention caused by frequency division in both test screens and actual normal displays.

[0067] In one embodiment, this embodiment provides a display panel, as shown in Figures 8 to 10. The display panel includes at least two display zones and multiple data lines for transmitting data voltage. Each display zone includes at least one pixel circuit, and each pixel circuit is connected to a corresponding data line. The display panel also includes a first driving mode and a second driving mode. In the first driving mode, each display zone displays at the same refresh rate. In the second driving mode, each display zone displays at multiple different refresh rates. In the first driving mode, the data voltage amplitude corresponding to a low grayscale pattern is greater than the data voltage amplitude corresponding to the same grayscale pattern in the second driving mode.

[0068] It is understood that the display panel provided in this embodiment displays each display partition at the same refresh rate in the first driving mode and each display partition at multiple different refresh rates in the second driving mode. In the first driving mode, the data voltage amplitude corresponding to the low grayscale pattern is greater than the data voltage amplitude corresponding to the same grayscale pattern in the second driving mode. This can adjust the on-state stress of the driving transistors of the pixel circuits in each display partition in the second driving mode, thereby reducing the difference in on-state stress caused by the data voltage amplitude at different refresh rates. This reduces the brightness difference between the low grayscale patterns in different display partitions, thereby improving the image retention caused by frequency division display.

[0069] It should be noted that the display panel also includes a data driver, a timing controller, and a gate drive circuit. The data driver is connected to multiple data lines; the timing controller is connected to the data driver, and the timing controller identifies the low grayscale pattern and high grayscale pattern in each frame of the video signal, and controls the data driver to output a data voltage of corresponding amplitude according to the low grayscale pattern and high grayscale pattern; the gate drive circuit is connected to the timing controller and the pixel circuit. Under the control of the timing controller, the gate drive circuit controls the pixel circuit in each display zone to display according to the corresponding refresh rate.

[0070] The pixel circuit includes a driving transistor T1. When the driving transistor T1 is a P-channel transistor, the data voltage amplitude is the absolute value of the negative pulse voltage in the data line; or, when the driving transistor T1 is an N-channel transistor, the data voltage amplitude is the voltage amplitude of the positive pulse in the data line.

[0071] Each frame may include at least one of a low-grayscale pattern and a high-grayscale pattern. A low-grayscale pattern is a pattern displayed at a low grayscale level, and a high-grayscale pattern is a pattern displayed at a high grayscale level. The distinction between low and high grayscale levels can be made using a threshold grayscale level as the dividing line; all grayscale levels greater than or equal to this threshold grayscale level are collectively referred to as high grayscale levels; all grayscale levels less than this threshold grayscale level are collectively referred to as low grayscale levels. The data voltage amplitude is the voltage amplitude of the data signal pulse.

[0072] In one embodiment, the data voltage amplitude corresponding to the high grayscale pattern in the first driving mode is equal to the data voltage amplitude corresponding to the same grayscale pattern in the second driving mode.

[0073] It should be noted that research has found that high grayscale patterns do not cause corresponding image retention when frequency division is used, or the resulting image retention is so slight as to be negligible. Therefore, the amplitude of the data voltage received by the pixel circuit for displaying high grayscale patterns is not adjusted, in order to reduce the frequency of change of the amplitude of the data voltage received by the pixel circuit for displaying high grayscale patterns, thereby reducing the power consumption and load of the data driver.

[0074] In one embodiment, in the second driving mode, the data voltage amplitude corresponding to the low grayscale pattern in the display partition increases as the refresh rate of the display partition increases.

[0075] For example, in Figure 8, in the second driving mode, at least two display partitions include a first display partition and a second display partition; the first display partition displays at a first refresh rate, and the second display partition displays at a second refresh rate, wherein the first refresh rate is less than the second refresh rate; the data voltage amplitude connected to the pixel circuit displaying the low grayscale pattern in the first display partition is less than the data voltage amplitude connected to the pixel circuit displaying the same grayscale pattern in the second display partition.

[0076] It should be noted that in the second driving mode, the data voltage amplitude connected to the pixel circuit displaying the high grayscale pattern in the first display partition is equal to the data voltage amplitude connected to the pixel circuit displaying the same grayscale pattern in the second display partition.

[0077] For example, the first refresh rate is 10Hz and the second refresh rate is 120Hz. The low grayscale pattern is the pattern displayed in the left portion of the first display zone and the pattern displayed in the left portion of the second display zone. The high grayscale pattern is the pattern displayed in the right portion of the first display zone and the pattern displayed in the right portion of the second display zone.

[0078] Specifically, a first data signal DS1 with a first voltage amplitude V1 is provided to the pixel circuit in the left part of the first display partition, and a first data signal DS1 with a second voltage amplitude V2 is provided to the pixel circuit in the left part of the second display partition. The first voltage amplitude V1 is smaller than the second voltage amplitude V2. This can reduce the difference in open-state stress caused by the data voltage amplitude at different refresh rates, thereby reducing the brightness difference between low grayscale patterns in different display partitions and improving the afterimage caused by frequency division display.

[0079] Among them, a second data signal DS2 is provided for the pixel circuits in the right part of the first display partition and the second display partition.

[0080] In one embodiment, as shown in FIG9, at least two display partitions further include a third display partition; the third display partition displays at a third refresh rate, which is greater than the second refresh rate; the data voltage amplitude connected to the pixel circuit displaying the low grayscale pattern in the second display partition is less than the data voltage amplitude connected to the pixel circuit displaying the same grayscale pattern in the third display partition.

[0081] It should be noted that in the second driving mode, the data voltage amplitude connected to the pixel circuit displaying the high grayscale pattern in the second display partition is equal to the data voltage amplitude connected to the pixel circuit displaying the same grayscale pattern in the third display partition.

[0082] For example, the first refresh rate is 10Hz, the second refresh rate is 60Hz, and the third refresh rate is 120Hz. The low grayscale pattern is the pattern displayed in the left portion of the first display zone, the left portion of the second display zone, and the left portion of the third display zone. The high grayscale pattern is the pattern displayed in the right portion of the first display zone, the right portion of the second display zone, and the right portion of the third display zone.

[0083] Specifically, a first data signal DS1 with a first voltage amplitude V1 is provided to the pixel circuit in the left part of the first display partition, a first data signal DS1 with a second voltage amplitude V2 is provided to the pixel circuit in the left part of the second display partition, and a first data signal DS1 with a third voltage amplitude V3 is provided to the pixel circuit in the left part of the third display partition. The first voltage amplitude V1 is less than the second voltage amplitude V2, and the second voltage amplitude V2 is less than the third voltage amplitude V3. This can reduce the difference in open-state stress caused by the data voltage amplitude at different refresh rates, thereby reducing the brightness difference between low grayscale patterns in different display partitions and improving the afterimage caused by frequency division display.

[0084] The second data signal DS2 is provided for the pixel circuits in the right part of the first display partition, the second display partition, and the third display partition.

[0085] In one embodiment, as shown in FIG10, at least two display partitions further include a third display partition; the third display partition displays at a third refresh rate, which is equal to the first refresh rate; the data voltage amplitude connected to the pixel circuit displaying the low grayscale pattern in the second display partition is equal to the data voltage amplitude connected to the pixel circuit displaying the same grayscale pattern in the third display partition; the data voltage amplitude connected to the pixel circuit displaying the high grayscale pattern in the second display partition is equal to the data voltage amplitude connected to the pixel circuit displaying the same grayscale pattern in the third display partition.

[0086] For example, the first refresh rate is 60Hz, the second refresh rate is 120Hz, and the third refresh rate is 60Hz. The low grayscale pattern is the pattern displayed in the left portion of the first display zone, the left portion of the second display zone, and the left portion of the third display zone. The high grayscale pattern is the pattern displayed in the right portion of the first display zone, the right portion of the second display zone, and the right portion of the third display zone.

[0087] Specifically, a first data signal DS1 with a first voltage amplitude V1 is provided to the pixel circuit in the left part of the first display partition, a first data signal DS1 with a second voltage amplitude V2 is provided to the pixel circuit in the left part of the second display partition, and a first data signal DS1 with a third voltage amplitude V3 is provided to the pixel circuit in the left part of the third display partition. The first voltage amplitude V1 is less than the second voltage amplitude V2, and the third voltage amplitude V3 is equal to the first voltage amplitude V1. This can reduce the difference in open-state stress caused by the data voltage amplitude at different refresh rates, thereby reducing the brightness difference between low grayscale patterns in different display partitions and improving the afterimage caused by frequency division display.

[0088] The second data signal DS2 is provided for the pixel circuits in the right part of the first display partition, the second display partition, and the third display partition.

[0089] In one embodiment, this embodiment provides a display device that includes the display panel described above.

[0090] It is understood that, since the display device provided in this embodiment includes the aforementioned display panel, it can also display each display partition at the same refresh rate in the first driving mode and at multiple different refresh rates in the second driving mode. In the first driving mode, the data voltage amplitude corresponding to the low grayscale pattern is greater than that corresponding to the same grayscale pattern in the second driving mode. This can adjust the on-state stress of the driving transistors of the pixel circuits in each display partition in the second driving mode, thereby reducing the difference in on-state stress caused by the data voltage amplitude at different refresh rates. This reduces the brightness difference between the low grayscale patterns in different display partitions, thereby improving the image retention caused by frequency division display.

[0091] It should be noted that the aforementioned display devices can be electronic products with display functions, such as mobile phones, tablets, televisions, smartwatches, wristbands, virtual reality devices, and augmented reality devices.

[0092] It is understood that those skilled in the art can make equivalent substitutions or changes based on the technical solution and inventive concept of this application, and all such substitutions or changes should fall within the protection scope of the appended claims.

Claims

1. A display panel, wherein, The display panel includes at least two display zones and multiple data lines for transmitting data voltage. Each display zone includes at least one pixel circuit, and each pixel circuit is connected to a corresponding data line. The display panel also includes: In the first driving mode, each of the display partitions is displayed at the same refresh rate; The second driving mode, in which each of the display partitions is displayed at multiple different refresh rates; In the first driving mode, the data voltage amplitude corresponding to the low grayscale pattern is greater than the data voltage amplitude corresponding to the same grayscale pattern in the second driving mode.

2. The display panel according to claim 1, wherein, In the second driving mode, the data voltage amplitude corresponding to the low grayscale pattern in the display partition increases as the refresh rate of the display partition increases.

3. The display panel according to claim 1, wherein, In the first driving mode, the data voltage amplitude corresponding to the high grayscale pattern is equal to the data voltage amplitude corresponding to the same grayscale pattern in the second driving mode.

4. The display panel according to claim 1, wherein, The at least two display partitions include a first display partition, a second display partition, and a third display partition; The first display partition is displayed at a first refresh rate, and the second display partition is displayed at a second refresh rate, wherein the first refresh rate is less than the second refresh rate; The data voltage amplitude connected to the pixel circuit displaying the low grayscale pattern in the first display partition is less than the data voltage amplitude connected to the pixel circuit displaying the same grayscale pattern in the second display partition. The third display partition is displayed at a third refresh rate, which is greater than the second refresh rate; The data voltage amplitude connected to the pixel circuit displaying the low grayscale pattern in the second display partition is less than the data voltage amplitude connected to the pixel circuit displaying the same grayscale pattern in the third display partition.

5. The display panel according to claim 4, wherein, In the second driving mode, the data voltage amplitude connected to the pixel circuit displaying the high grayscale pattern in the first display partition is equal to the data voltage amplitude connected to the pixel circuit displaying the same grayscale pattern in the second display partition. The data voltage amplitude connected to the pixel circuit displaying the high grayscale pattern in the second display partition is equal to the data voltage amplitude connected to the pixel circuit displaying the same grayscale pattern in the third display partition.

6. The display panel according to claim 1, wherein, The at least two display partitions include a first display partition, a second display partition, and a third display partition; The first display partition is displayed at a first refresh rate, and the second display partition is displayed at a second refresh rate, wherein the first refresh rate is less than the second refresh rate; The data voltage amplitude connected to the pixel circuit displaying the low grayscale pattern in the first display partition is less than the data voltage amplitude connected to the pixel circuit displaying the same grayscale pattern in the second display partition. The third display partition is displayed at a third refresh rate, which is equal to the first refresh rate; The data voltage amplitude connected to the pixel circuit displaying the low grayscale pattern in the first display partition is equal to the data voltage amplitude connected to the pixel circuit displaying the same grayscale pattern in the third display partition. The data voltage amplitude connected to the pixel circuit displaying the high grayscale pattern in the second display partition is equal to the data voltage amplitude connected to the pixel circuit displaying the same grayscale pattern in the first or third display partition.

7. The display panel according to claim 2, wherein, The pixel circuit includes a driving transistor, and when the driving transistor is a P-channel transistor, the data voltage amplitude is the absolute value of the negative pulse voltage in the data line.

8. The display panel according to claim 2, wherein, The pixel circuit includes a driving transistor, and when the driving transistor is an N-channel transistor, the data voltage amplitude is the voltage amplitude of the positive pulse in the data line.

9. The display panel according to any one of claims 1-7, wherein, The display panel also includes: A data driver, which is connected to the plurality of data lines; A timing controller is connected to the data driver. The timing controller identifies low-grayscale patterns and high-grayscale patterns in each frame of the incoming video signal, and controls the data driver to output data voltages with corresponding amplitudes based on the low-grayscale patterns and the high-grayscale patterns. A gate driving circuit is connected to the timing controller and the pixel circuit. Under the control of the timing controller, the gate driving circuit controls the pixel circuits in each display zone to display according to the corresponding refresh rate.

10. A display device, wherein, The display device includes a display panel, which includes at least two display zones and multiple data lines for transmitting data voltage. Each display zone includes at least one pixel circuit, and each pixel circuit is connected to a corresponding data line. The display panel also includes: In the first driving mode, each of the display partitions is displayed at the same refresh rate; The second driving mode, in which each of the display partitions is displayed at multiple different refresh rates; In the first driving mode, the data voltage amplitude corresponding to the low grayscale pattern is greater than the data voltage amplitude corresponding to the same grayscale pattern in the second driving mode.

11. The display device according to claim 10, wherein, In the second driving mode, the data voltage amplitude corresponding to the low grayscale pattern in the display partition increases as the refresh rate of the display partition increases.

12. The display device according to claim 10, wherein, In the first driving mode, the data voltage amplitude corresponding to the high grayscale pattern is equal to the data voltage amplitude corresponding to the same grayscale pattern in the second driving mode.

13. The display device according to claim 10, wherein, The at least two display partitions include a first display partition, a second display partition, and a third display partition; The first display partition is displayed at a first refresh rate, and the second display partition is displayed at a second refresh rate, wherein the first refresh rate is less than the second refresh rate; The data voltage amplitude connected to the pixel circuit displaying the low grayscale pattern in the first display partition is less than the data voltage amplitude connected to the pixel circuit displaying the same grayscale pattern in the second display partition. The third display partition is displayed at a third refresh rate, which is greater than the second refresh rate; The data voltage amplitude connected to the pixel circuit displaying the low grayscale pattern in the second display partition is less than the data voltage amplitude connected to the pixel circuit displaying the same grayscale pattern in the third display partition.

14. The display device according to claim 13, wherein, In the second driving mode, the data voltage amplitude connected to the pixel circuit displaying the high grayscale pattern in the first display partition is equal to the data voltage amplitude connected to the pixel circuit displaying the same grayscale pattern in the second display partition. The data voltage amplitude connected to the pixel circuit displaying the high grayscale pattern in the second display partition is equal to the data voltage amplitude connected to the pixel circuit displaying the same grayscale pattern in the third display partition.

15. The display device according to claim 10, wherein, The at least two display partitions include a first display partition, a second display partition, and a third display partition; The first display partition is displayed at a first refresh rate, and the second display partition is displayed at a second refresh rate, wherein the first refresh rate is less than the second refresh rate; The data voltage amplitude connected to the pixel circuit displaying the low grayscale pattern in the first display partition is less than the data voltage amplitude connected to the pixel circuit displaying the same grayscale pattern in the second display partition. The third display partition is displayed at a third refresh rate, which is equal to the first refresh rate; The data voltage amplitude connected to the pixel circuit displaying the low grayscale pattern in the first display partition is equal to the data voltage amplitude connected to the pixel circuit displaying the same grayscale pattern in the third display partition. The data voltage amplitude connected to the pixel circuit displaying the high grayscale pattern in the second display partition is equal to the data voltage amplitude connected to the pixel circuit displaying the same grayscale pattern in the first or third display partition.

16. The display device according to claim 11, wherein, The pixel circuit includes a driving transistor, and when the driving transistor is a P-channel transistor, the data voltage amplitude is the absolute value of the negative pulse voltage in the data line.

17. The display device according to claim 11, wherein, The pixel circuit includes a driving transistor, and when the driving transistor is an N-channel transistor, the data voltage amplitude is the voltage amplitude of the positive pulse in the data line.

18. The display device according to any one of claims 10-17, wherein, The display panel also includes: A data driver, which is connected to the plurality of data lines; A timing controller is connected to the data driver. The timing controller identifies low-grayscale patterns and high-grayscale patterns in each frame of the incoming video signal, and controls the data driver to output data voltages with corresponding amplitudes based on the low-grayscale patterns and the high-grayscale patterns. A gate driving circuit is connected to the timing controller and the pixel circuit. Under the control of the timing controller, the gate driving circuit controls the pixel circuits in each display zone to display according to the corresponding refresh rate.

19. A display device, wherein, The display device includes a display panel, which includes at least two display zones and multiple data lines for transmitting data voltage. Each display zone includes at least one pixel circuit, and each pixel circuit is connected to a corresponding data line. The display panel also includes: In the first driving mode, each of the display partitions is displayed at the same refresh rate; The second driving mode, in which each of the display partitions is displayed at multiple different refresh rates; In the first driving mode, the data voltage amplitude corresponding to the low grayscale pattern is greater than the data voltage amplitude corresponding to the same grayscale pattern in the second driving mode; the pixel circuit includes a light-emitting device, which is an organic light-emitting diode, a mini light-emitting diode, a micro light-emitting diode, or a quantum dot light-emitting diode.

20. The display device according to claim 19, wherein, In the second driving mode, the data voltage amplitude corresponding to the low grayscale pattern in the display partition increases as the refresh rate of the display partition increases.

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