Display panel, display motherboard and display device

Abstract

The embodiments of the present disclosure relate to the technical field of display. Provided are a display panel, a display motherboard and a display device, which are used for improving the yield of the display panel. The display panel is provided with a through hole. The display panel comprises a display region and a transition region, which are adjacent to each other, wherein the display region surrounds the transition region, and the transition region surrounds the through hole. The display panel further comprises a rigid substrate, a first etching barrier layer and a light-emitting device layer. The first etching barrier layer is located on one side of the rigid substrate and is located in the transition region. The first etching barrier layer is arranged around the through hole, and the boundary of the first etching barrier layer close to the through hole is arranged adjacent to or flush with the boundary of the rigid substrate close to the through hole. The light-emitting device layer is located on the side of the first etching barrier layer away from the substrate and is located in the transition region and the display region. The display panel is used for displaying images.

Description

Display panel, display motherboard and display device

[0001] This application claims priority to Chinese patent application No. 202410703983.9, filed on May 31, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to the field of display technology, and in particular to a display panel, a display motherboard, and a display device. Background Technology

[0003] With the development of smartphones, consumers are increasingly demanding products with larger screen ratios and narrower bezels, giving rise to HIAA (Hole In Active Area) technology. HIAA technology places the phone's camera and other components below the display panel, with that area not displaying anything; this is what is commonly known as a punch-hole screen or cutout screen on the market today. Summary of the Invention

[0004] On one hand, a display motherboard is provided. The display motherboard includes a display area, a transition area, and a pre-aperture area that are sequentially adjacent to each other. The display area surrounds the transition area, and the transition area surrounds the pre-aperture area. The display motherboard further includes a rigid substrate, a first etch barrier layer, and a light-emitting device layer. The first etch barrier layer is located on one side of the rigid substrate and is located within the transition area and the pre-aperture area. The first etch barrier layer is disposed around the central region of the pre-aperture area. The light-emitting device layer is located on the side of the first etch barrier layer away from the rigid substrate and is located within the transition area and the display area.

[0005] In some embodiments, the display motherboard further includes an inorganic stack. The inorganic stack is located on the side of the first etch barrier layer closest to the rigid substrate. The inorganic stack includes a first portion located in the display area, a second portion located in the transition area, and a third portion located in the pre-aperture area. The thickness of the region corresponding to the first etch barrier layer in the third portion and the thickness of the second portion are both less than the thickness of the first portion.

[0006] In some embodiments, the display motherboard further includes an alignment mark and at least one second blocking portion. The alignment mark is located within the third portion and at the center of the pre-drilled area. At least one second blocking portion is embedded within the third portion. The second blocking portion is disposed around the alignment mark. In cases where the display motherboard includes a plurality of second blocking portions, the plurality of second blocking portions are sequentially spaced apart along a direction away from the alignment mark.

[0007] In some embodiments, the distance between the second blocking portion and the rigid substrate is less than the distance between the alignment mark and the rigid substrate.

[0008] In some embodiments, the material of the second barrier portion includes an organic material.

[0009] In some embodiments, the display motherboard further includes a first planarization layer and a second planarization layer sequentially stacked along a direction away from the rigid substrate. The first planarization layer and the second planarization layer are located between the inorganic stack and the light-emitting device layer, and are located between the display area and the pre-aperture area.

[0010] The first planarization layer and the second blocking portion are disposed in the same layer. Alternatively, the second blocking portion penetrates through the first planarization layer, and the second blocking portion and the second planarization layer are disposed in the same layer.

[0011] In some embodiments, the display motherboard further includes a plurality of virtual pixel circuits. The plurality of virtual pixel circuits are disposed in the pre-aperture area and located between the light-emitting device layer and the rigid substrate. The plurality of virtual pixel circuits are closer to the display area than the alignment mark.

[0012] The second blocking portion is located between two adjacent virtual pixel circuits. Alternatively, the second blocking portion is located between the alignment mark and the virtual pixel circuit adjacent to the alignment mark.

[0013] On the other hand, a display panel is provided. The display panel has a through hole. The display panel includes an adjacent display area and a transition area, the display area surrounding the transition area and the transition area surrounding the through hole.

[0014] The display panel further includes a rigid substrate, a first etch barrier layer, and a light-emitting device layer. The first etch barrier layer is located on one side of the rigid substrate and in the transition region. The first etch barrier layer is disposed around the via, and the boundary of the first etch barrier layer near the via is adjacent to or flush with the boundary of the rigid substrate near the via. The light-emitting device layer is located on the side of the first etch barrier layer away from the rigid substrate and is located in both the transition region and the display region.

[0015] In some embodiments, the first etching barrier layer comprises an organic material.

[0016] In some embodiments, the display panel further includes a first planarization layer. The first planarization layer is located between the rigid substrate and the light-emitting device layer. The first etch barrier layer and the first planarization layer are disposed in the same layer.

[0017] In some embodiments, the display panel further includes at least one first blocking portion. The first blocking portion is located between the first etch stop layer and the light-emitting device layer, and is located in the transition region. The first blocking portion is disposed around the through-hole. In the case where the display panel includes a plurality of first blocking portions, the plurality of first blocking portions are sequentially spaced apart along a direction away from the through-hole.

[0018] In some embodiments, the material of the first blocking portion includes metal.

[0019] In some embodiments, the display panel further includes a second source / drain metal layer. The second source / drain metal layer is located between the first etch barrier layer and the light-emitting device layer. The first barrier portion is located within the second source / drain metal layer.

[0020] In some embodiments, the display panel further includes a second etch barrier layer. The second etch barrier layer is located between the first etch barrier layer and the light-emitting device layer, and is situated in the transition region. The second etch barrier layer is disposed around the via, and the boundary of the second etch barrier layer near the via is adjacent to or flush with the boundary of the rigid substrate near the via.

[0021] In some embodiments, the display panel further includes a second planarization layer and a pixel definition layer. The first planarization layer, the second planarization layer, and the pixel definition layer are stacked sequentially along a direction away from the rigid substrate.

[0022] The second etch barrier layer is disposed on the same layer as either the second planarization layer or the pixel definition layer. Alternatively, the second etch barrier layer includes a first sub-layer and a second sub-layer sequentially stacked along a direction away from the rigid substrate, wherein the first sub-layer and the second planarization layer are disposed on the same layer, and the second sub-layer and the pixel definition layer are disposed on the same layer.

[0023] In some embodiments, the display panel further includes a first blocking portion. The first blocking portion is located between the first etch stop layer and the second etch stop layer.

[0024] In some embodiments, the surface of the first etch barrier layer is in contact with the rigid substrate.

[0025] In some embodiments, the display panel further includes an inorganic stack. The inorganic stack includes a first portion located in the display area and a second portion located in the transition area. The thickness of the first portion is greater than the thickness of the second portion, and the second portion surrounds the through-hole. The inorganic stack forms a trench at the second portion, and the first etch barrier layer is at least partially embedded in the trench.

[0026] In some embodiments, the thickness of the second portion is less than or equal to

[0027] In another aspect, a display device is provided, comprising a display panel and a photosensitive device as described above. The photosensitive device is disposed within a through-hole in the display panel. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0029] Figure 1 is a structural diagram of a display device according to some embodiments;

[0030] Figure 2 is a structural diagram of a display panel according to some embodiments;

[0031] Figure 3A is a structural diagram of a display motherboard according to some embodiments;

[0032] Figure 3B is an enlarged view of the EE area of ​​the display motherboard in Figure 3A;

[0033] Figure 4 is a cross-sectional view of a partial area of ​​a display motherboard according to some embodiments;

[0034] Figure 5 is a diagram of the film structure of a sub-pixel according to some embodiments;

[0035] Figure 6 is a cross-sectional view of the display motherboard in Figure 3B along section line CC;

[0036] Figure 7 is a flowchart of a method for manufacturing a display panel according to some embodiments;

[0037] Figure 8 is a structural diagram corresponding to step S1 in the method for preparing the display panel according to the embodiment shown in Figure 7;

[0038] Figure 9 is a structural diagram corresponding to step S2 in the manufacturing method of the display panel according to the embodiment shown in Figure 7;

[0039] Figure 10 is a structural diagram corresponding to step S3 in the method for preparing the display panel according to the embodiment shown in Figure 7;

[0040] Figure 11A is another cross-sectional view of a partial area of ​​a display motherboard according to some embodiments;

[0041] Figure 11B is a plan view of the first etch barrier layer of a display motherboard according to some embodiments;

[0042] Figure 12 is a cross-sectional view of a partial area of ​​a display panel formed using the display motherboard shown in Figure 11A;

[0043] Figure 13 is yet another cross-sectional view of a partial area of ​​a display motherboard according to some embodiments;

[0044] Figure 14A is yet another cross-sectional view of a partial area of ​​a display motherboard according to some embodiments;

[0045] Figure 14B is yet another cross-sectional view of a partial area of ​​a display motherboard according to some embodiments;

[0046] Figure 14C is a plan view of the second etch barrier layer of a display motherboard according to some embodiments;

[0047] Figure 15A is a cross-sectional view of a partial area of ​​a display panel formed using the display motherboard shown in Figure 14A;

[0048] Figure 15B is a cross-sectional view of a partial area of ​​a display panel formed using the display motherboard shown in Figure 14B;

[0049] Figure 16A is yet another cross-sectional view of a partial area of ​​a display motherboard according to some embodiments;

[0050] Figure 16B is a plan view of the first blocking portion of the display motherboard according to some embodiments;

[0051] Figure 17 is a cross-sectional view of a partial area of ​​a display panel formed using the display motherboard shown in Figure 16A;

[0052] Figure 18 is yet another cross-sectional view of a partial area of ​​a display motherboard according to some embodiments;

[0053] Figure 19 is a cross-sectional view of a partial area of ​​a display panel formed using the display motherboard shown in Figure 18;

[0054] Figure 20 is yet another cross-sectional view of a partial area of ​​a display motherboard according to some embodiments;

[0055] Figure 21 is a cross-sectional view of a partial area of ​​a display panel formed using the display motherboard shown in Figure 20;

[0056] Figure 22 is yet another cross-sectional view of a partial area of ​​a display motherboard according to some embodiments;

[0057] Figure 23 is a plan view of the second blocking portion of the display motherboard according to some embodiments;

[0058] Figure 24 is yet another cross-sectional view of a partial area of ​​a display motherboard according to some embodiments;

[0059] Figure 25 is yet another cross-sectional view of a partial area of ​​a display motherboard according to some embodiments;

[0060] Figure 26 is a cross-sectional view of a partial area of ​​a display panel formed using the display motherboard shown in Figure 25;

[0061] Figure 27 is another cross-sectional view of a partial area of ​​a display motherboard according to some embodiments;

[0062] Figure 28 is a cross-sectional view of a partial area of ​​a display panel formed using the display motherboard shown in Figure 27. Detailed Implementation

[0063] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0064] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0065] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0066] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. The term "connected" should be interpreted broadly; for example, a "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection via an intermediate medium. The term "coupled," for example, indicates that two or more components have direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0067] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0068] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0069] As used herein, depending on the context, the term “if” may optionally be interpreted as meaning “when”, “in the event of”, “in response to determination”, or “in response to detection”. Similarly, depending on the context, the phrase “if it is determined that…” or “if [the stated condition or event] is detected” may optionally be interpreted as meaning “in the event of determination that…”, “in response to determination that…”, “when [the stated condition or event] is detected”, or “in response to the detection of [the stated condition or event]”.

[0070] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0071] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0072] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0073] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable range of deviation for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.

[0074] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0075] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0076] For ease of description below, an XYZ coordinate system is established. The third direction Z represents the thickness direction of the display device, the XY plane is perpendicular to the Z direction, and the first direction X intersects the second direction Y. For example, the first direction X and the second direction Y are perpendicular to each other.

[0077] As shown in FIG1, some embodiments of the present disclosure provide a display device 100.

[0078] Exemplarily, display device 100 can be any device that displays images, whether moving (e.g., video) or stationary (e.g., still images), and whether text or images. More specifically, the embodiments described are contemplated to be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controllers and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging and aesthetic structures (e.g., displays of images of a piece of jewelry), etc. Figure 1 illustrates display device 100 as an example of a mobile phone.

[0079] For example, the display device 100 may be an electroluminescent display device or a photoluminescent display device. When the display device 100 is an electroluminescent display device, it may be an organic light-emitting diode (OLED) or a quantum dot light-emitting diode (QLED). When the display device 100 is a photoluminescent display device, it may be a quantum dot photoluminescent display device.

[0080] The following uses an organic light-emitting diode (OLED) display device 100 as an example to illustrate some embodiments of the present disclosure. However, the implementation of the present disclosure includes, but is not limited to, these embodiments. Any other display device can also be considered as long as the same technical concept is applied.

[0081] In some embodiments, referring to FIG1, the display device 100 may include a display panel 10 and a circuit board (not shown). The circuit board is electrically connected to the display panel 10 and is configured to drive the display panel 10 to display an image.

[0082] For example, circuit boards include, but are not limited to, PCBs (Printed Circuit Boards) and FPCs (Flexible Printed Circuit Boards).

[0083] In some embodiments, please continue to refer to FIG1, the display device 100 may further include a photosensitive element 20.

[0084] For example, the photosensitive device 20 may include a camera, enabling the display device 100 to perform various functions such as taking pictures, recording videos, or facial recognition.

[0085] The photosensitive device 20 may also include sensors, etc. For example, the photosensitive device 20 may include an under-display fingerprint recognition sensor, enabling the display device 100 to perform functions such as fingerprint recognition.

[0086] The display panel 10 described above will be described in detail below.

[0087] In some embodiments, as shown in FIG2, FIG2 is a structural diagram of a display panel 10 according to some embodiments. The display panel 10 may be a rectangular structure.

[0088] It should be noted that the aforementioned "rectangular structure" refers to the fact that the overall shape of the boundary of the display panel 10 is rectangular, but it is not limited to a standard rectangle. That is, the "rectangle" here includes not only the shape of a standard rectangle, but also shapes similar to rectangles, taking into account manufacturing conditions. For example, as shown in Figure 2, the long and short sides of the rectangle are curved at each intersection point (i.e., at the corner G), meaning that the corner G is smooth, making the boundary of the display panel 10 a rounded rectangle in the plan view.

[0089] In other embodiments, the display panel 10 may be a circular structure or other shapes with corners.

[0090] The following uses a rectangular structure for the display panel 10 as an example to illustrate some embodiments of the present disclosure. However, the implementation of the present disclosure includes, but is not limited to, this, and the shape of the display panel 10 can also be any other shape.

[0091] In some embodiments, please continue to refer to FIG2, the display panel 10 has a display area AA for displaying images and a peripheral area AN located on at least one side of the display area AA.

[0092] For example, the peripheral area AN is located on one side of the display area AA.

[0093] For example, the peripheral area AN is located on both sides of the display area AA.

[0094] For example, as shown in Figure 2, the peripheral area AN surrounds the display area AA.

[0095] It should be noted that the specific setting of the peripheral area AN is related to the specific design of the display panel 10, and can be designed according to actual needs. This is only an example and is not intended to limit this disclosure.

[0096] In some embodiments, please continue to refer to FIG2, a plurality of sub-pixels 9 are provided in the display area AA of the display panel 10, and the sub-pixel 9 is the smallest light-emitting unit in the display area AA.

[0097] For example, multiple sub-pixels 9 within the display area AA of the display panel 10 can emit light of the same color. The display panel 10 may also include a color filter layer disposed on the light-emitting side of the multiple sub-pixels 9. For instance, the multiple sub-pixels 9 may emit light of colors such as white, red, green, or blue. In this case, the colored light emitted by the sub-pixels 9 may remain as the same color light after passing through the color filter layer, or be converted into other colors of light for emission. Thus, when the multiple sub-pixels 9 emit light of the same color, the display panel 10 can achieve multi-color light emission.

[0098] Alternatively, multiple sub-pixels 9 within the display area AA of the display panel 10 can emit light of different colors. For example, the multiple sub-pixels 9 may include a red light sub-pixel that emits red light, a green light sub-pixel that emits green light, and a blue light sub-pixel that emits blue light, thereby achieving multi-color light emission from the display panel 10.

[0099] In some embodiments, a plurality of pixel driving circuits (not shown in the figure) are also provided in the display area AA of the display panel 10. The pixel driving circuits are connected to the sub-pixels 9 and are used to drive the sub-pixels 9 to emit light.

[0100] For example, the pixel driving circuit includes multiple transistors. The pixel driving circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. Here, T represents a transistor, and the number preceding T indicates the number of transistors; C represents a capacitor, and the number preceding C indicates the number of capacitors.

[0101] For example, the transistors in the pixel driving circuit can be low-temperature polycrystalline silicon (LTPS) transistors, oxide transistors, or a combination of both. The active layer of the LTPS transistor is made of low-temperature polycrystalline silicon (LTPS), while the active layer of the oxide transistor is made of oxide semiconductor (Oxide). LTPS transistors have advantages such as high mobility and fast charging, while oxide transistors have advantages such as low leakage current. When LTPS transistors and oxide transistors are integrated onto a single display panel 10, a low-temperature polycrystalline oxide (LTPO) display panel can be formed. Utilizing the advantages of both, the refresh rate of the display panel 10 can be switched to achieve low-frequency driving, which helps reduce power consumption and improve display quality.

[0102] For example, the transistor in the pixel driving circuit can be a top-gate transistor, a bottom-gate transistor, or a dual-gate transistor. A dual-gate transistor includes an active layer pattern and top-gate and bottom-gate patterns disposed on either side of the active layer pattern. By driving the active layer pattern through the top-gate and bottom-gate patterns, the threshold voltage can be controlled more easily; simultaneously, carrier mobility can be improved. That is, compared to top-gate and bottom-gate transistors, dual-gate transistors offer higher stability.

[0103] For example, the transistor in the pixel driving circuit can be a P-type transistor or an N-type transistor.

[0104] In some embodiments, referring to FIG2, the display panel 10 is also provided with a through hole K, namely HIAA (Hole In Active Area). A photosensitive device 20 (e.g., a camera or sensor) in the display device 100 can be disposed in the through hole K of the display panel 10.

[0105] For example, in a plane (i.e., the XY plane) parallel to the display panel 10, the shape of the through hole K of the display panel 10 can be a regular or irregular shape such as a square, rectangle, polygon, circle, ellipse or semicircle.

[0106] For example, referring to Figure 2, the through hole K of the display panel 10 can be circular in shape.

[0107] It should be noted that the aforementioned shapes such as "squares, rectangles, polygons, circles, ovals, or semicircles" are not necessarily squares, rectangles, polygons, circles, ovals, or semicircles in the strict sense. They can be shapes that are approximately squares, rectangles, polygons, circles, ovals, or semicircles. For example, the aforementioned shapes may have minor deformations due to tolerances, and may also have chamfers or curved edges.

[0108] The following describes some embodiments of the present disclosure by taking the shape of the through hole K of the display panel 10 as a circle in the plane (i.e., the XY plane) parallel to the display panel 10 as an example. However, the embodiments of the present disclosure include, but are not limited to, this. The shape of the through hole K of the display panel 10 in the plane (i.e., the XY plane) parallel to the display panel 10 can also be any other shape.

[0109] For example, the through hole K of the display panel 10 is opened in the display area AA of the display panel 10, and can be opened at any position in the display area AA of the display panel 10.

[0110] For example, the through hole K of the display panel 10 can be opened in the middle of the display area AA of the display panel 10.

[0111] For example, please refer to Figure 2. The through hole K of the display panel 10 can be opened at the edge of the display area AA of the display panel 10.

[0112] The following describes some embodiments of the present disclosure by taking the example that the through hole K of the display panel 10 is opened at the edge of the display area AA of the display panel 10. However, the embodiments of the present disclosure include, but are not limited to, this, and the through hole K of the display panel 10 can also be opened at other positions of the display panel 10.

[0113] In some embodiments, referring to FIG2, the display panel 10 further includes a transition region BB, which is adjacent to the display area AA of the display panel 10. The display area AA of the display panel 10 surrounds the transition region BB of the display panel 10, and the transition region BB of the display panel 10 surrounds the through hole K of the display panel 10.

[0114] For example, the transition area BB of the display panel 10 may surround at least one side of the through hole K of the display panel 10.

[0115] For example, the transition area BB of the display panel 10 may surround one, two, or three sides of the through hole K of the display panel 10.

[0116] For example, referring to Figure 2, the transition area BB of the display panel 10 can be arranged in a closed ring around the through hole K of the display panel 10.

[0117] The following describes some embodiments of the present disclosure by taking the example of the transition area BB of the display panel 10 surrounding the through hole K of the display panel 10 in a closed ring shape. However, the implementation of the present disclosure includes but is not limited to this, and the present disclosure does not make any specific limitation.

[0118] The aforementioned display panel 10 can be formed from a display motherboard 10m, which will be described in detail below.

[0119] In some embodiments, as shown in Figures 3A and 3B, Figure 3A is a structural diagram of a display motherboard 10m according to some embodiments, and Figure 3B is an enlarged view of the EE region of the display motherboard 10m in Figure 3A. The display motherboard 10m includes a display area AA, a peripheral area AN, a transition area BB, and a pre-drilled area K1. The display area AA, the transition area BB, and the pre-drilled area K1 are sequentially adjacent, with the display area AA surrounding the transition area BB, and the transition area BB surrounding the pre-drilled area K1. The transition area BB and the pre-drilled area K1 of the display motherboard 10m can be separated by a trim line TL.

[0120] It should be noted that the display area AA, peripheral area AN, and transition area BB in the display motherboard 10m are set in the same way as the display area AA, peripheral area AN, and transition area BB in the display panel 10, and will not be described again here.

[0121] Referring to Figures 2 and 3B, it can be understood that the difference between the display panel 10 and the display motherboard 10m is that the display motherboard 10m includes a pre-drilled area K1, while the display panel 10 does not include the pre-drilled area K1, and a through hole K is provided in the area corresponding to the pre-drilled area K1.

[0122] The shape of the pre-drilled area K1 of the display motherboard 10m in the plane parallel to the display motherboard 10m (i.e., the XY plane) is the same as the shape of the through hole K of the display panel 10 in the plane parallel to the display panel 10 (i.e., the XY plane). In other words, the pre-drilled area K1 of the display motherboard 10m and the through hole K of the display panel 10 are conformal. The relative position of the pre-drilled area K1 of the display motherboard 10m and the display area AA is consistent with the relative position of the through hole K of the display panel 10 and the display area AA. Therefore, the shape of the pre-drilled area K1 of the display motherboard 10m in the plane parallel to the display motherboard 10m (i.e., the XY plane), and the relative position of the pre-drilled area K1 of the display motherboard 10m and the display area AA will not be described again here.

[0123] In some embodiments, as shown in FIG4, FIG4 is a cross-sectional view of a partial region of a display motherboard 10m according to some embodiments. The display motherboard 10m includes a rigid substrate 1.

[0124] For example, the material of the rigid substrate 1 may include inorganic materials, such as soda-lime glass, quartz glass, sapphire glass, and other glass materials.

[0125] In some embodiments, referring to FIG4, the display motherboard 10m further includes a pixel driving layer 2. The pixel driving layer 2 is located on one side of the rigid substrate 1. The pixel driving layer 2 can be used to configure the pixel driving circuit 9a within the display motherboard 10m.

[0126] For example, please continue to refer to FIG4. The pixel driving layer 2 may include a first gate insulating layer 21, a first active film layer 22, a second gate insulating layer 23, a first gate film layer 24, a third gate insulating layer 25, a second gate film layer 26, an interlayer dielectric layer 27, a first source / drain metal layer 28, a first planarization layer 29, a second source / drain metal layer 210, and a second planarization layer 211, which are sequentially stacked along the direction away from the rigid substrate 1.

[0127] The first active film layer 22 can be made of any one of low-temperature polycrystalline silicon, indium gallium zinc oxide, and low-temperature polycrystalline oxide. The first active film layer 22 can be obtained using excimer laser annealing or physical vapor deposition (PVD) processes. The active layer pattern of the transistor T in the pixel driving circuit can be set on the first active film layer 22.

[0128] The first gate film layer 24 and the second gate film layer 26 can be obtained by depositing metal materials such as MO / Ti / Al / Cu (molybdenum / titanium / aluminum / copper) using a physical vapor deposition (PVD) process. The gate pattern of the transistor T in the pixel driving circuit can be set on the first gate film layer 24 or the second gate film layer 26.

[0129] The first planarization layer 29 and the second planarization layer 211 are mainly used to block water and oxygen and to block alkaline ions. They can be obtained by spin-coating polyimide (PI) or by depositing silicon nitride, silicon oxide or silicon oxynitride using PECVD.

[0130] The materials of the first gate insulating layer 21, the second gate insulating layer 23, the third gate insulating layer 25 and the interlayer dielectric layer 27 can be inorganic materials (such as silicon nitride, silicon oxide or silicon oxynitride, etc.) and are deposited using PECVD process.

[0131] The pixel driving layer 2 is formed by an insulating film layer (e.g., a first gate insulating layer 21, a second gate insulating layer 23, a third gate insulating layer 25, and an interlayer dielectric layer 27) made of inorganic materials, which together form an inorganic stack 2a.

[0132] In some embodiments, referring to FIG4, the display motherboard 10m further includes a light-emitting device layer 3. The light-emitting device layer 3 is located on the side of the pixel driving layer 2 away from the rigid substrate 1. That is, the pixel driving layer 2 is located between the light-emitting device layer 3 and the rigid substrate 1. The light-emitting device layer 3 can be used to set the sub-pixels 9 within the display motherboard 10m.

[0133] For example, please continue to refer to FIG4, the light-emitting device layer 3 may include a first electrode layer 31, a light-emitting functional layer 33 and a second electrode layer 32 stacked sequentially along the third direction Z (i.e. the thickness direction of the display device 100).

[0134] The first electrode layer 31 and the second electrode layer 32 can provide charge carriers such as electrons and holes to the light-emitting functional layer 33, so that the light-emitting functional layer 33 emits light.

[0135] The first electrode layer 31 is provided with a plurality of first electrodes 311, the second electrode layer 32 is provided with a plurality of second electrodes 321, and the light-emitting functional layer 33 includes a plurality of light-emitting parts 331, each light-emitting part 331 and a first electrode 311 and a second electrode 321 overlapping in the third direction Z (i.e. the thickness direction of the display device 100).

[0136] Each sub-pixel 9 within the light-emitting device layer 3 may include a first electrode 311 and a second electrode 321 stacked together, and a light-emitting portion 331 located between the first electrode 311 and the second electrode 321. In some examples, the second electrodes 321 of multiple sub-pixels 9 may be interconnected to form a complete film structure.

[0137] For example, referring to Figure 4, the first electrode layer 31 may be closer to the pixel driving layer 2 than the second electrode layer 32.

[0138] For example, one of the first electrode 311 in the first electrode layer 31 and the second electrode 321 in the second electrode layer 32 can serve as the anode of the sub-pixel 9, and the other can serve as the cathode of the sub-pixel 9.

[0139] For example, the first electrode 311 in the first electrode layer 31 can serve as the anode of the sub-pixel 9, and the second electrode 321 in the second electrode layer 32 can serve as the cathode of the sub-pixel 9.

[0140] For example, the material used to form the first electrode layer 31 may include metallic materials, such as any one or more of magnesium (Mg), silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo).

[0141] The material used to form the first electrode layer 31 may also include alloys of the aforementioned metallic materials, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb).

[0142] For example, the first electrode layer 31 may be a single-layer structure.

[0143] Alternatively, the first electrode layer 31 can also be a multilayer composite structure. For example, the first electrode layer 31 can be a Ti / Al / Ti structure, etc. Another example is that the first electrode layer 31 can be a stacked structure formed of metallic materials and transparent conductive materials, such as ITO / Ag / ITO, Mo / AlNd / ITO, etc.

[0144] For example, the material used to form the second electrode layer 32 may include any one or more of magnesium (Mg), silver (Ag), aluminum (Al), etc.

[0145] The material used to form the second electrode layer 32 may also include alloys made of any one or more of magnesium (Mg), silver (Ag), aluminum (Al), etc.

[0146] The material used to form the second electrode layer 32 may also include a transparent conductive material, such as indium tin oxide (ITO).

[0147] For example, as shown in FIG5, FIG5 is a film structure diagram of a sub-pixel 9 according to some embodiments. The light-emitting portion 331 in the sub-pixel 9 includes a light-emitting layer 331a.

[0148] For example, the display motherboard 10m can be an OLED display panel. Based on the fact that the display motherboard 10m is an OLED display panel, the light-emitting layer 331a can include an organic light-emitting layer (EML). For example, the organic light-emitting layer EML can include a host material and a guest material, and the guest material can be a fluorescent dopant or a phosphorescent dopant.

[0149] For example, the display motherboard 10m can also be a QLED display panel. Based on the fact that the display motherboard 10m is a QLED display panel, the light-emitting layer 331a can include a quantum dot layer (QDL). For example, the quantum dot layer (QDL) can have quantum dot particles, which can be interconnected through surface-modified groups.

[0150] For example, referring to Figure 5, the light-emitting part 331 may also include one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron block layer (EBL), a hole block layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL).

[0151] In some embodiments, referring to FIG4, the motherboard 10m further includes a pixel definition layer (PDL) 4. The pixel definition layer (PDL) 4 is located on the side of the first electrode layer 31 away from the rigid substrate 1. A plurality of pixel openings are formed in the pixel definition layer (PDL) 4, and the pixel openings are correspondingly disposed with respect to the first electrodes 311 in the first electrode layer 31. Each pixel opening exposes at least a portion of a first electrode 311. The light-emitting portion 331 in the light-emitting functional layer 33 is disposed within the pixel opening and is electrically connected to both the first electrode 311 and the second electrode 321.

[0152] By exposing at least a portion of a first electrode 311 through each pixel opening, the pixel definition layer (PDL) 4 can effectively define the actual effective area of ​​the first electrode 311 (i.e., the area where the first electrode 311 is directly electrically connected to the light-emitting part 331 in the light-emitting functional layer 33), thereby defining the light-emitting area and light-emitting area of ​​the sub-pixel 9.

[0153] For example, the material used to form the pixel definition layer (PDL) 4 may include organic materials such as polyimide, acrylic, or polyethylene terephthalate.

[0154] In some embodiments, please continue referring to Figure 4, which shows that the motherboard 10m also includes an encapsulation structure 5. The encapsulation structure 5 is located on the side of the light-emitting device layer 3 away from the rigid substrate 1. The encapsulation structure 5 is used to encapsulate the light-emitting device layer 3, thereby protecting the light-emitting device layer 3 from corrosion caused by external water and oxygen.

[0155] For example, referring to FIG4, the encapsulation structure 5 includes a first inorganic encapsulation layer 51, an organic encapsulation layer 53, and a second inorganic encapsulation layer 52, which are sequentially stacked along a direction away from the rigid substrate 1. That is, the first inorganic encapsulation layer 51 is closer to the light-emitting device layer 3 than the second inorganic encapsulation layer 52.

[0156] The materials of the first inorganic encapsulation layer 51 and the second inorganic encapsulation layer 52 include inorganic materials that can be used to block water and oxygen. For example, the materials of the first inorganic encapsulation layer 51 and the second inorganic encapsulation layer 52 may include alkali metal compounds (e.g., LiF), alkaline earth metal compounds (e.g., MgF2), SiON, SiNx, or SiOy, etc. The first inorganic encapsulation layer 51 and the second inorganic encapsulation layer 52 can be formed using processes such as plasma enhanced chemical vapor deposition (PECVD), magnetron sputtering (SUPTTER), or atomic layer deposition (ALD).

[0157] The organic encapsulation layer 53 is made of organic materials, which can serve to flatten interfaces, cover defects, and relieve stress. For example, the organic encapsulation layer 53 may include organic inks. The organic encapsulation layer 53 can be formed using processes such as inkjet printing (IJP), plasma-enhanced chemical vapor deposition (PECVD), screen printing, or flash evaporation.

[0158] In some embodiments, as shown in FIG6, FIG6 is a cross-sectional view of the display motherboard 10m in FIG3B along the section line CC. The rigid substrate 1 may be located in the display area AA, the transition area BB and the pre-opening area K1 of the display motherboard 10m.

[0159] Please refer to Figure 6. The pixel driving layer 2 can be located in the display area AA of the display motherboard 10m. The pixel driving layer 2 located in the display area AA of the display motherboard 10m can be used to set up the pixel driving circuit 9a.

[0160] For example, referring to Figure 6, some of the film layers in the pixel driving layer 2 can also be located in the transition area BB of the display motherboard 10m. That is, some of the film layers in the pixel driving layer 2 can be located simultaneously in the display area AA and the transition area BB of the display motherboard 10m.

[0161] For example, the inorganic stack 2a in the pixel driving layer 2 can be located simultaneously in the display area AA and the transition area BB of the display motherboard 10m. The inorganic stack 2a in the pixel driving layer 2 includes a first part 2aa located in the display area AA of the display motherboard 10m and a second part 2ab located in the transition area BB of the display motherboard 10m.

[0162] For example, referring to FIG6, the pixel driving layer 2 may also be located in the pre-aperture area K1 of the display motherboard 10m. The inorganic stack 2a in the pixel driving layer 2 also includes a third portion 2ac located in the pre-aperture area K1 of the display motherboard 10m.

[0163] The pixel driving layer 2 located in the pre-aperture area K1 of the display motherboard 10m can be used to set the virtual pixel circuit 9b. The virtual pixel circuit 9b and the pixel driving circuit 9a can be formed in the same etching process, which is beneficial to improving etching uniformity. The virtual pixel circuit 9b is not connected to other conductive structures (such as sub-pixels 9), and therefore does not have the function of driving the sub-pixels 9 to emit light.

[0164] Multiple virtual pixel circuits 9b can be provided in the pixel driving layer 2 located in the pre-aperture area K1 of the display motherboard 10m. Since the pixel driving layer 2 is located between the light-emitting device layer 3 and the rigid substrate 1, the multiple virtual pixel circuits 9b in the pixel driving layer 2 located in the pre-aperture area K1 of the display motherboard 10m are also located between the light-emitting device layer 3 and the rigid substrate 1.

[0165] The pixel driving layer 2 located in the pre-aperture area K1 of the display motherboard 10m can also be used to set the alignment mark 71. The alignment mark 71 can be located in the third part 2ac of the inorganic stack 2a in the pixel driving layer 2, and located in the central region Q of the pre-aperture area K1 of the display motherboard 10m. When multiple virtual pixel circuits 9b are provided in the pixel driving layer 2 located in the pre-aperture area K1 of the display motherboard 10m, the multiple virtual pixel circuits 9b are closer to the display area AA of the display motherboard 10m than the alignment mark 71.

[0166] It should be noted that the "central region Q of the pre-drilled area K1" mentioned above refers to the region where the centroid of the pre-drilled area K1 is located. For example, when the shape of the pre-drilled area K1 of the display motherboard 10m is circular in a plane (i.e., the XY plane) parallel to the display motherboard 10m, the centroid of the pre-drilled area K1 in the plane (i.e., the XY plane) parallel to the display motherboard 10m is the center of the circle, and the central region Q of the pre-drilled area K1 refers to the region where the center of the pre-drilled area K1 is located.

[0167] For example, when the pre-drilled area K1 of the display motherboard 10m is rectangular in shape in a plane (i.e., the XY plane) parallel to the display motherboard 10m, the centroid of the pre-drilled area K1 in the plane (i.e., the XY plane) parallel to the display motherboard 10m is the intersection of the diagonals of the rectangle, and the central area Q of the pre-drilled area K1 refers to the area where the intersection of the diagonals is located.

[0168] For example, when the pre-drilled area K1 of the display motherboard 10m is triangular in shape in a plane (i.e., the XY plane) parallel to the display motherboard 10m, the centroid of the pre-drilled area K1 in the plane (i.e., the XY plane) parallel to the display motherboard 10m is the intersection of the midlines of the triangle, and the central area Q of the pre-drilled area K1 refers to the area where the midlines intersect.

[0169] By setting an alignment mark 71 in the center region Q of the pre-aperture area K1 of the display motherboard 10m, when cutting the film layer structure in the pre-aperture area K1 of the display motherboard 10m to form a display panel 10 with through holes K, it is convenient to cut and align, and misalignment is avoided when cutting the film layer structure in the pre-aperture area K1 of the display motherboard 10m. This allows the through holes K of the display panel 10 formed using the display motherboard 10m to be located in a pre-set position, which is beneficial to improving the yield of the display panel 10.

[0170] The aforementioned alignment mark 71 can be located in the conductive film layer between two adjacent inorganic material film layers in the inorganic stack 2a within the pixel driving layer 2.

[0171] It should be noted that Figure 6 only illustrates the setting position of the alignment mark 71 by taking the example of the alignment mark 71 being located in the first gate film layer 24 in the pixel driving layer 2. The setting position of the alignment mark 71 is not limited to this. For example, the alignment mark 71 can also be located in the first active film layer 22, the second gate film layer 26, the first source / drain metal layer 28, or the second source / drain metal layer 210, etc., conductive film layers in the pixel driving layer 2.

[0172] Please refer to Figure 6. The light-emitting device layer 3 can be located in the display area AA of the display motherboard 10m. The light-emitting device layer 3 located in the display area AA of the display motherboard 10m can be used to set the sub-pixels 9 in the display area AA of the display motherboard 10m.

[0173] Please continue to refer to Figure 6, and in conjunction with Figure 2, the inner film layer of the light-emitting device layer 3 (e.g., the light-emitting functional layer 33) includes organic materials. Organic materials are prone to react with external moisture and oxygen. After the film structure in the pre-opened area K1 of the display motherboard 10m is removed to form the display panel 10 with through holes K, external moisture and oxygen can easily enter the display area AA of the display panel 10 through the through holes K, thereby affecting the display effect of the display area AA.

[0174] Based on this, please continue to refer to Figure 6. The portion of the light-emitting device layer 3 located in the display area AA of the display motherboard 10m and close to the transition area BB of the display motherboard 10m can be isolated by the isolation structure 72. That is, the isolation structure 72 blocks the transmission path of external water vapor and oxygen through the through hole K of the display panel 10 into the display area AA of the display panel 10, thus ensuring the normal display of the display panel 10.

[0175] For example, referring to Figure 6, the light-emitting device layer 3 may also be located in the transition region BB of the display motherboard 10m. After removing the film structure in the pre-aperture region K1 of the display motherboard 10m to form a display panel 10 with through holes K, extending the light-emitting device layer 3 to the transition region BB of the display motherboard 10m helps to improve the edge reliability of the light-emitting device layer 3, thereby improving the performance of the display panel 10.

[0176] For example, please continue to refer to Figure 6, the light-emitting device layer 3 can also be located in the pre-opened area K1 of the display motherboard 10m.

[0177] Please refer to Figure 6. The Pixel Definition Layer (PDL) 4 can be located within the display area AA of the display motherboard 10m.

[0178] For example, please continue to refer to Figure 6, the pixel definition layer (PDL) 4 can also be located within the pre-aperture area K1 of the display motherboard 10m.

[0179] Please refer to Figure 6. The encapsulation structure 5 can be located in the display area AA, transition area BB and pre-opening area K1 of the display motherboard 10m.

[0180] For example, please continue to refer to Figure 6 and in conjunction with Figure 4. When forming the organic encapsulation layer 53 in the encapsulation structure 5, the barrier dam 73 located in the display area AA of the display motherboard 10m and / or the barrier dam 73 located in the pre-aperture area K1 of the display motherboard 10m can prevent the organic material used to form the organic encapsulation layer 53 from overflowing out of the barrier dam 73. The organic material used to form the organic encapsulation layer 53 can be intercepted at the barrier dam 73 located in the display area AA of the display motherboard 10m or the barrier dam 73 located in the pre-aperture area K1 of the display motherboard 10m, avoiding contact between the organic material used to form the organic encapsulation layer 53 and external water and oxygen, thereby preventing the finally formed organic encapsulation layer 53 from contacting external water and oxygen, which is beneficial to improving the encapsulation effect.

[0181] The following provides a detailed description of the method for preparing the display panel 10 using the aforementioned display motherboard 10m.

[0182] In some embodiments, referring to FIG3B, the cutting wheel can be controlled to move along the cutting line TL (Trim Line) between the transition area BB and the pre-aperture area K1 of the display motherboard 10m, separating the film layer (e.g., inorganic stack 2a and light-emitting device layer 3, etc.) in the pre-aperture area K1 of the display motherboard 10m from the film layer (e.g., inorganic stack 2a and light-emitting device layer 3, etc.) in the transition area BB of the display motherboard 10m, that is, removing the film layer in the pre-aperture area K1 of the display motherboard 10m to form a display panel 10 with through holes K as shown in FIG2.

[0183] Please refer to Figure 2. The smoothness of the interface 10a of the transition area BB of the display panel 10 formed by the blade cutting process is poor. Usually, a grinding process is required to grind the interface 10a of the transition area BB of the display panel 10 near the through hole K to ensure that the interface 10a is smooth. Dust is easily generated during the cutting and grinding process, and the blade cutting of the rigid substrate 1 can easily reduce the strength and toughness of the rigid substrate 1.

[0184] Based on this, in some embodiments, as shown in FIG7, FIG7 is a flowchart of a method for manufacturing a display panel 10 according to some embodiments. The method for manufacturing a display panel 10 includes steps S1 to S3.

[0185] S1: As shown in Figure 8, Figure 8 is a structural diagram corresponding to step S1 in the preparation method of the display panel 10 according to the embodiment shown in Figure 7. The portion of the rigid substrate 1 located near the cutting line TL (Trim Line) within the display motherboard 10m is modified to reduce the acid resistance of the portion of the rigid substrate 1 located near the cutting line TL (Trim Line).

[0186] For example, a portion of the rigid substrate 1 located near the trim line TL can be modified by laser (e.g., infrared laser).

[0187] S2: As shown in Figure 9, Figure 9 is a structural diagram corresponding to step S2 in the fabrication method of the display panel 10 according to the embodiment shown in Figure 7. A portion of the rigid substrate 1 located near the trim line TL is etched using an acidic etchant, so that the rigid substrate 1 in the transition area BB of the display motherboard 10m and the rigid substrate 1 in the pre-aperture area K1 of the display motherboard 10m are separated at the trim line TL.

[0188] It should be noted that acidic etchants can corrode metals or silicon-containing materials. Since rigid substrate 1 typically includes glass materials such as soda-lime glass, quartz glass, and sapphire glass, which contain silicon, rigid substrate 1 can be etched by acidic etchants.

[0189] For example, acidic etchants may include hydrofluoric acid (HF), etc.

[0190] S3: As shown in Figure 10, Figure 10 is a structural diagram corresponding to step S3 in the fabrication method of the display panel 10 according to the embodiment shown in Figure 7. The film layers (e.g., inorganic stack 2a and light-emitting device layer 3, etc.) in the transition region BB of the display mother plate 10m and the film layers (e.g., inorganic stack 2a and light-emitting device layer 3, etc.) in the pre-aperture region K1 of the display mother plate 10m are broken at the cutting line TL by laser, and the film layers (e.g., rigid substrate 1, inorganic stack 2a and light-emitting device layer 3, etc.) in the pre-aperture region K1 of the display mother plate 10m are removed to form a display panel 10 with through holes K.

[0191] On the one hand, the above-mentioned method for manufacturing the display panel 10 modifies the portion of the rigid substrate 1 located near the trim line TL of the display motherboard 10m, thereby reducing the acid resistance of the portion of the rigid substrate 1 located near the trim line TL. When etching the rigid substrate 1 with an acidic etchant, the acidic etchant has a faster etching rate on the portion of the rigid substrate 1 located near the trim line TL, which facilitates the breaking of the rigid substrate 1 in the transition region BB of the display motherboard 10m and the rigid substrate 1 in the pre-aperture region K1 of the display motherboard 10m at the trim line TL. Furthermore, other film layers (e.g., inorganic stack 2a, light-emitting device layer 3, and encapsulation structure 5, etc.) in the transition region BB of the display motherboard 10m and other film layers (e.g., inorganic stack 2a, light-emitting device layer 3, and encapsulation structure 5, etc.) in the pre-aperture region K1 of the display motherboard 10m can be etched by laser at the trim line TL. The cut at the line can prevent dust from being generated during the cutting process and also ensure the strength and toughness of the rigid substrate 1.

[0192] On the other hand, please continue to refer to Figure 9. When using an acidic etchant to etch the rigid substrate 1, in addition to etching the part of the rigid substrate 1 located near the trim line TL, the acidic etchant can also etch other areas of the rigid substrate 1 (e.g., the rigid substrate 1 located in the display area AA of the display motherboard 10m). Since the rigid substrate 1 in other areas is not modified, when the acidic etchant etches the rigid substrate 1 in other areas (e.g., the rigid substrate 1 located in the display area AA of the display motherboard 10m), it will not completely remove the rigid substrate 1 in other areas of the display motherboard 10m (e.g., the rigid substrate 1 located in the display area AA of the display motherboard 10m). It only thins the rigid substrate 1 in other areas of the display motherboard 10m (e.g., the rigid substrate 1 located in the display area AA of the display motherboard 10m), that is, reduces the thickness h1 of the rigid substrate 1, which is beneficial to the thinning of the final formed display panel 10.

[0193] It should be noted that the "thickness h1 of the rigid substrate 1" mentioned above refers to the dimension h1 of the rigid substrate 1 along the third direction Z. The following description of the "thickness h1 of the rigid substrate 1" will also follow this explanation and will not be repeated.

[0194] In some embodiments, please continue to refer to FIG9 and in conjunction with FIG7. In step S2 of the method for preparing the display panel 10 shown in FIG7, after the acid etcher completely etches the portion of the rigid substrate 1 located near the dicing line TL (Trim Line) when the acid etcher is used to etch the portion of the rigid substrate 1 located near the dicing line TL (Trim Line), the acid etcher may continue to etch other film layers located on one side of the rigid substrate 1.

[0195] For example, acidic etchants can corrode metals or silicon-containing materials. Since the inorganic stack 2a typically includes inorganic materials such as silicon nitride, silicon oxide, or silicon oxynitride, and the light-emitting device layer 3 typically includes metallic materials, the inorganic stack 2a and the light-emitting device layer 3 can be etched by acidic etchants.

[0196] The other films mentioned above, such as "when using an acidic etchant to etch a portion of the rigid substrate 1 near the truncation line TL (Trim Line), after the acidic etchant completely etches the portion of the rigid substrate 1 near the truncation line TL (Trim Line), the acidic etchant may continue to etch other films on one side of the rigid substrate 1", can be inorganic stacked layers 2a and light-emitting device layers 3, etc.

[0197] For example, acidic etchants may sequentially etch the inorganic stack 2a and the light-emitting device layer 3 located near the trim line TL along the etching path L1, which may easily damage the light-emitting device layer 3 located in the transition area BB of the display motherboard 10m and close to the trim line TL, resulting in reduced edge reliability of the light-emitting device layer 3 of the display panel 10 formed by the fabrication method of the display panel 10 shown in FIG7.

[0198] For example, acidic etchants may sequentially etch the second part 2ab of the inorganic stack 2a in the transition region BB of the display motherboard 10m and the light-emitting device layer 3 in the transition region BB of the display motherboard 10m along the etching path L2, which may easily damage the light-emitting device layer 3 in the transition region BB of the display motherboard 10m, resulting in a decrease in the edge reliability of the light-emitting device layer 3 of the display panel 10 formed by the fabrication method of the display panel 10 shown in FIG7.

[0199] For example, acidic etchants may sequentially etch the third part 2ac of the inorganic stack 2a in the pre-aperture area K1 of the display motherboard 10m and the alignment mark 71 in the central region Q of the pre-aperture area K1 of the display motherboard 10m along the etching path L4. This can easily damage the alignment mark 71 in the central region Q of the pre-aperture area K1 of the display motherboard 10m, causing misalignment when removing the film structure in the pre-aperture area K1 of the display motherboard 10m. This affects the position and shape of the through hole K in the formed display panel 10, reducing the yield of the final formed display panel 10.

[0200] For example, acidic etchants may sequentially etch the second part 2ab of the inorganic stack 2a in the transition area BB of the display motherboard 10m and the first part 2aa of the inorganic stack 2a in the display area AA of the display motherboard 10m along the etching path L5, which may easily damage the pixel driving circuit 9a in the display area AA of the display motherboard 10m, and may cause the display area AA of the display panel 10 formed by the fabrication method of the display panel 10 shown in FIG7 to fail to display normally.

[0201] Based on this, the following is a detailed description of an embodiment that addresses the technical problem of damage to the light-emitting device layer 3 in the transition zone BB located on the display motherboard 10m caused by the sequential etching of the inorganic stack 2a and the light-emitting device layer 3 by the acidic etchant along etching paths L1 and L2.

[0202] In some embodiments, as shown in FIG11A, FIG11A is a cross-sectional view of a partial region of a display motherboard 10m according to some embodiments. The display motherboard 10m also includes a first etch barrier layer 61. The first etch barrier layer 61 is located on one side of the rigid substrate 1, and the light-emitting device layer 3 is located on the side of the first etch barrier layer 61 away from the rigid substrate 1, that is, the first etch barrier layer 61 is located between the light-emitting device layer 3 and the rigid substrate 1.

[0203] The first etching barrier layer 61 is located in the transition area BB and the pre-aperture area K1 of the display motherboard 10m. That is, the first etching barrier layer 61 is provided near the cutting line TL (Trim Line) used to divide the transition area BB and the pre-aperture area K1 of the display motherboard 10m.

[0204] As shown in Figure 11B, which is a plan view of the first etch barrier layer 61 of the display motherboard 10m according to some embodiments, the first etch barrier layer 61 is disposed around the central region Q of the pre-aperture area K1 of the display motherboard 10m.

[0205] By providing a first etching barrier layer 61 between the light-emitting device layer 3 and the rigid substrate 1, when the acid etchant is used to etch a portion of the rigid substrate 1 near the dicing line TL, and after the acid etchant has completely etched the portion of the rigid substrate 1 near the dicing line TL, when the acid etchant continues to etch other film layers of the display motherboard 10m near the dicing line TL, the first etching barrier layer 61 will not be etched by the acid etchant. The etching barrier effect of the first etching barrier layer 61 can stop the etching at the first etching barrier layer 61, which can block the etching paths L1 and L2 of the acid etchant, and prevent the acid etchant from etching the light-emitting device layer 3 located in the transition region BB. This is beneficial to improving the edge reliability of the light-emitting device layer 3 of the display panel 10 formed by the manufacturing method of the display panel 10 shown in FIG. 7, thereby improving the yield of the final formed display panel 10.

[0206] As shown in Figure 12, Figure 12 is a cross-sectional view of a partial area of ​​the display panel 10 formed using the display motherboard 10m shown in Figure 11A. The display motherboard 10 shown in Figure 12 is formed after removing the film layer structure in the pre-aperture area K1 of the display motherboard 10m shown in Figure 11A. The area corresponding to the pre-aperture area K1 of the display motherboard 10m is the through hole K of the display panel 10.

[0207] It is understood that when the display motherboard 10 shown in Figure 11A is formed by removing the film layer structure in the pre-aperture area K1 of the display motherboard 10m, the first etch barrier layer 61 in the pre-aperture area K1 of the display motherboard 10m is removed. That is, in the display panel 10 formed from the display motherboard 10m, the first etch barrier layer 61 is located in the transition area BB of the display panel 10. The first etch barrier layer 61 is disposed around the through hole K of the display panel 10, and the boundary 61a of the first etch barrier layer 61 near the through hole K of the display panel 10 is disposed adjacent to or flush with the boundary 1a of the rigid substrate 1 near the through hole K of the display panel 10 (Figure 12 shows the case where the boundary 61a of the first etch barrier layer 61 near the through hole K of the display panel 10 is flush with the boundary 1a of the rigid substrate 1 near the through hole K of the display panel 10).

[0208] The film layer structure of other areas of the display panel 10 (e.g., the display area AA and the transition area BB of the display panel 10) is the same as that of other areas of the display motherboard 10m (e.g., the display area AA and the transition area BB of the display motherboard 10m), and will not be described again here.

[0209] For example, the first etch barrier layer 61 may include an organic material. For instance, the first etch barrier layer 61 may include polyimide (PI) or the like.

[0210] Since acidic etchants (e.g., hydrofluoric acid (HF) and the like) do not corrode organic materials, the first etch barrier layer 61 will not be etched by the acidic etchant and can play an etch barrier role, so that the etching stops at the first etch barrier layer 61.

[0211] For example, please continue to refer to Figures 11A and 12, the first etch barrier layer 61 can be disposed in the same layer as the first planarization layer 29 in the pixel driving layer 2.

[0212] It is understandable that, since the pixel driving layer 2 is located between the rigid substrate 1 and the light-emitting device layer 3, the first planarization layer 29 in the pixel driving layer 2 is also located between the rigid substrate 1 and the light-emitting device layer 3.

[0213] In some embodiments, as shown in FIG13, FIG13 is a cross-sectional view of a partial area of ​​a display motherboard 10m according to some embodiments. When the display motherboard 10m includes a first etch barrier layer 61, in step S1 of the method for manufacturing the display panel 10 shown in FIG7, when the portion of the rigid substrate 1 located near the trim line TL in the display motherboard 10m is modified to reduce the acid resistance of the portion of the rigid substrate 1 located near the trim line TL, damage may be caused to the portion of the first etch barrier layer 61 located near the trim line TL, resulting in a weakening of the acid resistance of the portion of the first etch barrier layer 61 located near the trim line TL.

[0214] If the portion of the first etch barrier layer 61 near the etch line TL is damaged, resulting in a weakening of the acid resistance of the portion of the first etch barrier layer 61 near the etch line TL, in step S2 of the manufacturing method of the display panel 10 shown in FIG7, an acidic etchant is used to etch the portion of the rigid substrate 1 near the etch line TL. After the acidic etchant completely etches the portion of the rigid substrate 1 near the etch line TL, the acidic etchant may continue to etch other film layers (such as inorganic stack 2a, first etch barrier layer 61, and light-emitting device layer 3, etc.) on one side of the rigid substrate 1 along the etching path L3, which may easily cause damage to the light-emitting device layer 3 in the transition area BB of the display motherboard 10m, resulting in a decrease in the edge reliability of the light-emitting device layer 3 of the formed display panel 10.

[0215] Furthermore, the acidic etchant may continue to etch along the etching path L3 into the display area AA of the display motherboard 10m, which may damage the light-emitting device layer 3 in the display area AA of the display motherboard 10m, easily affecting the normal display of the formed display panel 10 and reducing the yield of the display panel 10 formed using the preparation method of the display panel 10 shown in FIG7.

[0216] Based on this, the following is a detailed description of an embodiment that addresses the technical problem of damage to the light-emitting device layer 3 in the transition area BB and display area AA located on the display motherboard 10m caused by the acidic etchant sequentially etching the inorganic stack 2a, the first etch barrier layer 61, and the light-emitting device layer 3 along the etching path L3.

[0217] In some embodiments, as shown in Figures 14A and 14B, which are cross-sectional views of a partial area of ​​a display motherboard 10m according to some embodiments, the display motherboard 10m further includes a second etch barrier layer 62. The second etch barrier layer 62 is located between the first etch barrier layer 61 and the light-emitting device layer 3, and is located between the transition region BB and the pre-aperture region K1 of the display panel 10m. That is, the second etch barrier layer 62 is disposed near the trim line TL used to divide the transition region BB and the pre-aperture region K1 of the display motherboard 10m.

[0218] As shown in Figure 14C, which is a plan view of the second etch barrier layer 62 of the display motherboard 10m according to some embodiments, the second etch barrier layer 62 is disposed around the central region Q of the pre-drilled area K1 of the display motherboard 10m.

[0219] By providing a second etch barrier layer 62 between the first etch barrier layer 61 and the light-emitting device layer 3, and the second etch barrier layer 62 being located in the transition area BB and pre-aperture area K1 of the display motherboard 10m, in the case where the portion of the first etch barrier layer 61 near the trim line TL is damaged, resulting in a weakening of the acid resistance of the portion of the first etch barrier layer 61 near the trim line TL, in step S2 of the manufacturing method of the display panel 10 shown in FIG7, an acidic etchant is used to etch the portion of the rigid substrate 1 near the trim line TL. After the rigid substrate 1 near Line is completely etched, when the acid etchant continues to etch other film layers located on one side of the rigid substrate 1 along the etching path L3, since the second etch barrier layer 62 is located between the first etch barrier layer 61 and the light-emitting device layer 3, that is, the second etch barrier layer 62 is closer to the first etch barrier layer 61 than the light-emitting device layer 3, and the second etch barrier layer 62 will not be etched by the acid etchant, after the acid etchant etches the first etch barrier layer 61 along the etching path L3, the acid etchant utilizes... The etching barrier effect of the second etching barrier layer 62 can stop the etching at the second etching barrier layer 62, which can block the etching path L3 of the acid etchant and prevent the acid etchant from etching the light-emitting device layer 3 located in the display area AA and transition area BB of the display motherboard 10m along the etching path L3. This is beneficial to improving the edge reliability of the light-emitting device layer 3 of the display panel 10 formed by the manufacturing method of the display panel 10 shown in FIG7, and ensuring the normal display of the display panel 10, thereby improving the yield of the display panel 10.

[0220] As shown in Figures 15A and 15B, Figure 15A is a cross-sectional view of a partial area of ​​the display panel 10 formed using the display motherboard 10m shown in Figure 14A, and Figure 15B is a cross-sectional view of a partial area of ​​the display panel 10 formed using the display motherboard 10m shown in Figure 14B. The display panel 10 shown in Figure 15A is formed by removing the film layer structure within the pre-aperture area K1 of the display motherboard 10m shown in Figure 14A. The display panel 10 shown in Figure 15B is formed by removing the film layer structure within the pre-aperture area K1 of the display motherboard 10m shown in Figure 14B. The area corresponding to the pre-aperture area K1 of the display motherboard 10m is the through-hole K of the display panel 10.

[0221] It is understandable that when the display motherboard 10m shown in Figure 14A or Figure 14B is formed by removing the film layer structure in the pre-aperture area K1 of the display motherboard 10m, the second etch barrier layer 62 in the pre-aperture area K1 of the display motherboard 10m is removed. That is, in the display panel 10 shown in Figure 15A or Figure 15B formed from the display motherboard 10m shown in Figure 14A or Figure 14B, the second etch barrier layer 62 is located in the transition area BB of the display panel 10. The second etch barrier layer 62 is disposed around the through hole K of the display panel 10, and the boundary 62a of the second etch barrier layer 62 near the through hole K of the display panel 10 is disposed adjacent to or flush with the boundary 1a of the rigid substrate 1 near the through hole K of the display panel 10 (Figures 15A and 15B show the case where the boundary 62a of the second etch barrier layer 62 near the through hole K of the display panel 10 is flush with the boundary 1a of the rigid substrate 1 near the through hole K of the display panel 10).

[0222] The film layer structure of other areas of the display panel 10 shown in Figure 15A or Figure 15B (e.g., the display area AA and the transition area BB of the display panel 10) is the same as the film layer structure of other areas of the display motherboard 10m shown in Figure 14A or Figure 14B (e.g., the display area AA and the transition area BB of the display motherboard 10m), and will not be described again here.

[0223] For example, the boundary 62a of the second etch barrier layer 62 near the via K of the display panel 10 and the boundary 61a of the first etch barrier layer 61 near the via K of the display panel 10 can also be arranged adjacent to each other or flush with each other (Figures 15A and 15B show the case where the boundary 62a of the second etch barrier layer 62 near the via K of the display panel 10 and the boundary 61a of the first etch barrier layer 61 near the via K of the display panel 10 are flush with each other). That is, the boundary 1a of the rigid substrate 1 near the via K of the display panel 10, the boundary 61a of the first etch barrier layer 61 near the via K of the display panel 10, and the boundary 62a of the second etch barrier layer 62 near the via K of the display panel 10 can be arranged adjacent to each other or flush with each other.

[0224] For example, the second etch barrier layer 62 comprises an organic material. Since acidic etchants (e.g., hydrofluoric acid (HF) etc.) do not corrode organic materials, the second etch barrier layer 62 will not be etched by the acidic etchant. In the event that the portion of the first etch barrier layer 61 near the trim line TL is damaged, resulting in a weakening of the acid resistance of the portion of the first etch barrier layer 61 near the trim line TL, the second etch barrier layer 62 can act as an etch barrier. After the acidic etchant etches the first etch barrier layer 61 along the etch path L3, the etch barrier effect of the second etch barrier layer 62 can stop the etching at the second etch barrier layer 62, thus blocking the etch path L3 of the acidic etchant.

[0225] In some embodiments, referring to Figures 14A and 15A, the second etch barrier layer 62 may be disposed on the same layer as one of the second planarization layer 211 and the pixel definition layer (PDL) 4.

[0226] For example, the second etch barrier layer 62 can be set on the same layer as the pixel definition layer (PDL) 4.

[0227] Alternatively, please refer to Figures 14A and 15A. The second etch barrier layer 62 can be disposed in the same layer as the second planarization layer 211.

[0228] In some other embodiments, please continue to refer to FIG14B and FIG15B, the second etch barrier layer 62 includes a first sublayer 621 and a second sublayer 622 sequentially stacked in a direction away from the rigid substrate 1, that is, the first sublayer 621 is closer to the rigid substrate 1 than the second sublayer 622.

[0229] The first sub-layer 621 within the second etch barrier layer 62 can be disposed on the same layer as the second planarization layer 211, and the second sub-layer 622 within the second etch barrier layer 62 can be disposed on the same layer as the pixel definition layer (PDL) 4.

[0230] It is understandable that, since both the first planarization layer 29 and the second planarization layer 211 are located within the pixel driving layer 2, and the pixel definition layer (PDL) 4 is located on the side of the pixel driving layer 2 away from the rigid substrate 1, the first planarization layer 29, the second planarization layer 211, and the pixel definition layer (PDL) 4 are sequentially stacked along the direction away from the rigid substrate 1. That is, the first planarization layer 29 is closer to the rigid substrate 1 than the pixel definition layer (PDL) 4.

[0231] The following describes some embodiments of the present disclosure using the example of the second etch barrier layer 62 comprising a first sublayer 621 and a second sublayer 622 sequentially stacked in a direction away from the rigid substrate 1.

[0232] In some embodiments, as shown in FIG16A, FIG16A is a cross-sectional view of a partial area of ​​a display motherboard 10m according to some embodiments. The display motherboard 10m also includes at least one first blocking portion 81. The first blocking portion 81 is located between the first etch blocking layer 61 and the light-emitting device layer 3, and is located between the transition region BB and the pre-aperture region K1 of the display motherboard 10m. That is, the first blocking portion 81 is provided near the cutting line TL (Trim Line) used to divide the transition region BB and the pre-aperture region K1 of the display motherboard 10m.

[0233] As shown in Figure 16B, which is a plan view of the first blocking portion 81 of the display motherboard 10m according to some embodiments, the first blocking portion 81 is disposed around the central region Q of the pre-drilled area K1.

[0234] By providing a first blocking portion 81 between the first etch barrier layer 61 and the light-emitting device layer 3, and the first blocking portion 81 being located in the transition area BB and pre-aperture area K1 of the display motherboard 10m, in the case where the portion of the first etch barrier layer 61 near the etch line TL is damaged, resulting in a weakening of the acid resistance of the portion of the first etch barrier layer 61 near the etch line TL, in step S2 of the method for manufacturing the display panel 10 shown in FIG7, an acidic etchant is used to etch the portion of the rigid substrate 1 near the etch line TL. After the rigid substrate 1 near the Line is completely etched, when the acid etchant continues to etch other film layers located on one side of the rigid substrate 1 along the etching path L3, on the one hand, since the first barrier 81 is located between the first etch barrier layer 61 and the light-emitting device layer 3, that is, the first barrier 81 is closer to the first etch barrier layer 61 than the light-emitting device layer 3, after the acid etchant etches the first etch barrier layer 61 along the etching path L3, the acid etchant will continue to etch the first barrier 81, which can protect the light-emitting device layer 3 located on the side of the first barrier 81 away from the first etch barrier layer 61, weaken or avoid the acid etchant etching the light-emitting device layer 3 in the transition area BB of the display motherboard 10m, which is beneficial to improving the edge reliability of the light-emitting device layer 3 of the display panel 10 formed by the manufacturing method of the display panel 10 shown in FIG7.

[0235] On the other hand, when the acidic etchant continues to etch the display area AA of the display motherboard 10m along the etching path L3, the acidic etchant will first etch the first blocking part 81, which can protect the light-emitting device layer 3 located in the display area AA of the display motherboard 10m, reduce or avoid the acidic etchant etching the light-emitting device layer 3 in the display area AA of the display motherboard 10m, which is beneficial to ensure the normal display of the display panel 10 formed by the manufacturing method of the display panel 10 shown in FIG7, and improve the yield of the display panel 10.

[0236] For example, the display motherboard 10m may include a first blocking portion 81.

[0237] Alternatively, please refer to Figures 16A and 16B, which show that the motherboard 10m may also include multiple first blocking parts 81.

[0238] For example, the display motherboard 10m may include three first blocking parts 81.

[0239] For example, the display motherboard 10m may include six first blocking parts 81.

[0240] For example, the display motherboard 10m may include eight first blocking parts 81.

[0241] It should be noted that the number of the first blocking parts 81 within 10m of the display motherboard in Figures 16A and 16B is only schematic. The number of the first blocking parts 81 within 10m of the display motherboard can be set according to actual needs. The embodiments of this disclosure do not impose any specific limitations on this.

[0242] For example, referring to Figures 16A and 16B, when the display motherboard 10m includes a plurality of first blocking portions 81, the plurality of first blocking portions 81 can be arranged sequentially at intervals along the direction away from the center region Q of the pre-opening area K1 of the display motherboard 10m. That is, a gap is provided between two adjacent first blocking portions 81.

[0243] For example, the material of the first barrier portion 81 may include metal. Since acidic etchants (e.g., hydrofluoric acid (HF) and the like) corrode metal, by making the material of the first barrier portion 81 include metal, in the event that the portion of the first etch barrier layer 61 near the trim line TL is damaged, resulting in a weakening of the acid resistance of the portion of the first etch barrier layer 61 near the trim line TL, after the acidic etchant etches the first etch barrier layer 61 along the etching path L3, the acidic etchant will continue to etch the first barrier portion 81, so that the first barrier portion 81 can protect the light-emitting device layer 3 located on the side of the first barrier portion 81 away from the first etch barrier layer 61, and minimize the etching of the light-emitting device layer 3 in the display area AA and transition area BB of the display motherboard 10m by the acidic etchant.

[0244] For example, the second source / drain metal layer 210 within the pixel driving layer 2 may be located between the first etch barrier layer 61 and the light-emitting device layer 3. The first blocking portion 81 may be located within the second source / drain metal layer 210 within the pixel driving layer 2.

[0245] As shown in Figure 17, Figure 17 is a cross-sectional view of a partial area of ​​the display panel 10 formed using the display motherboard 10m shown in Figure 16A. The display motherboard 10 shown in Figure 17 is formed after removing the film layer structure in the pre-aperture area K1 of the display motherboard 10m shown in Figure 16A. The area corresponding to the pre-aperture area K1 of the display motherboard 10m is the through hole K of the display panel 10.

[0246] It is understandable that when the display motherboard 10m shown in Figure 16A is formed by removing the film layer structure in the pre-aperture area K1 of the display motherboard 10m, the first blocking portion 81 in the pre-aperture area K1 of the display motherboard 10m is removed. That is, in the display panel 10 formed from the display motherboard 10m, the first blocking portion 81 is located in the transition area BB of the display panel 10. The first blocking portion 81 is provided around the through hole K of the display panel 10.

[0247] When the display panel 10 includes a plurality of first blocking portions 81, the plurality of first blocking portions 81 may be arranged sequentially at intervals along a direction away from the through hole K of the display panel 10.

[0248] The material and film layer of the first blocking portion 81 of the display panel 10 shown in Figure 17 are the same as those of the first blocking portion 81 of the display motherboard 10m shown in Figure 16A. The film layer structure of other areas of the display panel 10 shown in Figure 17 (e.g., the display area AA and the transition area BB of the display panel 10) are also the same as those of other areas of the display motherboard 10m shown in Figure 16A (e.g., the display area AA and the transition area BB of the display motherboard 10m), and will not be described again here.

[0249] In some embodiments, please continue to refer to FIG16A, showing that the motherboard 10m may simultaneously include a first blocking portion 81 and a second etch barrier layer 62. When the motherboard 10m simultaneously includes a first blocking portion 81 and a second etch barrier layer 62, the first blocking portion 81 may be located between the first etch barrier layer 61 and the second etch barrier layer 62.

[0250] By including both a first blocking portion 81 and a second etching blocking layer 62 in the display motherboard 10m, and damaging the portion of the first etching blocking layer 61 near the trim line TL, thus weakening its acid resistance, in step S2 of the method for manufacturing the display panel 10 shown in FIG7, an acidic etchant is used to etch the portion of the rigid substrate 1 near the trim line TL. After the rigid substrate 1 near the line is completely etched, when the acid etchant continues to etch other film layers located on one side of the rigid substrate 1 along the etching path L3, since the first blocking portion 81 is located between the first etch barrier layer 61 and the second etch barrier layer 62 (that is, the first blocking portion 81 is closer to the first etch barrier layer 61 than the second barrier layer 62), after the acid etchant etches the first etch barrier layer 61 along the etching path L3, the acid etchant will continue to etch the first blocking portion 81, and after etching the first blocking portion 81, it can also... By utilizing the etching blocking effect of the second etching barrier layer 62, the etching stops at the second etching barrier layer 62, which can further block the etching path L3 of the acid etchant. This further prevents the acid etchant from etching the light-emitting device layer 3 located in the display area AA and transition area BB of the display motherboard 10m along the etching path L3. This is beneficial to further improve the edge reliability of the light-emitting device layer 3 of the display panel 10 formed by the manufacturing method of the display panel 10 shown in Figure 7, and ensure the normal display of the display panel 10, thereby further improving the yield of the display panel 10.

[0251] Referring to Figures 16A and 17, it can be understood that when the display motherboard 10m includes both the first blocking portion 81 and the second etch stop layer 62, after removing the film structure within the pre-aperture area K1 of the display motherboard 10m shown in Figure 16A to form the display panel 10 shown in Figure 17, both the first blocking portion 81 and the second etch stop layer 62 within the pre-aperture area K1 of the display motherboard 10m are removed. That is, in the display panel 10 shown in Figure 17 formed from the display motherboard 10m shown in Figure 16A, the first blocking portion 81 and the second etch stop layer 62 are located in the transition area BB of the display panel 10. Both the first blocking portion 81 and the second etch stop layer 62 are disposed around the through-hole K of the display panel 10. Furthermore, the first blocking portion 81 is located between the first etch stop layer 61 and the second etch stop layer 62.

[0252] The following describes in detail the embodiments that address the technical problems of acidic etchant sequentially etching the second part 2ab of the inorganic stack 2a located in the transition area BB of the display motherboard 10m and the first part 2aa of the inorganic stack 2a located in the display area AA of the display motherboard 10m along the etching path L5, causing damage to the first part 2aa of the inorganic stack 2a located in the display area AA of the display motherboard 10m, and acidic etchant sequentially etching the third part 2ac of the inorganic stack 2a located in the pre-aperture area K1 of the display motherboard 10m and the alignment mark 71 of the central region Q of the pre-aperture area K1 of the display motherboard 10m along the etching path L4, causing damage to the alignment mark 71 of the central region Q of the pre-aperture area K1 of the display motherboard 10m.

[0253] In some embodiments, as shown in FIG18, FIG18 is a cross-sectional view of a partial region of a display motherboard 10m according to some embodiments. The inorganic stack 2a is located in the second portion 2ab of the transition region BB of the display motherboard 10m, and forms a trench m in the region corresponding to the first etch barrier layer 61 in the third portion 2ac of the pre-aperture region K1 of the display motherboard 10m. The first etch barrier layer 61 is at least partially embedded in the trench m.

[0254] Because the inorganic stack 2a is located in the second part 2ab of the transition region BB of the display motherboard 10m, and the part corresponding to the first etching barrier layer 61 in the third part 2ac of the pre-aperture region K1 of the display motherboard 10m forms a trench m, that is, at least a portion of the film layer (e.g., the first etching barrier layer 61 in the inorganic stack 2a in the second part 2ab of the transition region BB of the display motherboard 10m, and the part corresponding to the first etching barrier layer 61 in the third part 2ac of the pre-aperture region K1 of the display motherboard 10m) is located in the region of the first etching barrier layer 61. One or more of the following layers (such as gate insulating layer 21, second gate insulating layer 23, third gate insulating layer 25, and interlayer dielectric layer 27) are removed. Therefore, the thickness h3 of the second portion 2ab of the inorganic stacked layer 2a in the transition region BB of the display motherboard 10m, and the thickness h4 of the region corresponding to the first etch barrier layer 61 in the third portion 2ac of the pre-aperture region K1 of the display motherboard 10m, are both reduced and are less than the thickness h2 of the first portion 2aa of the inorganic stacked layer 2a in the display region AA of the display motherboard 10m. That is, the thickness h2 of the first portion 2aa of the inorganic stacked layer 2a in the display region AA of the display motherboard 10m is greater than the thickness h3 of the second portion 2ab of the transition region BB of the inorganic stacked layer 2a in the display motherboard 10m, and the thickness h4 of the region corresponding to the first etch barrier layer 61 in the third portion 2ac of the pre-aperture region K1 of the display motherboard 10m.

[0255] It should be noted that the aforementioned "thickness h2 of the first part 2aa of the inorganic stacked layer 2aa in the display area AA of the display motherboard 10m" refers to the dimension h2 of the first part 2aa of the inorganic stacked layer 2aa in the display area AA of the display motherboard 10m along the third direction Z. The aforementioned "thickness h3 of the second part 2ab of the inorganic stacked layer 2aa in the transition area BB of the display motherboard 10m" refers to the dimension h3 of the second part 2ab of the inorganic stacked layer 2aa in the transition area BB of the display motherboard 10m along the third direction Z. The aforementioned "thickness h4 of the region corresponding to the first etch barrier layer 61 in the third part 2ac of the pre-aperture area K1 of the inorganic stacked layer 2aa in the display motherboard 10m" refers to the dimension h4 of the region corresponding to the first etch barrier layer 61 in the third part 2ac of the pre-aperture area K1 of the display motherboard 10m along the third direction Z. The following descriptions regarding "the thickness h2 of the first part 2aa of the inorganic stack 2a located in the display area AA of the display motherboard 10m", "the thickness h3 of the second part 2ab of the inorganic stack 2a located in the transition area BB of the display motherboard 10m", and "the thickness h4 of the region corresponding to the first etching barrier layer 61 in the third part 2ac of the pre-aperture area K1 of the inorganic stack 2a located in the display motherboard 10m" will also follow this explanation and will not be repeated.

[0256] By forming trenches m in the second portion 2ab of the transition region BB of the inorganic stacked layer 2a located in the display motherboard 10m and the third portion 2ac of the pre-aperture region K1 of the display motherboard 10m, corresponding to the first etch barrier layer 61, the thickness h3 of the second portion 2ab of the inorganic stacked layer 2a located in the transition region BB of the display motherboard 10m and the thickness h4 of the third portion 2ac of the inorganic stacked layer 2a located in the pre-aperture region K1 of the display motherboard 10m corresponding to the first etch barrier layer 61 are both reduced, and the first etch barrier layer 61 is at least partially embedded in the trench m. The first etch barrier layer 61 will not be etched by the acid etchant. In step S2 of the method for preparing the display panel 10 shown in FIG7, an acid etchant is used to etch a portion of the rigid substrate 1 located near the cutting line TL (Trim Line). The acid etchant will etch the portion of the rigid substrate 1 located near the cutting line TL (Trim Line). After the rigid substrate 1 near the Line is completely etched, on the one hand, when the acid etchant sequentially etches the second part 2ab of the inorganic stack 2a in the transition area BB of the display motherboard 10m and the first part 2aa of the inorganic stack 2a in the display area AA of the display motherboard 10m along the etching path L5, since the thickness h3 of the second part 2ab of the inorganic stack 2a in the transition area BB of the display motherboard 10m is reduced, the etching rate of the acid etchant etching the second part 2ab of the inorganic stack 2a in the transition area BB of the display motherboard 10m along the etching path L5 can be reduced, so as to avoid the acid etchant continuing to etch the first part 2aa of the inorganic stack 2a in the display area AA of the display motherboard 10m as much as possible, thereby reducing or avoiding the damage caused by the acid etchant to the first part 2aa of the inorganic stack 2a in the display area AA of the display motherboard 10m, ensuring the normal display of the display panel 10, and thus improving the yield of the display panel 10.

[0257] On the other hand, when the acidic etchant sequentially etches the third portion 2ac of the inorganic stack 2a located in the pre-aperture area K1 of the display motherboard 10m and the alignment mark 71 located in the center region Q of the pre-aperture area K1 of the display motherboard 10m along the etching path L4, the thickness h4 of the region corresponding to the first etching barrier layer 61 in the third portion 2ac of the inorganic stack 2a located in the pre-aperture area K1 of the display motherboard 10m is reduced. This reduces the etching effect of the acidic etchant along the etching path L4 on the third portion of the inorganic stack 2a located in the transition region BB of the display motherboard 10m. At an etching rate of 2ac, the acid etchant is used to minimize further etching of the alignment mark 71 in the center region Q of the pre-aperture area K1 of the display motherboard 10m. This reduces or avoids damage to the alignment mark 71 in the center region Q of the pre-aperture area K1 of the display motherboard 10m by the acid etchant, thereby preventing misalignment when removing the film structure in the pre-aperture area K1 of the display motherboard 10m. This reduces the impact on the position and shape of the through holes K in the display panel 10 formed using the display motherboard 10m, and improves the yield of the final display panel 10.

[0258] On the other hand, by embedding the first etch barrier layer 61 at least partially in the trench m, the thickness h5 of the first etch barrier layer 61 can be increased. This is beneficial to improving the etching barrier effect of the first etch barrier layer 61 against acidic etchants. On the other hand, since the thickness h5 of the first etch barrier layer 61 is increased, the strength of the first etch barrier layer 61 is improved. In step S1 of the method for preparing the display panel 10 shown in FIG7, when the part of the rigid substrate 1 located near the cutting line TL (Trim Line) in the display motherboard 10m is modified to reduce the acid resistance of the part of the rigid substrate 1 located near the cutting line TL (Trim Line), the probability of damage to the part of the first etch barrier layer 61 located near the cutting line TL (Trim Line) and the weakening of the acid resistance of the part of the first etch barrier layer 61 located near the cutting line TL (Trim Line) can be reduced.

[0259] It should be noted that the "thickness h5 of the first etch barrier layer 61" mentioned above refers to the dimension h5 of the first etch barrier layer 61 along the third direction Z. The following description of the "thickness h5 of the first etch barrier layer 61" also follows this explanation.

[0260] For example, referring to Figure 18, the thickness h3 of the second portion 2ab of the inorganic stack 2a in the transition region BB, and the thickness h4 of the third portion 2ac of the inorganic stack 2a in the pre-aperture region K1 of the display motherboard 10m, corresponding to the region of the first etching barrier layer 61, are both less than or equal to

[0261] For example, the thickness h3 of the second part 2ab of the inorganic stack 2a located in the transition region BB can be 0, or wait.

[0262] The thickness h4 of the inorganic stack 2a in the third part 2ac of the pre-opened area K1 of the display motherboard 10m, corresponding to the area of ​​the first etching barrier layer 61, can be 0. or wait.

[0263] For example, please continue to refer to FIG18. The thickness h3 of the second part 2ab of the transition area BB of the inorganic stack 2a in the display motherboard 10m can be the same as the thickness h4 of the region corresponding to the first etching barrier layer 61 in the third part 2ac of the pre-aperture area K1 of the inorganic stack 2a in the display motherboard 10m.

[0264] As shown in Figure 19, Figure 19 is a cross-sectional view of a partial area of ​​the display panel 10 formed using the display motherboard 10m shown in Figure 18. The display motherboard 10 shown in Figure 19 is formed by removing the film layer structure in the pre-aperture area K1 of the display motherboard 10m shown in Figure 18. The area corresponding to the pre-aperture area K1 of the display motherboard 10m is the through hole K of the display panel 10.

[0265] It is understandable that when the display motherboard 10m shown in Figure 18 is formed by removing the film layer structure in the pre-aperture area K1 of the display motherboard 10m, the first etch barrier layer 61 and the third portion 2ac of the inorganic stack 2a in the pre-aperture area K1 of the display motherboard 10m are removed. That is, in the display panel 10 formed from the display motherboard 10m, the first etch barrier layer 61 and the second portion 2ab of the inorganic stack 2a located in the transition area BB of the display motherboard 10m are both arranged around the through hole K of the display panel 10. The trench m is formed at the second portion 2ab of the inorganic stack 2a located in the transition area BB of the display motherboard 10m, and the first etch barrier layer 61 is at least partially embedded in the trench m.

[0266] The thickness h2 of the first portion 2aa of the inorganic laminate 2a in the display area AA of the display motherboard 10m is the same as the thickness h2 of the first portion 2aa of the inorganic laminate 2a in the display area AA of the display panel 10. Similarly, the thickness h3 of the second portion 2ab of the inorganic laminate 2a in the transition area BB of the display motherboard 10m is the same as the thickness h3 of the second portion 2ab of the inorganic laminate 2a in the transition area BB of the display panel 10. Since the thickness h2 of the first portion 2aa of the inorganic laminate 2a in the display area AA of the display motherboard 10m is greater than the thickness h3 of the second portion 2ab of the inorganic laminate 2a in the transition area BB of the display motherboard 10, the thickness h2 of the first portion 2aa of the inorganic laminate 2a in the display area AA of the display panel 10 is also greater than the thickness h3 of the second portion 2ab of the inorganic laminate 2a in the transition area BB of the display panel 10.

[0267] In some embodiments, as shown in FIG20 and in conjunction with FIG18, FIG20 is a cross-sectional view of a partial region of a display motherboard 10m according to some embodiments. When the thickness h3 of the inorganic stack 2a in the second portion 2ab of the transition region BB and the thickness h4 of the inorganic stack 2a in the third portion 2ac of the pre-aperture region K1 of the display motherboard 10m corresponding to the first etch barrier layer 61 are both 0, the surface of the first etch barrier layer 61 can contact the rigid substrate 1. That is, no other film layer (e.g., inorganic stack 2a) is disposed between the first etch barrier layer 61 and the rigid substrate 1.

[0268] By bringing the first etch barrier layer 61 into contact with the rigid substrate 1, and ensuring that the first etch barrier layer 61 is not etched by the acidic etchant, in step S2 of the method for fabricating the display panel 10 shown in FIG7, an acidic etchant is used to etch a portion of the rigid substrate 1 located near the trim line TL. After the rigid substrate 1 near the Line is completely etched, on the one hand, when the acid etchant sequentially etches the second part 2ab of the inorganic stack 2a in the transition area BB of the display motherboard 10m and the first part 2aa of the inorganic stack 2a in the display area AA of the display motherboard 10m along the etching path L5, the etching can be stopped at the first etching barrier layer 61, that is, the etching path L5 of the acid etchant is blocked, and the acid etchant is prevented from etching the first part 2aa of the inorganic stack 2a in the display area AA of the display motherboard 10m. This avoids the acid etchant from damaging the first part 2aa of the inorganic stack 2a in the display area AA of the display motherboard 10m, ensuring the normal display of the display panel 10 and further improving the yield of the display panel 10.

[0269] On the other hand, when the acidic etchant sequentially etches the third part 2ac of the inorganic stack 2a in the pre-aperture area K1 of the display motherboard 10m and the alignment mark 71 in the central region Q of the pre-aperture area K1 of the display motherboard 10m along the etching path L4, the etching can be stopped at the first etching barrier layer 61, that is, the etching path L4 of the acidic etchant is blocked, and the acidic etchant is prevented from etching the alignment mark 71 in the central region Q of the pre-aperture area K1 of the display motherboard 10m. In other words, the acidic etchant is prevented from damaging the alignment mark 71 in the central region Q of the pre-aperture area K1 of the display motherboard 10m, thereby preventing misalignment when removing the film structure in the pre-aperture area K1 of the display motherboard 10m, and further improving the yield of the final formed display panel 10.

[0270] As shown in Figure 21, Figure 21 is a cross-sectional view of a partial area of ​​the display panel 10 formed using the display motherboard 10m shown in Figure 20. The display motherboard 10m shown in Figure 21 is formed by removing the film layer structure in the pre-aperture area K1 of the display motherboard 10m. The area corresponding to the pre-aperture area K1 of the display motherboard 10m is the through hole K of the display panel 10.

[0271] It is understandable that when the display motherboard 10m shown in Figure 20 is formed by removing the film layer structure in the pre-aperture area K1 of the display motherboard 10m, the first etching barrier layer 61 in the pre-aperture area K1 of the display motherboard 10m is removed. That is to say, in the display panel 10 formed by the display motherboard 10m, the first etching barrier layer 61 is located in the transition area BB of the display panel 10 and is disposed around the through hole K of the display panel 10.

[0272] Since the surface of the first etch barrier layer 61 in the display motherboard 10m shown in FIG20 is in contact with the rigid substrate 1, the surface of the first etch barrier layer 61 in the display panel 10 shown in FIG21 is also in contact with the rigid substrate 1.

[0273] The following is a detailed description of an embodiment that addresses the technical problem of damage to the alignment mark 71 in the central region Q of the pre-aperture area K1 in the display motherboard 10m caused by the acidic etchant sequentially etching the third part 2ac of the inorganic stack 2a in the pre-aperture area K1 of the display motherboard 10m along the etching path L4.

[0274] In some embodiments, as shown in FIG22, FIG22 is a cross-sectional view of a partial region of a display motherboard 10m according to some embodiments. The display motherboard 10m also includes at least one second blocking portion 82. The second blocking portion 82 is embedded in the third portion 2ac of the pre-opened area K1 of the inorganic laminate 2a located in the display motherboard 10m.

[0275] As shown in Figure 23, Figure 23 is a plan view of the second blocking portion 82 of the display motherboard 10m according to some embodiments.

[0276] The second blocking part 82 is provided around the alignment mark 71 in the central area Q of the pre-drilled area K1 located on the display motherboard 10m.

[0277] By embedding at least one second blocking portion 82 within the third portion 2ac of the pre-aperture area K1 of the inorganic stack 2a located on the display motherboard 10m, and by providing at least one second blocking portion 82 around the alignment mark 71 located in the central region Q of the pre-aperture area K1 of the display motherboard 10m, and by ensuring that the second blocking portion 82 is not etched by the acid etchant, in step S2 of the method for manufacturing the display panel 10 shown in FIG7, an acid etchant is used to etch a portion of the rigid substrate 1 located near the cutting line TL (Trim Line). After the rigid substrate 1 near the Line is completely etched, when the acidic etchant sequentially etches the third part 2ac of the inorganic stack 2a located in the pre-aperture area K1 of the display motherboard 10m and the alignment mark 71 of the central region Q of the pre-aperture area K1 of the display motherboard 10m along the etching path L4, the acidic etchant needs to pass through the second barrier 82 before etching the alignment mark 71 of the central region Q of the pre-aperture area K1 of the display motherboard 10m. Through the etching blocking effect of the second barrier 82, the acidity can be reduced. The etching rate when the etchant etches the third part 2ac of the inorganic stack 2a in the pre-aperture area K1 of the display motherboard 10m is such that the acid etchant avoids etching the alignment mark 71 of the central region Q of the pre-aperture area K1 of the display motherboard 10m. In other words, the acid etchant is avoided from damaging the alignment mark 71 of the central region Q of the pre-aperture area K1 of the display motherboard 10m. This avoids misalignment when removing the film structure in the pre-aperture area K1 of the display motherboard 10m and improves the yield of the final display panel 10.

[0278] It is understandable that since the second blocking part 82 is embedded in the third part 2ac of the pre-aperture area K1 of the inorganic laminate 2a located in the display motherboard 10m, that is, the second blocking part 82 is disposed in the pre-aperture area K1 of the display motherboard 10m, when the display panel 10 is formed by removing the film layer structure in the pre-aperture area K1 of the display motherboard 10m, the second blocking part 82 located in the pre-aperture area K1 of the display motherboard 10m is also removed. Therefore, the display panel 10 formed after removing the film layer structure in the pre-aperture area K1 of the display motherboard 10m does not include the second blocking part 82.

[0279] For example, the display motherboard 10m may include a second blocking portion 82.

[0280] Alternatively, please refer to Figures 22 and 23, which show that the motherboard 10m may also include multiple second blocking parts 82.

[0281] For example, the display motherboard 10m may include three second blocking parts 82.

[0282] For example, the display motherboard 10m may include six second blocking parts 82.

[0283] For example, the display motherboard 10m may include eight second blocking parts 82.

[0284] It should be noted that the number of the second blocking parts 82 within 10m of the display motherboard in Figures 22 and 23 is only schematic. The number of the second blocking parts 82 within 10m of the display motherboard can be set according to actual needs. The embodiments of this disclosure do not impose any specific limitations on this.

[0285] For example, referring to Figures 22 and 23, when the display motherboard 10m includes a plurality of second blocking portions 82, the plurality of second blocking portions 82 can be sequentially spaced along the direction away from the center region Q of the pre-opening area K1 of the display motherboard 10m. That is, there is a gap between two adjacent second blocking portions 82.

[0286] For example, please continue to refer to FIG22. When the display motherboard 10m includes a plurality of second blocking parts 82, and a plurality of virtual pixel circuits 9b are provided in the pixel driving layer 2 located in the pre-aperture area K1 of the display motherboard 10m, and an alignment mark 71 is provided in the pixel driving layer 2 located in the central region Q of the pre-aperture area K1 of the display motherboard 10m, the second blocking part 82 may be located between two adjacent virtual pixel circuits 9b.

[0287] Alternatively, the second blocking part 82 may be located between the alignment mark 71 and the virtual pixel circuit 9b adjacent to the alignment mark 71.

[0288] For example, the material of the second blocking portion 82 may include an organic material. Since acidic etchants (e.g., hydrofluoric acid (HF)) do not corrode organic materials, the second blocking part 82 will not be etched by the acidic etchant. When the acidic etchant sequentially etches the third part 2ac of the inorganic stack 2a in the pre-aperture area K1 of the display motherboard 10m and the alignment mark 71 in the central region Q of the pre-aperture area K1 of the display motherboard 10m along the etching path L4, the acidic etchant needs to pass through the second blocking part 82 before etching the alignment mark 71 in the central region Q of the pre-aperture area K1 of the display motherboard 10m. Through the etching blocking effect of the second blocking part 82, the etching rate of the acidic etchant when etching the third part 2ac of the inorganic stack 2a in the pre-aperture area K1 of the display motherboard 10m can be reduced, thereby avoiding the acidic etchant from etching the alignment mark 71 in the central region Q of the pre-aperture area K1 of the display motherboard 10m as much as possible.

[0289] In some embodiments, please continue to refer to FIG22, the second blocking portion 82 may be disposed on the same layer as the first planarization layer 29 within the pixel driving layer 2.

[0290] Alternatively, as shown in FIG24, FIG24 is a cross-sectional view of a partial area of ​​a display motherboard 10m according to some embodiments. The second blocking portion 82 penetrates the first planarization layer 29 within the pixel driving layer 2, and the second blocking portion 82 and the second planarization layer 211 within the pixel driving layer 2 are disposed on the same layer.

[0291] It is understandable that, since the first planarization layer 29 and the second planarization layer 211 in the pixel driving layer 2 are located on the side of the inorganic stack 2a in the pixel driving layer 2 away from the rigid substrate 1, the first planarization layer 29 and the second planarization layer 211 in the pixel driving layer 2 are located between the inorganic stack 2a and the light-emitting device layer 3 in the pixel driving layer 2.

[0292] In some embodiments, referring to Figures 22 and 24, the distance d1 between the second blocking portion 82 and the rigid substrate 1 is less than the distance d2 between the alignment mark 71 in the central region Q of the pre-aperture area K1 located on the display motherboard 10m and the rigid substrate 1.

[0293] Since the second blocking part 82 is provided around the alignment mark 71 in the central region Q of the pre-aperture area K1 located in the display motherboard 10m, and the second blocking part 82 is not etched by acidic etchants (e.g., hydrofluoric acid (HF) etc.), when the acidic etchant sequentially etches the third part 2ac of the inorganic stack 2a located in the pre-aperture area K1 of the display motherboard 10m and the alignment mark 71 in the central region Q of the pre-aperture area K1 of the display motherboard 10m along the etching path L4, the acidic etchant needs to pass through the second blocking part 82 before etching the alignment mark 71 in the central region Q of the pre-aperture area K1 of the display motherboard 10m. By making the distance d1 between the second blocking part 82 and the rigid substrate 1 smaller... The distance d2 between the alignment mark 71 in the central region Q of the pre-aperture area K1 of the display motherboard 10m and the rigid substrate 1 can further reduce the etching rate of the third part 2ac of the inorganic stack 2a located between the second blocking part 82 and the rigid substrate 1 when the acid etchant etches it. This avoids the acid etchant etching the alignment mark 71 in the central region Q of the pre-aperture area K1 of the display motherboard 10m, that is, it avoids the damage caused by the acid etchant to the alignment mark 71 in the central region Q of the pre-aperture area K1 of the display motherboard 10m. This further avoids misalignment when removing the film structure in the pre-aperture area K1 of the display motherboard 10m and further improves the yield of the final formed display panel 10.

[0294] Although some embodiments of this application have been described herein in conjunction with Figures 11A to 24, in the embodiments shown in Figures 11A to 12, a first etching barrier layer 61 is provided to solve the technical problem that the light-emitting device layer 3 located in the transition region BB of the display motherboard 10m is damaged when the acidic etchant sequentially etches the inorganic stack 2a and the light-emitting device layer 3 along the etching path L1 and the etching path L2.

[0295] Based on the embodiments shown in Figures 11A and 12, the embodiments shown in Figures 14A and 15B solve the technical problem that the light-emitting device layer 3 in the transition area BB and display area AA of the display motherboard 10m is damaged when the acidic etchant sequentially etches the inorganic stack 2a, the first etch barrier layer 61 and the light-emitting device layer 3 along the etching path L3.

[0296] Based on the embodiments shown in Figures 11A and 12, the embodiments shown in Figures 16A and 17 solve the technical problem that the light-emitting device layer 3 in the transition area BB and display area AA located on the display motherboard 10m is damaged due to the acid etchant sequentially etching the inorganic stack 2a, the first etch barrier layer 61 and the light-emitting device layer 3 along the etching path L3.

[0297] Based on the embodiments shown in Figures 11A and 12, in the embodiments shown in Figures 18 to 21, the thickness h2 of the first portion 2aa of the inorganic stacked layer 2a in the display area AA of the display motherboard 10m is made greater than the thickness h3 of the second portion 2ab of the inorganic stacked layer 2a in the transition area BB of the display motherboard 10m, and the thickness h4 of the region corresponding to the first etching barrier layer 61 in the third portion 2ac of the pre-aperture area K1 of the inorganic stacked layer 2a in the display motherboard 10m, so as to simultaneously solve the problem of acidic etchant sequentially etching the pre-aperture area K1 of the display motherboard 10m along the etching path L4. The technical problem is that the alignment mark 71 of the third part 2ac of the inorganic stack 2a and the center region Q of the pre-aperture area K1 in the display motherboard 10m is damaged, and the second part 2ab of the inorganic stack 2a in the transition area BB of the display motherboard 10m and the first part 2aa of the inorganic stack 2a in the display area AA of the display motherboard 10m are sequentially etched by the acid etchant along the etching path L5, causing damage to the first part 2aa of the inorganic stack 2a in the display area AA of the display motherboard 10m.

[0298] Based on the embodiments shown in Figures 11A to 12, the embodiments shown in Figures 22 to 24 solve the problem that the acidic etchant sequentially etches the third part 2ac of the inorganic stack 2a in the pre-aperture area K1 of the display motherboard 10m and the alignment mark 71 in the central region Q of the pre-aperture area K1 of the display motherboard 10m along the etching path L4, causing damage to the alignment mark 71 in the central region Q of the pre-aperture area K1 of the display motherboard 10m.

[0299] However, the foregoing description of some embodiments of this application in conjunction with Figures 11A to 24 is exemplary and not exhaustive, and therefore not limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the foregoing embodiments.

[0300] Specifically, the arrangement of the second etching barrier layer 62 in the embodiments shown in Figures 14A to 15B, the arrangement of the first barrier portion 81 in the embodiments shown in Figures 16A to 17, the thickness h2 of the first part 2aa of the inorganic stacked layer 2a in the display area AA of the display motherboard 10m and the thickness h3 of the second part 2ab of the inorganic stacked layer 2a in the transition area BB of the display motherboard 10m, and the thickness h4 of the area corresponding to the first etching barrier layer 61 in the third part 2ac of the pre-opening area K1 of the inorganic stacked layer 2a in the display motherboard 10m, and the arrangement of the second barrier portion 82 in the embodiments shown in Figures 22 to 24, etc., can all be arbitrarily combined, and any combination of the above embodiments is within the protection scope of this application.

[0301] For example, as shown in FIG25, FIG25 is a cross-sectional view of a partial area of ​​a display motherboard 10m according to some embodiments. In the embodiment shown in FIG25, the thickness h2 of the first portion 2aa of the inorganic stack 2a in the display area AA of the display motherboard 10m, the thickness h3 of the second portion 2ab of the inorganic stack 2a in the transition area BB of the display motherboard 10m, and the thickness h4 of the region corresponding to the first etching barrier layer 61 in the third portion 2ac of the pre-aperture area K1 of the inorganic stack 2a in the display motherboard 10m are combined with the arrangement of the second barrier portion 82 in the embodiments shown in FIG22 to FIG24.

[0302] Please refer to Figure 25, which shows that the motherboard 10m includes a first etch barrier layer 61 and a second barrier portion 82.

[0303] The thickness h2 of the first part 2aa of the inorganic stacked layer 2a in the display area AA of the display motherboard 10m is greater than the thickness h3 of the second part 2ab of the inorganic stacked layer 2a in the transition area BB of the display motherboard 10m, and the thickness h4 of the region corresponding to the first etching barrier layer 61 in the third part 2ac of the pre-aperture area K1 of the inorganic stacked layer 2a in the display motherboard 10m.

[0304] By setting a first etching barrier layer 61 and a second barrier portion 82 within the display motherboard 10m, and making the thickness h2 of the first portion 2aa of the inorganic stacked layer 2a in the display area AA of the display motherboard 10m greater than the thickness h3 of the second portion 2ab of the inorganic stacked layer 2a in the transition area BB of the display motherboard 10m, and the thickness h4 of the region corresponding to the first etching barrier layer 61 in the third portion 2ac of the pre-aperture area K1 of the display motherboard 10m, that is, the thickness h3 of the second portion 2ab of the inorganic stacked layer 2a in the transition area BB of the display motherboard 10m and the thickness h4 of the region corresponding to the first etching barrier layer 61 in the third portion 2ac of the pre-aperture area K1 of the display motherboard 10m are smaller, on the one hand, the acidic etchant sequentially etches the area located on the display motherboard along the etching path L5. In the case of the second part 2ab of the inorganic stack 2a in the transition zone BB of 10m and the first part 2aa of the inorganic stack 2a in the display area AA of the display motherboard 10m, since the thickness h3 of the second part 2ab of the inorganic stack 2a in the transition zone BB of the display motherboard 10m is small, the etching rate of the acid etchant along the etching path L5 can be reduced when etching the second part 2ab of the inorganic stack 2a in the transition zone BB of the display motherboard 10m. This can minimize the acid etchant from continuing to etch the first part 2aa of the inorganic stack 2a in the display area AA of the display motherboard 10m, reduce or avoid the damage caused by the acid etchant to the first part 2aa of the inorganic stack 2a in the display area AA of the display motherboard 10m, ensure the normal display of the display panel 10, and thus improve the yield of the display panel 10.

[0305] On the other hand, when the acidic etchant sequentially etches the third portion 2ac of the inorganic stack 2a located in the pre-aperture area K1 of the display motherboard 10m and the alignment mark 71 located in the central region Q of the pre-aperture area K1 of the display motherboard 10m along the etching path L4, since the thickness h4 of the region corresponding to the first etching barrier layer 61 in the third portion 2ac of the inorganic stack 2a in the pre-aperture area K1 of the display motherboard 10m is small, the etching rate of the acidic etchant when etching the third portion 2ac of the inorganic stack 2a located in the transition region BB of the display motherboard 10m along the etching path L4 can be reduced. Before the alignment mark 71, it needs to pass through the second blocking part 82. Through the etching blocking effect of the second blocking part 82, the etching rate of the third part 2ac of the inorganic stack 2a located in the pre-aperture area K1 of the display motherboard 10m can be further reduced, avoiding the acid etchant from etching the alignment mark 71 in the central area Q of the pre-aperture area K1 of the display motherboard 10m. That is, avoiding the damage caused by the acid etchant to the alignment mark 71 in the central area Q of the pre-aperture area K1 of the display motherboard 10m, thereby further avoiding misalignment when removing the film structure in the pre-aperture area K1 of the display motherboard 10m, and further improving the yield of the final formed display panel 10.

[0306] As shown in Figure 26, Figure 26 is a cross-sectional view of a partial area of ​​the display panel 10 formed using the display motherboard 10m shown in Figure 25. The display motherboard 10 shown in Figure 26 is formed after removing the film layer structure in the pre-aperture area K1 of the display motherboard 10m shown in Figure 25. The area corresponding to the pre-aperture area K1 of the display motherboard 10m is the through hole K of the display panel 10.

[0307] It is understandable that when the display motherboard 10m shown in Figure 25 is formed by removing the film layer structure in the pre-aperture area K1 of the display motherboard 10m, the first etch barrier layer 61 and the second barrier portion 82 in the pre-aperture area K1 of the display motherboard 10m are removed. That is to say, the second barrier portion 82 is not included in the display panel 10 formed from the display motherboard 10m, and the first etch barrier layer 61 is provided around the through hole K of the display panel 10.

[0308] For example, as shown in Figure 27, which is a cross-sectional view of a partial area of ​​a display motherboard 10m according to some embodiments, the embodiment shown in Figure 27 combines the thickness h2 of the first portion 2aa of the inorganic stacked layer 2a in the display area AA of the display motherboard 10m in the embodiments shown in Figures 18 to 21, the thickness h3 of the second portion 2ab of the inorganic stacked layer 2a in the transition area BB of the display motherboard 10m, and the thickness h4 of the region corresponding to the first etch barrier layer 61 in the third portion 2ac of the pre-aperture area K1 of the inorganic stacked layer 2a in the display motherboard 10m, the arrangement of the second barrier portion 82 in the embodiments shown in Figures 22 to 24, the arrangement of the second etch barrier layer 62 in the embodiments shown in Figures 14A to 15B, and the arrangement of the first barrier portion 81 in the embodiments shown in Figures 16A to 17.

[0309] Please refer to Figure 27, which shows that the motherboard 10m includes a first etch barrier layer 61, a second etch barrier layer 62, a first barrier portion 81, and a second barrier portion 82.

[0310] The thickness h2 of the first part 2aa of the inorganic stacked layer 2a in the display area AA of the display motherboard 10m is greater than the thickness h3 of the second part 2ab of the inorganic stacked layer 2a in the transition area BB of the display motherboard 10m, and the thickness h4 of the region corresponding to the first etching barrier layer 61 in the third part 2ac of the pre-aperture area K1 of the inorganic stacked layer 2a in the display motherboard 10m.

[0311] As shown in Figure 28, Figure 28 is a cross-sectional view of a partial area of ​​the display panel 10 formed using the display motherboard 10m shown in Figure 27. The display panel 10 shown in Figure 28 is formed after removing the film layer structure in the pre-aperture area K1 of the display motherboard 10m shown in Figure 27. The area corresponding to the pre-aperture area K1 of the display motherboard 10m is the through hole K of the display panel 10.

[0312] It is understandable that when the display motherboard 10m shown in Figure 27 is formed by removing the film layer structure in the pre-aperture area K1 of the display motherboard 10m, the first etch barrier layer 61, the second etch barrier layer 62, the first blocking part 81 and the second blocking part 82 in the pre-aperture area K1 of the display motherboard 10m are removed. That is to say, the second blocking part 82 is not included in the display panel 10 formed by the display motherboard 10m. The first etch barrier layer 61, the second etch barrier layer 62 and the first blocking part 81 are arranged around the through hole K of the display panel 10.

[0313] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A display panel provided with a through hole; the display panel comprises a display area and a transition area which are adjacent to each other, the display area surrounds the transition area, and the transition area surrounds the through hole; the display panel further comprises: a rigid substrate; a first etching stop layer located on one side of the rigid substrate and in the transition area; the first etching stop layer is arranged around the through hole, and a boundary of the first etching stop layer close to the through hole is arranged adjacent to or flush with a boundary of the rigid substrate close to the through hole; a light emitting device layer located on a side of the first etching stop layer away from the rigid substrate and in the transition area and the display area.

2. The display panel of claim 1, wherein, The first etching stop layer comprises an organic material.

3. The display panel of claim 2, wherein, The display panel further comprises a first planarization layer between the rigid substrate and the light emitting device layer; the first etching stop layer and the first planarization layer are arranged in the same layer.

4. The display panel of claim 3, wherein, The display panel further comprises at least one first barrier portion between the first etching stop layer and the light emitting device layer and in the transition area; the first barrier portion is arranged around the through hole; In the case where the display panel comprises a plurality of first barrier portions, the plurality of first barrier portions are sequentially and spaced apart in a direction away from the through hole.

5. The display panel of claim 4, wherein, The material of the first barrier portion comprises metal.

6. The display panel of claim 5, wherein, The display panel further comprises a second source-drain metal layer between the first etching stop layer and the light emitting device layer; the first barrier portion is located in the second source-drain metal layer.

7. The display panel of claim 3, wherein, The display panel further comprises a second etching stop layer between the first etching stop layer and the light emitting device layer and in the transition area; the second etching stop layer is arranged around the through hole, and a boundary of the second etching stop layer close to the through hole is arranged adjacent to or flush with a boundary of the rigid substrate close to the through hole.

8. The display panel of claim 7, wherein, The display panel further comprises a second planarization layer and a pixel definition layer, the first planarization layer, the second planarization layer and the pixel definition layer are sequentially and stacked in a direction away from the rigid substrate; the second etching stop layer is arranged in the same layer as one of the second planarization layer and the pixel definition layer; or the second etching stop layer comprises a first sub-layer and a second sub-layer which are sequentially and stacked in a direction away from the rigid substrate, the first sub-layer is arranged in the same layer as the second planarization layer, and the second sub-layer is arranged in the same layer as the pixel definition layer.

9. The display panel of claim 7, wherein, The display panel further comprises a first barrier portion between the first etching stop layer and the second etching stop layer.

10. The display panel according to any one of claims 1 to 9, wherein, The surface of the first etching stop layer is in contact with the rigid substrate.

11. The display panel according to any one of claims 1 to 9, wherein The display panel further comprises an inorganic stack, the inorganic stack comprises a first part located in the display area and a second part located in the transition area, the thickness of the first part is greater than the thickness of the second part, and the second part surrounds the through hole; the inorganic stack forms a groove at the second part, and the first etching stop layer is at least partially embedded in the groove.

12. The display panel of claim 11, wherein, the thickness of the second portion is less than or equal to 13.A display mother substrate, comprising a display area, a transition area and a pre-opening area which are sequentially adjacent, the display area surrounding the transition area, and the transition area surrounding the pre-opening area; the display mother substrate further comprising: a rigid substrate; a first etching stop layer located on a side of the rigid substrate and in the transition area and the pre-opening area; the first etching stop layer being arranged around a central region of the pre-opening area; a light emitting device layer located on a side of the first etching stop layer away from the rigid substrate and in the transition area and the display area.

14. The display motherboard of claim 13, wherein, the display mother substrate further comprising an inorganic stack located on a side of the first etching stop layer close to the rigid substrate; the inorganic stack comprising a first portion in the display area, a second portion in the transition area and a third portion in the pre-opening area; a thickness of a region of the third portion corresponding to the first etching stop layer and a thickness of the second portion are both less than a thickness of the first portion.

15. The display motherboard of claim 14, wherein, the display mother substrate further comprising: an alignment mark located in the third portion and in a central region of the pre-opening area; at least one second barrier embedded in the third portion; the second barrier being arranged around the alignment mark; in a case where the display mother substrate comprises a plurality of the second barriers, the plurality of the second barriers are sequentially and spaced apart in a direction away from the alignment mark.

16. The display motherboard of claim 15, wherein, a distance between the second barrier and the rigid substrate is less than a distance between the alignment mark and the rigid substrate.

17. The display motherboard of claim 15, wherein, a material of the second barrier comprises an organic material.

18. The display motherboard of claim 17, wherein, the display mother substrate further comprising a first planar layer and a second planar layer which are sequentially and laminatedly arranged in a direction away from the rigid substrate, the first planar layer and the second planar layer being located between the inorganic stack and the light emitting device layer and in the display area and the pre-opening area; the first planar layer and the second barrier are arranged in the same layer; or the second barrier penetrates the first planar layer, and the second barrier and the second planar layer are arranged in the same layer.

19. The display motherglass of any one of claims 15-18, wherein, the display mother substrate further comprising a plurality of virtual pixel circuits which are arranged in the pre-opening area and between the light emitting device layer and the rigid substrate; the plurality of virtual pixel circuits are closer to the display area than the alignment mark; the second barrier is located between two adjacent virtual pixel circuits, or the second barrier is located between the alignment mark and a virtual pixel circuit adjacent to the alignment mark. 20.A display device, comprising: the display panel according to any one of claims 1 to 12; a light sensing device arranged in a through hole of the display panel.

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