Gate driver circuit unit, gate driver circuit, display substrate and manufacturing method therefor, and display device

Abstract

Disclosed in the present disclosure are a gate driver circuit unit, a gate driver circuit, a manufacturing method for a display substrate, a display substrate, and a display device. The gate driver circuit unit comprises: a first input sub-circuit (100) configured to control the voltage of a first node (N1) on the basis of a signal of a first input end (101); a second input sub-circuit (400) configured to control the voltage of a second node (N2) on the basis of a signal of a second input end (102); a coupling sub-circuit (200) at least configured to control the voltage of a third node (N3) on the basis of the voltage of the first node (N1); and a first output sub-circuit (300) configured to transmit a signal of a third input end (103) or a signal of a fourth input end (104) to a first output end (OUT1) on the basis of the voltages applied to the second node (N2) and the third node (N3).

Description

Gate driving circuit unit and circuit thereof, display substrate and manufacturing method thereof, display device Cross-references to related applications

[0001] This disclosure claims priority to Chinese patent application No. 2024106924810, filed on May 30, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to the field of display technology, and in particular to a gate driving circuit unit, a gate driving circuit, a method for manufacturing a display substrate, a display substrate, and a display device. Background Technology

[0003] In the existing technology, in order to achieve low cost and narrow bezel, most of them adopt GOA (Gate driver on Array) technology, and the gate driver circuit unit is the GOA unit.

[0004] However, there are some problems with the gate drive circuit unit in the related technology, such as the inability to meet the requirements of structural simplification or stable output of electrical signals that meet display requirements. Summary of the Invention

[0005] This disclosure provides a gate driving circuit unit, a gate driving circuit, a method for manufacturing a display substrate, a display substrate, and a display device, which can improve the problems existing in the gate driving circuit unit in the related art.

[0006] In a first aspect of this disclosure, a gate drive circuit unit is provided, comprising: a first input sub-circuit configured to control a voltage of a first node based on a signal at a first input terminal; a second input sub-circuit configured to control a voltage of a second node based on a signal at a second input terminal; a coupling sub-circuit configured to control a voltage of a third node based on the voltage of the first node; and a first output sub-circuit configured to transmit a signal at a third input terminal or a signal at a fourth input terminal to a first output terminal based on voltages applied to the second node and the third node.

[0007] In some implementations, at least one of the following conditions is met: the first input terminal receives a signal from the first signal line; the second input terminal receives a signal from the first potential signal line; the third input terminal receives a signal from the first clock signal line; and the fourth input terminal receives a signal from the second potential signal line.

[0008] In some embodiments, the gate drive circuit unit further includes a first sustaining sub-circuit and a first reset sub-circuit; the first input sub-circuit is electrically connected to the first signal line, the second clock signal line, and the first node, and is configured to input the signal of the first signal line to the first node under the signal control of the second clock signal line; the second input sub-circuit is electrically connected to the first potential signal line, the second clock signal line, the second node, the first node, and the second potential signal line, and is configured to transmit the signal of the second potential signal line or the first potential signal line to the second node under the signal control of the first node and the second clock signal line; the first sustaining sub-circuit is electrically connected to the second node, the first clock signal line, the second node, the first node, and the second potential signal line. The first sustaining sub-circuit is configured to transmit the signal of the second potential signal line to the third node under the potential control of the second node; the first output sub-circuit is electrically connected to the first clock signal line, the third node, the second node, and the second potential signal line, and is configured to transmit the signal of the first clock signal line or the second potential signal line to the first output terminal under the potential control of the third node and the second node; the first reset sub-circuit is electrically connected to the first reset control terminal, the reset signal line, and one end of the coupling sub-circuit, and is configured to transmit the potential of the reset signal line to one end of the coupling sub-circuit under the signal control of the first reset control terminal.

[0009] In some embodiments, the first input sub-circuit includes a first input transistor, the gate of which is electrically connected to the second clock signal line, the first electrode of which is electrically connected to the first signal line, and the second electrode of which is electrically connected to the first node; the coupling sub-circuit includes a coupling capacitor, the first plate of which is electrically connected to the first node, and the second plate of which is electrically connected to the third node; the first output sub-circuit includes a first output transistor and a second output transistor, the gate of which is electrically connected to the third node, the first electrode of which is electrically connected to the first clock signal line, the second electrode of which is electrically connected to the first output terminal, the gate of which is electrically connected to the second node, the second electrode of which is electrically connected to the second potential signal line, and the first electrode of which is electrically connected to the first output terminal.

[0010] In some embodiments, the second input sub-circuit includes a second input transistor and a third input transistor. The gate of the second input transistor is electrically connected to the first node, the first terminal of the second input transistor is electrically connected to the second potential signal line, and the second terminal of the second input transistor is electrically connected to the second node. The gate of the third input transistor is electrically connected to the second clock signal line, the first terminal of the third input transistor is electrically connected to the first potential signal line, and the second terminal of the third input transistor is electrically connected to the second node. The first sustaining sub-circuit includes a first sustaining transistor. The gate of the first sustaining transistor is electrically connected to the second node, the first terminal of the first sustaining transistor is electrically connected to the third node, and the second terminal of the first sustaining transistor is electrically connected to the second potential signal line.

[0011] In some embodiments, the first reset sub-circuit includes a first reset transistor, the gate of the first reset transistor being the first reset control terminal, the first electrode of the first reset transistor being electrically connected to the reset signal line, and the second electrode of the first reset transistor being electrically connected to the third node.

[0012] In some embodiments, the first reset control terminal is electrically connected to any one of the first signal line, the first node of the cascaded gate drive circuit unit in the gate drive circuit, the third node of the cascaded gate drive circuit unit in the gate drive circuit, and the first plate of the cascaded coupling capacitor in the gate drive circuit.

[0013] In some embodiments, the first input sub-circuit further includes a fourth input transistor, the gate of which is electrically connected to the first potential signal line, the first terminal of which is electrically connected to the second terminal of the first input transistor, and the second terminal of which is electrically connected to the first plate of the coupling capacitor; or / and the first output sub-circuit further includes a first capacitor, the first plate of which is electrically connected to the gate of the second output transistor, and the second plate of which is electrically connected to the second terminal of the second output transistor.

[0014] In some implementations, the first signal line is a start signal line. Before the first signal line outputs a first low-level signal, the signal of the reset signal line is a high-level signal, and the high-level signal of the reset signal line is greater than the high-level signal of the first signal line. When the first signal line outputs a first low-level signal, the signal of the reset signal line is a low-level signal.

[0015] In some embodiments, the gate drive circuit unit further includes at least one of a second reset sub-circuit and a second sustaining sub-circuit; the first reset sub-circuit is electrically connected to one end of the coupling sub-circuit electrically connected to the third node, the second reset sub-circuit is electrically connected to a second reset control terminal, the reset signal line, and one end of the coupling sub-circuit electrically connected to the first node, and the second reset sub-circuit is used to transmit the potential of the reset signal line to one end of the coupling sub-circuit electrically connected to the first node under the signal control of the second reset control terminal; the second sustaining sub-circuit is electrically connected to the second node, the second potential signal line, and one end of the coupling sub-circuit electrically connected to the first node, and the second sustaining sub-circuit is used to transmit the signal of the second potential signal line to one end of the coupling sub-circuit electrically connected to the first node under the potential control of the second node.

[0016] In some embodiments, the second reset sub-circuit includes a second reset transistor, the gate of which is the second reset control terminal, the first terminal of which is electrically connected to the reset signal line, and the second terminal of which is electrically connected to one end of the coupling sub-circuit electrically connected to the first node; the second sustaining sub-circuit includes a second sustaining body transistor, the gate of which is electrically connected to the second node, the first terminal of which is electrically connected to one end of the coupling sub-circuit electrically connected to the first node, and the second terminal of which is electrically connected to the second potential signal line.

[0017] In some embodiments, the gate drive circuit unit further includes a second output sub-circuit configured to transmit a signal from a fifth input terminal or a sixth input terminal to a second output terminal based on the voltage applied to the second node and the third node.

[0018] In some implementations, the fifth input terminal receives a signal from the first clock signal line, and the sixth input terminal receives a signal from the second potential signal line.

[0019] In some embodiments, the first clock signal line received by the fifth input terminal is different from the first clock signal line received by the third input terminal; the high potential in the first clock signal line received by the fifth input terminal is greater than the high potential in the first clock signal line received by the third input terminal; the low potential in the first clock signal line received by the fifth input terminal is less than the low potential in the first clock signal line received by the third input terminal; the second potential signal line received by the sixth input terminal is different from the second potential signal line received by the fourth input terminal; the potential in the second potential signal line received by the sixth input terminal is greater than the potential in the second potential signal line received by the fourth input terminal.

[0020] In some embodiments, the signal in the first signal line is a start signal, the signal in the first potential signal line is a low potential, the signal in the second potential signal line is a high potential, and the thin-film transistors in the gate drive circuit unit are all P-type.

[0021] In a second aspect of this disclosure, a gate driving circuit is provided, including at least one cascaded circuit, each cascaded circuit including a plurality of gate driving circuit units connected in sequence, wherein the gate driving circuit units are the gate driving circuit units provided in the first aspect of this disclosure.

[0022] In a third aspect of this disclosure, a method for manufacturing a display substrate is provided, comprising: providing a substrate; and manufacturing at least one cascaded circuit on the substrate, each cascaded circuit including a plurality of gate driving circuit units cascaded in sequence, wherein the gate driving circuit units are the gate driving circuit units provided in the first aspect of this disclosure.

[0023] In a fourth aspect of this disclosure, a display substrate is provided, including the gate driving circuit unit provided in the first aspect of this disclosure.

[0024] In some embodiments, the coupling sub-circuit in the gate driving circuit unit includes a coupling capacitor; the first output sub-circuit includes a first output transistor and a second output transistor; the display substrate includes a substrate and a gate metal layer disposed on one side of the substrate, the gate metal layer includes the second plate of the coupling capacitor and the gate of the first output transistor, and the second plate of the coupling capacitor and the gate of the first output transistor are directly connected.

[0025] In some embodiments, the first output sub-circuit in the gate driving circuit unit further includes a first capacitor, the coupling capacitor and the first capacitor are arranged along a first direction; the gate metal layer further includes a second plate of the first capacitor and the gate of the second output transistor, and the second plate of the first capacitor and the gate of the second output transistor are directly connected; in a second direction, the first output transistor and the second output transistor are located on the same side of the coupling capacitor and the first capacitor, and the first direction intersects the second direction.

[0026] In some embodiments, the second input sub-circuit in the gate driving circuit unit includes a second input transistor and a third input transistor; the display substrate further includes a first sustaining sub-circuit and a first reset sub-circuit, the first sustaining sub-circuit including a first sustaining transistor; the first reset sub-circuit including a first reset transistor; the display substrate includes a semiconductor layer located between the substrate and the gate metal layer, the semiconductor layer including a continuous first semiconductor pattern, and the active portions of the second input transistor, the first sustaining transistor, and the first reset transistor are formed by the first semiconductor pattern.

[0027] In some embodiments, the first semiconductor pattern includes a first sub-semiconductor pattern, a second sub-semiconductor pattern, and a third sub-semiconductor pattern, wherein the second sub-semiconductor pattern is connected between the first sub-semiconductor pattern and the third sub-semiconductor pattern, the extension direction of the first sub-semiconductor pattern is parallel to the extension direction of the third sub-semiconductor pattern, and the extension direction of the second sub-semiconductor pattern is non-linear; the first sub-semiconductor pattern includes the active portion of the second input transistor, the second sub-semiconductor pattern includes the active portion of the first sustaining transistor, and the third sub-semiconductor pattern includes the active portion of the first reset transistor.

[0028] In some embodiments, the channel extension direction of the active portion of the second input transistor, the channel extension direction of the active portion of the first sustaining transistor, and the channel extension direction of the active portion of the first reset transistor are parallel to each other.

[0029] In some embodiments, the first input sub-circuit in the gate drive circuit unit includes a first input transistor; the first input sub-circuit also includes a fourth input transistor; in the second direction, the first input transistor, the fourth input transistor, the second input transistor, the third input transistor, the first sustaining transistor, and the first reset transistor are all located on one side of the coupling capacitor and the first capacitor, and the first output transistor and the second output transistor are both located on the other side of the coupling capacitor and the first capacitor.

[0030] In some embodiments, the display substrate includes a first clock signal line, a second clock signal line, a first potential signal line, a second potential signal line, and a reset signal line; the first clock signal line includes a first sub-clock line and a second sub-clock line, and the signals in the first sub-clock line and the second sub-clock line are the same; the second clock signal line includes a third sub-clock line and a fourth sub-clock line, and the signals in the third sub-clock line and the fourth sub-clock line are the same; the second potential signal line includes a first sub-potential line and a second sub-potential line, and the signals in the first sub-potential line and the second sub-potential line are the same; the first sub-clock line, the third sub-clock line, the first sub-potential line, the first potential signal line, the reset signal line, the fourth sub-clock line, the second sub-clock line, and the second sub-potential line are arranged sequentially along the second direction; the orthographic projection of the coupling capacitor on the substrate at least partially overlaps with the orthographic projections of the reset signal line, the fourth sub-clock line, and the second sub-clock line on the substrate.

[0031] In some embodiments, the orthographic projection of the first reset transistor on the substrate at least partially overlaps with the orthographic projection of the reset signal line on the substrate; the orthographic projection of the first capacitor on the substrate at least partially overlaps with the orthographic projections of the fourth sub-clock line and the second sub-clock line on the substrate; in the first direction, the first reset transistor and the first capacitor are located on the same side of the coupling capacitor; the orthographic projection of the second sub-potential line on the substrate is located on the side of the first output transistor and the second output transistor away from the coupling capacitor.

[0032] In a fifth aspect of this disclosure, a display device is provided, including a gate driving circuit, the gate driving circuit including the gate driving circuit unit provided in the first aspect of this disclosure. Attached Figure Description

[0033] Figure 1 is a schematic diagram of a first type of gate drive circuit unit provided in some embodiments of the present disclosure;

[0034] Figure 2 is a waveform diagram of multiple signal lines or signals of a first type of gate drive circuit unit provided in some embodiments of this disclosure;

[0035] Figure 3 is a second circuit diagram of a gate drive circuit unit provided in some embodiments of this disclosure;

[0036] Figure 4 is a third circuit diagram of a gate drive circuit unit provided in some embodiments of this disclosure;

[0037] Figure 5 is a waveform diagram of multiple signal lines or signals of a second type of gate drive circuit unit provided in some embodiments of this disclosure;

[0038] Figure 6 is a fourth circuit diagram of a gate drive circuit unit provided in some embodiments of this disclosure;

[0039] Figure 7 is a fifth circuit diagram of a gate drive circuit unit provided in some embodiments of this disclosure;

[0040] Figure 8 is a sixth circuit diagram of a gate drive circuit unit provided in some embodiments of this disclosure;

[0041] Figure 9 is a schematic layout diagram of one of the gate drive circuit units provided in some embodiments of this disclosure;

[0042] Figure 10 is a schematic layout diagram of the semiconductor layer of a gate drive circuit unit provided in some embodiments of this disclosure;

[0043] Figure 11 is a schematic layout of the gate metal layer of a gate driving circuit unit provided in some embodiments of the present disclosure;

[0044] Figure 12 is a schematic layout of the capacitor metal layer of a gate drive circuit unit provided in some embodiments of this disclosure;

[0045] Figure 13 is a schematic layout of the second insulating layer of a gate drive circuit unit provided in some embodiments of the present disclosure;

[0046] Figure 14 is a schematic layout of the first metal layer of a gate drive circuit unit provided in some embodiments of the present disclosure;

[0047] Figure 15 is a schematic layout of the third insulating layer of a gate drive circuit unit provided in some embodiments of the present disclosure;

[0048] Figure 16 is a schematic layout of the second metal layer of a gate drive circuit unit provided in some embodiments of the present disclosure. Detailed Implementation

[0049] To better understand the technical solutions provided in the embodiments of this specification, the technical solutions of the embodiments of this specification will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the embodiments of this specification and the specific features in the embodiments are detailed descriptions of the technical solutions of the embodiments of this specification, rather than limitations on the technical solutions of this specification. In the absence of conflict, the embodiments of this specification and the technical features in the embodiments can be combined with each other.

[0050] In this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, without necessarily requiring or implying any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. The term "two or more" includes two or more cases.

[0051] In related technologies, to stably output high-performance electrical signals, gate drive circuit units require a large number of thin-film transistors and capacitors. These units occupy a significant area in the layout or display panel, resulting in structural complexity that hinders the narrow bezel requirements of display panels. While some gate drive circuit units have simplified structures, they still suffer from unstable high-performance signal output. The output signal potential is insufficient (e.g., the high-potential signal is not high enough, and the low-potential signal is not low enough), making it difficult for the gate drive circuit to stably output electrical signals that meet display or driving requirements.

[0052] In view of this, the present disclosure provides a gate drive circuit unit that can improve or solve the above-mentioned technical problems.

[0053] This disclosure also provides a gate driving circuit, including at least one cascaded circuit, each cascaded circuit including a plurality of gate driving circuit units cascaded in sequence, the gate driving circuit units being the gate driving circuit units described above.

[0054] This disclosure also provides a method for manufacturing a display substrate, comprising: providing a substrate; and manufacturing at least one cascaded circuit on the substrate, each cascaded circuit including a plurality of gate driving circuit units cascaded in sequence, wherein the gate driving circuit units are the gate driving circuit units described above.

[0055] This disclosure also provides a display substrate, which includes the gate driving circuit unit described above.

[0056] This disclosure also provides a display device, which includes a gate driving circuit, the gate driving circuit including the gate driving circuit unit described above.

[0057] This disclosure provides a gate drive circuit unit, comprising: a first input sub-circuit configured to control the voltage of a first node based on a signal at a first input terminal; a second input sub-circuit configured to control the voltage of a second node based on a signal at a second input terminal; a coupling sub-circuit configured to control the voltage of a third node based on the voltage of the first node; and a first output sub-circuit configured to transmit a signal at a third input terminal or a signal at a fourth input terminal to a first output terminal based on the voltages applied to the second node and the third node.

[0058] In the following detailed description, different embodiments are described in order to better illustrate the inventive spirit of this disclosure, but the description of different embodiments is not intended to limit the combination of different implementations or features in this disclosure.

[0059] Please refer to Figures 1 to 8. Figure 1 is a first circuit diagram of a gate driving circuit unit provided in some embodiments of this disclosure; Figure 2 is a waveform diagram of multiple signal lines or signals of a first gate driving circuit unit provided in some embodiments of this disclosure; Figure 3 is a second circuit diagram of a gate driving circuit unit provided in some embodiments of this disclosure; Figure 4 is a third circuit diagram of a gate driving circuit unit provided in some embodiments of this disclosure; Figure 5 is a waveform diagram of multiple signal lines or signals of a second gate driving circuit unit provided in some embodiments of this disclosure; Figure 6 is a fourth circuit diagram of a gate driving circuit unit provided in some embodiments of this disclosure; Figure 7 is a fifth circuit diagram of a gate driving circuit unit provided in some embodiments of this disclosure; and Figure 8 is a sixth circuit diagram of a gate driving circuit unit provided in some embodiments of this disclosure.

[0060] This disclosure provides a gate driving circuit unit 1000, as shown in FIG1. ​​The gate driving circuit unit 1000 includes a first input sub-circuit 100, a second input sub-circuit 400, a coupling sub-circuit 200, and a first output sub-circuit 300. The first input sub-circuit 100 is configured to control the voltage of a first node N1 based on a signal from a first input terminal 101; the second input sub-circuit 400 is configured to control the voltage of a second node N2 based on a signal from a second input terminal 102; the coupling sub-circuit 200 is at least configured to control the voltage of a third node N3 based on the voltage of the first node N1; the first output sub-circuit 300 is configured to transmit a signal from a third input terminal 103 or a signal from a fourth input terminal 104 to a first output terminal OUT1 based on the voltages applied to the second node N2 and the third node N3.

[0061] For example, the gate drive circuit unit 1000 may also be referred to as a shift register.

[0062] For example, the signal output by the first output terminal OUT1 can be a gate drive signal (scan drive signal), which can be provided to the pixel drive circuit.

[0063] For example, the signal output by the first output terminal OUT1 can also be a cascade signal, which can be provided to the next stage or other cascaded gate drive circuit units 1000.

[0064] For example, the coupling sub-circuit 200 may also be configured to control the voltage of the first node N1 based on the voltage of the third node N3. For instance, in one time phase, the coupling sub-circuit 200 may be configured to control the voltage of the third node N3 based on the voltage of the first node N1, and in another time phase, the coupling sub-circuit 200 may also be configured to control the voltage of the first node N1 based on the voltage of the third node N3.

[0065] In this disclosure, the first input sub-circuit 100 is configured to control the voltage of the first node N1 based on the signal from the first input terminal 101; the second input sub-circuit 400 is configured to control the voltage of the second node N2 based on the signal from the second input terminal 102; the coupling sub-circuit 200 is configured to control the voltage of the third node N3 based on the voltage of the first node N1; and the first output sub-circuit 300 is configured to transmit the signal from the third input terminal 103 or the signal from the fourth input terminal 104 to the first output terminal OUT1 based on the voltages applied to the second node N2 and the third node N3. By configuring the coupling sub-circuit 200, the voltage of the third node N3 can be controlled according to the voltage of the first node N1, so that the electrical signal of the third node N3 can better match the display or driving requirements. For example, the high potential of the third node N3 can be made higher, or the low potential of the third node N3 can be made lower. This allows the thin-film transistor in the first output sub-circuit 300 that is electrically connected to the third node N3 to be fully turned on or fully turned off. Thus, when the thin-film transistor electrically connected to the third node N3 is turned on, the signal of the third input terminal 103 can be better transmitted to the first output terminal OUT1. Thus, when the thin-film transistor electrically connected to the third node N3 is turned off, the signal of the third input terminal 103 can be better isolated from the first output terminal OUT1, thereby improving the stability of the output signal of the gate drive circuit unit 1000.

[0066] In this disclosure, the gate driving circuit unit 1000 includes the first input sub-circuit 100, the second input sub-circuit 400, the coupling sub-circuit 200, and the first output sub-circuit 300. The gate driving circuit unit 1000 has a simple structure, and the number of thin-film transistors and capacitors included in the gate driving circuit unit 1000 is relatively small. The area occupied by the gate driving circuit unit 1000 in the layout or display panel is relatively small. That is, the gate driving circuit unit 1000 has the effect of simple structure, which is beneficial to the narrow bezel of the display panel.

[0067] Therefore, the gate drive circuit unit 1000 provided in this disclosure has the advantages of simple structure and stable output of electrical signals that meet display requirements.

[0068] In some embodiments, as shown in FIG1, the gate drive circuit unit 1000 satisfies at least one of the following conditions: the first input terminal 101 receives the signal of the first signal line STV; the second input terminal 102 receives the signal of the first potential signal line VGL; the third input terminal 103 receives the signal of the first clock signal line CB; and the fourth input terminal 104 receives the signal of the second potential signal line VGH.

[0069] It should be noted that, as shown in Figure 1, the gate drive circuit unit 1000 simultaneously satisfies the following conditions: the first input terminal 101 receives the signal from the first signal line STV; the second input terminal 102 receives the signal from the first potential signal line VGL; the third input terminal 103 receives the signal from the first clock signal line CB; and the fourth input terminal 104 receives the signal from the second potential signal line VGH. However, this is not the only limitation. In other embodiments of this disclosure, the gate drive circuit unit 1000 may satisfy some of the above conditions.

[0070] For example, in some embodiments, one of the signals on the first potential signal line VGL and the second potential signal line VGH is a low potential signal and the other is a high potential signal.

[0071] It should be noted that, as shown in Figures 1 and 2, in this disclosure, the signal of the first potential signal line VGL is used as a low potential signal and the signal of the second potential signal line VGH is used as a high potential signal for illustration, but it is not limited to this.

[0072] For example, as shown in FIG1, this disclosure uses the signal of the first signal line STV as the starting signal for illustration, but is not limited thereto.

[0073] For example, as shown in FIG1, this disclosure is illustrated by the example of the third input terminal 103 receiving the signal of the first clock signal line CB, but is not limited thereto.

[0074] For example, as shown in FIG1, this disclosure uses the fourth input terminal 104 receiving the signal of the second potential signal line VGH as an example, but is not limited thereto.

[0075] For example, in this disclosure, the signal of the first clock signal line CB and the signal of the second clock signal line CK are out of phase for at least a portion of the time. For instance, the first clock signal line CB is the inverted signal of the second clock signal line CK, but this is not limited to that. As shown in Figure 2.

[0076] For example, the third input terminal 103 receives the first clock signal line CB. The signal of the first clock signal line CB is an electrical signal that alternates between high and low potentials. The signal of the first clock signal line CB can also control the voltage of the third node N3 (e.g., through the coupling effect between the capacitor and the parasitic capacitance). Thus, the potential of the third node N3 can be controlled simultaneously by the first output sub-circuit 300 (first output transistor T5). This reduces the number of thin-film transistors and capacitors included in the gate drive circuit unit 1000, resulting in a simple structure for the gate drive circuit unit 1000, which is beneficial for narrow bezels of the display panel.

[0077] In some embodiments, as shown in FIG1, the gate drive circuit unit 1000 further includes a first sustaining sub-circuit 500 and a first reset sub-circuit 600.

[0078] The first input sub-circuit 100 is electrically connected to the first signal line STV, the second clock signal line CK and the first node N1. The first input sub-circuit 100 is used to input the signal of the first signal line STV to the first node N1 under the signal control of the second clock signal line CK.

[0079] The second input sub-circuit 400 is electrically connected to the first potential signal line VGL, the second clock signal line CK, the second node N2, the first node N1 and the second potential signal line VGH. The second input sub-circuit 400 is used to transmit the signal of the second potential signal line VGH or the first potential signal line VGL to the second node N2 under the signal control of the first node N1 and the second clock signal line CK.

[0080] The first sustaining sub-circuit 500 is electrically connected to the second node N2, the third node N3 and the second potential signal line VGH. The first sustaining sub-circuit 500 is used to transmit the signal of the second potential signal line VGH to the third node N3 under the potential control of the second node N2.

[0081] The first output sub-circuit 300 is electrically connected to the first clock signal line CB, the third node N3, the second node N2 and the second potential signal line VGH. The first output sub-circuit 300 is used to transmit the signal of the first clock signal line CB or the second potential signal line VGH to the first output terminal OUT1 under the potential control of the third node N3 and the second node N2.

[0082] The first reset sub-circuit 600 is electrically connected to the first reset control terminal 601K, the reset signal line PCX, and one end of the coupling sub-circuit 200. The first reset sub-circuit 600 is used to transmit the potential of the reset signal line PCX to one end of the coupling sub-circuit 200 under the signal control of the first reset control terminal 601K.

[0083] For example, the first sustaining sub-circuit 500 is configured to transmit the signal of the second potential signal line VGH to the third node N3 according to the potential of the second node N2;

[0084] For example, the first reset sub-circuit 600 is configured to transmit the potential of the reset signal line PCX to one end of the coupling sub-circuit 200 under the signal control of the first reset control terminal 601K.

[0085] In some implementations, as shown in FIG1, the first input sub-circuit 100 includes a first input transistor T1, the gate of the first input transistor T1 is electrically connected to the second clock signal line CK, the first electrode of the first input transistor T1 is electrically connected to the first signal line STV, and the second electrode of the first input transistor T1 is electrically connected to the first node N1.

[0086] The coupling sub-circuit 200 includes a coupling capacitor C2, the first plate C2a of the coupling capacitor C2 is electrically connected to the first node N1, and the second plate C2b of the coupling capacitor C2 is electrically connected to the third node N3.

[0087] The first output sub-circuit 300 includes a first output transistor T5 and a second output transistor T4. The gate of the first output transistor T5 is electrically connected to the third node N3. The first electrode of the first output transistor T5 is electrically connected to the first clock signal line CB. The second electrode of the first output transistor T5 is electrically connected to the first output terminal OUT1. The gate of the second output transistor T4 is electrically connected to the second node N2. The second electrode of the second output transistor T4 is electrically connected to the second potential signal line VGH. The first electrode of the second output transistor T4 is electrically connected to the first output terminal OUT1.

[0088] It should be noted that, as shown in Figure 1, in this disclosure, the electrode / end on the left or lower side of the thin-film transistor is defined as the first electrode of the thin-film transistor, and the electrode / end on the right or upper side of the thin-film transistor is defined as the second electrode of the thin-film transistor. The first electrode of the thin-film transistor is one of the source and drain, and the second electrode of the thin-film transistor is the other of the source and drain. In some embodiments, the source and drain of the thin-film transistor can be interchanged.

[0089] In some embodiments, as shown in FIG1, the second input sub-circuit 400 includes a second input transistor T2 and a third input transistor T3. The gate of the second input transistor T2 is electrically connected to the first node N1, the first electrode of the second input transistor T2 is electrically connected to the second potential signal line VGH, and the second electrode of the second input transistor T2 is electrically connected to the second node N2. The gate of the third input transistor T3 is electrically connected to the second clock signal line CK, the first electrode of the third input transistor T3 is electrically connected to the first potential signal line VGL, and the second electrode of the third input transistor T3 is electrically connected to the second node N2.

[0090] The first sustaining sub-circuit 500 includes a first sustaining transistor T6, the gate of the first sustaining transistor T6 is electrically connected to the second node N2, the first electrode of the first sustaining transistor T6 is electrically connected to the third node N3, and the second electrode of the first sustaining transistor T6 is electrically connected to the second potential signal line VGH.

[0091] In some embodiments, as shown in FIG1, the first reset sub-circuit 600 includes a first reset transistor T7, the gate of the first reset transistor T7 is the first reset control terminal 601K, the first terminal of the first reset transistor T7 is electrically connected to the reset signal line PCX, and the second terminal of the first reset transistor T7 is electrically connected to the third node N3.

[0092] In some embodiments, as shown in FIG1, the first reset control terminal 601K is electrically connected to any one of the following: the first signal line STV, the first node N1 of the cascaded gate drive circuit unit 1000 in the gate drive circuit, the third node N3 of the cascaded gate drive circuit unit 1000 in the gate drive circuit, and the first plate of the cascaded coupling capacitor C2 in the gate drive circuit.

[0093] For example, Figures 1, 3, and 4 illustrate that the first reset control terminal 601K is electrically connected to the first signal line STV; Figure 6 illustrates that the first reset control terminal 601K is electrically connected to the first node N1 of the cascaded previous stage gate drive circuit unit 1000 in the gate drive circuit (the first node of the previous stage gate drive circuit unit is N1(N-1)). The first reset control terminal 601K can also be electrically connected to one of the third node N3 of the cascaded previous stage gate drive circuit unit 1000 in the gate drive circuit, and the first plate of the cascaded previous stage coupling capacitor C2 in the gate drive circuit.

[0094] For example, by electrically connecting the first reset control terminal 601K to the signal line or node in this way, the number of signal lines can be reduced without adding new signal lines separately, thereby simplifying the structure of the gate drive circuit unit 1000.

[0095] In some embodiments, as shown in FIG1, the first input sub-circuit 100 further includes a fourth input transistor T8, the gate of which is electrically connected to the first potential signal line VGL, the first terminal of which is electrically connected to the second terminal of the first input transistor T1, and the second terminal of which is electrically connected to the first plate C2a of the coupling capacitor C2; or / and, the first output sub-circuit 300 further includes a first capacitor C1, the first plate C1a of which is electrically connected to the gate of the second output transistor T4, and the second plate C1b of which is electrically connected to the second terminal of the second output transistor T4.

[0096] For example, the fourth input transistor T8 can protect the first input transistor T1 and the second input transistor T2. For instance, when the potential of the first plate C2a of the coupling capacitor C2 or the fourth node N4 is too low, the fourth input transistor T8 can prevent the low potential of the first plate C2a of the coupling capacitor C2 or the fourth node N4 from flowing directly into the first node N1, thereby preventing damage to the first input transistor T1 and the second input transistor T2.

[0097] In some implementations, referring to Figures 1 and 5, the first signal line STV is a start signal line. Before the first signal line STV outputs the first low-level signal, the signal of the reset signal line PCX is a high-level signal (shown by the dashed box in Figure 5), and the high-level signal of the reset signal line PCX is greater than the high-level signal of the first signal line STV. Starting from the first signal line STV outputting the first low-level signal, the signal of the reset signal line PCX is a low-level signal.

[0098] For example, to prevent the low voltage of the third node N3 from mistakenly turning on the first output transistor T5 and outputting a low-voltage signal when the display panel is powered on (when the display panel is lit), the reset signal line PCX is given a high-voltage signal before the first signal line STV turns into a low-voltage signal when powered on. The high potential of the reset signal line PCX is greater than the high potential of the first signal line STV, causing the first reset transistor T7 to turn on and the third node N3 to be set to a high-voltage signal, ensuring that the first output transistor T5 is turned off and preventing erroneous output. The waveform of the reset signal line PCX is shown in Figure 5. The high potential time of the reset signal line PCX is before the first signal line STV, which is electrically connected to the first-stage gate drive circuit unit 1000, outputs a low potential.

[0099] In some embodiments, as shown in Figures 3 and 4, the gate drive circuit unit 1000 further includes at least one of a second reset sub-circuit 700 and a second sustaining sub-circuit 800.

[0100] The first reset sub-circuit 600 is electrically connected to one end of the coupling sub-circuit 200 that is electrically connected to the third node N3. The second reset sub-circuit 700 is electrically connected to the second reset control terminal 602K, the reset signal line PCX, and one end of the coupling sub-circuit 200 that is electrically connected to the first node N1. The second reset sub-circuit 700 is used to transmit the potential of the reset signal line PCX to the one end of the coupling sub-circuit 200 that is electrically connected to the first node N1 under the signal control of the second reset control terminal 602K.

[0101] The second sustaining sub-circuit 800 is electrically connected to the second node N2, the second potential signal line VGH, and one end of the coupling sub-circuit 200 that is electrically connected to the first node N1. The second sustaining sub-circuit 800 is used to transmit the signal of the second potential signal line VGH to the end of the coupling sub-circuit 200 that is electrically connected to the first node N1 under the potential control of the second node N2.

[0102] In some embodiments, as shown in Figures 3 and 4, the second reset sub-circuit 700 includes a second reset transistor T9, the gate of the second reset transistor T9 is the second reset control terminal 602K, the first terminal of the second reset transistor T9 is electrically connected to the reset signal line PCX, and the second terminal of the second reset transistor T9 is electrically connected to one end of the coupling sub-circuit 200 that is electrically connected to the first node N1.

[0103] The second sustaining sub-circuit 800 includes a second sustaining transistor T10, the gate of the second sustaining transistor T10 is electrically connected to the second node N2, the first electrode of the second sustaining transistor T10 is electrically connected to one end of the coupling sub-circuit 200 which is electrically connected to the first node N1, and the second electrode of the second sustaining transistor T10 is electrically connected to the second potential signal line VGH.

[0104] For example, as shown in FIG3, the gate of the second reset transistor T9 is the second reset control terminal 602K, which is electrically connected to any one of the following: the first signal line STV, the first node N1 of the cascaded gate drive circuit unit 1000 in the gate drive circuit, the third node N3 of the cascaded gate drive circuit unit 1000 in the gate drive circuit, and the first plate of the cascaded coupling capacitor C2 in the gate drive circuit.

[0105] For example, as shown in FIG3, the first terminal of the second reset transistor T9 is electrically connected to the reset signal line PCX, and the second terminal of the second reset transistor T9 is electrically connected to the first plate C2a of the coupling capacitor C2.

[0106] For example, as shown in FIG4, the gate of the second sustaining transistor T10 is electrically connected to the second node N2, the first electrode of the second sustaining transistor T10 is electrically connected to the first plate C2a of the coupling capacitor C2, and the second electrode of the second sustaining transistor T10 is electrically connected to the second potential signal line VGH.

[0107] For example, as shown in Figures 2 and 4, in the first stage, at time t1, the second reset transistor T9 of the second reset sub-circuit 700 resets the potential of the fourth node N4, thereby improving the stability of the potential of the fourth node N4.

[0108] For example, as shown in Figures 2 and 4, in the third stage, at time t3, the second sustaining body tube T10 of the second sustaining sub-circuit 800 maintains the stability of the potential of the fourth node N4.

[0109] In some embodiments, as shown in Figures 7 and 8, the gate drive circuit unit 1000 further includes a second output sub-circuit 900, which is configured to transmit a signal from the fifth input terminal 105 or the sixth input terminal 106 to the second output terminal OUT2 based on the voltage applied to the second node N2 and the third node N3.

[0110] For example, one of the first output terminal OUT1 and the second output terminal OUT2 can output a gate drive signal, and the other of the first output terminal OUT1 and the second output terminal OUT2 can output a stage transmission signal.

[0111] For example, the second output sub-circuit 900 includes a third output transistor T12 and a fourth output transistor T11. The gate of the third output transistor T12 is electrically connected to the third node N3, the first electrode of the third output transistor T12 is electrically connected to the first clock signal line CB, and the second electrode of the third output transistor T12 is electrically connected to the second output terminal OUT2. The gate of the fourth output transistor T11 is electrically connected to the second node N2, the second electrode of the fourth output transistor T11 is electrically connected to the second potential signal line VGH, and the first electrode of the fourth output transistor T11 is electrically connected to the second output terminal OUT2.

[0112] It should be noted that the first plate C1a of the first capacitor C1 is electrically connected to the gate of the second output transistor T4, and the second plate C1b of the first capacitor C1 is electrically connected to the second terminal of the second output transistor T4. In some other embodiments, the first plate C1a of the first capacitor C1 may also be electrically connected to the gate of the fourth output transistor T11, and the second plate C1b of the first capacitor C1 may be electrically connected to the second terminal of the fourth output transistor T11. In some other embodiments, the first capacitor C1 may be electrically connected at corresponding positions on the gates of the second output transistor T4 and the fourth output transistor T11.

[0113] In some implementations, as shown in Figures 7 and 8, the fifth input terminal 105 receives the signal from the first clock signal line CB, and the sixth input terminal 106 receives the signal from the second potential signal line VGH.

[0114] In some implementations, as shown in Figures 7 and 8, the first clock signal line CB received by the fifth input terminal 105 is different from the first clock signal line CB received by the third input terminal 103.

[0115] For example, the high potential in the first clock signal line CB received by the fifth input terminal 105 is greater than the high potential in the first clock signal line CB received by the third input terminal 103.

[0116] For example, the low potential in the first clock signal line CB received by the fifth input terminal 105 is less than the low potential in the first clock signal line CB received by the third input terminal 103.

[0117] In some implementations, as shown in Figures 7 and 8, the second potential signal line VGH received by the sixth input terminal 106 is different from the second potential signal line VGH received by the fourth input terminal 104.

[0118] For example, the potential in the second potential signal line VGH received by the sixth input terminal 106 is greater than the potential in the second potential signal line VGH received by the fourth input terminal 104.

[0119] For example, taking the signal in the second potential signal line VGH as a high potential, the first clock signal line CB received by the first terminal of the third output transistor T12 is different from the first clock signal line CB received by the first terminal of the first output transistor T5; the high potential in the first clock signal line CB received by the first terminal of the third output transistor T12 is greater than the high potential in the first clock signal line CB received by the first terminal of the first output transistor T5; the low potential in the first clock signal line CB received by the first terminal of the third output transistor T12 is less than the low potential in the first clock signal line CB received by the first terminal of the first output transistor T5; the second potential signal line VGH received by the second terminal of the fourth output transistor T11 is different from the second potential signal line VGH received by the second terminal of the second output transistor T4; the potential in the second potential signal line VGH received by the second terminal of the fourth output transistor T11 is greater than the potential in the second potential signal line VGH received by the second terminal of the second output transistor T4.

[0120] For example, as shown in Figure 8, the first electrode of the third output transistor T12 is electrically connected to the second output clock signal line CB2, the second electrode of the fourth output transistor T11 is electrically connected to the second output potential signal line VGH2; the first electrode of the first output transistor T5 is electrically connected to the first output clock signal line CB1, and the second electrode of the second output transistor T4 is electrically connected to the first output potential signal line VGH1.

[0121] For example, when the high potential of the first clock signal line CB received by the fifth input terminal 105 is greater than the high potential of the first clock signal line CB received by the third input terminal 103, the low potential of the first clock signal line CB received by the fifth input terminal 105 is less than the low potential of the first clock signal line CB received by the third input terminal 103, and the potential of the second potential signal line VGH received by the sixth input terminal 106 is greater than the potential of the second potential signal line VGH received by the fourth input terminal 104, the first output terminal OUT1 can be configured to output a stage transmission signal, and the second output terminal OUT2 can output a gate drive signal. This allows a larger voltage difference to be formed between the gate and source of the third output transistor T12, better maintaining the turn-on performance of the third output transistor T12, and allowing the first output terminal OUT1 to output an electrical signal better. Similarly, this allows a larger voltage difference to be formed between the gate and source of the fourth output transistor T11, better maintaining the turn-off performance of the fourth output transistor T11, and preventing interference with the output electrical signal of the second output terminal OUT2.

[0122] In some embodiments, as shown in Figures 1 to 8, the signal in the first signal line STV is a start signal, the signal in the first potential signal line VGL is a low potential, the signal in the second potential signal line VGH is a high potential, and the thin-film transistors in the gate drive circuit unit 1000 are all P-type.

[0123] For example, in some other embodiments, the signal in the first signal line STV is a start signal, the signal in the first potential signal line is a high potential, the signal in the second potential signal line is a low potential, and the thin-film transistors in the gate drive circuit unit 1000 are all N-type, but not limited thereto.

[0124] For example, the operation of the gate drive circuit unit 1000 shown in Figure 1 is described. The signal in the first signal line STV is the start signal, the signal in the first potential signal line VGL is at a low potential, and the signal in the second potential signal line VGH is at a high potential. The thin film transistors in the gate drive circuit unit 1000 are all P-type. However, in other embodiments or during operation, the signal in the first potential signal line VGL, the signal in the second potential signal line VGH, and the type of thin film transistor may not be limited to these. Please refer to Figures 1 and 2.

[0125] In the first stage, at time t1, the second clock signal line CK is at a low voltage, the first input sub-circuit 100 is working, the first input transistor T1 is turned on, and the low voltage signal of the first signal line STV is written to the first node N1. Since the fourth input transistor T8 is normally open, the low voltage signal is written to the fourth node N4. Due to the capacitive coupling effect of the coupling capacitor C2, the voltage of the third node N3 is pulled down. Since the signal of the first clock signal line CB is at a high voltage at this time, the first output sub-circuit 300 is working, so the first output transistor T5 is turned on, and the first output terminal OUT1 outputs a high voltage signal. At the same time, the first node N1 is at a low voltage, the second input sub-circuit 400 is working, the second input transistor T2 is turned on, the signal of the second potential signal line VGH is written to the second node N2, and the second output transistor T4 is turned off.

[0126] In the second stage, at time t2, the first clock signal line CB switches to a low voltage signal. Due to the inter-electrode capacitance of the thin-film transistor (the first output transistor T5), when the signal of the first clock signal line CB changes from a high potential to a low potential, the third node N3 is pulled low, ensuring that the first clock signal line CB outputs a low voltage signal normally. At this time, due to the effect of the first capacitor C1, the second node N2 maintains the high voltage signal of the previous moment, and the second output transistor T4 is turned off. The first output terminal OUT1 outputs a low voltage signal.

[0127] In the third stage, at time t3, the high-voltage signal of the first signal line STV is written to the first node N1 and the fourth node N4. Due to the capacitive coupling effect of the coupling capacitor C2, the potential of the third node N3 is pulled high, and the first output transistor T5 is turned off. At this time, the second input sub-circuit 400 is working, the third input transistor T3 is turning on, the second input transistor T2 is turning off, the signal of the first potential signal line VGL is written to the second node N2, the second output transistor T4 is turning on, and the first output terminal OUT1 outputs a high-potential signal (the signal of the second potential signal line VGH). And because the second node N2 has a low voltage, the first sustaining sub-circuit 500 is working, the first sustaining transistor T6 is turning on, and the signal of the second potential signal line VGH is written to the third node N3, ensuring that the first output transistor T5 is turned off.

[0128] For example, when the signal in the first signal line STV is low voltage, the first reset sub-circuit 600 operates, the first reset transistor T7 turns on, the PCX signal is written to the third node N3 to reset the third node N3, and in order to ensure that the third node N3 has a sufficiently low voltage at the next moment, so as to ensure that the low voltage signal of the first clock signal line CB can be output normally and reduce the output waveform loss due to the pull-down transistor Vth threshold (threshold voltage) problem, the signal of the reset signal line PCX is a low voltage signal.

[0129] For example, in order to improve the reset function of the reset signal line PCX, the low potential of the reset signal line PCX can be set to be lower than the low potential in the first potential signal line VGL (when the signal in the first potential signal line VGL is at a low potential).

[0130] This disclosure also provides a gate driving circuit, which includes at least one cascaded circuit, each of the cascaded circuits including a plurality of gate driving circuit units cascaded in sequence, wherein the gate driving circuit unit is the gate driving circuit unit 1000 described in any one of the above, or the gate driving circuit unit is the gate driving circuit unit 1000 in combination of any of the above.

[0131] Please refer to Figures 9 to 16. Figure 9 is a layout schematic diagram of a gate driving circuit unit 1000 according to some embodiments of the present disclosure; Figure 10 is a layout schematic diagram of the semiconductor layer of a gate driving circuit unit 1000 according to some embodiments of the present disclosure; Figure 11 is a layout schematic diagram of the gate metal layer of a gate driving circuit unit 1000 according to some embodiments of the present disclosure; Figure 12 is a layout schematic diagram of the capacitor metal layer of a gate driving circuit unit 1000 according to some embodiments of the present disclosure; Figure 13 is a layout schematic diagram of the second insulating layer of a gate driving circuit unit 1000 according to some embodiments of the present disclosure; Figure 14 is a layout schematic diagram of the first metal layer of a gate driving circuit unit 1000 according to some embodiments of the present disclosure; Figure 15 is a layout schematic diagram of the third insulating layer of a gate driving circuit unit 1000 according to some embodiments of the present disclosure; and Figure 16 is a layout schematic diagram of the second metal layer of a gate driving circuit unit 1000 according to some embodiments of the present disclosure. Figures 9 to 16 are illustrated using the gate driving circuit unit (first circuit schematic diagram) shown in Figure 1 as an example.

[0132] This disclosure also provides a method for manufacturing a display substrate, the method comprising: providing a substrate; and manufacturing at least one cascaded circuit on the substrate, each cascaded circuit comprising a plurality of gate driving circuit units cascaded in sequence, wherein the gate driving circuit unit is any one of the gate driving circuit units 1000 described above, or the gate driving circuit unit 1000 is a combination of any of the above-described gate driving circuit units 1000.

[0133] For example, in some embodiments, the method for manufacturing a display substrate includes the following steps S10 to S19.

[0134] Step S10: Provide a substrate.

[0135] For example, the substrate may be glass or a flexible substrate, and the material of the substrate may be polyimide, but is not limited thereto.

[0136] Step S11, as shown in FIG10, forms a semiconductor layer PO on one side of the substrate.

[0137] For example, the semiconductor layer PO includes the active portion P1 of the first input transistor T1, the active portion P8 of the fourth input transistor T8, the active portion P2 of the second input transistor T2, the active portion P3 of the third input transistor T3, the active portion P6 of the first sustaining transistor T6, the active portion P7 of the first reset transistor T7, the active portion P5 of the first output transistor T5, and the active portion P4 of the second output transistor T4.

[0138] Step S12: A gate insulating layer GI (not shown in the figure) is formed on the side of the semiconductor layer PO away from the substrate.

[0139] Step S13, as shown in FIG11, forms a gate metal layer Ge1 on the side of the gate insulating layer GI away from the substrate.

[0140] For example, the gate metal layer Ge1 includes the gate G1 of the first input transistor T1, the gate G8 of the fourth input transistor T8, the gate G2 of the second input transistor T2, the gate G3 of the third input transistor T3, the gate G6 of the first sustaining transistor T6, the gate G7 of the first reset transistor T7, the gate G5 of the first output transistor T5, and the gate G4 of the second output transistor T4.

[0141] For example, the gate metal layer Ge1 further includes the second plate C2b of the coupling capacitor and the second plate C1b of the first capacitor.

[0142] Step S14: A first insulating layer (not shown) is formed on the side of the gate metal layer Ge1 away from the gate metal layer Ge1.

[0143] Step S15, as shown in FIG12, forms a capacitor metal layer Ge2 on the side of the gate insulating layer GI away from the first insulating layer.

[0144] For example, the capacitor metal layer Ge2 includes the first plate C2a of the coupling capacitor and the first plate C1a of the first capacitor.

[0145] Step S16, as shown in FIG13, forms a second insulating layer ILD on the side of the capacitor metal layer Ge2 away from the substrate.

[0146] For example, Figure 13 illustrates multiple vias in the second insulating layer ILD.

[0147] Step S17, as shown in FIG14, forms a first metal layer SD1 on the side of the second insulating layer ILD away from the substrate.

[0148] For example, the first metal layer SD1 includes the first terminal S1 and the second terminal D1 of the first input transistor T1, the first terminal S8 and the second terminal D8 of the fourth input transistor T8, the first terminal S2 and the second terminal D2 of the second input transistor T2, the first terminal S3 and the second terminal D2 of the third input transistor T3, the first terminal S6 and the second terminal D6 of the first sustaining transistor T6, the first terminal S7 and the second terminal D7 of the first reset transistor T7, the first terminal S5 and the second terminal D5 of the first output transistor T5, and the first terminal S4 and the second terminal D4 of the second output transistor T4.

[0149] For example, the first metal layer SD1 further includes a first sub-clock line CB-1 of the first clock signal line CB and a third sub-clock line CK-1 of the second clock signal line CK.

[0150] Step S18, as shown in FIG15, forms a third insulating layer PLN on the side of the first metal layer SD1 away from the substrate.

[0151] For example, the third insulating layer PLN can be a planar layer.

[0152] For example, Figure 15 illustrates multiple vias in the third insulating layer PLN.

[0153] Step S19, as shown in FIG16, forms a second metal layer SD2 on the side of the third insulating layer PLN away from the substrate.

[0154] For example, the second metal layer SD2 includes the first sub-potential line VGH-1, the first potential signal line VGL, the reset signal line PCX, the fourth sub-clock line CK-2, the second sub-clock line CB-2, and the second sub-potential line VGH-2.

[0155] This disclosure also provides a display substrate 2000, which includes the gate driving circuit unit 1000 described in any one of the above descriptions, or the display substrate 2000 includes the gate driving circuit unit 1000 in combination of any of the above descriptions.

[0156] For example, the display substrate 2000 may be manufactured using any of the above-described methods for manufacturing a display substrate 2000.

[0157] For example, the display substrate 2000 may include at least one cascaded circuit, each cascaded circuit including a plurality of gate driving circuit units cascaded in sequence, wherein the gate driving circuit unit is any one of the gate driving circuit units 1000 described above, or the gate driving circuit unit is any combination of the gate driving circuit units 1000 described above.

[0158] In some embodiments, as shown in Figures 9 and 11, the coupling sub-circuit 200 includes a coupling capacitor C2; the first output sub-circuit 300 includes a first output transistor T5 and a second output transistor T4; the display substrate 2000 includes the substrate and a gate metal layer Ge1 disposed on one side of the substrate, the gate metal layer Ge1 includes the second plate C2b of the coupling capacitor C2 and the gate of the first output transistor T5, and the second plate C2b of the coupling capacitor C2 and the gate of the first output transistor T5 are directly connected.

[0159] For example, as shown in Figures 9 and 11, the gate metal layer Ge1 includes the second plate C2b of the coupling capacitor C2 and the gate of the first output transistor T5. The second plate C2b of the coupling capacitor C2 and the gate of the first output transistor T5 are directly connected, which can reduce wiring and reduce the area occupied by the gate drive circuit unit 1000 or the gate drive circuit in the layout or display panel, which is helpful for narrow bezel design.

[0160] In some embodiments, as shown in Figures 9 and 11, the first output sub-circuit 300 further includes a first capacitor C1, and the coupling capacitor C2 and the first capacitor C1 are arranged along a first direction Y; the gate metal layer Ge1 further includes a second plate C1b of the first capacitor C1 and the gate of the second output transistor T4, and the second plate C1b of the first capacitor C1 and the gate of the second output transistor T4 are directly connected; in the second direction X, the first output transistor T5 and the second output transistor T4 are located on the same side of the coupling capacitor C2 and the first capacitor C1, and the first direction Y intersects the second direction X.

[0161] For example, Figure 9 illustrates that the first direction Y is perpendicular to the second direction X, but is not limited thereto.

[0162] For example, the display panel may include a display area and a border area, the display area and the border area having a dividing line, the first direction Y may be parallel to the extension direction of the dividing line between the display area and the border area, and the second direction X may be perpendicular to the extension direction of the dividing line between the display area and the border area, but is not limited thereto.

[0163] For example, as shown in Figures 9 and 11, the coupling capacitor C2 and the first capacitor C1 are arranged along the first direction Y. In the second direction X, the first output transistor T5 and the second output transistor T4 are located on the same side of the coupling capacitor C2 and the first capacitor C1. This can reduce the length of the gate drive circuit unit 1000 in the first direction Y, which helps to provide a larger number of the gate drive circuit units 1000 in the first direction Y in a high-resolution display panel.

[0164] In some embodiments, as shown in Figures 9 and 10, the second input sub-circuit 400 includes a second input transistor T2 and a third input transistor T3; the display substrate 2000 further includes a first sustaining sub-circuit 500 and a first reset sub-circuit 600, the first sustaining sub-circuit 500 including a first sustaining transistor T6; the first reset sub-circuit 600 including a first reset transistor T7; the display substrate 2000 includes a semiconductor layer PO located between the substrate and the gate metal layer Ge1, the semiconductor layer PO including a continuous first semiconductor pattern PO1, and the active portion P2 of the second input transistor T2, the active portion P6 of the first sustaining transistor T6, and the active portion P7 of the first reset transistor T7 are formed by the first semiconductor pattern PO1.

[0165] For example, as shown in Figures 9 and 10, the active portion P2 of the second input transistor T2, the active portion P6 of the first sustaining transistor T6, and the active portion P7 of the first reset transistor T7 are all formed by the first semiconductor pattern PO1. The first semiconductor pattern PO1 is a continuous structure, which can reduce the number of vias and electrodes connecting the second input transistor T2, the first sustaining transistor T6, and the first reset transistor T7, and can reduce the number of wire changes. This is beneficial for reducing the area occupied by the gate drive circuit unit 1000 or the gate drive circuit in the layout or display panel, and helps with narrow bezel design.

[0166] For example, as shown in Figures 9 and 10, the active pattern / active portion P1 of the first input transistor T1 is configured as a U-shaped structure, and the active pattern / active portion P1 of the first input transistor T1 includes a first input sub-active portion P1-1 and a second sub-active portion P1-2, so that the first input transistor T1 is formed as a dual-gate structure.

[0167] For example, as shown in Figures 9 to 11, the active pattern / active portion P1 of the first input transistor T1 is configured as a U-shaped structure, the first input transistor T1 is formed as a dual-gate structure, and the gate G1 of the first input transistor T1 includes a first input sub-gate G11 and a second input sub-gate G12.

[0168] For example, as shown in Figures 9 to 11, the first input sub-gate G11 of the first input transistor T1, the second input sub-gate G12 of the first input transistor T1, and the gate G3 of the third input transistor T3 are a continuous structure.

[0169] For example, as shown in Figures 9 to 11, the active pattern / active part P1 of the first input transistor T1 is set to a U-shaped structure, so that the first input transistor T1 forms a dual-gate structure, and the first input transistor T1 occupies a smaller layout space while better realizing the connection between the gate G1 of the first input transistor T1 and the second clock signal line (third sub-clock line CK-1) and the gate G3 of the third input transistor T3.

[0170] For example, as shown in Figures 9 and 10, the active portion P1 of the first input transistor T1, the active portion P8 of the fourth input transistor T8, and the active portion P3 of the third input transistor T3 included in the semiconductor layer PO are spaced apart from each other, and the active portions of these thin-film transistors are spaced apart from the active portions of other thin-film transistors in Figure 1 or Figure 9.

[0171] In some embodiments, as shown in Figures 9 and 10, the first semiconductor pattern PO1 includes a first sub-semiconductor pattern PO1-1, a second sub-semiconductor pattern PO1-2, and a third sub-semiconductor pattern PO1-3. The second sub-semiconductor pattern PO1-2 is connected between the first sub-semiconductor pattern PO1-1 and the third sub-semiconductor pattern PO1-3. The extension direction of the first sub-semiconductor pattern PO1-1 is parallel to the extension direction of the third sub-semiconductor pattern PO1-3, and the extension direction of the second sub-semiconductor pattern PO1-2 is non-linear. The first sub-semiconductor pattern PO1-1 includes the active portion P2 of the second input transistor T2, the second sub-semiconductor pattern PO1-2 includes the active portion P6 of the first holding transistor T6, and the third sub-semiconductor pattern PO1-3 includes the active portion P7 of the first reset transistor T7.

[0172] For example, as shown in Figures 9 and 10, the extension direction of the first sub-semiconductor pattern PO1-1 and the extension direction of the third sub-semiconductor pattern PO1-3 are both parallel to the first direction Y.

[0173] It should be noted that, in other embodiments, the extension direction of the first sub-semiconductor pattern PO1-1 and the extension direction of the third sub-semiconductor pattern PO1-3 may also be other directions besides the first direction Y.

[0174] For example, as shown in Figures 9 and 10, the extension direction of the first sub-semiconductor pattern PO1-1 is parallel to the extension direction of the third sub-semiconductor pattern PO1-3, and the extension direction of the second sub-semiconductor pattern PO1-2 is non-linear. This can reduce the distance between the first sub-semiconductor pattern PO1-1 and the third sub-semiconductor pattern PO1-3, thereby helping to reduce the area occupied by the gate drive circuit unit 1000 or the gate drive circuit in the layout or display panel, which is conducive to narrow bezel design.

[0175] In some embodiments, as shown in Figures 9 and 10, the channel extension direction of the active portion P2 of the second input transistor T2, the channel extension direction of the active portion P6 of the first sustaining transistor T6, and the channel extension direction of the active portion P7 of the first reset transistor T7 are parallel to each other.

[0176] For example, as shown in Figures 9 and 10, the channel extension direction of the active portion P2 of the second input transistor T2, the channel extension direction of the active portion P6 of the first sustaining transistor T6, and the channel extension direction of the active portion P7 of the first reset transistor T7 are all parallel to the first direction Y.

[0177] It should be noted that, in other embodiments, the channel extension direction of the active portion P2 of the second input transistor T2, the channel extension direction of the active portion P6 of the first sustaining transistor T6, and the channel extension direction of the active portion P7 of the first reset transistor T7 may also be other directions besides the first direction Y.

[0178] For example, as shown in Figures 9 and 10, the channel extension direction of the active portion P2 of the second input transistor T2, the channel extension direction of the active portion P6 of the first sustaining transistor T6, and the channel extension direction of the active portion P7 of the first reset transistor T7 are parallel to each other. This helps to control the uniformity and carrier migration performance of the channels of the active portion P2 of the second input transistor T2, the active portion P6 of the first sustaining transistor T6, and the active portion P7 of the first reset transistor T7 during the manufacturing process of the display substrate 2000 or the display panel.

[0179] In some embodiments, as shown in Figures 9 and 10, the first input sub-circuit 100 includes a first input transistor T1; the first input sub-circuit 100 also includes a fourth input transistor T8; in the second direction X, the first input transistor T1, the fourth input transistor T8, the second input transistor T2, the third input transistor T3, the first sustaining transistor T6, and the first reset transistor T7 are all located on one side of the coupling capacitor C2 and the first capacitor C1, and the first output transistor T5 and the second output transistor T4 are both located on the other side of the coupling capacitor C2 and the first capacitor C1.

[0180] For example, as shown in Figures 9 and 10, the first input transistor T1, the fourth input transistor T8, the second input transistor T2, the third input transistor T3, the first holding transistor T6, and the first reset transistor T7 are located on both sides of the coupling capacitor C2 and the first capacitor C1 in the second direction X, along with the first output transistor T5 and the second output transistor T4. The coupling capacitor C2 and the first capacitor C1 are arranged along the first direction Y, which helps to reduce the area occupied by the gate drive circuit unit 1000 or the gate drive circuit in the layout or display panel, and is conducive to narrow bezel design.

[0181] In some embodiments, as shown in Figures 9, 14 and 16, the display substrate 2000 includes a first clock signal line CB, a second clock signal line CK, a first potential signal line VGL, a second potential signal line VGH and a reset signal line PCX;

[0182] The first clock signal line CB includes a first sub-clock line CB-1 and a second sub-clock line CB-2, and the signals in the first sub-clock line CB-1 and the second sub-clock line CB-2 are the same;

[0183] The second clock signal line CK includes a third sub-clock line CK-1 and a fourth sub-clock line CK-2, and the signals in the third sub-clock line CK-1 and the fourth sub-clock line CK-2 are the same;

[0184] The second potential signal line VGH includes a first sub-potential line VGH-1 and a second sub-potential line VGH-2, and the signals in the first sub-potential line VGH-1 and the second sub-potential line VGH-2 are the same;

[0185] The first sub-clock line CB-1, the third sub-clock line CK-1, the first sub-potential line VGH-1, the first potential signal line VGL, the reset signal line PCX, the fourth sub-clock line CK-2, the second sub-clock line CB-2, and the second sub-potential line VGH-2 are arranged sequentially along the second direction X;

[0186] The orthographic projection of the coupling capacitor C2 on the substrate at least partially overlaps with the orthographic projection of the reset signal line PCX on the substrate, the orthographic projection of the fourth sub-clock line CK-2 on the substrate, and the orthographic projection of the second sub-clock line CB-2 on the substrate.

[0187] For example, as shown in Figures 9, 14, and 16, the first clock signal line CB includes a first sub-clock line CB-1 and a second sub-clock line CB-2, with the same signal in the first sub-clock line CB-1 and the second sub-clock line CB-2; the second clock signal line CK includes a third sub-clock line CK-1 and a fourth sub-clock line CK-2, with the same signal in the third sub-clock line CK-1 and the fourth sub-clock line CK-2; the second potential signal line VGH includes a first sub-potential line VGH-1 and a second sub-potential line VGH-2, with the same signal in the first sub-potential line VGH-1 and the second sub-potential line VGH-2. In these signal lines, two sub-traces are arranged close together, allowing structures electrically connected to these sub-traces (gate, source, and drain, etc.) to be electrically connected close together. This reduces the number of vias and electrodes required for connection, reduces the number of line changes, and eliminates the need for long connection electrodes. This helps reduce the area occupied by the gate drive circuit unit 1000 or the gate drive circuit in the layout or display panel, contributing to narrow bezel designs. At the same time, some sub-routes are directly connected to the structure electrically connected to them, and the orthographic projection of some sub-routes on the substrate at least partially overlaps with the orthographic projection of the structure electrically connected to them on the substrate, so that it is not necessary to set long connection electrodes, and it is also beneficial to reduce the area occupied by the gate drive circuit unit 1000 or the gate drive circuit in the layout or display panel.

[0188] For example, as shown in Figures 9, 14, and 16, the inventors minimized the layout area of ​​the gate drive circuit unit 1000 while considering its electrical performance. The first input transistor T1, the fourth input transistor T8, the second input transistor T2, the third input transistor T3, the first sustaining transistor T6, the first reset transistor T7, the first output transistor T5, and the second output transistor T4 were arranged as shown in Figure 9. To accommodate the arrangement of these thin-film transistors, the first sub-clock line CB-1, the third sub-clock line CK-1, the first sub-potential line VGH-1, the first potential signal line VGL, the reset signal line PCX, the fourth sub-clock line CK-2, the second sub-clock line CB-2, and the second sub-potential line VGH-2 were arranged sequentially along the second direction X.

[0189] For example, in some embodiments, the display substrate includes a first clock signal bus connected between a pad area (the pad area is electrically connected to a driver chip or circuit board, etc.) and a setting area of ​​the gate drive circuit unit. The first clock signal bus connects (leads out) a first sub-clock line CB-1 and a second sub-clock line CB-2, and the first clock signal bus provides the same electrical signal in the first sub-clock line CB-1 and the second sub-clock line CB-2.

[0190] For example, in some embodiments, the display substrate includes a second clock signal bus connected between a pad area (which is electrically connected to a driver chip or circuit board, etc.) and the setting area of ​​the gate drive circuit unit. The second clock signal bus connects (leads out) the third sub-clock line CK-1 and the fourth sub-clock line CK-2, and the second clock signal bus provides the same electrical signal in the third sub-clock line CK-1 and the fourth sub-clock line CK-2.

[0191] For example, in some embodiments, the display substrate includes a second potential signal bus connected between a pad area (which is electrically connected to a driver chip or circuit board, etc.) and the setting area of ​​the gate drive circuit unit. The second potential signal bus connects (leads out) the first sub-potential line VGH-1 and the second sub-potential line VGH-2, and the second potential signal bus provides the same electrical signal in the first sub-potential line VGH-1 and the second sub-potential line VGH-2.

[0192] For example, as shown in Figures 1, 9, 14 and 16, the first input sub-circuit 100 includes a first input transistor T1, the gate of the first input transistor T1 is electrically connected to the second clock signal line CK (the third sub-clock line CK-1), the first electrode of the first input transistor T1 is electrically connected to the first signal line STV, and the second electrode of the first input transistor T1 is electrically connected to the first node N1.

[0193] For example, as shown in Figures 1, 9, 14 and 16, the coupling sub-circuit 200 includes a coupling capacitor C2, the first plate C2a of which is electrically connected to the first node N1, and the second plate C2b of which is electrically connected to the third node N3.

[0194] For example, as shown in Figures 1, 9, 14 and 16, the first output sub-circuit 300 includes a first output transistor T5 and a second output transistor T4. The gate of the first output transistor T5 is electrically connected to the third node N3, the first electrode of the first output transistor T5 is electrically connected to the first clock signal line CB (the second sub-clock line CB-2), the second electrode of the first output transistor T5 is electrically connected to the first output terminal OUT1, the gate of the second output transistor T4 is electrically connected to the second node N2, the second electrode of the second output transistor T4 is electrically connected to the second potential signal line VGH (the second sub-potential line VGH-2), and the first electrode of the second output transistor T4 is electrically connected to the first output terminal OUT1.

[0195] For example, as shown in Figures 1, 9, 14, and 16, the second input sub-circuit 400 includes a second input transistor T2 and a third input transistor T3. The gate of the second input transistor T2 is electrically connected to the first node N1, the first electrode of the second input transistor T2 is electrically connected to the second potential signal line VGH (the first sub-potential line VGH-1), and the second electrode of the second input transistor T2 is electrically connected to the second node N2. The gate of the third input transistor T3 is electrically connected to the second clock signal line CK (the third sub-clock line CK-1), the first electrode of the third input transistor T3 is electrically connected to the first potential signal line VGL, and the second electrode of the third input transistor T3 is electrically connected to the second node N2.

[0196] For example, as shown in Figures 1, 9, 14 and 16, the first sustaining sub-circuit 500 includes a first sustaining transistor T6, the gate of the first sustaining transistor T6 is electrically connected to the second node N2, the first electrode of the first sustaining transistor T6 is electrically connected to the third node N3, and the second electrode of the first sustaining transistor T6 is electrically connected to the second potential signal line VGH (the first sub-potential line VGH-1).

[0197] For example, as shown in Figures 1, 9, 14 and 16, the first reset sub-circuit 600 includes a first reset transistor T7, the gate of the first reset transistor T7 is the first reset control terminal 601K, the first electrode of the first reset transistor T7 is electrically connected to the reset signal line PCX, and the second electrode of the first reset transistor T7 is electrically connected to the third node N3.

[0198] For example, as shown in Figures 1, 9, 14, and 16, the first input sub-circuit 100 further includes a fourth input transistor T8, the gate of which is electrically connected to the first potential signal line VGL, the first terminal of which is electrically connected to the second terminal of the first input transistor T1, and the second terminal of which is electrically connected to the first plate C2a of the coupling capacitor C2; or / and, the first output sub-circuit 300 further includes a first capacitor C1, the first plate C1a of which is electrically connected to the gate of the second output transistor T4, and the second plate C1b of which is electrically connected to the second terminal of the second output transistor T4.

[0199] In some embodiments, as shown in Figures 9, 14 and 16, the orthographic projection of the first reset transistor T7 on the substrate at least partially overlaps with the orthographic projection of the reset signal line PCX on the substrate;

[0200] The orthographic projection of the first capacitor C1 on the substrate, the orthographic projection of the fourth sub-clock line CK-2 on the substrate, and the orthographic projection of the second sub-clock line CB-2 on the substrate all at least partially overlap;

[0201] In the first direction Y, the first reset transistor T7 and the first capacitor C1 are located on the same side of the coupling capacitor C2;

[0202] The orthogonal projection of the second sub-potential line (VGH-2) onto the substrate is located on the side of the first output transistor T5 and the second output transistor T4 away from the coupling capacitor C2.

[0203] For example, as shown in Figures 9, 14, and 16, the orthographic projection of the first capacitor C1 on the substrate at least partially overlaps with the orthographic projections of the fourth sub-clock line CK-2 and the second sub-clock line CB-2 on the substrate; the orthographic projection of the first reset transistor T7 on the substrate at least partially overlaps with the orthographic projection of the reset signal line PCX on the substrate. With this arrangement, the area occupied by the gate drive circuit unit 1000 or the gate drive circuit in the layout or display panel can be reduced.

[0204] This disclosure also provides a display device, which includes a gate driving circuit, the gate driving circuit including the gate driving circuit unit 1000 described in any one of the above, or the gate driving circuit including the gate driving circuit unit 1000 in combination of any of the above.

[0205] This disclosure also provides a display device, a display substrate 2000, the display substrate 2000 including a gate driving circuit, the gate driving circuit including the gate driving circuit unit 1000 as described in any one of the above, or the gate driving circuit including the gate driving circuit unit 1000 in combination of any of the above.

[0206] For example, the display device may be a smartphone, laptop, television, tablet computer or other display, and some embodiments of this disclosure are not specifically limited.

[0207] This disclosure provides a gate driving circuit unit, a gate driving circuit, a method for manufacturing a display substrate, a display substrate, and a display device. A first input sub-circuit is configured to control the voltage of a first node based on a signal from a first input terminal; a second input sub-circuit is configured to control the voltage of a second node based on a signal from a second input terminal; a coupling sub-circuit is at least configured to control the voltage of a third node based on the voltage of the first node; and a first output sub-circuit is configured to transmit a signal from a third input terminal or a signal from a fourth input terminal to a first output terminal based on the voltages applied to the second and third nodes. By configuring the coupling sub-circuit, the voltage of the third node can be controlled according to the voltage of the first node, allowing the electrical signal of the third node to better match display or driving requirements. For example, the high potential of the third node can be made higher, or the low potential of the third node can be made lower. This allows the thin-film transistor in the first output sub-circuit electrically connected to the third node to be fully turned on or fully turned off. Thus, when the thin-film transistor electrically connected to the third node is turned on, the signal at the third input terminal can be better transmitted to the first output terminal. Conversely, when the thin-film transistor electrically connected to the third node is turned off, the signal at the third input terminal can be better isolated from the first output terminal, thereby improving the stability of the output signal of the gate drive circuit unit.

[0208] In some embodiments of this disclosure, the gate driving circuit unit includes the first input sub-circuit, the second input sub-circuit, the coupling sub-circuit, and the first output sub-circuit. The gate driving circuit unit has a simple structure, and the number of thin-film transistors and capacitors included in the gate driving circuit unit is small. The area occupied by the gate driving circuit unit in the layout or display panel is small. That is, the gate driving circuit unit has the effect of simple structure, which is beneficial to the narrow bezel of the display panel.

[0209] In some embodiments of this disclosure, the provided gate drive circuit unit has the advantages of simple structure and stable output of electrical signals that meet display requirements.

[0210] It should be noted that the technical features in the above embodiments / examples can be combined with each other to obtain new shift registers.

[0211] It should be noted that the descriptions of each embodiment in the above embodiments have different focuses. For parts that are not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0212] The above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit it. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this disclosure.

[0213] Although preferred embodiments have been described in this specification, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this specification.

[0214] Obviously, those skilled in the art can make various modifications and variations to this specification without departing from its spirit and scope. Therefore, if such modifications and variations fall within the scope of the claims and their equivalents, this specification is also intended to include such modifications and variations.

Claims

1. A gate drive circuit unit, comprising: a first input sub-circuit configured to control a voltage of a first node according to a signal of a first input terminal; a second input sub-circuit configured to control a voltage of a second node according to a signal of a second input terminal; a coupling sub-circuit configured to control a voltage of a third node according to the voltage of the first node; a first output sub-circuit configured to transmit a signal of a third input terminal or a signal of a fourth input terminal to a first output terminal according to the voltages applied to the second node and the third node.

2. The gate drive circuit unit according to claim 1, wherein at least one of the following conditions is met: the first input terminal receives a signal of a first signal line; the second input terminal receives a signal of a first potential signal line; the third input terminal receives a signal of a first clock signal line, and the fourth input terminal receives a signal of a second potential signal line. 3.The gate drive circuit unit of claim 2, further comprising a first maintaining sub-circuit and a first resetting sub-circuit; the first input sub-circuit is electrically connected with the first signal line, a second clock signal line and the first node, and is configured to input the signal of the first signal line to the first node under the control of the signal of the second clock signal line; the second input sub-circuit is electrically connected with the first potential signal line, the second clock signal line, the second node, the first node and the second potential signal line, and is configured to transmit the signal of the second potential signal line or the first potential signal line to the second node under the control of the signals of the first node and the second clock signal line; the first maintaining sub-circuit is electrically connected with the second node, the third node and the second potential signal line, and is configured to transmit the signal of the second potential signal line to the third node under the control of the potential of the second node; the first output sub-circuit is electrically connected with the first clock signal line, the third node, the second node and the second potential signal line, and is configured to transmit the signal of the first clock signal line or the second potential signal line to the first output terminal under the control of the potentials of the third node and the second node; the first resetting sub-circuit is electrically connected with a first resetting control terminal, a resetting signal line and one end of the coupling sub-circuit, and is configured to transmit the potential of the resetting signal line to one end of the coupling sub-circuit under the control of the signal of the first resetting control terminal.

4. The gate drive circuit unit according to claim 3, wherein the first input sub-circuit comprises a first input transistor, a gate of the first input transistor is electrically connected with the second clock signal line, a first pole of the first input transistor is electrically connected with the first signal line, and a second pole of the first input transistor is electrically connected with the first node; the coupling sub-circuit comprises a coupling capacitor, a first pole plate of the coupling capacitor is electrically connected with the first node, and a second pole plate of the coupling capacitor is electrically connected with the third node. The first output sub-circuit comprises a first output transistor and a second output transistor, a gate of the first output transistor is electrically connected with the third node, a first pole of the first output transistor is electrically connected with the first clock signal line, and a second pole of the first output transistor is electrically connected with the first output end, a gate of the second output transistor is electrically connected with the second node, a second pole of the second output transistor is electrically connected with the second potential signal line, and a first pole of the second output transistor is electrically connected with the first output end.

5. The gate drive circuit unit according to claim 4, wherein The second input sub-circuit comprises a second input transistor and a third input transistor, a gate of the second input transistor is electrically connected with the first node, a first pole of the second input transistor is electrically connected with the second potential signal line, and a second pole of the second input transistor is electrically connected with the second node, a gate of the third input transistor is electrically connected with the second clock signal line, a first pole of the third input transistor is electrically connected with the first potential signal line, and a second pole of the third input transistor is electrically connected with the second node. The first maintaining sub-circuit comprises a first maintaining transistor, a gate of the first maintaining transistor is electrically connected with the second node, a first pole of the first maintaining transistor is electrically connected with the third node, and a second pole of the first maintaining transistor is electrically connected with the second potential signal line.

6. The gate drive circuit unit according to claim 5, wherein The first reset sub-circuit comprises a first reset transistor, a gate of the first reset transistor is the first reset control end, a first pole of the first reset transistor is electrically connected with the reset signal line, and a second pole of the first reset transistor is electrically connected with the third node.

7. The gate drive circuit unit according to claim 6, wherein The first reset control end is electrically connected with any one of the first signal line, the first node of the gate drive circuit unit of the upper stage in the cascade, the third node of the gate drive circuit unit of the upper stage in the cascade, and the first pole plate of the coupling capacitor of the upper stage in the cascade.

8. The gate drive circuit unit according to claim 7, wherein The first input sub-circuit further comprises a fourth input transistor, a gate of the fourth input transistor is electrically connected with the first potential signal line, a first pole of the fourth input transistor is electrically connected with the second pole of the first input transistor, and a second pole of the fourth input transistor is electrically connected with the first pole plate of the coupling capacitor; or / and The first output sub-circuit further comprises a first capacitor, a first pole plate of the first capacitor is electrically connected with the gate of the second output transistor, and a second pole plate of the first capacitor is electrically connected with the second pole of the second output transistor.

9. The gate drive circuit unit according to any one of claims 3 to 8, wherein The first signal line is a start signal line, before a first low potential signal is output from the first signal line, a signal of the reset signal line is a high potential signal, and the high potential of the reset signal line is greater than the high potential of the first signal line; Starting from the first low potential signal output from the first signal line, the signal of the reset signal line is a low potential signal.

10. The gate drive circuit unit according to any one of claims 3 to 8, wherein The gate drive circuit unit further comprises at least one of a second reset sub-circuit and a second maintaining sub-circuit; The first reset sub-circuit is electrically connected to one end of the coupling sub-circuit and the third node, and the second reset sub-circuit is electrically connected to the second reset control end, the reset signal line and one end of the coupling sub-circuit and the first node, and is configured to transmit the potential of the reset signal line to one end of the coupling sub-circuit and the first node under the signal control of the second reset control end. The second maintaining sub-circuit is electrically connected to the second node, the second potential signal line and one end of the coupling sub-circuit and the first node, and is configured to transmit the signal of the second potential signal line to one end of the coupling sub-circuit and the first node under the potential control of the second node.

11. The gate drive circuit unit of claim 10, wherein, The second reset sub-circuit comprises a second reset transistor, a gate of the second reset transistor is the second reset control end, a first pole of the second reset transistor is electrically connected to the reset signal line, and a second pole of the second reset transistor is electrically connected to one end of the coupling sub-circuit and the first node. The second maintaining sub-circuit comprises a second maintaining transistor, a gate of the second maintaining transistor is electrically connected to the second node, a first pole of the second maintaining transistor is electrically connected to one end of the coupling sub-circuit and the first node, and a second pole of the second maintaining transistor is electrically connected to the second potential signal line.

12. The gate drive circuit unit according to claim 1, further comprising: a second output sub-circuit configured to transmit the signal of the fifth input end or the sixth input end to the second output end according to the voltage applied to the second node and the third node.

13. The gate drive circuit unit of claim 12, wherein, The fifth input end receives the signal of the first clock signal line, and the sixth input end receives the signal of the second potential signal line.

14. The gate drive circuit unit of claim 13, wherein, The first clock signal line received by the fifth input end is different from the first clock signal line received by the third input end. The high potential in the first clock signal line received by the fifth input end is greater than the high potential in the first clock signal line received by the third input end. The low potential in the first clock signal line received by the fifth input end is less than the low potential in the first clock signal line received by the third input end. The second potential signal line received by the sixth input end is different from the second potential signal line received by the fourth input end. The potential in the second potential signal line received by the sixth input end is greater than the potential in the second potential signal line received by the fourth input end.

15. The gate drive circuit unit according to any one of claims 2 to 8, wherein, The signal in the first signal line is a start signal, the signal in the first potential signal line is a low potential, the signal in the second potential signal line is a high potential, and all the thin film transistors in the gate drive circuit unit are P-type.

16. A gate drive circuit comprising at least one cascade circuit, each cascade circuit comprising a plurality of gate drive circuit units connected in cascade, the gate drive circuit unit being the gate drive circuit unit according to any one of claims 1 to 15.

17. A manufacturing method of a display substrate, comprising: providing a substrate; manufacturing at least one cascade circuit on the substrate, each cascade circuit comprising a plurality of gate drive circuit units connected in series, the gate drive circuit unit being the gate drive circuit unit according to any one of claims 1 to 15.

18. A display substrate, comprising the gate drive circuit unit according to claim 1.

19. The display substrate of claim 18, wherein, the coupling sub-circuit comprises a coupling capacitor; the first output sub-circuit comprises a first output transistor and a second output transistor; the display substrate comprises a substrate and a gate metal layer disposed on one side of the substrate, the gate metal layer comprising a second plate of the coupling capacitor and a gate of the first output transistor, and the second plate of the coupling capacitor and the gate of the first output transistor are directly connected. 20.The display substrate of claim 19, wherein, the first output sub-circuit further comprises a first capacitor, and the coupling capacitor and the first capacitor are arranged along a first direction; the gate metal layer further comprises a second plate of the first capacitor and a gate of the second output transistor, and the second plate of the first capacitor and the gate of the second output transistor are directly connected; in a second direction, the first output transistor and the second output transistor are located on the same side of the coupling capacitor and the first capacitor, and the first direction intersects the second direction. 21.The display substrate of claim 20, wherein, the second input sub-circuit comprises a second input transistor and a third input transistor; the display substrate further comprises a first sustain sub-circuit and a first reset sub-circuit, the first sustain sub-circuit comprising a first sustain transistor, and the first reset sub-circuit comprising a first reset transistor; the display substrate comprises a semiconductor layer between the substrate and the gate metal layer, the semiconductor layer comprising a continuous first semiconductor pattern, and an active part of the second input transistor, an active part of the first sustain transistor, and an active part of the first reset transistor are formed by the first semiconductor pattern.

22. The display substrate of claim 21, wherein, the first semiconductor pattern comprises a first sub-semiconductor pattern, a second sub-semiconductor pattern, and a third sub-semiconductor pattern, the second sub-semiconductor pattern is connected between the first sub-semiconductor pattern and the third sub-semiconductor pattern, an extension direction of the first sub-semiconductor pattern is parallel to an extension direction of the third sub-semiconductor pattern, and the second sub-semiconductor pattern extends in a non-straight line; the first sub-semiconductor pattern comprises the active part of the second input transistor, the second sub-semiconductor pattern comprises the active part of the first sustain transistor, and the third sub-semiconductor pattern comprises the active part of the first reset transistor.

23. The display substrate of claim 22, wherein, channel extension directions of the active part of the second input transistor, the active part of the first sustain transistor, and the active part of the first reset transistor are parallel to each other.

24. The display substrate of claim 21, wherein, the first input sub-circuit comprises a first input transistor; the first input sub-circuit further comprises a fourth input transistor; In the second direction, the first input transistor, the fourth input transistor, the second input transistor, the third input transistor, the first sustain transistor and the first reset transistor are located on one side of the coupling capacitor and the first capacitor, and the first output transistor and the second output transistor are located on the other side of the coupling capacitor and the first capacitor. 25.The display substrate of claim 24, wherein, The display substrate comprises a first clock signal line, a second clock signal line, a first potential signal line, a second potential signal line and a reset signal line. The first clock signal line comprises a first sub-clock line and a second sub-clock line, and the signals in the first sub-clock line and the second sub-clock line are the same. The second clock signal line comprises a third sub-clock line and a fourth sub-clock line, and the signals in the third sub-clock line and the fourth sub-clock line are the same. The second potential signal line comprises a first sub-potential line and a second sub-potential line, and the signals in the first sub-potential line and the second sub-potential line are the same. The first sub-clock line, the third sub-clock line, the first sub-potential line, the first potential signal line, the reset signal line, the fourth sub-clock line, the second sub-clock line and the second sub-potential line are arranged in the second direction in sequence. The first reset transistor is at least partially overlapped with the reset signal line in the projection on the substrate. 26.The display substrate of claim 25, wherein, The first capacitor is at least partially overlapped with the fourth sub-clock line and the second sub-clock line in the projection on the substrate. In the first direction, the first reset transistor and the first capacitor are located on the same side of the coupling capacitor. The second sub-potential line is located on the side of the first output transistor and the second output transistor away from the coupling capacitor in the projection on the substrate.

27. A display device comprising a gate driving circuit, the gate driving circuit comprising the gate driving circuit unit according to any one of claims 1 to 15. ​

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