Display substrate and display

Abstract

A display substrate and a display. The display substrate has a display area and a non-display area, and the display substrate comprises: a substrate, and a driving structure layer group and a light-emitting structure layer which are sequentially stacked on the substrate. Multiple pixel driving circuits located in the display area are provided on the driving structure layer group, multiple light-emitting devices located in the display area are provided on the light-emitting structure layer, and the light-emitting devices are electrically connected to the pixel driving circuits. The driving structure layer group comprises a number K of driving structure layers which are sequentially stacked along the substrate. At least one driving structure layer comprises at least one pixel driving circuit. An orthographic projection of at least one light-emitting device onto the substrate at least partially overlaps with an orthographic projection of at least one pixel driving circuit in at least two driving structure layers among the K driving structure layers onto the substrate, and the orthographic projection of the at least one pixel driving circuit located in the at least one driving structure layer at least partially overlaps with the orthographic projection of at least two light-emitting devices onto the substrate.

Description

Display substrate and display device

[0001] This application claims priority to Chinese Patent Application No. 202410705272.5, filed on May 31, 2024, entitled “Display Substrate and Display Device”, the contents of which are to be understood as incorporated herein by reference. Technical Field

[0002] This disclosure relates to, but is not limited to, the field of display technology, and specifically to a display substrate and a display device. Background Technology

[0003] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in this application. This overview is not intended to limit the scope of the claims.

[0005] In a first aspect, this disclosure provides a display substrate having a display area and a non-display area. The display substrate includes: a substrate and a driving structure layer group and a light-emitting structure layer sequentially stacked on the substrate. The driving structure layer group is provided with a plurality of pixel driving circuits located in the display area. The light-emitting structure layer is provided with a plurality of light-emitting devices located in the display area. The light-emitting devices are electrically connected to the pixel driving circuits.

[0006] The driving structure layer group includes: K driving structure layers stacked sequentially along the substrate, at least one driving structure layer including: at least one pixel driving circuit, the orthographic projection of at least one light-emitting device on the substrate at least partially overlaps with the orthographic projection of at least one pixel driving circuit on the substrate in at least two of the K driving structure layers, and the orthographic projection of at least one pixel driving circuit in at least one of the at least one driving structure layer on the substrate at least partially overlaps with the orthographic projection of at least two light-emitting devices on the substrate, wherein K is a positive integer greater than or equal to 2.

[0007] In an exemplary embodiment, at least one driving structure layer includes: an M-row N-column pixel driving circuit;

[0008] The orthographic projections of the pixel driving circuits in the m-th row and n-th column of at least two of the K driving structure layers onto the substrate at least partially overlap, 1≤m≤M, 1≤n≤N.

[0009] In an exemplary embodiment, the light-emitting device includes: a first electrode electrically connected to a pixel driving circuit; the first electrodes of the plurality of light-emitting devices are arranged in an array; the pixel driving circuits connected to the first electrodes of adjacent light-emitting devices in the same row are located in the same driving circuit layer; and the pixel driving circuits connected to the first electrodes of adjacent light-emitting devices in the same column are located in different driving circuit layers.

[0010] In an exemplary embodiment, at least one driving structure layer includes: a plurality of anode connection electrodes, the plurality of anode connection electrodes corresponding one-to-one with a plurality of pixel driving circuits in at least one driving structure layer, the pixel driving circuit including: at least one transistor, the transistor including: an active layer, a gate electrode, a first electrode and a second electrode.

[0011] At least one anode connection electrode is electrically connected to a corresponding pixel driving circuit and a light-emitting device connected to the corresponding pixel driving circuit. The film layer in which the anode connection electrode is located is on the side of the film layer in which at least one of the active layer, gate electrode, first electrode, and second electrode of at least one transistor is located, away from the substrate.

[0012] In an exemplary embodiment, the orthogonal projections of the anode connection electrodes corresponding to the pixel driving circuits in the m-th row and n-th column of two adjacent driving structure layers in the K driving structure layers on the substrate at least partially overlap.

[0013] In an exemplary embodiment, at least one anode connection electrode extends at least partially along a first direction.

[0014] In an exemplary embodiment, the drive structure layer group further includes: a plurality of vias exposing the anode connection electrode;

[0015] The orthographic projection of the via of at least one anode connection electrode in the r-th driving structure layer on the substrate does not overlap with the orthographic projection of the structure in at least two driving structure layers from the (r+1)-th to the K-th driving structure layers on the substrate, and 1≤r≤K-1.

[0016] The structure in the at least one driving structure layer includes: a pixel driving circuit in the driving structure layer and a signal line connected to the pixel driving circuit.

[0017] In an exemplary embodiment, vias exposing the anode connection electrodes corresponding to the pixel driving circuits in the m-th row and n-th column of two adjacent driving structure layers in the K driving structure layers are arranged along the first direction.

[0018] In an exemplary embodiment, the orthographic projection of at least one anode connection electrode on the substrate and the orthographic projection of the first signal line connected to the pixel driving circuit corresponding to the anode connection electrode on the substrate do not overlap.

[0019] The first signal line includes a first power line and a data signal line.

[0020] In an exemplary embodiment, the drive structure layer group further includes: K-1 protective layers;

[0021] The r-th protection layer is located between the r-th driving structure layer and the (r+1)-th driving structure layer, where 1 ≤ r ≤ K-1.

[0022] In an exemplary embodiment, the at least one driving circuit layer includes: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer; the pixel driving circuit includes: at least one transistor and a capacitor; the capacitor includes: two plates; and the signal lines connected to the pixel driving circuit include: a scan signal line, a reset signal line, a first initial signal line, a second initial signal line, a light emission signal line, a data signal line, and a first power supply line.

[0023] The semiconductor layer includes at least: an active layer of at least one transistor;

[0024] The first conductive layer includes at least: a gate electrode of at least one transistor, one of the plates of a capacitor, a scan signal line, a reset signal line, and a light emission signal line;

[0025] The second conductive layer includes at least: the other electrode of the capacitor, a first initial signal line, and a second initial signal line;

[0026] The third conductive layer includes at least: a first and second electrode of at least one transistor, a data signal line, and a first power supply line;

[0027] The fourth conductive layer includes at least an anode connection electrode.

[0028] In an exemplary embodiment, the at least one driving circuit layer further includes: a first flattening layer and a second flattening layer;

[0029] The first planarization layer is located between the third conductive layer and the fourth conductive layer, and the second planarization layer is located on the side of the fourth conductive layer away from the substrate.

[0030] In an exemplary embodiment, it further includes: K source driver chip groups located in the non-display area, wherein at least one source driver chip group includes: at least one source driver chip;

[0031] The data signal lines connecting the k-th source driver chip group and the pixel driver circuit in the k-th driver structure layer are electrically connected, where 1≤k≤K.

[0032] In an exemplary embodiment, the data signal line connected to at least one column of pixel driving circuits in the r-th driving structure layer is electrically connected to the data signal line connected to at least one column of pixel driving circuits in the (r+1)-th driving structure layer, where 1≤r≤K-1.

[0033] In an exemplary embodiment, it further includes: K gate driving circuits located in the non-display area;

[0034] The kth gate driving circuit is located on the kth driving structure layer, and the kth gate driving circuit is electrically connected to the scan signal line connected to the pixel driving circuit in the kth driving structure layer; the K gate driving circuits are stacked sequentially along the substrate direction, 1≤k≤K.

[0035] In an exemplary embodiment, at least one gate driving circuit is electrically connected to an initial signal line, and different gate driving circuits are connected to different initial signal lines.

[0036] In an exemplary embodiment, it further includes: K first light-emitting power lines located in the non-display area, and the signal lines connected to at least one pixel driving circuit include: the first power lines;

[0037] The kth first light-emitting power line is located on the kth driving structure layer, and the kth first light-emitting power line is electrically connected to the first power line connected to the pixel driving circuit located in the kth driving structure layer.

[0038] At least two of the K first light-emitting power lines are electrically connected to each other.

[0039] In an exemplary embodiment, it further includes: K first driving power lines and K second driving power lines located in the non-display area.

[0040] The kth first driving power line is located on the kth driving structure layer and is electrically connected to the kth gate drive; the kth second driving power line is located on the kth driving structure layer and is electrically connected to the kth gate drive.

[0041] The first drive power lines in at least two of the K drive structure layers are electrically connected to each other.

[0042] The second drive power lines in at least two of the K drive structure layers are electrically connected to each other.

[0043] Secondly, this disclosure also provides a display device, including: the aforementioned display substrate.

[0044] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood.

[0045] Overview of the attached figures

[0046] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0047] Figure 1 is a schematic diagram of a display device;

[0048] Figure 2 is a schematic diagram of a planar structure of a display substrate;

[0049] Figure 3 is a schematic diagram of a planar structure of a display substrate;

[0050] Figure 4 is a schematic diagram of a planar structure of a display substrate;

[0051] Figure 5 is a schematic diagram of the equivalent circuit of a pixel driving circuit;

[0052] Figure 6 is a timing diagram of a pixel driving circuit.

[0053] Figure 7A is a schematic diagram of the structure of the display substrate provided in an embodiment of this disclosure;

[0054] Figure 7B is a schematic diagram of the driving structure layer group;

[0055] Figure 8 is a top view of the display substrate provided in an embodiment of this disclosure;

[0056] Figure 9A is a top view of the first driving structure layer in Figure 8;

[0057] Figure 9B is a top view of the first driving structure layer in Figure 8;

[0058] Figure 10 is a top view of the second driving structure layer in Figure 8;

[0059] Figure 11 is a schematic diagram of part of the film layers in Figure 8;

[0060] Figure 12 is another schematic diagram of the display substrate structure;

[0061] Figure 13 is a schematic diagram after the semiconductor layer pattern of the first driving structure layer is formed;

[0062] Figure 14 is a schematic diagram after the first conductive layer pattern of the first driving structure layer is formed;

[0063] Figure 15 is a schematic diagram after the second conductive layer pattern of the first driving structure layer is formed;

[0064] Figure 16 is a schematic diagram after the formation of the third conductive layer pattern of the first driving structure layer;

[0065] Figure 17 is a schematic diagram of the fourth conductive layer pattern after the formation of the first driving structure layer;

[0066] Figure 18 is a schematic diagram after the semiconductor layer pattern of the second driving structure layer is formed;

[0067] Figure 19 is a schematic diagram after the first conductive layer pattern of the second driving structure layer is formed;

[0068] Figure 20 is a schematic diagram after the second conductive layer pattern of the second driving structure layer is formed;

[0069] Figure 21 is a schematic diagram after the formation of the third conductive layer pattern of the second driving structure layer;

[0070] Figure 22 is a schematic diagram after the fourth conductive layer pattern of the second driving structure layer is formed;

[0071] Figure 23 is a schematic diagram after the second planarization layer pattern of the second driving structure layer is formed;

[0072] Figure 24 is a schematic diagram after the formation of the anodic conductive layer in the light-emitting structure layer.

[0073] Detailed Explanation

[0074] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and components have been omitted. The accompanying drawings of the embodiments of this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in general design.

[0075] The scale of the figures in this disclosure can be used as a reference in actual manufacturing processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The figures described in this disclosure are only schematic diagrams of the structure, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0076] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0077] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0078] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0079] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0080] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0081] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures through the same patterning process, and their materials may be the same or different. For example, the precursors forming multiple structures in a same-layer arrangement may be made of the same material, while the final materials may be the same or different.

[0082] Figure 1 is a schematic diagram of a display device. As shown in Figure 1, the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is connected to the data driver, the scan driver, and the light-emitting driver. The data driver is connected to multiple data signal lines (D1 to Dn), the scan driver is connected to multiple scan signal lines (S1 to Sm), and the light-emitting driver is connected to multiple light-emitting signal lines (E1 to Eo). The pixel array may include multiple sub-pixels Pxij, where i and j can be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting device connected to the circuit unit. The circuit unit may include a pixel driving circuit, which may be connected to the scan signal lines, the light-emitting signal lines, and the data signal lines, respectively.

[0083] In an exemplary embodiment, the timing controller can provide grayscale values ​​and control signals of specifications suitable for the data driver to the data driver, clock signals, scan start signals, etc. of specifications suitable for the scan driver to the scan driver, and clock signals, transmit stop signals, etc. of specifications suitable for the light-emitting driver to the light-emitting driver. The data driver can use the grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to data signal lines D1, D2, D3, ..., Dn. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn on a pixel-row basis, where n can be a natural number. The scan driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ..., Sm by receiving clock signals, scan start signals, etc. from the timing controller. For example, the scan driver can sequentially provide scan signals with on-level pulses to scan signal lines S1 to Sm. For example, a scan driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals, provided in the form of on-level pulses, to the next stage circuit under the control of a clock signal, where m can be a natural number. An LED driver can generate transmit signals to be provided to LED signal lines E1, E2, E3, ..., Eo by receiving clock signals, transmit stop signals, etc., from a timing controller. For example, an LED driver can sequentially provide transmit signals with off-level pulses to LED signal lines E1 to Eo. For example, an LED driver can be configured as a shift register and can generate transmit signals by sequentially transmitting transmit stop signals, provided in the form of off-level pulses, to the next stage circuit under the control of a clock signal, where o can be a natural number.

[0084] Figure 2 is a schematic diagram of a planar structure of a display substrate (one type), Figure 3 is a schematic diagram of a planar structure of a display substrate (two types), and Figure 4 is a schematic diagram of a planar structure of a display substrate (three types). As shown in Figures 2 to 4, the display substrate may include multiple pixel units P arranged in a matrix. At least one of the multiple pixel units P includes a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light. Each of the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 includes a pixel driving circuit and a light-emitting device. The pixel driving circuits in the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are respectively connected to a scan signal line, a data signal line, and a light-emitting signal line. The pixel driving circuits are configured to receive the data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting device. The light-emitting devices in the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are respectively connected to the pixel driving circuit of their respective sub-pixels. The light-emitting devices are configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of their respective sub-pixels.

[0085] In an exemplary embodiment, the first sub-pixel P1 can be a red sub-pixel (R) emitting red light, the second sub-pixel P2 can be a blue sub-pixel (B) emitting blue light, and the third sub-pixel P3 can be a green sub-pixel (G) emitting green light. In an exemplary embodiment, the shape of the sub-pixels can be rectangular, rhomboid, pentagonal, or hexagonal, and the three sub-pixels can be arranged horizontally side by side, vertically side by side, or in a triangular arrangement; this disclosure does not limit the specific arrangement.

[0086] In an exemplary embodiment, a pixel unit may include three sub-pixels. The three sub-pixels may be arranged horizontally side by side, vertically side by side, or in a triangular arrangement, etc., and this disclosure does not limit the arrangement. Figure 2 illustrates the arrangement of three sub-pixels horizontally side by side as an example, and Figure 3 illustrates the arrangement of three sub-pixels in a triangular arrangement as an example.

[0087] In other exemplary embodiments, a pixel unit may include four sub-pixels, which may be arranged in a horizontal, vertical, or square manner, etc., and this disclosure does not limit the specific arrangement. Figure 4 illustrates an example of four sub-pixels arranged in a square manner.

[0088] In an exemplary embodiment, the light-emitting device may include a first electrode (anode), an organic light-emitting layer, and a second electrode (cathode) stacked together. Exemplarily, the anode of the light-emitting device is electrically connected to a pixel driving circuit, and the cathode of the light-emitting device is electrically connected to a second power line.

[0089] In an exemplary embodiment, the light-emitting device L may include a current-driven device, such as a current-driven light-emitting diode, like a micro light-emitting diode (Micro LED), a mini light-emitting diode (Mini LED), an organic light-emitting diode (OLED), or a quantum light-emitting diode (QLED). The typical size (e.g., length) of a Micro LED can be less than 100 μm, for example, 10 μm to 50 μm. The typical size (e.g., length) of a Mini LED can be approximately 100 μm to 300 μm, for example, 120 μm to 260 μm.

[0090] In an exemplary embodiment, the organic light-emitting layer may include stacked hole injection layer (HIL), hole transport layer (HTL), electron block layer (EBL), emitting layer (EML), hole block layer (HBL), electron transport layer (ETL), and electron injection layer (EIL). In this exemplary embodiment, the hole injection layers of all sub-pixels may be a common layer connected together, the electron injection layers of all sub-pixels may be a common layer connected together, the hole transport layers of all sub-pixels may be a common layer connected together, the hole block layers of all sub-pixels may be a common layer connected together, and the emitting layers of adjacent sub-pixels may have a small overlap or may be isolated. Similarly, the electron block layers of adjacent sub-pixels may have a small overlap or may be isolated.

[0091] In an exemplary embodiment, the first power line VDD continuously provides a high-level signal, and the signal of the first power line VDD is a DC signal.

[0092] In an exemplary embodiment, the second power line VSS continuously provides a low-level signal, and the signal of the second power line VSS is a DC signal.

[0093] Figure 5 is an equivalent circuit diagram of a pixel driving circuit. In an exemplary embodiment, the pixel driving circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. As shown in Figure 5, the pixel driving circuit can include seven transistors (first transistor T1 to seventh transistor T7) and one capacitor C. The pixel driving circuit can be connected to the data signal line Data, the scan signal line Gate, the reset signal line Reset, the light emission signal line EM, the first initial signal line INIT1, the second initial signal line INIT2, and the first power supply line VDD, respectively.

[0094] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, and a third node N3. The first node N1 is connected to the first terminal of the third transistor T3, the second terminal of the fourth transistor T4, and the second terminal of the fifth transistor T5, respectively. The second node N2 is connected to the second terminal of the first transistor T1, the first terminal of the second transistor T2, the control terminal of the third transistor T3, and the second terminal of the capacitor C, respectively. The third node N3 is connected to the second terminal of the second transistor T2, the second terminal of the third transistor T3, and the first terminal of the sixth transistor T6, respectively.

[0095] In an exemplary embodiment, the first end of capacitor C is connected to the first power line VDD, and the second end of capacitor C is connected to the second node N2, that is, the second end of capacitor C is connected to the control electrode of the third transistor T3.

[0096] The control electrode of the first transistor T1 is connected to the reset signal line Reset, the first electrode of the first transistor T1 is connected to the first initial signal line INIT1, and the second electrode of the first transistor T1 is connected to the second node N2. When the on-level scan signal is applied to the reset signal line Reset, the first transistor T1 transmits the initialization voltage of the first initial signal line INIT1 to the control electrode of the third transistor T3, so as to initialize the charge of the control electrode of the third transistor T3.

[0097] The control electrode of the second transistor T2 is connected to the scan signal line Gate, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3. When a conduction-level scan signal is applied to the scan signal line Gate, the second transistor T2 connects the control electrode of the third transistor T3 to its second electrode.

[0098] The control electrode of the third transistor T3 is connected to the second node N2, meaning the control electrode of the third transistor T3 is connected to the second terminal of capacitor C. The first electrode of the third transistor T3 is connected to the first node N1, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 can be called the driving transistor. The third transistor T3 determines the magnitude of the driving current flowing between the first power line VDD and the second power line VSS based on the potential difference between its control electrode and its first electrode.

[0099] The control electrode of the fourth transistor T4 is connected to the scan signal line Gate, the first electrode of the fourth transistor T4 is connected to the data signal line Data, and the second electrode of the fourth transistor T4 is connected to the first node N1. The fourth transistor T4 can be called a switching transistor, scan transistor, etc. When a conduction-level scan signal is applied to the scan signal line Gate, the fourth transistor T4 causes the data voltage of the data signal line Data to be input to the pixel driving circuit.

[0100] The control electrode of the fifth transistor T5 is connected to the light-emitting signal line EM, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1. The control electrode of the sixth transistor T6 is connected to the light-emitting signal line EM, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light-emitting device. The fifth transistor T5 and the sixth transistor T6 can be referred to as light-emitting transistors. When a conduction-level light-emitting signal is applied to the light-emitting signal line EM, the fifth transistor T5 and the sixth transistor T6 form a driving current path between the first power supply line VDD and the second power supply line VSS, causing the light-emitting device to emit light.

[0101] The control electrode of the seventh transistor T7 is connected to the reset signal line Reset, the first electrode of the seventh transistor T7 is connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light-emitting device. When the on-level scan signal is applied to the reset signal line Reset, the seventh transistor T7 transmits the initialization voltage of the second initial signal line INIT2 to the first electrode of the light-emitting device, so as to initialize or release the accumulated charge in the first electrode of the light-emitting device.

[0102] In an exemplary embodiment, the second electrode of the light-emitting device is connected to the second power line VSS, where the signal of the second power line VSS is a low-level signal, and the signal of the first power line VDD is a continuously high-level signal. The scan signal line Gate is the scan signal line Gate in the pixel driving circuit of this display row, and the reset signal line Reset is the scan signal line Gate in the pixel driving circuit of the previous display row. That is, the reset signal line Reset of this display row and the scan signal line Gate in the pixel driving circuit of the previous display row are the same signal line, which can reduce the number of signal lines on the display panel and achieve a narrow bezel on the display panel.

[0103] Based on their characteristics, transistors can be classified into N-type transistors and P-type transistors. When a transistor is P-type, its turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage), and its turn-off voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage). When a transistor is N-type, its turn-on voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage), and its turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage).

[0104] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 can be either P-type transistors or N-type transistors. Using the same type of transistor in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first transistor T1 to the seventh transistor T7 may include both P-type and N-type transistors.

[0105] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 can be a low-temperature polycrystalline silicon (LTPS) thin-film transistor, or an oxide thin-film transistor, or a combination of both. The active layer of the LTPS is made of low-temperature polycrystalline silicon, while the active layer of the oxide thin-film transistor is made of oxide. LTPS transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. Integrating LTPS and oxide thin-film transistors onto a single display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate leverages the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0106] In an exemplary embodiment, the scan signal line Gate, the reset signal line Reset, the light emission signal line EM, the first initial signal line INIT1, and the second initial signal line INIT2 can extend in the horizontal direction, while the second power line VSS, the first power line VDD, and the data signal line Data can extend in the vertical direction.

[0107] In an exemplary embodiment, the first initial signal line INIT1 and the second initial signal line INIT2 can be the same signal line.

[0108] Figure 6 is a timing diagram of a pixel driving circuit. The following describes an exemplary embodiment of this disclosure through the operation of the pixel driving circuit illustrated in Figure 5. The pixel driving circuit in Figure 5 includes 7 transistors (first transistor T1 to seventh transistor T7) and 1 capacitor C. All 7 transistors are P-type transistors.

[0109] In an exemplary embodiment, the operation of the pixel driving circuit may include:

[0110] The first stage, A1, is called the reset stage. The Reset signal is low, while the Gate and EM signals are high. When the Reset signal is low, transistors T1 and T7 are turned on. The INIT1 signal is sent to node N2 to initialize (reset) capacitor C, clearing its charge. The INIT2 signal is sent to the anode of the light-emitting device to initialize (reset) its first electrode, clearing its charge. When the Gate and EM signals are high, transistors T2, T4, T5, and T6 are turned off. During this stage, the light-emitting device does not emit light.

[0111] The second stage, A2, is called the data writing stage or threshold compensation stage. During this stage, the Gate signal is low, while the Reset and EM signals are high. The Data signal outputs a data voltage. Because the second terminal of capacitor C is low, the third transistor T3 is turned on. The low Gate signal turns on the second and fourth transistors T4. The turn on T2 and T4 allows the data voltage output from the Data signal to be supplied to the second node N2 via the first node N1, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2. The difference between the data voltage output from the Data signal and the threshold voltage of the third transistor T3 is charged into capacitor C. The voltage at the second terminal of capacitor C (second node N2) is Vd - |Vth|, where Vd is the data voltage output from the Data signal and Vth is the threshold voltage of the third transistor T3. The Reset signal is high, turning off the first transistor T1 and the seventh transistor T7. The signal on the luminous signal line EM is a high-level signal, which disconnects the fifth transistor T5 and the sixth transistor T6.

[0112] The third stage, A3, is called the light-emitting stage. During this stage, the light-emitting signal line EM is at a low level, while the scan signal line Gate and the reset signal line Reset are at a high level. The low-level signal on the light-emitting signal line EM turns on the fifth transistor T5 and the sixth transistor T6. The power supply voltage output from the first power supply line VDD then provides a driving voltage to the first electrode of the light-emitting device through the turned-on fifth transistor T5, third transistor T3, and sixth transistor T6, driving the light-emitting device to emit light.

[0113] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and its first electrode. Since the voltage at the second node N2 is Vd - |Vth|, the driving current of the third transistor T3 is: I = K*(Vgs - Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*(Vdd-Vd) 2

[0114] Where I is the driving current flowing through the third transistor T3, which is the driving current driving the OLED, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage output by the data signal line Data, and Vdd is the power supply voltage output by the first power supply line VDD.

[0115] As can be seen from the derivation of the above current formula, during the light-emitting stage, the driving current of the third transistor T3 is no longer affected by the threshold voltage of the third transistor T3, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the driving current. This ensures uniform display brightness of the display product and improves the overall display effect of the display product.

[0116] The low density of light-emitting devices in display devices makes it difficult to achieve a high PPI.

[0117] Figure 7A is a schematic diagram of the structure of the display substrate provided in the embodiment of this disclosure, Figure 7B is a schematic diagram of the structure of the driving structure layer group, and Figure 8 is a top view of the display substrate provided in the embodiment of this disclosure. As shown in Figures 7A, 7B, and 8, the display substrate provided in the embodiment of this disclosure has a display area and a non-display area. The display substrate includes: a substrate 10 and a driving structure layer group 20 and a light-emitting structure layer 30 sequentially stacked on the substrate. The driving structure layer group 20 is provided with a plurality of pixel driving circuits located in the display area, and the light-emitting structure layer 30 is provided with a plurality of light-emitting devices located in the display area. The light-emitting devices are electrically connected to the pixel driving circuits. The driving structure layer group 20 includes: K driving structure layers 21 sequentially stacked along the substrate 10. At least one driving structure layer includes: at least one pixel driving circuit. The orthographic projection of at least one light-emitting device on the substrate at least partially overlaps with the orthographic projection of at least one pixel driving circuit in at least two of the K driving structure layers on the substrate. The orthographic projection of at least one pixel driving circuit in at least one driving structure layer on the substrate at least partially overlaps with the orthographic projection of at least two light-emitting devices on the substrate. Wherein, K is a positive integer greater than or equal to 2. Figures 7A, 7B, and 8 are illustrated using K=2 as an example.

[0118] In an exemplary embodiment, this disclosure provides a driving structure layer group comprising K driving structure layers stacked sequentially along a substrate, wherein the orthographic projection of at least one light-emitting device on the substrate at least partially overlaps with the orthographic projection of at least one pixel driving circuit in at least two of the K driving structure layers on the substrate, and the orthographic projection of at least one pixel driving circuit in at least one driving structure layer on the substrate at least partially overlaps with the orthographic projection of at least two light-emitting devices on the substrate. This allows multiple pixel driving circuits to be stacked along the substrate, and the orthographic projection of the light-emitting device connected to the multiple pixel driving circuits on the substrate can at least partially overlap with the orthographic projection of the multiple pixel driving circuits on the substrate, increasing the density of light-emitting devices and thereby achieving a high PPI for the display device.

[0119] In an exemplary embodiment, the substrate may be a flexible substrate or a rigid substrate. The rigid substrate may include, but is not limited to, one or more of glass and quartz, and the flexible substrate may include, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers.

[0120] In exemplary embodiments, the pixel driving circuits located in different driving structure layers may have the same structure or different structures. Having the same structure for the pixel driving circuits in different driving structure layers can reduce the number of photomasks used in the display substrate, thus lowering manufacturing costs. Figure 8 illustrates an example where the pixel driving circuits in different driving structure layers have the same structure.

[0121] In an exemplary embodiment, as shown in FIG8, at least one driving structure layer may include: an M-row N-column pixel driving circuit; the orthographic projections of the m-th row and n-th column pixel driving circuits in at least two of the K driving structure layers on the substrate at least partially overlap, 1≤m≤M, 1≤n≤N.

[0122] In an exemplary embodiment, as shown in FIG8, the light-emitting device includes: a first electrode 31 electrically connected to a pixel driving circuit; an array of first electrodes 31 of multiple light-emitting devices are arranged; the pixel driving circuits connected to the first electrodes 31 of adjacent light-emitting devices in the same row are located in the same driving circuit layer; and the pixel driving circuits connected to the first electrodes of adjacent light-emitting devices in the same column are located in different driving circuit layers.

[0123] In an exemplary embodiment, at least one driving structure layer includes: a plurality of anode connection electrodes AL, the plurality of anode connection electrodes AL corresponding one-to-one with a plurality of pixel driving circuits in at least one driving structure layer, and the pixel driving circuit includes: at least one transistor, the transistor including: an active layer, a gate electrode, a first electrode and a second electrode.

[0124] In an exemplary embodiment, at least one anode connection electrode AL is electrically connected to a corresponding pixel driving circuit and a light-emitting device connected to the corresponding pixel driving circuit. The film layer in which the anode connection electrode AL is located is on the side of the film layer in which at least one of the active layer, gate electrode, first electrode, and second electrode of at least one transistor is located, away from the substrate.

[0125] Figure 9A is a top view of the first driving structure layer in Figure 8, Figure 9B is a top view of the first driving structure layer in Figure 8, and Figure 10 is a top view of the second driving structure layer in Figure 8. AL1 in Figures 9A and 9B refers to the anode connection electrode in the first driving structure layer, and AL2 in Figure 10 refers to the anode connection electrode in the second driving structure layer.

[0126] Figure 11 is a schematic diagram of a portion of the film layers in Figure 8. Figure 11 includes the film layer containing the anode connection electrode in the first driving structure layer and the film layer containing the anode connection electrode in the second driving structure layer. In an exemplary embodiment, as shown in Figure 11, the orthographic projections of the anode connection electrodes corresponding to the pixel driving circuits in the m-th row and n-th column of two adjacent driving structure layers in the K driving structure layers on the substrate at least partially overlap.

[0127] In an exemplary embodiment, as shown in Figures 9A to 11, at least one anode connection electrode AL extends at least partially along a first direction D1.

[0128] In an exemplary embodiment, at least one anode connection electrode AL located in the first drive structure layer may extend at least partially along the second direction D2.

[0129] In an exemplary embodiment, as shown in FIG8, the drive structure layer group further includes: a plurality of vias V exposing the anode connection electrode.

[0130] In an exemplary embodiment, as shown in Figures 8 to 11, the orthographic projection of the via exposing at least one anode connection electrode in the r-th driving structure layer onto the substrate does not overlap with the orthographic projection of the structures in at least two of the driving structure layers from the (r+1)-th to the K-th driving structure layers onto the substrate, where 1 ≤ r ≤ K-1. The structure in at least one driving structure layer includes a pixel driving circuit within the driving structure layer and signal lines connected to the pixel driving circuit. In Figures 9 and 11, V1 refers to the via exposing the anode connection electrode in the first driving structure layer, and in Figures 10 and 11, V2 refers to the via exposing the anode connection electrode in the second driving structure layer.

[0131] In an exemplary embodiment, the absence of an overlap between the orthographic projection of the via exposing at least one anode connection electrode in the r-th driving structure layer and the orthographic projection of the structures in at least two of the driving structure layers from the (r+1)-th to the K-th driving structure layers on the substrate ensures that the first electrode of the light-emitting device located in the light-emitting structure layer can be accurately and reliably electrically connected to the anode connection electrode through the via exposing at least one anode connection electrode in the r-th driving structure layer.

[0132] In an exemplary embodiment, as shown in FIG11, the anode connection electrode is electrically connected to the film layer where the second electrode of the sixth transistor (which is also the second electrode of the seventh transistor) is located through the via V.

[0133] In an exemplary embodiment, the anode connection electrode can serve as the second electrode of the sixth transistor (which is also the second electrode of the seventh transistor) and be electrically connected to the film layer containing the active layers of the sixth and seventh transistors through a via. This disclosure does not limit this in any way.

[0134] In an exemplary embodiment, the anode connection electrodes in the first to the (K-1)th driving structure layers may be at least partially disposed in the blank area, wherein the blank area refers to the area where there is no overlap between any structure of the pixel driving circuit and the orthogonal projection of the signal connected to the pixel driving circuit on the substrate.

[0135] In an exemplary embodiment, the anode connection electrode in the Kth driving structure layer can be located at any position, and it is not necessary to set blank areas in some regions.

[0136] In an exemplary embodiment, as shown in Figures 9A, 9B and 10, the signal lines connected to the pixel driving circuit may include: a first initial signal line INIT1, a second initial signal line INIT2, an EM light emission signal line, a Gate scan signal line, a Reset reset signal line, a Data signal line Data, and a first power supply line VDD.

[0137] In an exemplary embodiment, as shown in FIG11, vias exposing the anode connection electrodes corresponding to the pixel driving circuits in the m-th row and n-th column of two adjacent driving structure layers in the K driving structure layers are arranged along the first direction D1. In an exemplary embodiment, at least one via V1 and at least one via V2 are arranged along the first direction D1, wherein the orthographic projection of the pixel driving circuit connected to the anode connection electrode exposed by the via V1 arranged along the first direction D1 on the substrate at least partially overlaps with the orthographic projection of the pixel driving circuit connected to the anode connection electrode exposed by the via V2 on the substrate.

[0138] In an exemplary embodiment, as shown in Figures 9 and 10, the orthographic projection of at least one anode connection electrode AL on the substrate and the orthographic projection of the first signal line connected to the pixel driving circuit corresponding to the anode connection electrode AL on the substrate do not overlap; the first signal line includes: a first power line VDD and a data signal line Data.

[0139] In an exemplary embodiment, FIG12 is another structural schematic diagram of the display substrate, wherein the driving structure layer group 20 further includes: K-1 protective layers 22. The r-th protective layer is located between the r-th driving structure layer and the (r+1)-th driving structure layer, and 1≤r≤K-1.

[0140] In an exemplary embodiment, the protective layer may be a single-layer structure or a multi-layer structure.

[0141] In an exemplary embodiment, the protective layer may be made of inorganic materials, such as silicon oxide and silicon nitride, or it may be made of organic materials. This disclosure does not limit the application of these materials.

[0142] In an exemplary embodiment, at least one driving circuit layer includes: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer; the pixel driving circuit includes: at least one transistor and a capacitor; the capacitor includes: two plates; and the signal lines connected to the pixel driving circuit include: a scan signal line, a reset signal line, a first initial signal line, a second initial signal line, a light emission signal line, a data signal line, and a first power supply line.

[0143] The semiconductor layer includes at least: an active layer for at least one transistor;

[0144] The first conductive layer includes at least: the gate electrode of at least one transistor, one of the plates of a capacitor, a scan signal line, a reset signal line, and a light emission signal line;

[0145] The second conductive layer includes at least: the other electrode of the capacitor, a first initial signal line, and a second initial signal line;

[0146] The third conductive layer includes at least: a first and second electrode of at least one transistor, a data signal line, and a first power supply line;

[0147] The fourth conductive layer includes at least an anode connection electrode.

[0148] In the exemplary embodiments, the film structure of different driving circuit layers may be the same or different, and this disclosure does not limit this in any way.

[0149] In an exemplary embodiment, at least one driving circuit layer further includes: a first planarization layer and a second planarization layer; wherein the first planarization layer is located between the third conductive layer and the fourth conductive layer, and the second planarization layer is located on the side of the fourth conductive layer away from the substrate.

[0150] In an exemplary embodiment, at least a portion of the via exposing the anode connection electrode is formed on the second planar layer.

[0151] In an exemplary embodiment, the sides of the display area may include a first side, a second side, a third side, and a fourth side, wherein the first side and the second side are arranged opposite to each other, and the third side and the fourth side are arranged opposite to each other.

[0152] In an exemplary embodiment, the display substrate may further include: K source driver chip groups located in the non-display area, at least one source driver chip group including: at least one source driver chip; the kth source driver chip group is electrically connected to the data signal line connected to the pixel driver circuit in the kth driving structure layer, 1≤k≤K. Exemplarily, the first source driver chip group is electrically connected to the data signal line connected to the pixel driver circuit in the first driving structure layer, the second source driver chip group is electrically connected to the data signal line connected to the pixel driver circuit in the second driving structure layer, and so on.

[0153] In an exemplary embodiment, the display substrate may further include: a source driver chipset, wherein the data signal lines connected to at least one column of pixel driver circuits in at least one driving structure layer are electrically connected to the source driver chipset, and the data signal lines connected to at least one column of pixel driver circuits in the r-th driving structure layer are electrically connected to the data signal lines connected to at least one column of pixel driver circuits in the (r+1)-th driving structure layer, where 1≤r≤K-1.

[0154] In an exemplary embodiment, the data signal lines connected to at least one column of pixel driving circuits in the r-th driving structure layer can be electrically connected to the data signal lines connected to at least one column of pixel driving circuits in the (r+1)-th driving structure layer through vias located in the non-display area. For example, the vias can be located on the third or fourth side of the display area.

[0155] In an exemplary embodiment, the source driver chipset may be located on the third or fourth side of the display area.

[0156] In an exemplary embodiment, the display substrate further includes K gate driving circuits located in the non-display area. The kth gate driving circuit is located on the kth driving structure layer, and the kth gate driving circuit is electrically connected to the scan signal line connected to the pixel driving circuit in the kth driving structure layer; the K gate driving circuits are stacked sequentially along the substrate direction, 1≤k≤K. Exemplarily, the first gate driving circuit is electrically connected to the scan signal line connected to the pixel driving circuit in the first driving structure layer, and the second group of gate driving circuits is electrically connected to the scan signal line connected to the pixel driving circuit in the second driving structure layer.

[0157] In an exemplary embodiment, the gate driving circuit may be located on at least one of the first and second sides of the display area.

[0158] In an exemplary embodiment, at least one gate driving circuit is electrically connected to an initial signal line, and different gate driving circuits are connected to different initial signal lines.

[0159] In an exemplary embodiment, the output signals of at least two of the K gate driving circuits are at the same time or may be different, that is, the timing of the pixel driving circuits in different driving structure layers may be controlled together or individually.

[0160] In an exemplary embodiment, the display substrate further includes: K first light-emitting power lines located in the non-display area; the signal lines connected to at least one pixel driving circuit include: first power lines; the kth first light-emitting power line is located on the kth driving structure layer, and the kth first light-emitting power line is electrically connected to the first power line connected to the pixel driving circuit located in the kth driving structure layer. At least two of the K first light-emitting power lines are electrically connected to each other.

[0161] In an exemplary embodiment, the display substrate further includes a second light-emitting power line located in the non-display area, and the second electrode of at least one light-emitting device is electrically connected to the second light-emitting power line through a via.

[0162] In an exemplary embodiment, the second light-emitting power line may be located in at least one driving structure layer.

[0163] In an exemplary embodiment, the display substrate further includes: K first driving power lines and K second driving power lines located in the non-display area, wherein the kth first driving power line is located on the kth driving structure layer and is electrically connected to the kth gate drive, and the kth second driving power line is located on the kth driving structure layer and is electrically connected to the kth gate drive.

[0164] In an exemplary embodiment, the first drive power lines in at least two of the K drive structure layers are electrically connected to each other. For example, the first drive power lines in at least two of the K drive structure layers can be electrically connected to each other through vias.

[0165] In an exemplary embodiment, the second drive power lines in at least two of the K drive structure layers are electrically connected to each other. For example, the second drive power lines in at least two of the K drive structure layers can be electrically connected to each other through vias.

[0166] In an exemplary embodiment, the light-emitting structure layer may include an anode, a pixel definition layer, an organic light-emitting layer, and a cathode. The anode is connected to the pixel driving circuit via a via, the organic light-emitting layer is connected to the anode, and the cathode is connected to the organic light-emitting layer. The organic light-emitting layer emits light of the corresponding color under the driving of the anode and cathode.

[0167] In an exemplary embodiment, the display substrate may further include isolation pillars.

[0168] In an exemplary embodiment, the organic light-emitting layer may include an emissive layer (EML) and one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, one or more of the hole injection layer, hole transport layer, electron blocking layer, hole blocking layer, electron transport layer, and electron injection layer of all sub-pixels may be common layers connected together, and the emissive layers of adjacent sub-pixels may have a small amount of overlap or may be isolated.

[0169] In an exemplary embodiment, the display substrate may also include other film layers, such as an encapsulation structure layer and a touch structure layer, which are not limited herein.

[0170] In an exemplary embodiment, the encapsulation structure layer may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first and third encapsulation layers may be made of inorganic materials, while the second encapsulation layer may be made of organic materials. The second encapsulation layer is disposed between the first and third encapsulation layers to ensure that external moisture cannot enter the light-emitting structure layer.

[0171] In an exemplary embodiment, the touch structure layer may include a first touch insulating layer disposed on the encapsulation structure layer, a first touch metal layer disposed on the first touch insulating layer, a second touch insulating layer covering the first touch metal layer, a second touch metal layer disposed on the second touch insulating layer, and a touch protective layer covering the second touch metal layer. The first touch metal layer may include a plurality of bridging electrodes, and the second touch metal layer may include a plurality of first touch electrodes and second touch electrodes. The first touch electrodes or the second touch electrodes may be connected to the bridging electrodes through vias.

[0172] In exemplary embodiments, the display substrate of this disclosure can be applied to display devices with pixel driving circuits, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED) or quantum dot light-emitting diode display (QDLED), etc., and this disclosure does not limit it.

[0173] The substrate fabrication process is illustrated below with reference to Figure 8, which illustrates an example of a driving structure layer group comprising two driving structure layers with identical film structures. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, processes include organic material coating, mask exposure, and development. Deposition can be performed using sputtering, evaporation, or chemical vapor deposition; coating can be performed using spraying, spin coating, or inkjet printing; and etching can be performed using dry etching or wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film made of a material on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0174] (1) Forming a semiconductor layer pattern for the first driving structure layer. In an exemplary embodiment, forming a semiconductor layer pattern for the first driving structure layer may include: sequentially depositing a first insulating film and a first semiconductor film on a substrate, patterning the first semiconductor film through a patterning process to form a first insulating layer covering the substrate and a semiconductor layer pattern located on the first insulating layer of the first driving structure layer, as shown in FIG13, FIG13 being a schematic diagram after forming the semiconductor layer pattern of the first driving structure layer.

[0175] In an exemplary embodiment, as shown in FIG13, the semiconductor layer pattern of the first driving structure layer may include at least the active pattern T11-1 of the first transistor to the active pattern T71-1 of the seventh transistor of at least one pixel driving circuit located in the first driving structure layer.

[0176] (2) Forming a first conductive layer pattern of the first driving structure layer. In an exemplary embodiment, forming a first conductive layer pattern of the first driving structure layer may include: depositing a second insulating film and a first conductive film sequentially on a substrate on which the aforementioned pattern is formed, patterning the first conductive film by a patterning process to form a second insulating layer covering the semiconductor layer pattern of the first driving structure layer and a first conductive layer pattern disposed on the second insulating layer, as shown in FIG14, FIG14 being a schematic diagram after forming the first conductive layer pattern of the first driving structure layer.

[0177] In an exemplary embodiment, as shown in FIG14, the first conductive layer pattern of the first driving structure layer may include at least: the gate electrode T21-1 to the gate electrode T72-1 of the first transistor of at least one pixel driving circuit located in the first driving structure layer and the first plate C1-1 of the capacitor, as well as the reset signal line Reset-1, the light emission signal line EM-1 and the scan signal line Gate-1 connected to at least one pixel driving circuit located in the first driving structure layer.

[0178] (3) Forming a second conductive layer pattern of the first driving structure layer includes: depositing a third insulating film and a second conductive film sequentially on the substrate on which the aforementioned pattern is formed, and patterning the third insulating film and the second conductive film through a patterning process to form a third insulating layer of the first driving structure layer and a second conductive layer pattern located on the third insulating layer, as shown in Figure 15. Figure 15 is a schematic diagram after the formation of the second conductive layer pattern of the first driving structure layer.

[0179] In an exemplary embodiment, as shown in FIG15, the second conductive layer pattern may include at least: the second plate C2-1 of the capacitor of at least one pixel driving circuit located in the first driving structure layer, and the first initial signal line INIT1-1 and the second initial signal line INIT2-1 connected to at least one pixel driving circuit in the first driving structure layer.

[0180] (4) Forming a third conductive layer pattern of the first driving structure layer includes: depositing a fourth insulating film on the substrate on which the aforementioned pattern is formed, patterning the fourth insulating film through a patterning process to form a fourth insulating layer including multiple vias, depositing a third conductive film on the fourth insulating layer, and patterning the third conductive film through a patterning process to form a third conductive layer pattern located on the fourth insulating layer of the first driving structure layer, as shown in Figure 16. Figure 16 is a schematic diagram after forming the third conductive layer pattern of the first driving structure layer.

[0181] In an exemplary embodiment, as shown in FIG16, the third conductive layer pattern of the first driving structure layer may include at least: the first pole T13-1 and the second pole T14-1 of the first transistor of at least one pixel driving circuit located in the first driving structure layer to the first pole T73-1 and the second pole T74-2 of the seventh transistor.

[0182] (5) Forming a fourth conductive layer pattern of the first driving structure layer includes: coating a first planar thin film on the substrate on which the aforementioned pattern is formed, patterning the first planar thin film by a patterning process to form a first planar layer including vias, depositing a fourth conductive thin film on the first planar layer, and patterning the fourth conductive thin film by a patterning process to form a fourth conductive layer pattern located on the first planar layer of the first driving structure layer, as shown in FIG17. FIG17 is a schematic diagram after forming the fourth conductive layer pattern of the first driving structure layer.

[0183] In an exemplary embodiment, as shown in FIG17, the fourth conductive layer pattern of the first driving structure layer may include at least: an anode connection electrode AL1 connected to at least one pixel driving circuit located in the first driving structure layer.

[0184] (6) Forming a semiconductor layer pattern for the second driving structure layer. In an exemplary embodiment, forming a semiconductor layer pattern for the second driving structure layer may include: coating a second planar thin film on a substrate on which the aforementioned pattern is formed, sequentially depositing a fifth insulating thin film and a second semiconductor thin film, and patterning the second semiconductor thin film using a patterning process to form a first insulating layer of the second driving structure layer and a semiconductor layer pattern located on the first insulating layer, as shown in FIG18, FIG18 being a schematic diagram after forming the semiconductor layer pattern of the second driving structure layer.

[0185] In an exemplary embodiment, as shown in FIG18, the semiconductor layer pattern of the second driving structure layer may include at least the active pattern T11-2 of the first transistor to the active pattern T71-2 of the seventh transistor of at least one pixel driving circuit located in the second driving structure layer.

[0186] (7) Forming a first conductive layer pattern for the second driving structure layer. In an exemplary embodiment, forming a first conductive layer pattern for the second driving structure layer may include: depositing a sixth insulating film and a fifth conductive film sequentially on a substrate on which the aforementioned pattern is formed, patterning the fifth conductive film using a patterning process to form a second insulating layer covering the semiconductor layer pattern of the second driving structure layer and a first conductive layer pattern disposed on the second insulating layer, as shown in FIG19, FIG19 being a schematic diagram after forming the first conductive layer pattern of the second driving structure layer.

[0187] In an exemplary embodiment, as shown in FIG19, the first conductive layer pattern of the second driving structure layer may include at least: the gate electrode T21-2 to the gate electrode T72-2 of the first transistor of at least one pixel driving circuit located in the second driving structure layer and the first plate C1-2 of the capacitor, as well as the reset signal line Reset-2, the light emission signal line EM-2 and the scan signal line Gate-2 connected to at least one pixel driving circuit located in the second driving structure layer.

[0188] (8) Forming a second conductive layer pattern of the second driving structure layer includes: depositing a seventh insulating film and a sixth conductive film sequentially on the substrate on which the aforementioned pattern is formed, and patterning the seventh insulating film and the sixth conductive film by a patterning process to form a third insulating layer of the second driving structure layer and a second conductive layer pattern located on the third insulating layer, as shown in Figure 20. Figure 20 is a schematic diagram after the second conductive layer pattern of the second driving structure layer is formed.

[0189] In an exemplary embodiment, as shown in FIG20, the second conductive layer pattern of the second driving structure layer may include at least: the second plate C2-2 of the capacitor of at least one pixel driving circuit located in the second driving structure layer, and the first initial signal line INIT1-2 and the second initial signal line INIT2-2 connected to at least one pixel driving circuit of the second driving structure layer.

[0190] (9) Forming a third conductive layer pattern of the second driving structure layer includes: depositing a fourth insulating film on the substrate on which the aforementioned pattern is formed, patterning the fourth insulating film through a patterning process to form a fourth insulating layer including multiple vias, depositing a third conductive film on the fourth insulating layer, and patterning the third conductive film through a patterning process to form a third conductive layer pattern located on the fourth insulating layer of the second driving structure layer, as shown in Figure 21. Figure 21 is a schematic diagram after forming the third conductive layer pattern of the second driving structure layer.

[0191] In an exemplary embodiment, as shown in FIG21, the third conductive layer pattern of the second driving structure layer may include at least: the first pole T13-2 and the second pole T14-2 of the first transistor of at least one pixel driving circuit located in the second driving structure layer to the first pole T73-2 and the second pole T74-2 of the seventh transistor.

[0192] (10) Forming a fourth conductive layer pattern of the second driving structure layer includes: coating a third planar thin film on a substrate on which the aforementioned pattern is formed; patterning the third planar thin film using a patterning process to form a first planar layer of the second driving structure layer including vias; depositing a fourth conductive thin film on the first planar layer; and patterning the fourth conductive thin film using a patterning process to form a fourth conductive layer pattern located on the first planar layer of the second driving structure layer, as shown in FIG22. FIG22 is a schematic diagram after forming the fourth conductive layer pattern of the second driving structure layer.

[0193] In an exemplary embodiment, as shown in FIG22, the fourth conductive layer pattern of the second driving structure layer may include at least: an anode connection electrode AL2 connected to at least one pixel driving circuit located in the second driving structure layer.

[0194] (11) Forming a second planarization layer pattern for the second driving structure layer. In an exemplary embodiment, forming a second planarization layer pattern for the second driving structure layer may include: coating a fourth planarization film on a substrate on which the aforementioned pattern is formed, and patterning the fourth planarization film by a patterning process to form a second planarization layer of the second driving structure layer, as shown in FIG23, FIG23 being a schematic diagram after forming the second planarization layer pattern of the second driving structure layer.

[0195] In an exemplary embodiment, as shown in FIG23, the second planarization layer of the second driving structure layer may include a plurality of vias, including via V1 exposing the anode connection electrode of the first driving structure layer and via V2 exposing the anode connection electrode of the second driving structure layer.

[0196] At this point, the driving structure layer assembly is complete on the substrate. In a plane parallel to the display substrate, the driving structure layer assembly may include multiple driving structure layers, and at least one driving structure layer may include multiple pixel driving circuits. The pixel driving circuits are connected to scan signal lines, light emission signal lines, reset signal lines, first initial signal lines, second initial signal lines, data signal lines, and a first power supply line. The driving structure layer may be disposed on the substrate. The driving structure layer may include, sequentially disposed on the substrate, a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a third conductive layer, a first planarization layer, a fourth conductive layer, and a second planarization layer.

[0197] In an exemplary embodiment, the semiconductor layer can be an amorphous silicon layer, a polycrystalline silicon layer, or a metal oxide layer. The metal oxide layer can be an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium, and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium, and tin, an oxide containing indium and zinc, an oxide containing silicon, indium, and tin, or an oxide containing indium or gallium and zinc. The metal oxide layer can be a single layer, a double layer, or a multilayer.

[0198] In an exemplary embodiment, the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer may be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). They may be single-layer structures or multi-layer composite structures, such as Mo / Cu / Mo.

[0199] In an exemplary embodiment, the first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer.

[0200] In an exemplary embodiment, the first planarization layer and the second planarization layer may be made of organic materials, such as resin.

[0201] In an exemplary embodiment, after the driving structure layer is prepared, a light-emitting structure layer is prepared on the driving structure layer. The preparation process of the light-emitting structure layer may include the following operations.

[0202] (12) Forming an anode conductive layer pattern. In an exemplary embodiment, forming an anode conductive layer pattern may include: depositing an anode conductive film on a substrate on which the aforementioned pattern is formed, and patterning the anode conductive film using a patterning process to form an anode conductive layer disposed on the driving structure layer group. As shown in FIG24, FIG24 is a schematic diagram after forming the anode conductive layer in the light-emitting structure layer.

[0203] In an exemplary embodiment, the anode conductive layer includes at least a first electrode 31 of at least one light-emitting device.

[0204] In an exemplary embodiment, the first electrode may include the first electrode of the first light-emitting device, the first electrode of the second light-emitting device, the first electrode of the third light-emitting device, and the first electrode of the fourth light-emitting device. The first electrode of the first light-emitting device is located in the red sub-pixel that emits red light, the first electrode of the second light-emitting device may be located in the blue sub-pixel that emits blue light, the first electrode of the third light-emitting device may be located in the first green sub-pixel that emits green light, and the first electrode of the fourth light-emitting device may be located in the second green sub-pixel that emits green light.

[0205] In an exemplary embodiment, the first electrode of the first light-emitting device and the first electrode of the second light-emitting device may be alternately arranged along a second direction, and the first electrode of the third light-emitting device and the first electrode of the fourth light-emitting device may be alternately arranged along the second direction. Alternatively, the first electrode of the first light-emitting device and the first electrode of the second light-emitting device may be alternately arranged along a first direction, and the first electrode of the third light-emitting device and the first electrode of the fourth light-emitting device may be alternately arranged along the first direction.

[0206] In an exemplary embodiment, the first electrode of the first light-emitting device, the first electrode of the second light-emitting device, the first electrode of the third light-emitting device, and the first electrode of the fourth light-emitting device can be electrically connected to the anode connection electrode through vias that expose the anode connection electrode.

[0207] In an exemplary embodiment, the shape and area of ​​the first electrode of at least one light-emitting device may be the same or different.

[0208] In an exemplary embodiment, at least one of the first electrode of the first light-emitting device, the first electrode of the second light-emitting device, the first electrode of the third light-emitting device, and the first electrode of the fourth light-emitting device may include an anode body portion and an anode connection portion connected to each other, with the anode connection portion connected to a connection electrode.

[0209] In an exemplary embodiment, the first electrode of the first light-emitting device may include a first anode body portion and a first anode connecting portion connected to each other. The first anode body portion may be rectangular in shape, and the corners of the rectangle may be provided with rounded chamfers. The first anode connecting portion may be strip-shaped. In an exemplary embodiment, the first electrode of the second light-emitting device may include a second anode body portion and a second anode connecting portion connected to each other. The second anode body portion may be rectangular in shape, and the corners of the rectangle may be provided with rounded chamfers. The second anode connecting portion may be strip-shaped. In an exemplary embodiment, the first electrode of the third light-emitting device may include a third anode body portion and a third anode connecting portion connected to each other. The third anode body portion may be rectangular in shape, and the corners of the rectangle may be provided with rounded chamfers. The third anode connecting portion may be strip-shaped. In an exemplary embodiment, the first electrode of the fourth light-emitting device may include a fourth anode body portion and a fourth anode connecting portion connected to each other. The fourth anode body portion may be rectangular in shape, and the corners of the rectangle may be provided with rounded chamfers. The fourth anode connecting portion may be strip-shaped.

[0210] In an exemplary embodiment, the anode conductive layer adopts a single-layer structure, such as indium tin oxide (ITO) or indium zinc oxide (IZO), or it can adopt a multi-layer composite structure, such as ITO / Ag / ITO.

[0211] (13) Forming a cathode conductive layer pattern. In an exemplary embodiment, forming a cathode conductive layer may include: coating a pixel definition film on a substrate on which the aforementioned pattern is formed; depositing a pixel definition film on the substrate on which the aforementioned pattern is formed; patterning the pixel definition film using a patterning process to form a pixel definition layer pattern that exposes the anode conductive layer pattern; coating an organic light-emitting material on a substrate on which the pixel definition layer pattern is formed; patterning the organic light-emitting material using a patterning process to form an organic structure layer pattern; depositing a cathode conductive film on a substrate on which the organic material layer pattern is formed; and patterning the cathode conductive film using a patterning process to form a cathode conductive layer.

[0212] In an exemplary embodiment, the subsequent preparation process may include: forming an encapsulation structure layer on the cathode conductive layer. The encapsulation structure layer may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first and third encapsulation layers may be made of inorganic materials, and the second encapsulation layer may be made of organic materials. The second encapsulation layer is disposed between the first and third encapsulation layers to ensure that external moisture cannot enter the light-emitting structure layer.

[0213] In an exemplary embodiment, the organic structure layer may include at least an organic light-emitting layer of a light-emitting device.

[0214] In an exemplary embodiment, the cathode conductive layer may include at least: a second electrode (cathode) of a plurality of light-emitting devices.

[0215] In an exemplary embodiment, the cathode conductive layer in at least one light-emitting structural layer may be made of a metallic material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or the aforementioned conductive alloy materials, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). It may be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo.

[0216] This disclosure also provides a display device, including: a display substrate provided in any of the foregoing embodiments.

[0217] In an exemplary embodiment, the display device can be any product or component with display function, such as electronic paper, OLED panel, active-matrix organic light emitting diode (AMOLED) panel, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, navigator, etc.

[0218] The accompanying drawings of the embodiments disclosed herein only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in a general design.

[0219] For clarity, the thickness and dimensions of layers or microstructures are enlarged in the accompanying drawings used to describe embodiments of this disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “below” another element, the element may be located “directly” on or “below” the other element, or there may be intermediate elements present.

[0220] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit this disclosure. Any person skilled in the art to which this disclosure pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this disclosure shall still be determined by the scope defined in the appended claims.

Claims

1. A display substrate having a display area and a non-display area, the display substrate comprising: The substrate includes a driving structure layer group and a light-emitting structure layer stacked sequentially on the substrate. The driving structure layer group is provided with a plurality of pixel driving circuits located in the display area. The light-emitting structure layer is provided with a plurality of light-emitting devices located in the display area. The light-emitting devices are electrically connected to the pixel driving circuits. The driving structure layer group includes: K driving structure layers stacked sequentially along the substrate, at least one driving structure layer including: at least one pixel driving circuit, the orthographic projection of at least one light-emitting device on the substrate at least partially overlaps with the orthographic projection of at least one pixel driving circuit on the substrate in at least two of the K driving structure layers, and the orthographic projection of at least one pixel driving circuit in at least one of the at least one driving structure layer on the substrate at least partially overlaps with the orthographic projection of at least two light-emitting devices on the substrate, wherein K is a positive integer greater than or equal to 2.

2. The display substrate according to claim 1, wherein, At least one driving structure layer includes: M rows and N columns of pixel driving circuitry; The orthographic projections of the pixel driving circuits in the m-th row and n-th column of at least two of the K driving structure layers onto the substrate at least partially overlap, 1≤m≤M, 1≤n≤N.

3. The display substrate according to claim 2, wherein, The light-emitting device includes: a first electrode electrically connected to a pixel driving circuit; the first electrodes of the plurality of light-emitting devices are arranged in an array; the pixel driving circuits connected to the first electrodes of adjacent light-emitting devices in the same row are located in the same driving circuit layer; and the pixel driving circuits connected to the first electrodes of adjacent light-emitting devices in the same column are located in different driving circuit layers.

4. The display substrate according to claim 3, wherein, At least one driving structure layer includes: a plurality of anode connection electrodes, the plurality of anode connection electrodes corresponding one-to-one with a plurality of pixel driving circuits in at least one driving structure layer, the pixel driving circuit including: at least one transistor, the transistor including: an active layer, a gate electrode, a first electrode and a second electrode; At least one anode connection electrode is electrically connected to a corresponding pixel driving circuit and a light-emitting device connected to the corresponding pixel driving circuit. The film layer in which the anode connection electrode is located is on the side of the film layer in which at least one of the active layer, gate electrode, first electrode, and second electrode of at least one transistor is located, away from the substrate.

5. The display substrate according to claim 4, wherein, The orthogonal projections of the anode connection electrodes corresponding to the pixel driving circuits in the m-th row and n-th column of two adjacent driving structure layers in the K driving structure layers on the substrate at least partially overlap.

6. The display substrate according to claim 4 or 5, wherein, At least one anode-connected electrode extends at least partially along a first direction.

7. The display substrate according to claim 6, wherein, The drive structure layer group further includes: a plurality of vias exposing the anode connection electrode; The orthographic projection of the via of at least one anode connection electrode in the r-th driving structure layer on the substrate does not overlap with the orthographic projection of the structure in at least two driving structure layers from the (r+1)-th to the K-th driving structure layers on the substrate, and 1≤r≤K-1. The structure in the at least one driving structure layer includes: a pixel driving circuit in the driving structure layer and a signal line connected to the pixel driving circuit.

8. The display substrate according to claim 7, wherein, The vias exposing the anode connection electrodes of the pixel driving circuits in the m-th row and n-th column of two adjacent driving structure layers in the K driving structure layers are arranged along the first direction.

9. The display substrate according to claim 7, wherein, There is no overlap between the orthographic projection of at least one anode connection electrode on the substrate and the orthographic projection of the first signal line connected to the pixel driving circuit corresponding to the anode connection electrode on the substrate. The first signal line includes a first power line and a data signal line.

10. The display substrate according to claim 1, wherein, The drive structure layer group also includes: K-1 protective layers; The r-th protection layer is located between the r-th driving structure layer and the (r+1)-th driving structure layer, where 1 ≤ r ≤ K-1.

11. The display substrate according to claim 7, wherein, The at least one driving circuit layer includes: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer; the pixel driving circuit includes: at least one transistor and a capacitor; the capacitor includes: two plates; the signal lines connected to the pixel driving circuit include: a scan signal line, a reset signal line, a first initial signal line, a second initial signal line, a light emission signal line, a data signal line, and a first power supply line. The semiconductor layer includes at least: an active layer of at least one transistor; The first conductive layer includes at least: a gate electrode of at least one transistor, one of the plates of a capacitor, a scan signal line, a reset signal line, and a light emission signal line; The second conductive layer includes at least: the other electrode of the capacitor, a first initial signal line, and a second initial signal line; The third conductive layer includes at least: a first and second electrode of at least one transistor, a data signal line, and a first power supply line; The fourth conductive layer includes at least an anode connection electrode.

12. The display substrate according to claim 11, wherein, The at least one driving circuit layer further includes: a first flattening layer and a second flattening layer; The first planarization layer is located between the third conductive layer and the fourth conductive layer, and the second planarization layer is located on the side of the fourth conductive layer away from the substrate.

13. The display substrate according to claim 11, further comprising: The K source driver chip groups located in the non-display area, at least one source driver chip group includes: at least one source driver chip; The data signal lines connecting the k-th source driver chip group and the pixel driver circuit in the k-th driver structure layer are electrically connected, where 1≤k≤K.

14. The display substrate according to claim 11, wherein, The data signal line connected to at least one column of pixel driving circuits in the r-th driving structure layer is electrically connected to the data signal line connected to at least one column of pixel driving circuits in the (r+1)-th driving structure layer, where 1≤r≤K-1.

15. The display substrate according to claim 11, further comprising: K gate driving circuits located in the non-display area; The kth gate driving circuit is located on the kth driving structure layer, and the kth gate driving circuit is electrically connected to the scan signal line connected to the pixel driving circuit in the kth driving structure layer; the K gate driving circuits are stacked sequentially along the substrate direction, 1≤k≤K.

16. The display substrate according to claim 15, wherein, At least one gate drive circuit is electrically connected to the initial signal line, and different gate drive circuits are connected to different initial signal lines.

17. The display substrate according to claim 11, further comprising: The K first light-emitting power lines located in the non-display area, and the signal lines connected to at least one pixel driving circuit include: first power lines; The kth first light-emitting power line is located on the kth driving structure layer, and the kth first light-emitting power line is electrically connected to the first power line connected to the pixel driving circuit located in the kth driving structure layer. At least two of the K first light-emitting power lines are electrically connected to each other.

18. The display substrate according to claim 11, further comprising: The K first drive power lines and K second drive power lines located in the non-display area The kth first driving power line is located on the kth driving structure layer and is electrically connected to the kth gate drive; the kth second driving power line is located on the kth driving structure layer and is electrically connected to the kth gate drive. The first drive power lines in at least two of the K drive structure layers are electrically connected to each other. The second drive power lines in at least two of the K drive structure layers are electrically connected to each other.

19. A display device, comprising: The display substrate as described in any one of claims 1 to 18.

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