Display panel and display apparatus

Abstract

A display panel and a display apparatus. The display panel comprises circuit regions (PA) distributed in an array. The display panel comprises a base substrate (SBT), a transistor layer (TL), a first source / drain metal layer (SD1), a second source / drain metal layer (SD2) and a pixel layer (PIXL) that are sequentially stacked, wherein the first source / drain metal layer (SD1) is provided with power voltage switching structures (VDLP); each power voltage switching structure (VDLP) is used for simultaneously providing a power voltage (VDD) to two pixel driving circuits; the circuit regions (PA) comprise a non-heterogeneous circuit region (PAN) and a heterogeneous circuit region (PAM); the shape of a power voltage switching structure (VDLP) in the heterogeneous circuit region (PAM) is different from the shape of a power voltage switching structure (VDLP) in the non-heterogeneous circuit region (PAN), such that the first source / drain metal layer (SD1) has a cross-line channel extending in the column direction within the heterogeneous circuit region (PAM); and the first source / drain metal layer (SD1) is provided with a voltage jumper wire (VLA) in the cross-line channel, and the voltage jumper wire (VLA) is electrically connected to two voltage routing lines (VL) that are adjacent in the column direction. The display panel and the display apparatus provided with the display panel can reduce the voltage drop of a power signal.

Description

Display panel and display device

[0001] Cross-reference to related applications

[0002] The present disclosure claims priority to Chinese Patent Application No. 202410667161.X, filed May 27, 2024, entitled “Display panel and display device,” the entire contents of which are incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present disclosure relates to the technical field of display panels, and in particular, to a display panel and a display device. BACKGROUND

[0004] With the rapid development of the display industry, people's pursuit of display panel quality is getting higher and higher, and flexible organic light-emitting diode displays have emerged. The voltage drop of the power signal on the display panel is an important factor leading to the decline in picture quality, and it is necessary to provide a new design scheme to reduce the voltage drop of the power signal on the display panel.

[0005] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present disclosure, and therefore can include information that does not constitute prior art known to those of ordinary skill in the art. SUMMARY

[0006] The purpose of the present disclosure is to overcome the shortcomings of the prior art described above, and to provide a display panel and a display device that can help reduce the voltage drop of the power signal on the display panel.

[0007] According to one aspect of the present disclosure, a display panel is provided, comprising an array of circuit regions, each circuit region being provided with two pixel driving circuits for driving two sub-pixels, respectively;

[0008] The display panel comprises a substrate, a transistor layer, a first source-drain metal layer, a second source-drain metal layer and a pixel layer arranged in sequence;

[0009] The transistor layer is provided with a thin film transistor of each pixel driving circuit; at least one of the transistor layer and the first source-drain metal layer is provided with a voltage trace extending in the row direction;

[0010] The second source-drain metal layer is provided with a power voltage trace for loading a power voltage, and the first source-drain metal layer is provided with a power voltage switching structure in the circuit region; the power voltage switching structure is electrically connected with the power voltage trace, and is used to simultaneously provide a power voltage to the two pixel driving circuits of the circuit region;

[0011] The circuit region includes a non-heterogeneous circuit region and a heterogeneous circuit region; a shape of a power voltage switching structure in the heterogeneous circuit region is different from a shape of a power voltage switching structure in the non-heterogeneous circuit region, so that the first source-drain metal layer has a cross-line channel extending in the column direction in the heterogeneous circuit region; the first source-drain metal layer is provided with a voltage cross-line in the cross-line channel, and the voltage cross-line is electrically connected with two voltage tracks adjacent in the column direction.

[0012] According to an embodiment of the present disclosure, the voltage track includes a reference voltage track provided in the first source-drain metal layer and used for loading a reference voltage;

[0013] The heterogeneous circuit region includes a reference heterogeneous circuit region, and the voltage cross-line includes a reference voltage cross-line located in the reference heterogeneous circuit region, and the reference voltage cross-line electrically connects two reference voltage tracks adjacent in the column direction.

[0014] According to an embodiment of the present disclosure, the voltage track further includes an initialization voltage track located in the transistor layer and used for loading an initialization voltage to the pixel driving circuit;

[0015] The heterogeneous circuit region further includes an initialization heterogeneous circuit region, and the voltage cross-line further includes an initialization voltage cross-line, the initialization voltage cross-line is located in the initialization heterogeneous circuit region and electrically connects two initialization voltage tracks adjacent in the column direction;

[0016] The reference voltage track is interrupted at the cross-line channel of the initialization heterogeneous circuit region, and the initialization voltage cross-line passes through the interruption gap of the reference voltage track.

[0017] According to an embodiment of the present disclosure, the initialization voltage track has at least two types, and in each initialization heterogeneous circuit region, only the initialization voltage cross-line corresponding to one type of initialization voltage track is provided.

[0018] According to an embodiment of the present disclosure, in the non-heterogeneous circuit region, the power voltage switching structure has a first sub-switching structure, a second sub-switching structure and a third sub-switching structure; the first sub-switching structure extends in the column direction and is located in the middle of the non-heterogeneous circuit region in the row direction, and is used for simultaneously providing the driving power voltage to two pixel driving circuits; the second sub-switching structure and the third sub-switching structure are respectively located on both sides of the first sub-switching structure and are respectively electrically connected with the power voltage track through a via hole;

[0019] In the heterogeneous circuit region, the power voltage switching structure is composed of the first sub-switching structure and the second sub-switching structure.

[0020] According to an embodiment of the present disclosure, the first source-drain metal layer is further provided with an initialization voltage switching structure in the circuit region, the voltage trace includes an initialization voltage trace located in the transistor layer and used for loading an initialization voltage; the initialization voltage switching structure is electrically connected with the initialization voltage trace, and used for simultaneously providing the initialization voltage to two pixel driving circuits in the circuit region.

[0021] The shape of the initialization voltage switching structure in the non-heterogeneous circuit region is different from the shape of the initialization voltage switching structure in the heterogeneous circuit region, so that the initialization voltage switching structure in the heterogeneous circuit region avoids the cross-line channel.

[0022] According to an embodiment of the present disclosure, in the non-heterogeneous circuit region, the initialization voltage switching structure includes a fourth sub-switching structure, a fifth sub-switching structure and a sixth sub-switching structure connected in sequence; the fifth sub-switching structure and the sixth sub-switching structure are respectively arranged on both sides of the fourth sub-switching structure in the row direction, and are respectively used for being electrically connected with the initialization voltage trace through a via hole; the fourth sub-switching structure simultaneously provides the initialization voltage to two pixel driving circuits in the circuit region through a via hole.

[0023] In the heterogeneous circuit region, the initialization voltage switching structure is composed of the fourth sub-switching structure and the fifth sub-switching structure.

[0024] According to an embodiment of the present disclosure, the circuit region includes a first sub-circuit region and a second sub-circuit region adjacent in the row direction; the first sub-circuit region and the second sub-circuit region are respectively provided with the pixel driving circuit; the cross-line channel of the heterogeneous circuit region is arranged in the first sub-circuit region of the heterogeneous circuit region.

[0025] In the non-heterogeneous circuit region, the pattern of the first source-drain metal layer in the first sub-circuit region is arranged in axial symmetry with the pattern in the second sub-circuit region.

[0026] The pattern of the first source-drain metal layer in the second sub-circuit region of the non-heterogeneous circuit region is the same as the pattern in the second sub-circuit region of the heterogeneous circuit region.

[0027] The pattern of the first source-drain metal layer in the first sub-circuit region of the heterogeneous circuit region is different from the pattern in the first sub-circuit region of the non-heterogeneous circuit region.

[0028] According to an embodiment of the present disclosure, wherein the pattern of the first source-drain metal layer in the region outside the cross-line channel of the first sub-circuit region of the heterogeneous circuit region is the same as the pattern of the first source-drain metal layer in the same region of the first sub-circuit region of the non-heterogeneous circuit region.

[0029] According to an embodiment of the present disclosure, wherein in the circuit region, the pattern of the semiconductor layer in the first sub-circuit region is arranged axially symmetrically to the pattern in the second sub-circuit region.

[0030] According to an embodiment of the present disclosure, wherein in the circuit region row, the non-heterogeneous circuit region and the heterogeneous circuit region are arranged alternately.

[0031] According to an embodiment of the present disclosure, wherein in the circuit region column, the non-heterogeneous circuit region and the heterogeneous circuit region are arranged alternately.

[0032] According to an embodiment of the present disclosure, wherein the voltage trace includes a reference voltage trace arranged in the first source-drain metal layer and an initialization voltage trace arranged in the transistor layer; the reference voltage trace is used to load a reference voltage, and the initialization voltage trace is used to load an initialization voltage to the pixel driving circuit.

[0033] The heterogeneous circuit region includes a reference heterogeneous circuit region and an initialization heterogeneous circuit region; the first source-drain metal layer is provided with a reference voltage cross-over line in the reference heterogeneous circuit region, which electrically connects adjacent two reference voltage traces; the first source-drain metal layer is provided with an initialization voltage cross-over line in the initialization heterogeneous circuit region, which electrically connects adjacent two initialization voltage traces.

[0034] Along the row direction, at least one reference heterogeneous circuit region is arranged between adjacent two initialization heterogeneous circuit regions.

[0035] According to an embodiment of the present disclosure, wherein the initialization voltage trace includes a first initialization voltage trace for loading a first initialization voltage, a second initialization voltage trace for loading a second initialization voltage, and a third initialization voltage trace for loading a third initialization voltage; the initialization heterogeneous circuit region includes a first initialization heterogeneous circuit region provided with a first initialization voltage cross-over line in the first source-drain metal layer, a second initialization heterogeneous circuit region provided with a second initialization voltage cross-over line in the first source-drain metal layer, and a third initialization heterogeneous circuit region provided with a third initialization voltage cross-over line in the first source-drain metal layer; the first initialization voltage cross-over line electrically connects adjacent two first initialization voltage traces, the second initialization voltage cross-over line electrically connects adjacent two second initialization voltage traces, and the third initialization voltage cross-over line electrically connects adjacent two third initialization voltage traces.

[0036] The first initialization heterogeneous circuit region, the second initialization heterogeneous circuit region, the third initialization heterogeneous circuit region and the second initialization heterogeneous circuit region are arranged periodically in the same row.

[0037] According to an embodiment of the present disclosure, the initialization voltage traces include first initialization voltage traces for loading first initialization voltages, second initialization voltage traces for loading second initialization voltages, and third initialization voltage traces for loading third initialization voltages; the initialization heterogeneous circuit regions include first initialization heterogeneous circuit regions provided with first initialization voltage cross-over lines in the first source-drain metal layer, second initialization heterogeneous circuit regions provided with second initialization voltage cross-over lines in the first source-drain metal layer, and third initialization heterogeneous circuit regions provided with third initialization voltage cross-over lines in the first source-drain metal layer; the first initialization voltage cross-over lines electrically connect two adjacent first initialization voltage traces, the second initialization voltage cross-over lines electrically connect two adjacent second initialization voltage traces, and the third initialization voltage cross-over lines electrically connect two adjacent third initialization voltage traces;

[0038] In each of the initialization heterogeneous circuit regions provided in every two rows, the initialization heterogeneous circuit regions in one of the rows are arranged periodically in the first initialization heterogeneous circuit region, the second initialization heterogeneous circuit region, the third initialization heterogeneous circuit region and the second initialization heterogeneous circuit region;

[0039] The initialization heterogeneous circuit regions in the other of the two rows are arranged periodically in the third initialization heterogeneous circuit region, the second initialization heterogeneous circuit region, the first initialization heterogeneous circuit region and the second initialization heterogeneous circuit region.

[0040] According to an embodiment of the present disclosure, the voltage traces include reference voltage traces provided in the first source-drain metal layer and initialization voltage traces provided in the transistor layer; the reference voltage traces are used to load reference power supply voltages, and the initialization voltage traces are used to load initialization voltages to the pixel driving circuit.

[0041] The heterogeneous circuit regions include reference heterogeneous circuit regions and initialization heterogeneous circuit regions; the first source-drain metal layer is provided with reference voltage cross-over lines electrically connecting two adjacent reference voltage traces in the reference heterogeneous circuit regions; the first source-drain metal layer is provided with initialization voltage cross-over lines electrically connecting two adjacent initialization voltage traces in the initialization heterogeneous circuit regions; each of the heterogeneous circuit regions in the same circuit region column is the same.

[0042] According to one embodiment of this disclosure, the voltage trace includes an initialization voltage trace disposed on the transistor layer; the initialization voltage trace is used to apply an initialization voltage to the pixel driving circuit.

[0043] The circuit region has an initialization voltage transfer structure in the first source-drain metal layer. The initialization voltage transfer structure is electrically connected to the initialization voltage trace and the thin film transistor through a via, so that the initialization voltage is applied to the pixel driving circuit.

[0044] The heterogeneous circuit region includes an initialization heterogeneous circuit region; the first source-drain metal layer is provided with an initialization voltage jumper in the initialization heterogeneous circuit region, and the two ends of the initialization voltage jumper are respectively electrically connected to two adjacent initialization voltage transfer structures in the same column.

[0045] According to one embodiment of this disclosure, the display panel further includes a second planarization layer, a third source-drain metal layer, and a third planarization layer stacked sequentially on the side of the second source-drain metal layer away from the first source-drain metal layer; the third source-drain metal layer is provided with a reference voltage grid; the pixel layer is disposed on the side of the third planarization layer away from the second source-drain metal layer; and a plurality of sub-pixels are disposed in the cutout holes of the reference voltage grid.

[0046] According to one embodiment of this disclosure, wherein...

[0047] The reference voltage grid has a first reference voltage line segment extending along the column direction; along the row direction, the first reference voltage line segment is located between a blue sub-pixel and a red sub-pixel; wherein the distance between the first reference voltage line segment and the blue sub-pixel is greater than the distance between the first reference voltage line segment and the red sub-pixel.

[0048] According to another aspect of this disclosure, a display device is provided, including the display panel.

[0049] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0050] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0051] Figure 1 is a schematic diagram of the film layer structure of the display panel in one embodiment of this disclosure.

[0052] FIG. 2 is a schematic diagram of the distribution of the circuit region in the display panel according to an embodiment of the present disclosure.

[0053] FIG. 3 is a schematic diagram of the reference voltage bus and the initialization voltage bus according to an embodiment of the present disclosure.

[0054] FIG. 4 is a schematic diagram of the pixel driving circuit according to an embodiment of the present disclosure.

[0055] FIG. 5-1 is a schematic diagram of the arrangement of the heterogeneous circuit region and the non-heterogeneous circuit region according to an embodiment of the present disclosure.

[0056] FIG. 5-2 is a schematic diagram of the arrangement of the heterogeneous circuit region and the non-heterogeneous circuit region according to an embodiment of the present disclosure.

[0057] FIG. 6 is a schematic diagram of the structure of the low-temperature polysilicon semiconductor layer according to an embodiment of the present disclosure.

[0058] FIG. 7 is a schematic diagram of the structure of the first gate layer according to an embodiment of the present disclosure.

[0059] FIG. 8 is a schematic diagram of the structure of the second gate layer according to an embodiment of the present disclosure.

[0060] FIG. 9 is a schematic diagram of the structure of the metal-oxide semiconductor layer according to an embodiment of the present disclosure.

[0061] FIG. 10 is a schematic diagram of the structure of the third gate layer according to an embodiment of the present disclosure.

[0062] FIG. 11 is a schematic diagram of the structure of the first source-drain metal layer in the non-heterogeneous circuit region according to an embodiment of the present disclosure.

[0063] FIG. 12 is a schematic diagram of the structure of the second source-drain metal layer according to an embodiment of the present disclosure.

[0064] FIG. 13 is a schematic diagram of the structure of the first source-drain metal layer in the reference heterogeneous circuit region according to an embodiment of the present disclosure.

[0065] FIG. 14 is a schematic diagram of the structure of the first source-drain metal layer in the first initialization heterogeneous circuit region according to an embodiment of the present disclosure.

[0066] FIG. 15 is a schematic diagram of the structure of the first source-drain metal layer in the second initialization heterogeneous circuit region according to an embodiment of the present disclosure.

[0067] FIG. 16 is a schematic diagram of the structure of the first source-drain metal layer in the third initialization heterogeneous circuit region according to an embodiment of the present disclosure.

[0068] FIG. 17 is a schematic diagram of the structure of the third gate layer according to an embodiment of the present disclosure.

[0069] FIG. 18 is a schematic diagram of a structure of a third source-drain metal layer in an embodiment of the present disclosure.

[0070] FIG. 19 is a schematic diagram of a partial stack of a second source-drain metal layer and a third source-drain metal layer and a sub-pixel arrangement in an embodiment of the present disclosure.

[0071] FIG. 20-1 is a schematic diagram of an arrangement of a heterogeneous circuit region and a non-heterogeneous circuit region in an embodiment of the present disclosure.

[0072] FIG. 20-2 is a schematic diagram of an arrangement of a heterogeneous circuit region and a non-heterogeneous circuit region in an embodiment of the present disclosure.

[0073] FIG. 21 is a schematic diagram of a first initialization voltage cross-over line in an embodiment of the present disclosure.

[0074] FIG. 22 is a schematic diagram of a second initialization voltage cross-over line in an embodiment of the present disclosure.

[0075] FIG. 23 is a schematic diagram of a reference voltage cross-over line in an embodiment of the present disclosure.

[0076] FIG. 24 is a schematic diagram of a third initialization voltage cross-over line in an embodiment of the present disclosure.

[0077] FIG. 25 is a schematic diagram of a first initialization voltage cross-over line in an embodiment of the present disclosure.

[0078] FIG. 26 is a schematic diagram of a third initialization voltage cross-over line in an embodiment of the present disclosure.

[0079] FIG. 27 is a schematic diagram of a distribution of a second initialization heterogeneous circuit region in an embodiment of the present disclosure.

[0080] FIG. 28 is a schematic diagram of a distribution of a third initialization heterogeneous circuit region in an embodiment of the present disclosure.

[0081] Legend: PA, circuit region; PA1, first sub-circuit region; PA2, second sub-circuit region; PAN, non-heterogeneous circuit region; PAM, heterogeneous circuit region; PAMS, reference heterogeneous circuit region; PAMT, initialization heterogeneous circuit region; PAMT1, first initialization heterogeneous circuit region; PAMT2, second initialization heterogeneous circuit region; PAMT3, third initialization heterogeneous circuit region; VDDL, power voltage trace; VLA, voltage jumper; VSSW, reference voltage grid; VSSW1, first reference voltage segment; VSSW2, second reference voltage segment; VSSW3, third reference voltage segment; VSL, reference voltage trace; VSLA, reference voltage jumper; VTL, initialization voltage trace; VTL1, first initialization voltage trace; VTL2, second initialization voltage trace; VTL3, third initialization voltage trace; VTLA, initialization voltage jumper; VTL1A, first initialization voltage jumper; VTL2A, second initialization voltage jumper; VTL3A, third initialization voltage jumper; VTLP, initialization voltage transfer structure; MA1, first bridge portion; MA2, second bridge portion; MA3, third bridge portion; MA4, fourth bridge portion; MA5, fifth bridge portion; MA6, sixth bridge portion; MA7, seventh bridge portion; MA8, eighth bridge portion; MA9, ninth bridge portion; VDLP, power voltage transfer structure; MA31, first sub-transfer structure; MA32, second sub-transfer structure; MA33, third sub-transfer structure; MA61, fourth sub-transfer structure; MA62, fifth sub-transfer structure; MA63, sixth sub-transfer structure; SBT, substrate base plate; DRL, drive layer; TL, transistor layer; LS, light shielding layer; LSCL, low temperature polysilicon semiconductor layer; Buff1, first buffer layer; Buff2, second buffer layer; GI1, first gate insulating layer; GI2, second gate insulating layer; GT1, first gate layer; GT2, second gate layer; GT3, third gate layer; ILD, interlayer dielectric layer; SD1, first source-drain metal layer; SD2, second source-drain metal layer; SD3, third source-drain metal layer; PLN1, first planarization layer; PLN2, second planarization layer; PLN3, third planarization layer; OSCL, metal-oxide semiconductor layer; PDL, pixel definition layer; COML, common electrode layer; EL, light-emitting functional layer; ANL, pixel electrode layer; PIXL, pixel layer; PIX, sub-pixel; TFE, thin film encapsulation layer; T1, first capacitor reset transistor; T2, threshold compensation transistor; T3, drive transistor; T4, data write transistor; T5, first light-emitting control transistor; T6, second light-emitting control transistor; T7, electrode reset transistor; T8, second capacitor reset transistor; CST, storage capacitor; CP1, first electrode; CP2, second electrode; Vinit1, first initialization voltage; Vinit2, second initialization voltage;Vinit3, Third Initialization Voltage; Rest1, First Capacitor Reset Control Signal; Rest2, Second Capacitor Reset Control Signal; N1, First Node; N2, Second Node; N3, Third Node; N4, Fourth Node; N5, Fifth Node; GN, First Scan Signal; Source, Drive Data Signal; GP, Second Scan Signal; VDD, Power Supply Voltage; VSS, Reference Voltage; EM, Enable Signal; T1A, Channel Region of the First Capacitor Reset Transistor; T2A, Channel Region of the Threshold Compensation Transistor; T3A, Channel Region of the Drive Transistor; T4A, Channel Region of the Data Write Transistor; T5A, Channel Region of the First Light Emitting Control Transistor; T6A, Second Light Emitting Control Transistor. Transistor channel region; T7A, channel region of electrode reset transistor; T8A, channel region of second capacitor reset transistor; HB1, first upper via region; HB2, second upper via region; HB3, third upper via region; HB4, fourth upper via region; HB5, fifth upper via region; HB6, sixth upper via region; HB7, seventh upper via region; HB8, eighth upper via region; HB9, ninth upper via region; HB10, tenth upper via region; HB11, eleventh upper via region; HB12, twelfth upper via region; HB13, thirteenth upper via region; HB14, fourteenth upper via region; HB15, fifteenth upper via region; HB16, sixteenth upper via region; HB17, seventeenth upper via region. Zones; HB18, 18th upper via zone; HB19, 19th upper via zone; HB20, 20th upper via zone; HB21, 21st upper via zone; HA1, 1st lower via zone; HA2, 2nd lower via zone; HA3, 3rd lower via zone; HA4, 4th lower via zone; HA5, 5th lower via zone; HA6, 6th lower via zone; HA7, 7th lower via zone; HA8, 8th lower via zone; HA9, 9th lower via zone; HA10, 10th lower via zone; HA11, 11th lower via zone; HA12, 12th lower via zone; HA13, 13th lower via zone; HA14, 14th lower via zone; HA15, 15th lower via zone; HA16, 16th lower via zone Areas; HA17, 17th lower via area; HA18, 18th lower via area; HA19, 19th lower via area; HA20, 20th lower via area; HA21, 21st lower via area; RL1, 1st capacitor reset control signal line; RL2, 2nd capacitor reset control signal line; EML, Enable signal line; GNLA, 1st scan signal trace; GNLB, 2nd scan signal trace; GPL, 3rd scan signal trace; VL, Voltage trace; DH, Row direction; DV, Column direction; DL, Data signal trace; HPA, Circuit area row; VPA, Circuit area column; CG, Disconnect notch; RPIX, Red sub-pixel; BPIX, Blue sub-pixel; GPIX, Green sub-pixel. Detailed Implementation

[0082] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0083] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0084] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.

[0085] Structural layer A is located on the side of structural layer B that faces away from the substrate. This can be understood as structural layer A being formed on the side of structural layer B that faces away from the substrate. When structural layer B is a patterned structure, some structures of structural layer A may also be located at the same physical height as structural layer B or at a lower physical height than structural layer B, where the substrate serves as the height reference.

[0086] In this embodiment, the thin-film transistor includes an active layer, a gate insulating layer, and a gate, stacked together. The active layer is located within the semiconductor layer and includes a channel region and a first electrode and a second electrode located on opposite sides of the channel region. The channel region retains semiconductor characteristics, and both the first and second electrodes are conductive. In this embodiment, when using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "first electrode" and the "second electrode" are sometimes interchanged; that is, the "first electrode" and the "second electrode" can be interchanged. In this embodiment, for any given transistor, one of the "first electrode" and the "second electrode" is referred to as the first electrode of the transistor, and the other is referred to as the second electrode of the transistor.

[0087] With the rapid development of the display industry, people have increasingly higher demands for the image quality of display devices. The voltage drop of the power signal on the display panel is a significant factor leading to a decrease in display panel image quality, making it necessary to provide new design solutions to reduce the voltage drop of the power signal on the display panel.

[0088] Based on this, the present disclosure provides a display panel and a display device using the display panel. Referring to FIG1, the display panel may include a substrate SBT, a driving layer DRL, and a pixel layer PIXL stacked sequentially; the pixel layer PIXL is provided with light-emitting elements (not shown in this figure) serving as sub-pixels PIX, and the driving layer DRL is provided with a pixel driving circuit for driving the sub-pixels PIX; each sub-pixel PIX can emit light under the drive of the pixel driving circuit to display an image. Furthermore, the display panel also includes a thin film encapsulation layer TFE located on the side of the pixel layer PIXL away from the driving layer DRL, the thin film encapsulation layer TFE can encapsulate and protect the pixel layer PIXL.

[0089] Optionally, the substrate SBT can be an inorganic material substrate SBT or an organic material substrate SBT; of course, it can also be a composite substrate formed by stacking inorganic and organic material substrate SBTs. For example, in some embodiments of this disclosure, the material of the substrate SBT can be glass materials such as soda-lime glass, quartz glass, and sapphire glass. In other embodiments of this disclosure, the material of the substrate SBT can be polymethyl methacrylate, polyvinyl alcohol, polyvinylphenol, polyethersulfone, polyimide, polyamide, polyacetal, polycarbonate, polyethylene terephthalate, polyethylene naphthalate, or combinations thereof. In other embodiments of this disclosure, the substrate SBT can also be a flexible substrate SBT, for example, the material of the substrate SBT may include polyimide.

[0090] Optionally, in the driving layer DRL, any pixel driving circuit may include a thin-film transistor and a storage capacitor CST (not shown in the accompanying drawings). Further, the thin-film transistor may be selected from top-gate, bottom-gate, or dual-gate thin-film transistors; the material of the active layer of the thin-film transistor may be amorphous silicon semiconductor material, low-temperature polycrystalline silicon semiconductor material, metal oxide semiconductor material, organic semiconductor material, carbon nanotube semiconductor material, or other types of semiconductor material; the thin-film transistor may be an N-type or P-type thin-film transistor.

[0091] It is understood that any two transistors in a pixel driving circuit can be of the same or different types. For example, in some embodiments, some transistors in a pixel driving circuit can be N-type transistors and some transistors can be P-type transistors.

[0092] As further exemplarily, in some other embodiments, in a pixel driving circuit, the active layer of some transistors may be made of low-temperature polycrystalline silicon (LTPS) semiconductor material, and the active layer of some transistors may be made of metal-oxide-semiconductor (MODS) semiconductor material. In some embodiments of this disclosure, the thin-film transistor is an LTPS transistor. In other embodiments of this disclosure, some thin-film transistors are LTPS transistors, and some thin-film transistors are MODS transistors.

[0093] Optionally, the driving layer DRL may include a semiconductor layer (e.g., a low-temperature polysilicon semiconductor layer LSCL and a metal-oxide-semiconductor layer OSCL as shown in FIG. 1), a gate insulating layer (e.g., a first gate insulating layer GI1, a second gate insulating layer GI2, and a third gate insulating layer GI3 as shown in FIG. 1), a gate layer (e.g., a first gate layer GT1, a second gate layer GT2, and a third gate insulating layer GT3 as shown in FIG. 1), an interlayer dielectric layer ILD, source / drain metal layers (e.g., a first source / drain metal layer SD1, a second source / drain metal layer SD2, and a third source / drain metal layer SD3 as shown in FIG. 1), and a planarization layer (e.g., a first planarization layer PLN1, a second planarization layer PLN2, and a third planarization layer PLN3 as shown in FIG. 1), etc., stacked between the substrate SBT and the pixel layer PIXL. Each thin-film transistor and storage capacitor CST can be formed by the semiconductor layer, the gate insulating layer, the gate layer, the interlayer dielectric layer ILD, the source / drain metal layer, etc.; of course, other film layers can also be used. The positional relationship of each film layer can be determined according to the film layer structure of the thin-film transistor. Furthermore, the semiconductor layer can be used to form the channel region of the transistor (as part of the active layer), and can also be formed into partial traces or conductive structures by conductorization if necessary. The gate layer can be used to form one or more gate layer traces such as scan traces, reset control traces, and light emission control traces, or it can be used to form the gate of the transistor, or it can be used to form part or all of the electrode plates of the storage capacitor CST. The source / drain metal layer can be used to form source / drain metal layer traces such as data traces and power supply voltage traces VDDL (see Figure 12), or it can be used to form part of the electrode plates of the storage capacitor CST. Of course, in other embodiments of this disclosure, the driving layer DRL can also include other film layers as needed, such as a light-shielding layer LS located between the semiconductor layer and the substrate SBT.

[0094] As needed, any one of the aforementioned semiconductor layer, gate layer, source / drain metal layer, etc., can be multiple layers. For example, the driving layer DRL may include two different semiconductor layers, or two or three source / drain metal layers, or two or three gate layers. Correspondingly, the insulating film layers (such as gate insulating layer, interlayer dielectric layer ILD, planarization layer, etc.) in the driving layer DRL can be added or reduced as needed, or new insulating film layers can be added as needed.

[0095] Optionally, the driving layer DRL may also include a passivation layer (not specifically labeled in this figure), which may be disposed on the surface of the source / drain metal layer away from the substrate SBT in order to protect the source / drain metal layer.

[0096] As an example, the driving layer DRL may include a buffer layer (e.g., the first buffer layer Buff1 and the second buffer layer Buff2 shown in FIG1), a semiconductor layer, a gate insulating layer, a gate layer, an interlayer dielectric layer ILD, a source drain metal layer and a planarization layer stacked in sequence, and the thin film transistor formed therein is a top gate thin film transistor.

[0097] In another example, referring to Figure 1, the driving layer DRL may include a first buffer layer Buff1, a low-temperature polysilicon semiconductor layer LSCL, a first gate insulating layer GI1, a first gate layer GT1, a second buffer layer Buff2, a second gate insulating layer GI2, a second gate layer GT2, an interlayer dielectric layer ILD, a metal oxide semiconductor layer OSCL, a third gate insulating layer, a third gate layer GT3, a first source drain metal layer SD1, a first planarization layer PLN1, a second source drain metal layer SD2, a second planarization layer PLN2, a third source drain metal layer SD3, and a third planarization layer PLN3, stacked sequentially.

[0098] Optionally, referring to Figure 1, the pixel layer PIXL may include a pixel electrode layer ANL, a light-emitting functional layer EL, and a common electrode layer COML stacked sequentially. The pixel electrode layer ANL has multiple pixel electrodes in the display area of ​​the display panel (not specifically labeled in the accompanying drawings). The pixel definition layer PDL has multiple through-holes corresponding to the multiple pixel electrodes, with each pixel hole exposing at least a portion of the corresponding pixel electrode. For example, the pixel definition layer PDL covers the edge of the pixel electrode and exposes at least a portion of the internal area of ​​the pixel electrode, so that the pixel definition layer PDL can effectively define the actual effective area of ​​the pixel electrode (the area directly connected to the light-emitting functional layer EL), thereby defining the light-emitting area and light-emitting region of the sub-pixel PIX. The common electrode layer COML covers the light-emitting functional layer EL as a common electrode. The pixel electrodes and the common electrode layer COML provide electrons, holes, and other charge carriers to the light-emitting functional layer EL, causing the light-emitting functional layer EL to emit light. The portion of the light-emitting functional layer EL located between the pixel electrodes and the common electrode layer COML can serve as the light-emitting functional unit of the sub-pixel PIX. A pixel electrode, a common electrode layer (COML), and a light-emitting functional unit form a light-emitting element that serves as a sub-pixel (PIX). One of the pixel electrode and the common electrode layer (COML) serves as the anode of the sub-pixel (PIX), and the other serves as the cathode.

[0099] In this example, the display panel is an OLED (Organic Light Emitting Diode) display substrate. The light-emitting functional layer EL may include an organic light-emitting layer, and may include one or more of the following: a hole injection layer, a hole transport layer, an electron blocking layer, an electron transport layer, and an electron injection layer. Furthermore, the organic light-emitting layer may include a host material and a guest material, wherein the guest material may be a fluorescent dopant or a phosphorescent dopant, and particularly may be a thermally activated delayed fluorescence material.

[0100] It is understood that the display panel can also be other types of display panels, such as QLED (electroluminescent quantum dot) display panels, QD-OLED (electroluminescent quantum dot and organic light-emitting diode) display panels, or other types of display panels.

[0101] Referring to Figure 1, the thin-film encapsulation layer TFE can be disposed on the surface of the pixel layer PIXL away from the substrate SBT, and it can include alternating layers of inorganic and organic encapsulation layers. The inorganic encapsulation layer can effectively block external moisture and oxygen, preventing water and oxygen from invading the pixel layer PIXL and causing material aging of the pixel layer PIXL.

[0102] Optionally, the edge of the inorganic encapsulation layer can be located in the peripheral area. The organic encapsulation layer is located between two adjacent inorganic encapsulation layers to achieve planarization and reduce stress between the inorganic encapsulation layers. The edge of the organic encapsulation layer can be located between the edge of the display area and the edge of the inorganic encapsulation layer.

[0103] For example, the thin-film encapsulation layer TFE includes a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer sequentially stacked on the side of the pixel layer PIXL away from the substrate SBT (not specifically shown in the accompanying drawings). Of course, in other embodiments of this disclosure, the display panel may not have a thin-film encapsulation layer TFE, but may use other methods to encapsulate and protect the pixel layer PIXL.

[0104] In some embodiments of this disclosure, the display panel may further include a touch metal layer (not specifically shown in the accompanying drawings), which may be disposed on the side of the thin-film transistor away from the pixel layer PIXL, so that the display panel has touch functionality.

[0105] In this embodiment, referring to FIG1, the driving layer DRL may further include a transistor layer TL, a first source-drain metal layer SD1, and a second source-drain metal layer SD2; the transistor layer TL is a combination of various film layers disposed between the substrate SBT and the first source-drain metal layer SD1, which can form various thin-film transistors required for the pixel driving circuit.

[0106] Referring to Figure 2, depending on the position of the thin-film transistors, the display area of ​​the display panel may include arrayed circuit regions PA, each circuit region PA having two pixel driving circuits for driving two sub-pixels PIX respectively. Specifically, the circuit region PA may include a first sub-circuit region PA1 and a second sub-circuit region PA2 arranged adjacently along the row direction DH. The first sub-circuit region PA1 contains the thin-film transistors of one pixel driving circuit, and the second sub-circuit region PA2 contains the thin-film transistors of another pixel driving circuit. Furthermore, the capacitors of the pixel driving circuits may also be disposed within the transistors. Of course, at least a portion of the structure of the first source-drain metal layer SD1 can be used as part of the capacitors.

[0107] In this embodiment, referring to FIG2, at least one of the transistor layer TL and the first source-drain metal layer SD1 may be provided with a voltage trace VL extending along the row direction DH. The voltage trace VL may provide a power supply voltage to the pixel driving circuit or reduce the voltage drop of the power supply voltage applied to the pixel driving circuit or the sub-pixel PIX.

[0108] In one embodiment of this disclosure, referring to FIG3, the voltage trace VL may include a reference voltage trace VSL for loading a reference voltage VSS. The reference voltage trace VSL may be electrically connected to the common electrode layer COML of the pixel layer PIXL to reduce the voltage drop of the reference voltage VSS, improve the uniformity of the reference voltage VSS, and thereby improve the image quality of the display panel.

[0109] In one example, the reference voltage trace VSL can be electrically connected to the common electrode layer COML in the peripheral area of ​​the display panel. Furthermore, the reference voltage trace VSL can be located on the first source / drain metal layer SD1 of the drive layer DRL.

[0110] In one example of this implementation, the reference voltage trace VSL can be configured in a one-to-one correspondence with each circuit area row HPA. In other words, each circuit area PA has one reference voltage trace VSL. This maximizes the density of reference voltage traces VSL, thereby improving the uniformity of the reference voltage VSS.

[0111] In another embodiment of this disclosure, referring to FIG3, the voltage trace VL may include an initialization voltage trace VTL for applying an initialization voltage to the pixel driving circuit, so as to reset the voltage of the node or pixel electrode of the pixel driving circuit. Further, the voltage trace VL may be disposed on the transistor layer TL, for example, on the gate layer of the transistor layer TL. It is understood that in this embodiment, the initialization voltage applied to the pixel driving circuit may be one or more. When multiple initialization voltages are applied to the pixel driving circuit, the voltage values ​​of the multiple initialization voltages may be the same or different, and different types of initialization voltages are applied to different initialization voltage traces VTL.

[0112] For example, the initialization voltage trace VTL may include a first initialization voltage trace VTL1 located on the second gate layer GT2 (see Figure 8), and a second initialization voltage trace VTL2 (see Figure 10) and a third initialization voltage trace VTL3 (see Figure 10) located on the third gate layer GT3. The first initialization voltage trace VTL1 has a seventeenth lower via region HA17 at its end, which is connected to the seventeenth upper via region HB17 via a via region. The second initialization voltage trace VTL2 has a sixteenth lower via region HA16 at its end, which is connected to the sixteenth upper via region HB16 via a via region. The third initialization voltage trace VTL3 has a fifteenth upper via region HB15 overlapping with the fifteenth lower via region HA15, which is connected to the fifteenth upper via region HB15 via a via region. Thus, the first electrode of the electrode reset transistor T7 is electrically connected to the second initialization voltage trace VTL2. Of course, in other embodiments of this disclosure, the initialization voltage trace VTL can be entirely located in the first source-drain metal layer SD1.

[0113] Figure 4 is an equivalent circuit diagram of a pixel driving circuit according to an exemplary embodiment of this disclosure. In this pixel driving circuit, the initialization voltage includes a first initialization voltage Vinit1, a second initialization voltage Vinit2, and a third initialization voltage Vinit3, which are respectively applied to different nodes of the pixel driving circuit. Therefore, the transistor layer TL needs to have a first initialization voltage trace VTL1 (see Figure 8) for applying the first initialization voltage Vinit1, a second initialization voltage trace VTL2 (see Figure 10) for applying the second initialization voltage Vinit2, and a third initialization voltage trace VTL3 (see Figure 10) for applying the third initialization voltage Vinit3. Each row of circuit regions PA needs to have a corresponding first initialization voltage trace VTL1, second initialization voltage trace VTL2, and third initialization voltage trace VTL3.

[0114] Taking the pixel driving circuit illustrated in Figure 4 as an example, the pixel driving circuit may include a first capacitor reset transistor T1, a threshold compensation transistor T2, a driving transistor T3, a data writing transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, an electrode reset transistor T7, a second capacitor reset transistor T8, and a storage capacitor CST. Wherein:

[0115] Among them, threshold compensation transistor T2 is an N-type thin-film transistor, such as a metal oxide thin-film transistor; the other thin-film transistors are P-type thin-film transistors, such as low-temperature polycrystalline silicon thin-film transistors.

[0116] Referring to Figure 4, the first terminal of the first capacitor reset transistor T1 is used to load the first initialization voltage Vinit1, the gate is used to load the first capacitor reset control signal Rest1, and the second terminal is connected to the third node N3. The first capacitor reset transistor T1 is used to load the first initialization voltage Vinit1 onto the third node N3 in response to the first capacitor reset control signal Rest1. The first terminal of the threshold compensation transistor T2 is electrically connected to the third node N3, the second terminal is electrically connected to the first node N1, and the gate is used to load the first scan signal GN. The threshold compensation transistor T2 is used to turn on in response to the first scan signal GN to write the first initialization voltage Vinit1 of the first capacitor reset transistor T1 into the first node N1. The first terminal of the driving transistor T3 is connected to the second node N2, the second terminal is connected to the third node N3, and the gate is connected to the first node N1. The driving transistor T3 is configured to output a driving current under the control of the voltage at the control terminal of the driving transistor T3. The first terminal of the data writing transistor T4 is used to load the drive data signal Source, the second terminal is electrically connected to the second node N2, and the gate is used to load the second scan signal GP. The gate of the data writing transistor T4 is used to load the second scan signal GP, while the drive data signal Source is loaded to the second node N2. The first terminal of the first light-emitting control transistor T5 is electrically connected to the fifth node N5, the second terminal is connected to the second node N2, and the gate is used to load the enable signal EM. The first terminal of the second light-emitting control transistor T6 is connected to the third node N3, the second terminal is connected to the fourth node N4, and the gate is used to load the enable signal EM. The first and second light-emitting control transistors T5 and T6 are turned on in response to the enable signal EM. The first terminal of the electrode reset transistor T7 is used to load the second initialization voltage Vinit2, the gate is used to load the second capacitor reset control signal Rest2, and the second terminal is connected to the fourth node N4. The electrode reset transistor T7 is used to load the second initialization voltage Vinit2 to the fourth node N4 in response to the second capacitor reset control signal Rest2. The first terminal of the second capacitor reset transistor T8 is used to apply the third initialization voltage Vinit3, and the gate is used to apply the second capacitor reset control signal Rest2. The second terminal is connected to the second node N2. The second capacitor reset transistor T8 is used to apply the third initialization voltage Vinit3 to the second node N2 in response to the second capacitor reset control signal Rest2. The pixel electrode of the light-emitting element is electrically connected to the driving circuit (not specifically shown in this application), and the common electrode is used to apply the reference voltage VSS. One end of the storage capacitor CST is connected to the first node N1, and the other end is connected to the fifth node N5.

[0117] It is understood that, in the embodiments of this disclosure, the pixel driving circuit may also adopt other forms of pixel driving circuit, such as 7T1C (7 thin film transistors and 1 storage capacitor), 7T2C (7 thin film transistors and 2 storage capacitors), 5T1C (5 thin film transistors and 1 storage capacitor), etc.

[0118] In this embodiment of the disclosure, referring to FIG3, in order to further reduce the voltage drop of the power signal loaded on the voltage trace VL, the distribution of the power signal loaded on the voltage trace VL can be made gridded. In this embodiment of the disclosure, a voltage jumper VLA can be provided on the first source-drain metal layer SD1. The voltage jumper VLA can electrically connect two adjacent identical voltage traces VL, thereby making the voltage trace VL gridded. This can further reduce the voltage drop of the power signal loaded on the voltage trace VL.

[0119] In this embodiment of the disclosure, referring to FIG5, the circuit region PA can be divided into a non-heterogeneous circuit region PAN and a heterogeneous circuit region PAM according to whether a voltage jumper line VLA is provided (see FIG3). Compared to the non-heterogeneous circuit region PAN, the pattern of the first source-drain metal layer SD1 of the heterogeneous circuit region PAM is changed to provide the voltage jumper line VLA, thereby making the voltage signal distribution on the voltage trace VL gridded.

[0120] Specifically, the second source-drain metal layer SD2 is provided with a power supply voltage trace VDDL for loading the power supply voltage VDD (see Figure 12), and the first source-drain metal layer SD1 is provided with a power supply voltage transfer structure VDLP (equivalent to the third bridging part MA3 described in this application) in the circuit area PA; the power supply voltage transfer structure VDLP is electrically connected to the power supply voltage trace VDDL, and is used to simultaneously provide the power supply voltage VDD to the two pixel driving circuits of the circuit area PA.

[0121] The shape of the power supply voltage transfer structure VDLP in the heterogeneous circuit region PAM is different from the shape of the power supply voltage transfer structure VDLP in the non-heterogeneous circuit region PAN, so that the first source-drain metal layer SD1 has a cross-line channel extending along the column direction in the heterogeneous circuit region PAM; the first source-drain metal layer SD1 is provided with a voltage jumper VLA in the cross-line channel, and the voltage jumper VLA is electrically connected to two adjacent voltage traces VL on the column direction DV.

[0122] The following description uses the pixel driving circuit shown in Figure 4 as an example to illustrate one type of film layer structure for a display panel. It is understood that the film layer structure of the display panel can change when the pixel driving circuit is changed. Even if the pixel driving circuit of the display panel is the same as the example in Figure 4, the film layer structure of the display panel can still be adjusted.

[0123] Referring to Figure 6, which is a schematic diagram of the structure of a low-temperature polycrystalline silicon semiconductor layer (LSCL) in a PA of the exemplary display panel, the LSCL is provided with an active layer of a first capacitor reset transistor T1, an active layer of a driving transistor T3, an active layer of a data writing transistor T4, an active layer of a first light-emitting control transistor T5, an active layer of a second light-emitting control transistor T6, an active layer of an electrode reset transistor T7, and an active layer of a second capacitor reset transistor T8. The active layers of the transistors include the first electrode, the second electrode, and the channel region of the transistor.

[0124] The data writing transistor T4, the first light-emitting control transistor T5, and the first driving transistor T3 are electrically connected; the second driving transistor T3 and the first light-emitting control transistor T6 are electrically connected; and the second electrode reset transistor T7 and the second light-emitting control transistor T6 are electrically connected. The first electrode of the first capacitor reset transistor T1 has a first lower via region HA1, and the second electrode of the first capacitor reset transistor T1 has a second lower via region HA2. The first electrode of the data writing transistor T4 has a third lower via region HA3; the second electrode of the driving transistor T3 has a fourth lower via region HA4; the second electrode of the first light-emitting control transistor T5 has a fifth lower via region HA5; the second electrode of the second light-emitting control transistor T6 has a sixth lower via region HA6; the second electrode of the second capacitor reset transistor T8 has a seventh lower via region HA7; the first electrode of the first light-emitting control transistor T5 has an eighth lower via region HA8; the first electrode reset transistor T7 has a ninth lower via region HA9; and the first electrode of the second capacitor reset transistor T8 has a tenth lower via region HA10.

[0125] In one example, the channel region T4A of the data writing transistor and the channel region T5A of the first light-emitting control transistor are arranged along the column direction DV, and the channel regions T5A and T6A of the first and second light-emitting control transistors are arranged along the row direction DH. Along the row direction DH, the channel region T3A of the driving transistor and the channel region T7A of the electrode reset transistor are located between the channel regions T5A and T6A of the first and second light-emitting control transistors; along the column direction DV, the channel region T7A of the electrode reset transistor and the channel region T3A of the driving transistor are located on both sides of the channel region T5A of the first light-emitting control transistor.

[0126] Figure 7 is a schematic diagram of the structure of the first gate layer GT1 in a circuit area PA of the exemplary display panel. Referring to Figure 7, the first gate layer GT1 has a first capacitor reset control signal line RL1, a second capacitor reset control signal line RL2, a third scan signal trace GPL, an enable signal line EML, and a first electrode CP1 of a storage capacitor CST, all extending along the row direction DH. The first capacitor reset control signal line RL1 extends along the row direction DH and is used to load the first capacitor reset control signal Rest1 onto the first capacitor reset transistor T1. The second capacitor reset control signal line RL2 extends along the row direction DH and is used to load the second capacitor reset control signal Rest2 onto the second capacitor reset transistor T8. The enable signal line EML extends along the row direction DH and overlaps sequentially with the channel region T5A of the first light-emitting transistor and the channel region T6A of the second light-emitting transistor, thus multiplexing it as the gate of the first light-emitting transistor T5 and the gate of the second light-emitting transistor T6. The enable signal line EML can be used to load the enable signal EM. The first electrode CP1 of the storage capacitor CST overlaps with the channel region T3A of the driving transistor, and is reused as the gate of the driving transistor T3. The third scan signal trace GPL extends along the row direction DH, and can overlap with the channel region T4A of the data write transistor. The overlapping portion is reused as the gate of the data write transistor T4. The first electrode CP1 of the storage capacitor CST overlaps with the channel region T3A of the driving transistor, and is reused as the gate of the driving transistor T3. The first electrode CP1 of the storage capacitor CST has a thirteenth lower via region HA13.

[0127] Figure 8 is a schematic diagram of the structure of the second gate layer GT2 in a non-heterogeneous circuit area PAN of the exemplary display panel. Referring to Figure 8, the second gate layer GT2 is provided with a first initialization voltage trace VTL1, a second electrode CP2 of the storage capacitor CST, and a second scan signal trace GNLB. The first initialization voltage trace VTL1 extends along the row direction DH and can be used to load the first initialization voltage Vinit1. The second electrode CP2 of the storage capacitor CST overlaps with the first electrode CP1 of the storage capacitor CST, and a clearance hole is provided to expose a portion of the first electrode CP1 of the storage capacitor CST. The second scan signal trace GNLB extends along the row direction DH and is used to load the second scan signal. In the circuit area PA, the second electrode CP2 of the storage capacitor CST is provided with a fourteenth lower via area HA14. In the circuit area PA, the first initialization voltage trace VTL1 is provided with a seventeenth lower via area HA17 in any sub-circuit area (e.g., the first sub-circuit area PA1 or the second sub-circuit area PA2).

[0128] Figure 9 is a schematic diagram of the metal-oxide-semiconductor layer (OSCL) in a circuit area PA of this exemplary display panel. Referring to Figure 9, in any sub-circuit area of ​​circuit area PA (e.g., the first sub-circuit area PA1 or the second sub-circuit area PA2), the OSCL is provided with a second electrode, a first electrode, and a channel region for a threshold compensation transistor T2. In one example, along the column direction DV, the channel region T1A of the first capacitor reset transistor is located on the side of the threshold compensation transistor's channel region T2A away from the channel region T3A of the driving transistor. The channel region T2A of the threshold compensation transistor and the channel region T5A of the first light-emitting control transistor are located on opposite sides of the channel region T3A of the driving transistor. Referring to Figure 9, in any sub-circuit area of ​​circuit area PA (e.g., the first sub-circuit area PA1 or the second sub-circuit area PA2), the second electrode of the threshold compensation transistor T2 is provided with an eleventh lower via region HA11, and the first electrode of the threshold compensation transistor T2 is provided with a twelfth lower via region HA12.

[0129] Figure 10 is a schematic diagram of the structure of the third gate layer GT3 in a non-heterogeneous circuit area PAN of this exemplary display panel. Referring to Figure 10, the third gate layer GT3 is provided with a second initialization voltage trace VTL2, a third initialization voltage trace VTL3, and a first scan signal trace GNLA. The second initialization voltage trace VTL2 extends along the row direction DH and can be used to apply a second initialization voltage Vinit2. The third initialization voltage trace VTL3 extends along the row direction DH and can be used to apply a third initialization voltage Vinit3. The first scan signal trace GNLA extends along the row direction DH and overlaps with the channel region T2A of the threshold compensation transistor. The overlapping portion is multiplexed as the second gate of the threshold compensation transistor T2. Referring to Figure 10, in any sub-circuit region of the non-heterogeneous circuit region PAN (e.g., the first sub-circuit region PA1 or the second sub-circuit region PA2), the third initialization voltage trace VTL3 has a fifteenth lower via region HA15, and the second initialization voltage trace VTL2 has a sixteenth lower via region HA16.

[0130] Figure 11 is a schematic diagram of the structure of the first source / drain metal layer SD1 in a non-heterogeneous circuit area PAN of the exemplary display panel. Referring to Figure 11, in the circuit area PA, the first source / drain metal layer SD1 is provided with a first bridging portion MA1 to a ninth bridging portion MA9.

[0131] Referring to Figure 11, a first bridging portion MA1 is provided in any sub-circuit region of circuit region PA (e.g., the first sub-circuit region PA1 or the second sub-circuit region PA2). The first bridging portion MA1 has an eleventh upper via region HB11 and a thirteenth upper via region HB13; wherein, the eleventh upper via region HB11 overlaps with the eleventh lower via region HA11 and is connected through a via; the thirteenth upper via region HB13 overlaps with the thirteenth lower via region HA13 and is connected through a via. In this way, the second electrode of the threshold compensation transistor T2 is electrically connected to the first electrode CP1 through the first bridging portion MA1.

[0132] Referring to Figure 11, a second bridging section MA2 is provided in any sub-circuit region of circuit region PA (e.g., the first sub-circuit region PA1 or the second sub-circuit region PA2). The second bridging section MA2 has a second upper via region HB2, a fourth upper via region HB4, and a twelfth upper via region HB12. The second upper via region HB2 overlaps with the second lower via region HA2 and is connected through a via; the fourth upper via region HB4 overlaps with the fourth lower via region HA4 and is connected through a via; the twelfth upper via region HB12 overlaps with the twelfth lower via region HA12 and is connected through a via. In this way, the second terminal of the first capacitor reset transistor T1 is electrically connected to the second terminal of the driving transistor T3 through the second bridging section MA2, and the first terminal of the threshold compensation transistor T2 is electrically connected.

[0133] Referring to Figure 11, a third bridging section MA3 is provided in the circuit area PA. The third bridging section MA3 has a fourteenth upper via region HB14, an eighth upper via region HB8, a nineteenth lower via region HA19, and a twenty-first lower via region HA21. The fourteenth upper via region HB14 overlaps with the fourteenth lower via region HA14 and is connected through vias. The eighth upper via region HB8 overlaps with the eighth lower via region HA8 and is connected through vias. The nineteenth upper via region HB19 overlaps with the nineteenth lower via region HA19 and is connected through vias. The twenty-first upper via region HB21 overlaps with the twenty-first lower via region HA21 and is connected through vias. Thus, the second electrode CP2 of the storage capacitor CST and the first electrode of the first light-emitting control transistor T5 can be electrically connected to each other through the third bridging section MA3.

[0134] In one example, referring to Figures 11 and 12, in the non-heterogeneous circuit region PAN, the third bridging portion MA3 has a first sub-transfer structure MA31, a second sub-transfer structure MA32, and a third sub-transfer structure MA33. The first sub-transfer structure MA31 extends along the column direction DV and is located in the middle of the non-heterogeneous circuit region PAN in the row direction DH. It is used to provide power supply voltage VDD to two pixel driving circuits through vias. The first sub-transfer structure MA31 has a nineteenth lower via region HA19. The second sub-transfer structure MA32 has a twenty-first lower via region HA21; the third sub-transfer structure MA33 has a nineteenth lower via region HA19. The second sub-transfer structure MA32 and the third sub-transfer structure MA33 are located on both sides of the first sub-transfer structure MA31 and are electrically connected to the power supply voltage trace VDDL through vias.

[0135] Referring to Figure 11, a fourth bridging section MA4 is provided in any sub-circuit region of circuit region PA (e.g., the first sub-circuit region PA1 or the second sub-circuit region PA2). The fourth bridging section MA4 has a third upper via region HB3 and an eighteenth lower via region HA18. The third upper via region HB3 overlaps with the third lower via region HA3 and is connected through a via. The eighteenth upper via region HB18 overlaps with the eighteenth lower via region HA18 and is connected through a via. In this way, the first terminal of the data writing transistor T4 is connected to the data signal trace DL (see Figure 12) through the fourth bridging section MA4.

[0136] Referring to Figure 11, a fifth bridging section MA5 is provided in any sub-circuit region of circuit region PA (e.g., the first sub-circuit region PA1 or the second sub-circuit region PA2). The fifth bridging section MA5 has a fifth upper via region HB5 and a seventh upper via region HB7. The fifth upper via region HB5 overlaps with the fifth lower via region HA5 and is connected through a via; the seventh upper via region HB7 overlaps with the seventh lower via region HA7 and is connected through a via. In this way, the second terminal of the first light-emitting control transistor T5 is electrically connected to the first terminal of the second capacitor reset transistor T8 through the fifth bridging section MA5.

[0137] Referring to Figure 11, a sixth bridging section MA6 (equivalent to the initialization voltage transfer structure VTLP) is provided in any sub-circuit region of circuit region PA (e.g., the first sub-circuit region PA1 or the second sub-circuit region PA2). The sixth bridging section MA6 has a tenth upper via region HB10 and a fifteenth upper via region HB15. The tenth upper via region HB10 overlaps with the tenth lower via region HA10 and is connected through a via. The fifteenth upper via region HB15 overlaps with the fifteenth lower via region HA15 and is connected through a via. In this way, the third initialization voltage trace VTL3 is electrically connected to the second terminal of the second capacitor reset transistor T8 through the sixth bridging section MA6.

[0138] In one example, referring to Figure 11, in the non-heterogeneous circuit region PAN, the initialization voltage transfer structure VTLP includes a fourth sub-transfer structure MA61, a fifth sub-transfer structure MA62, and a sixth sub-transfer structure MA63. The fourth sub-transfer structure MA61 is located at the connection between the first sub-circuit region PA1 and the second sub-circuit region PA2, and is used to simultaneously provide initialization voltages (e.g., a third initialization voltage Vinit3) to both pixel driving circuits. The fifth sub-transfer structure MA62 is connected to the fourth sub-transfer structure MA61 and located in the second sub-circuit region PA2, and is electrically connected to VTL3 via a via. The sixth sub-transfer structure MA63 is connected to the fourth sub-transfer structure MA61 and located in the first sub-circuit region PA1, and is electrically connected to VTL3 via a via. The ends of the fifth sub-transfer structure MA62 and the sixth sub-transfer structure MA63 furthest from the fourth sub-transfer structure MA61 are each provided with a fifteenth upper via region HB15.

[0139] Referring to Figure 11, a seventh bridging section MA7 is provided in any sub-circuit region of circuit region PA (e.g., the first sub-circuit region PA1 or the second sub-circuit region PA2). The seventh bridging section MA7 has a ninth upper via region HB9 and a sixteenth upper via region HB16. The ninth upper via region HB9 overlaps with the ninth lower via region HA9 and is connected through a via. The sixteenth upper via region HB16 overlaps with the sixteenth lower via region HA16 and is connected through a via. In this way, the second initialization voltage trace VTL2 is electrically connected to the first electrode of the electrode reset transistor T7 through the seventh bridging section MA7.

[0140] Referring to Figure 11, an eighth bridging section MA8 is provided in any sub-circuit region of circuit region PA (e.g., the first sub-circuit region PA1 or the second sub-circuit region PA2). The eighth bridging section MA8 has a first upper via region HB1 and a seventeenth upper via region HB17. The first upper via region HB1 overlaps with the first lower via region HA1 and is connected through a via; the seventeenth upper via region HB17 overlaps with the seventeenth lower via region HA17 and is connected through a via; thus, the first initialization voltage trace VTL1 is electrically connected to the first electrode of the first capacitor reset transistor T1 through the eighth bridging section MA8.

[0141] Referring to Figure 11, a ninth bridging section MA9 is provided in any sub-circuit region of circuit region PA (e.g., the first sub-circuit region PA1 or the second sub-circuit region PA2). The ninth bridging section MA9 has a sixth upper via region HB6 and a twentieth lower via region HA20. The ninth upper via region HB9 and the ninth lower via region HA9 overlap and are connected through vias; the twentieth upper via region HB20 and the twentieth lower via region HA20 overlap and are connected through vias. In this way, the driving current generated by the pixel driving circuit can be transmitted to the ninth bridging section MA9, and then to the sub-pixel.

[0142] Referring to Figure 11, in this example, the first source-drain metal layer SD1 is further provided with a reference voltage trace VSL for loading the reference voltage VSS, and the reference voltage trace VSL extends along the row direction DH. In one example, the reference voltage trace VSL is located between the second bridge portion MA2 and the eighth bridge portion MA8. In one embodiment of this disclosure, each circuit region row HPA is provided with a corresponding reference voltage trace VSL. In this way, a large distribution density of the reference voltage trace VSL can be ensured, thereby further reducing the voltage drop of the reference voltage VSS.

[0143] Figure 12 is a partial structural schematic diagram of the second source-drain metal layer SD2 in this exemplary display panel. Referring to Figure 12, the second source-drain metal layer SD2 includes data signal traces DL and power supply voltage traces VDDL extending along the column direction DV. The second source-drain metal layer SD2 also has a first conductive structure MB1.

[0144] In this configuration, the data signal trace DL is arranged in a one-to-one correspondence with the pixel driving circuit array. Within the sub-circuit area, the data signal trace DL has an eighteenth upper via region HB18. The eighteenth upper via region HB18 overlaps with the eighteenth lower via region HA18 and is electrically connected via a via. Thus, the data signal trace DL is electrically connected to the fourth bridging portion MA4 via a via, thereby connecting the data signal trace DL to the first electrode of the data writing transistor T4. This allows the driving data signal Source loaded on the data signal trace DL to be loaded onto the first electrode of the data writing transistor T4.

[0145] In this configuration, power supply voltage traces VDDL are configured one-to-one with pixel driving circuit columns. In the non-heterogeneous circuit area PAN, each of the two power supply voltage traces VDDL has a nineteenth upper via region HB19 and a twenty-first upper via region HB21. These two via regions overlap with and are electrically connected to the two nineteenth lower via regions HA19 and the twenty-first lower via regions HB21 in the non-heterogeneous circuit area PAN vias. Thus, the third bridging portion MA3 in the non-heterogeneous circuit area PAN is electrically connected to the two power supply voltage traces VDDL vias. Furthermore, the two power supply voltage traces VDDL in the same circuit area column VPA are interconnected to form a single unit. In one example, the power supply voltage trace VDDL may have a protrusion (not specified in this application), which may cover the channel region T2A of the threshold compensation transistor. The protrusions of the two power supply voltage traces VDDL in the same circuit area column VPA are interconnected.

[0146] The first conductive structure MB1 has a twentieth upper via region HB20; the twentieth upper via region HB20 and the twentieth lower via region HA20 in the same sub-circuit region overlap and are electrically connected through vias. Furthermore, the pixel electrode of the sub-pixel is electrically connected to the first conductive structure MB1 in the corresponding sub-circuit region through vias; this allows the driving current generated by the pixel driving circuit in the sub-circuit region to be applied to the corresponding sub-pixel.

[0147] In the embodiments exemplified above, the initialization voltage includes a first initialization voltage Vinit1, a second initialization voltage Vinit2, and a third initialization voltage Vinit3. In this example, the initialization voltage trace VTL includes a first initialization voltage trace VTL1 for loading the first initialization voltage Vinit1, a second initialization voltage trace VTL2 for loading the second initialization voltage Vinit2, and a third initialization voltage trace VTL3 for loading the third initialization voltage Vinit3. In the examples of Figures 8 and 10, the first initialization voltage trace VTL1 is disposed on the second gate layer GT2, and the second initialization voltage trace VTL2 and the third initialization voltage trace VTL3 are disposed on the third gate layer GT3. It is understood that in other embodiments of this disclosure, the first initialization voltage trace VTL1, the second initialization voltage trace VTL2, and the third initialization voltage trace VTL3 may also be disposed on other film layers.

[0148] In this embodiment, the shape of the power supply voltage transfer structure VDLP in the heterogeneous circuit region PAM is different from the shape of the power supply voltage transfer structure VDLP in the non-heterogeneous circuit region PAN, so that the first source-drain metal layer SD1 has a cross-line channel extending along the column direction DV in the heterogeneous circuit region PAM. The first source-drain metal layer SD1 is provided with a voltage jumper line VLA in the heterogeneous circuit region PAM, and the voltage jumper line VLA is electrically connected to two adjacent voltage traces VL that carry the same signal.

[0149] It is understandable that when the driving layer DRL has multiple voltage traces VL, the voltage jumper VLA is used to electrically connect adjacent traces of the same voltage type VL. In this embodiment, since the power supply voltage transfer structure VDLP simultaneously provides power supply voltage VDD to two pixel driving circuits in the driving circuit area PA, even if the power supply voltage transfer structure VDLP deforms to avoid the jumper channel, it will not affect the power supply to the pixel driving circuit.

[0150] In one embodiment of this disclosure, a reference voltage trace VSL is disposed on the first source-drain metal layer SD1 and corresponds one-to-one with each circuit region row HPA, that is, each circuit region row HPA has a corresponding reference voltage trace VSL. In this embodiment, the heterogeneous circuit region PAM includes a reference heterogeneous circuit region PAMS. Referring to FIG13, the first source-drain metal layer SD1 has a reference voltage jumper VSLA, which serves as a voltage jumper VLA, in the cross-line channel of the reference heterogeneous circuit region PAMS. The reference voltage jumper VSLA can electrically connect two adjacent reference voltage traces VSL. In this example, the reference voltage jumper VSLA can be directly connected to the reference voltage trace VSL.

[0151] In one embodiment of this disclosure, the heterogeneous circuit region PAM includes an initialization heterogeneous circuit region PAMT, and the voltage jumper VLA includes an initialization voltage jumper VTLA located in the initialization heterogeneous circuit region PAMT and electrically connecting two adjacent initialization voltage traces VTL. Further, a reference voltage trace VSL is interrupted at the jumper channel of the initialization heterogeneous circuit region PAMT to form a break gap (as part of the jumper channel), and the initialization voltage jumper VTLA passes through the break gap of the reference voltage trace VSL.

[0152] In one example of this implementation, there are at least two types of initialization voltage traces (VTLs); in each initialization heterogeneous circuit region (PAMT), only one type of initialization voltage trace (VTL) corresponding to an initialization voltage jumper (VTLA) is provided.

[0153] In one example, the initialization voltage trace VTL includes a first initialization voltage trace VTL1 for applying a first initialization voltage Vinit1 to the pixel driving circuit. Referring to Figure 14, the initialization heterogeneous circuit region PAMT includes a first initialization heterogeneous circuit region PAMT1, and the first source-drain metal layer SD1 has a cross-line channel in the first initialization heterogeneous circuit region PAMT1 and a first initialization voltage jumper VTL1A located in the cross-line channel; the two ends of the first initialization voltage jumper VTL1A are electrically connected to two adjacent first initialization voltage traces VTL1 respectively (see Figure 25).

[0154] In one example, the first source / drain metal layer SD1 has an eighth bridge portion MA8 in the circuit region PA. The eighth bridge portion MA8 is connected to the first initialization voltage trace VTL1 through a via, and is also connected to the thin-film transistor of the pixel driving circuit through the via. In the first initialization heterogeneous circuit region PAMT1, the two ends of the first initialization voltage jumper VTL1A are respectively electrically connected to the eighth bridge portion MA8 that is electrically connected to the two first initialization voltage traces VTL1. In this way, the first initialization voltage jumper VTL1A connects the two eighth bridge portions MA8, thereby electrically connecting the two first initialization voltage traces VTL1. For example, in the example of FIG14, two adjacent eighth bridge portions MA8 in the same column are electrically connected through the first initialization voltage jumper VTL1A located in the first initialization heterogeneous circuit region PAMT1, thereby electrically connecting the first initialization voltage traces VTL1 in adjacent rows (see FIG25).

[0155] In one example, in the first initialization heterogeneous circuit region PAMT1, the reference voltage trace VSL has a break gap CG, and the first initialization voltage jumper VTL1A passes through the break gap CG of the reference voltage trace VSL (as part of the jumper channel). In this example, although the reference voltage trace VSL is provided with a break gap CG in the first initialization heterogeneous circuit region PAMT1 and is a discontinuous set of multiple sub-traces, the sub-traces located in different circuit region rows HPA can be electrically connected through the reference voltage jumper VSLA (see Figure 23), thereby connecting the individual sub-traces to form a mesh, and thus making the reference voltage VSS distributed in a mesh on the first source-drain metal layer SD1.

[0156] In one example, the initialization voltage trace VTL includes a second initialization voltage trace VTL2 for applying a second initialization voltage Vinit2 to the pixel driving circuit; referring to Figures 15 and 27, the initialization heterogeneous circuit region PAMT includes a second initialization heterogeneous circuit region PAMT2, and the first source-drain metal layer SD1 has a cross-line channel in the second initialization heterogeneous circuit region PAMT2; the first source-drain metal layer SD1 has a second initialization voltage jumper VTL2A disposed in the cross-line channel (see Figure 15). The two ends of the second initialization voltage jumper VTL2A are electrically connected to two adjacent second initialization voltage traces VTL2 respectively (see Figure 22).

[0157] In one example, the first source / drain metal layer SD1 is provided with a seventh bridging portion MA7, which is connected to the second initialization voltage trace VTL2 via a via, and is also connected to the thin-film transistor of the pixel driving circuit via a via. In the second initialization heterogeneous circuit region PAMT2, the two ends of the second initialization voltage jumper VTL2A are respectively electrically connected to the seventh bridging portion MA7 that is electrically connected to the two second initialization voltage traces VTL2. In this way, the second initialization voltage jumper VTL2A connects the two seventh bridging portions MA7, thereby electrically connecting the two second initialization voltage traces VTL2. For example, in the example of FIG15, two adjacent seventh bridging portions MA7 in the same column are electrically connected through the second initialization voltage jumper VTL2A located in the second initialization heterogeneous circuit region PAMT2, thereby electrically connecting the second initialization voltage traces VTL2 in adjacent rows (see FIG22 and FIG27).

[0158] In one example, referring to Figure 23, in the second initialization heterogeneous circuit region PAMT2, the reference voltage trace VSL has a break gap CG, and the second initialization voltage jumper VTL2A passes through the break gap CG of the reference voltage trace VSL (as part of the jumper channel). In this example, although the reference voltage trace VSL is provided with a break gap CG in the second initialization heterogeneous circuit region PAMT2 and is a discontinuous set of multiple sub-traces, the sub-traces located in different circuit region rows HPA can be electrically connected through the reference voltage jumper VSLA, thereby connecting the individual sub-traces to form a mesh, and thus making the reference voltage VSS appear as a mesh on the first source-drain metal layer SD1.

[0159] In one example, the initialization voltage trace VTL includes a third initialization voltage trace VTL3 for applying a third initialization voltage Vinit3 to the pixel driving circuit. Referring to Figures 5 and 16, the initialization heterogeneous circuit region PAMT includes a third initialization heterogeneous circuit region PAMT3. The first source-drain metal layer SD1 has a cross-line channel in the third initialization heterogeneous circuit region PAMT3; the first source-drain metal layer SD1 provides a third initialization voltage jumper VTL3A in the cross-line channel of the third initialization heterogeneous circuit region PAMT3, and the two ends of the third initialization voltage jumper VTL3A are electrically connected to two adjacent third initialization voltage traces VTL3 respectively (see Figure 26).

[0160] In one example, the first source / drain metal layer SD1 has a sixth bridge portion MA6 in the circuit region PA. The sixth bridge portion MA6 is connected to the third initialization voltage trace VTL3 through a via, and is also connected to the thin-film transistor of the pixel driving circuit through the via. In the third initialization heterogeneous circuit region PAMT3, the two ends of the third initialization voltage jumper VTL3A are respectively electrically connected to the sixth bridge portion MA6 that is electrically connected to the two third initialization voltage traces VTL3. In this way, the third initialization voltage jumper VTL3A connects the two sixth bridge portions MA6, thereby electrically connecting the two third initialization voltage traces VTL3. For example, in the example of FIG16, two adjacent sixth bridge portions MA6 in the same column are electrically connected through the third initialization voltage jumper VTL3A located in the third initialization heterogeneous circuit region PAMT3, thereby electrically connecting the third initialization voltage traces VTL3 in two adjacent columns.

[0161] In one example, in the third initialization heterogeneous circuit region PAMT3, the reference voltage trace VSL has a break gap CG, and the third initialization voltage jumper VTL3A passes through the break gap CG of the reference voltage trace VSL (as part of the jumper channel). In this example, although the reference voltage trace VSL is a discontinuous set of multiple sub-traces with a break gap CG in the third initialization heterogeneous circuit region PAMT3, the sub-traces located in different circuit region rows HPA can be electrically connected through the reference voltage jumper VSLA, thereby connecting the sub-traces to form a mesh, and thus making the reference voltage VSS appear as a mesh on the first source-drain metal layer SD1.

[0162] In one embodiment of this disclosure, the two pixel driving circuits in the circuit region PA can be arranged symmetrically overall, that is, symmetrically along an axis of symmetry extending along the column direction. It is understood that the symmetrical arrangement of the two pixel driving circuits in the circuit region PA does not mean that the patterns of each film layer of the circuit region PA are symmetrically arranged, but rather that the relative positions of the transistors of the two pixel driving circuits in the circuit region PA are substantially symmetrical. Of course, the driving layer DRL can also have a symmetrically arranged pattern in at least a portion of the film layers of the circuit region PA.

[0163] In one embodiment of this disclosure, referring to FIG6, the first light-emitting control transistor T5 in the first sub-circuit region PA1 and the first light-emitting control transistor T5 in the second sub-circuit region PA2 are arranged adjacent to each other, and the first terminals of the two first light-emitting control transistors T5 can be electrically connected to each other. The power supply voltage transfer structure VDLP in circuit region PA can be electrically connected to the first terminals of the two first light-emitting control transistors T5 through a via. For example, the eighth lower via region HA8 and the eighth upper via region HB8 can be located on the boundary line between the first sub-circuit region PA1 and the second sub-circuit region PA2, which can reduce the number of vias and thus help improve the resolution of the display panel.

[0164] In one embodiment of this disclosure, the cross-line channel of the heterogeneous circuit region PAM is disposed in the first sub-circuit region PA1 of the heterogeneous circuit region PAM. Referring to FIG11, in the non-heterogeneous circuit region PAN, the pattern of the first source-drain metal layer SD1 in the first sub-circuit region PA1 is axially symmetrically disposed with respect to the pattern in the second sub-circuit region PA2. Referring to FIG11, FIG13-16, the pattern of the first source-drain metal layer SD1 in the second sub-circuit region PA2 of the non-heterogeneous circuit region PAN is the same as the pattern in the second sub-circuit region PA2 of the heterogeneous circuit region PAM; the pattern of the first source-drain metal layer SD1 in the first sub-circuit region PA1 of the heterogeneous circuit region PAM is different from the pattern in the first sub-circuit region PA1 of the non-heterogeneous circuit region PAN. Further, the pattern of the first source-drain metal layer SD1 in the area other than the cross-line channel in the first sub-circuit region PA1 of the heterogeneous circuit region PAM is the same as the pattern of the first source-drain metal layer SD1 in the same area of ​​the first sub-circuit region PA1 of the non-heterogeneous circuit region PAN.

[0165] In one embodiment of this disclosure, referring to Figures 13-16, in the heterogeneous circuit region PAM, the third bridging portion MA3 is composed of a first sub-transfer structure MA31 and a second sub-transfer structure MA32. In other words, in the heterogeneous circuit region PAM, the third bridging portion MA3 does not have a third sub-transfer structure MA33 to avoid crossing the cross-line channel.

[0166] In one example, referring to Figures 13-16, the first sub-transition structure MA31 is disposed at the connection between the first sub-circuit region PA1 and the second sub-circuit region PA2, and the second sub-transition structure MA32 is disposed in the second sub-circuit region PA2. The first sub-circuit region PA1 of the non-heterogeneous circuit region PAN is provided with a third sub-transition structure MA33, while the first sub-circuit region PA1 of the heterogeneous circuit region PAM is not provided with a third sub-transition structure MA33.

[0167] In one embodiment of this disclosure, the pixel driving circuit includes a threshold compensation transistor T2 for threshold compensation of the driving transistor T3. Referring to Figures 13-16, any sub-circuit region (e.g., either the first sub-circuit region PA1 or the second sub-circuit region PA2) is provided with a first bridging portion MA1, which electrically connects the second terminal of the threshold compensation transistor T2 to the gate of the driving transistor T3. In the first sub-circuit region PA1 of the heterogeneous circuit region PAM, a voltage bridging line VLA is provided between the first bridging portion MA1 and the third bridging portion MA3.

[0168] It should be noted that in the display panel disclosed herein, the pixel driving circuit can reduce the leakage current of the first node N1 by setting the threshold compensation transistor T2 as a metal oxide transistor, thereby improving the voltage holding capability of the pixel driving circuit, reducing the risk of flickering of the display panel under low-frequency driving, and reducing the power consumption of the display panel.

[0169] In one embodiment of this disclosure, the first source-drain metal layer SD1 is further provided with an initialization voltage transfer structure VTLP (e.g., the sixth bridge part MA6) in the circuit region PA. The voltage trace VL includes an initialization voltage trace VTL (e.g., the third initialization voltage trace VTL3) located in the transistor layer and used to load the initialization voltage. The initialization voltage transfer structure is electrically connected to the initialization voltage trace VTL and is used to simultaneously provide an initialization voltage (e.g., Vinit3) to the two pixel driving circuits in the circuit region PA.

[0170] The shape of the initial voltage transfer structure in the non-heterogeneous circuit region PAN is different from that in the heterogeneous circuit region PAM, so that the initial voltage transfer structure VTLP in the heterogeneous circuit region PAM avoids the cross-line channel.

[0171] In this embodiment, the initialization voltage transfer structure VTLP in the heterogeneous circuit region PAM is also deformed to avoid the cross-line channel.

[0172] Optionally, the two thin-film transistors connected to the initialization voltage transfer structure VTLP are arranged adjacently, so that the initialization voltage transfer structure VTLP simultaneously drives two pixel driving circuits through a via. For example, the second capacitor reset transistor T8 in the first sub-circuit region PA1 and the second capacitor reset transistor T8 in the second sub-circuit region PA2 are arranged adjacently, and the first terminals of the two second capacitor reset transistors T8 are shared and a tenth lower via region HA10 is provided. The tenth lower via region HA10 and the tenth upper via region HB10 are located on the boundary line between the first sub-circuit region PA1 and the second sub-circuit region PA2. The first source-drain metal layer SD1 is provided with a sixth bridge part MA6 as the initialization voltage transfer structure, which simultaneously applies a third initialization voltage Vinit3 to the second capacitor reset transistors T8 of the two sub-circuit regions through a via.

[0173] In one embodiment of this disclosure, referring to Figures 13-16, in the heterogeneous circuit region PAM, the sixth bridging section MA6 is composed of a fourth sub-transfer structure MA61 and a fifth sub-transfer structure MA62. In other words, in the heterogeneous circuit region PAM, the sixth bridging section MA6 does not have a sixth sub-transfer structure MA63 to avoid crossing the cross-line channel.

[0174] In one example, referring to Figures 13-16, the fourth sub-transition structure MA61 is disposed at the connection between the first sub-circuit region PA1 and the second sub-circuit region PA2, and it has a tenth upper via region HB10; the fifth sub-transition structure MA62 is disposed in the second sub-circuit region PA2. The first sub-circuit region PA1 of the non-heterogeneous circuit region PAN is provided with a sixth sub-transition structure MA63, while the first sub-circuit region PA1 of the heterogeneous circuit region PAM is not provided with a sixth sub-transition structure MA63.

[0175] In the example of Figure 16, although a portion of the third initialization voltage jumper VTL3A is the same as or similar to the sixth sub-transition structure MA63, the fifth upper via region HB15, which is electrically connected to the third initialization voltage trace VTL3, is not provided on the third initialization voltage jumper VTL3A, and therefore it can be disregarded as the sixth sub-transition structure MA63. Alternatively, the fifth upper via region HB15 can be provided at the overlap between the third initialization voltage jumper VTL3A and the third initialization voltage trace VTL3, allowing the third initialization voltage jumper VTL3A to be directly electrically connected to the third initialization voltage trace VTL3 via.

[0176] In this embodiment, the shape of the third gate layer GT3 in the non-heterogeneous circuit region PAN may differ from its shape in the heterogeneous circuit region PAM. Figure 17 illustrates the structure of the third gate layer GT3 in the heterogeneous circuit region PAM in one embodiment. Figure 10 illustrates the structure of the third gate layer GT3 in the non-heterogeneous circuit region PAN in one embodiment. In the non-heterogeneous circuit region PAN, the third initialization voltage trace VTL3 has two bulges, each bulge having a fifteenth lower via region HA15 for electrical connection to the sixth bridge portion MA6 via. In other words, in the non-heterogeneous circuit region PAN, the third initialization voltage trace VTL3 has a bulge in the first sub-circuit region PA1 for electrical connection to the sixth sub-transition structure MA63, and a bulge in the second sub-circuit region PA2 for electrical connection to the fifth sub-transition structure MA62. In the heterogeneous circuit region PAM, the third initialization voltage trace VTL3 has one bulge; this bulge has a fifteenth lower via region HA15 for electrical connection to the sixth bridge portion MA6 via. In other words, in the heterogeneous circuit region PAM, the third initialization voltage trace VTL3 has an enlargement for electrical connection with the fifth sub-transfer structure MA62 only in the second sub-circuit region PA2, and no enlargement for electrical connection with the sixth sub-transfer structure MA63 is provided in the first sub-circuit region PA1.

[0177] Of course, in other embodiments of this disclosure, the third gate layer GT3 may have the same shape in both the non-heterogeneous circuit region PAN and the heterogeneous circuit region PAM.

[0178] In one embodiment of this disclosure, in the circuit area row HPA, the non-heterogeneous circuit area PAN and the heterogeneous circuit area PAM are alternately arranged. This ensures a gridded distribution of the power signal, guarantees grid density, and improves the uniformity of the power signal.

[0179] In one embodiment of this disclosure, in the circuit area column VPA, the non-heterogeneous circuit area PAN and the heterogeneous circuit area PAM are alternately arranged. This ensures a gridded distribution of the power signal, guarantees grid density, and improves the uniformity of the power signal.

[0180] In one example, within the same circuit area column VPA, the heterogeneous circuit area PAM is the same heterogeneous circuit area PAM.

[0181] In one embodiment of this disclosure, at least one reference heterogeneous circuit region (PAMS) is provided between two adjacent initialization heterogeneous circuit regions (PAMTs) along the row direction DH. For example, two reference heterogeneous circuit regions (PAMSs) are provided between two adjacent initialization heterogeneous circuit regions (PAMTs) along the row direction DH. On the one hand, this allows the reference voltage trace VSSL to maintain a meshed connection even when it is isolated in the initialization heterogeneous circuit region (PAMT). On the other hand, it results in a high mesh density for the reference voltage VSS, further improving the signal uniformity of the reference voltage VSS (see, for example, Figures 27 and 28, Figure 27 being a schematic diagram of the arrangement of the second initialization heterogeneous circuit region (PAMT2) and the reference heterogeneous circuit region (PAMS), and Figure 28 being a schematic diagram of the arrangement of the third initialization heterogeneous circuit region (PAMT3) and the reference heterogeneous circuit region (PAMS).

[0182] In one embodiment of this disclosure, along the row direction DH, the first initialization heterogeneous circuit region PAMT1, the second initialization heterogeneous circuit region PAMT2, the third initialization heterogeneous circuit region PAMT3, and the second initialization heterogeneous circuit region PAMT2 are arranged periodically in sequence. In this embodiment, the grid density of the second initialization voltage Vinit2 is greater than that of the first initialization voltage Vinit1 and the third initialization voltage Vinit3, which allows the more critical second initialization voltage Vinit2 to have better signal stability, thereby improving the image quality of the display panel.

[0183] It is understandable that if the stability of the first initialization voltage Vinit1 is more critical to the stability of the pixel driving circuit, the number of first initialization heterogeneous circuit regions PAMT1 can be greater than that of the second initialization heterogeneous circuit regions PAMT2 and the third initialization heterogeneous circuit regions PAMT3. Similarly, if the stability of the third initialization voltage Vinit3 is more critical to the stability of the pixel driving circuit, the number of third initialization heterogeneous circuit regions PAMT3 can be greater than that of the second initialization heterogeneous circuit regions PAMT2 and the first initialization heterogeneous circuit regions PAMT1.

[0184] In one embodiment of this disclosure, referring to Figures 5-1 and 5-2 (in Figure 5-2, N represents the non-heterogeneous circuit region PAN, S represents the reference heterogeneous circuit region PAMS, 1 represents the first initialized heterogeneous circuit region PAMT1, 2 represents the second initialized heterogeneous circuit region PAMT2, and 3 represents the third initialized heterogeneous circuit region PAMT3), in the same circuit region column VPA, the heterogeneous circuit regions PAM are of the same type. In one example, the circuit region column VPA containing the reference heterogeneous circuit region PAMS is marked as S; then the circuit region column VPA marked as S includes the non-heterogeneous circuit region PAN and the reference heterogeneous circuit region PAMS, which are alternately arranged along the column direction DV. The circuit region column VPA containing the first initialized heterogeneous circuit region PAMT1 is marked as 1; then the circuit region column VPA marked as 1 includes the non-heterogeneous circuit region PAN and the first initialized heterogeneous circuit region PAMT1, which are alternately arranged along the column direction DV. If the circuit area column VPA containing the second initial heterogeneous circuit area PAMT2 is marked as 2, then the circuit area column VPA marked as 2 includes the non-heterogeneous circuit area PAN and the second initial heterogeneous circuit area PAMT2, which are alternately arranged along the column direction DV. If the circuit area column VPA containing the third initial heterogeneous circuit area PAMT3 is marked as 3, then the circuit area column VPA marked as 3 includes the non-heterogeneous circuit area PAN and the third initial heterogeneous circuit area PAMT3, which are alternately arranged along the column direction DV. In at least a portion of the display area, the arrangement of 24 consecutive circuit area columns VPA can be 1SS1SS2SS2SS3SS3SS2SS2SS (see Figures 21-24).

[0185] In another embodiment of this disclosure, referring to Figures 20-1 and 20-2 (in Figure 20-2, N represents the non-heterogeneous circuit region PAN, S represents the reference heterogeneous circuit region PAMS, 1 represents the first initialized heterogeneous circuit region PAMT1, 2 represents the second initialized heterogeneous circuit region PAMT2, and 3 represents the third initialized heterogeneous circuit region PAMT3), in the same circuit region column VPA, the heterogeneous circuit regions PAM are of the same type. In one example, the circuit region column VPA containing the reference heterogeneous circuit region PAMS is marked as S. The circuit region column VPA marked as S includes the non-heterogeneous circuit region PAN and the reference heterogeneous circuit region PAMS, which are alternately arranged along the column direction DV. The circuit region column VPA containing the first initialized heterogeneous circuit region PAMT1 is marked as 1. The circuit region column VPA marked as 1 includes the non-heterogeneous circuit region PAN and the first initialized heterogeneous circuit region PAMT1, which are alternately arranged along the column direction DV. 1. The circuit column VPA containing the second initialization heterogeneous circuit area PAMT2 is marked as 2. The circuit column VPA marked as 2 includes the non-heterogeneous circuit area PAN and the second initialization heterogeneous circuit area PAMT2, which are alternately arranged along the column direction DV. The circuit column VPA containing the third initialization heterogeneous circuit area PAMT3 is marked as 3. The circuit column VPA marked as 3 includes the non-heterogeneous circuit area PAN and the third initialization heterogeneous circuit area PAMT3, which are alternately arranged along the column direction DV. In at least a portion of the display area, the arrangement of 24 consecutive circuit column VPAs can be 1SS3SS2SS2SS3SS1SS2SS2SS. This makes the distribution of the first initialization voltage jumper VTL1A and the third initialization voltage jumper VTL3A more uniform, which is beneficial to improving the uniformity of the first initialization voltage Vinit1 and the third initialization voltage Vinit3 (see Figures 25 and 26).

[0186] In one embodiment of this disclosure, referring to FIG1, the driving layer DRL may further include a third source / drain metal layer SD3 located on the side of the second source / drain metal layer SD2 away from the first source / drain metal layer SD1; a second planarization layer PLN2 is disposed between the second source / drain metal layer SD2 and the third source / drain metal layer SD3, and a third planarization layer PLN3 is disposed on the side of the third source / drain metal layer SD3 away from the second source / drain metal layer SD2. In other words, the driving layer DRL includes the second source / drain metal layer SD2, the second planarization layer PLN2, the third source / drain metal layer SD3, and the third planarization layer PLN3 stacked sequentially.

[0187] In one example, referring to Figure 18, the third source / drain metal layer SD3 can be provided with a reference voltage grid VSSW, which can be electrically connected to the common electrode layer COML in the peripheral region. This can further reduce the voltage drop of the reference voltage VSS and improve the uniformity of the reference voltage VSS.

[0188] In some implementations, the reference voltage grid VSSW includes a first reference voltage segment VSSW1 extending along the column direction DV and a second reference voltage segment VSSW2 extending along the row direction DH; the two ends of the first reference voltage segment VSSW1 are directly or indirectly connected to the adjacent second reference voltage segment VSSW2, thereby forming a grid structure.

[0189] In some examples, the reference voltage grid VSSW also includes a third reference voltage segment VSSW3 that connects the first reference voltage segment VSSW1 to the second reference voltage segment VSSW2. The shape of the third reference voltage segment VSSW3 is not limited; for example, it can be a zigzag structure or a multi-branch structure with multiple connecting arms. The adjacent ends of the first reference voltage segment VSSW1 and the second reference voltage segment VSSW2 are interconnected through the third reference voltage segment VSSW3, thereby forming a grid. It is understood that some portions of the third reference voltage segment VSSW3 may also extend along the row direction DH or along the column direction DV. Optionally, referring to Figure 19, multiple sub-pixels (PIX) are disposed within the cutouts of the reference voltage grid VSSW. For example, four sub-pixels (PIX) may be disposed within the cutouts of the reference voltage grid VSSW. In one example, four adjacent sub-pixels (PIX) in the same row are located within the same cutout.

[0190] In one embodiment of this disclosure, referring to FIG19, the reference voltage grid VSSW has a first reference voltage line segment VSSW1 extending along the column direction DV; along the row direction DH, the first reference voltage line segment VSSW1 is located between the blue sub-pixel BPIX and the red sub-pixel RPIX; wherein, the distance between the first reference voltage line segment VSSW1 and the blue sub-pixel BPIX is less than the distance between the first reference voltage line segment VSSW1 and the red sub-pixel RPIX.

[0191] This prevents the traces of the reference voltage grid VSSW from entering the area of ​​the blue sub-pixel PIX, avoids one side of the blue sub-pixel PIX from being raised and affecting its flatness, and thus avoids color shift problems.

[0192] In one embodiment of this disclosure, referring to FIG19, a planar structure (not specifically labeled in the accompanying drawings) exists between the sub-pixel PIX and the second source / drain metal layer SD2. This planar structure includes a sub-film layer located in the second planarization layer PLN2 and a sub-film layer located in the third planarization layer PLN3. In this example, the planar portion beneath the sub-pixel PIX includes two planarization layers with a large thickness and strong planarization performance, which can improve the planarity of the sub-pixel PIX and reduce the possibility of color shift.

[0193] In one embodiment of this disclosure, referring to FIG12, the second source / drain metal layer SD2 has a power supply voltage trace VDDL extending along the column direction DV. The power supply voltage trace VDDL includes a light-shielding portion and a cutout portion arranged sequentially along the column direction DV (the light-shielding portion and the cutout portion are not labeled in the accompanying drawings). At least one sub-pixel PIX is located on the light-shielding portion by its orthographic projection onto the second source / drain metal layer SD2. For example, a green sub-pixel PIX is disposed on the light-shielding portion.

[0194] This disclosure also provides a display device, which includes the display panel provided in the above embodiments.

[0195] The display device can be a smartphone screen, a smartwatch screen, or other types of display devices. Since the display device has any of the display panels described in the above-described display panel embodiments, it has the same beneficial effects, and will not be repeated here.

[0196] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A display panel comprising an array of circuit regions, each of the circuit regions being provided with two pixel driving circuits for driving two sub-pixels respectively; The display panel comprises a substrate, a transistor layer, a first source-drain metal layer, a second source-drain metal layer and a pixel layer which are sequentially stacked; The transistor layer is provided with thin film transistors of the pixel driving circuits; at least one of the transistor layer and the first source-drain metal layer is provided with voltage traces extending in a row direction; The second source-drain metal layer is provided with a power voltage trace for loading a power voltage; the first source-drain metal layer is provided with a power voltage switching structure in the circuit region; the power voltage switching structure is electrically connected with the power voltage trace for simultaneously providing the power voltage to the two pixel driving circuits of the circuit region; wherein The circuit region comprises a non-heterogeneous circuit region and a heterogeneous circuit region; The shape of the power voltage switching structure in the heterogeneous circuit region is different from that in the non-heterogeneous circuit region, so that the first source-drain metal layer has a cross-line channel extending in a column direction in the heterogeneous circuit region; The first source-drain metal layer is provided with a voltage cross-line in the cross-line channel, the voltage cross-line being electrically connected with two voltage traces adjacent in the column direction.

2. The display panel of claim 1, wherein, The voltage traces comprise reference voltage traces provided in the first source-drain metal layer for loading a reference voltage; The heterogeneous circuit region comprises a reference heterogeneous circuit region, and the voltage cross-line comprises a reference voltage cross-line in the reference heterogeneous circuit region, the reference voltage cross-line electrically connecting two reference voltage traces adjacent in the column direction.

3. The display panel of claim 2, wherein, The voltage traces further comprise initialization voltage traces provided in the transistor layer for loading an initialization voltage to the pixel driving circuits; The heterogeneous circuit region further comprises an initialization heterogeneous circuit region, and the voltage cross-line further comprises an initialization voltage cross-line, the initialization voltage cross-line being in the initialization heterogeneous circuit region and electrically connecting two initialization voltage traces adjacent in the column direction; The reference voltage traces are interrupted at the cross-line channel of the initialization heterogeneous circuit region, and the initialization voltage cross-line passes through the interruption gap of the reference voltage traces.

4. The display panel of claim 3, wherein, There are at least two types of initialization voltage traces, and in each initialization heterogeneous circuit region, only the initialization voltage cross-line corresponding to one type of initialization voltage trace is provided.

5. The display panel of claim 1, wherein, In the non-heterogeneous circuit region, the power voltage switching structure has a first sub-switching structure, a second sub-switching structure and a third sub-switching structure; The first sub-switching structure extends in the column direction and is located in the middle of the non-heterogeneous circuit region in the row direction, for simultaneously providing the power voltage to the two pixel driving circuits; the second sub-switching structure and the third sub-switching structure are respectively located on both sides of the first sub-switching structure and are respectively electrically connected with the power voltage trace through a via hole; In the heterogeneous circuit region, the power voltage switching structure is composed of the first sub-switching structure and the second sub-switching structure.

6. The display panel of claim 3, wherein, The first source-drain metal layer is further provided with an initialization voltage switching structure in the circuit region, the voltage trace includes an initialization voltage trace located in the transistor layer and used for loading an initialization voltage; the initialization voltage switching structure is electrically connected with the initialization voltage trace, and is used for simultaneously providing the initialization voltage to two pixel driving circuits in the circuit region; The shape of the initialization voltage switching structure in the non-heterogeneous circuit region is different from the shape of the initialization voltage switching structure in the heterogeneous circuit region, so that the initialization voltage switching structure in the heterogeneous circuit region avoids the cross-line channel.

7. The display panel of claim 6, wherein, In the non-heterogeneous circuit region, the initialization voltage switching structure includes a fourth sub-switching structure, a fifth sub-switching structure and a sixth sub-switching structure connected in sequence; The fifth sub-switching structure and the sixth sub-switching structure are respectively arranged on both sides of the fourth sub-switching structure in the row direction, and are respectively electrically connected with the initialization voltage trace through a via hole; the fourth sub-switching structure simultaneously provides the initialization voltage to two pixel driving circuits in the circuit region through a via hole; In the heterogeneous circuit region, the initialization voltage switching structure is composed of the fourth sub-switching structure and the fifth sub-switching structure.

8. The display panel of claim 1, wherein, The circuit region includes a first sub-circuit region and a second sub-circuit region adjacent in the row direction; the first sub-circuit region and the second sub-circuit region are respectively provided with the pixel driving circuit; The cross-line channel of the heterogeneous circuit region is arranged in the first sub-circuit region of the heterogeneous circuit region; In the non-heterogeneous circuit region, the pattern of the first source-drain metal layer in the first sub-circuit region is symmetrically arranged with the pattern in the second sub-circuit region; The pattern of the first source-drain metal layer in the second sub-circuit region of the non-heterogeneous circuit region is the same as the pattern in the second sub-circuit region of the heterogeneous circuit region; The pattern of the first source-drain metal layer in the first sub-circuit region of the heterogeneous circuit region is different from the pattern in the first sub-circuit region of the non-heterogeneous circuit region.

9. The display panel of claim 8, wherein, The pattern of the first source-drain metal layer in the region outside the cross-line channel in the first sub-circuit region of the heterogeneous circuit region is the same as the pattern of the first source-drain metal layer in the same region in the first sub-circuit region of the non-heterogeneous circuit region.

10. The display panel of claim 8, wherein, In the circuit region, the pattern of the semiconductor layer in the first sub-circuit region is symmetrically arranged with the pattern in the second sub-circuit region.

11. The display panel of claim 1, wherein, In the circuit region row, the non-heterogeneous circuit region and the heterogeneous circuit region are arranged alternately.

12. The display panel of claim 1, wherein, In the circuit region column, the non-heterogeneous circuit region and the heterogeneous circuit region are arranged alternately.

13. The display panel of claim 1, wherein, The voltage trace includes a reference voltage trace arranged in the first source-drain metal layer and an initialization voltage trace arranged in the transistor layer; the reference voltage trace is used for loading a reference voltage, and the initialization voltage trace is used for loading an initialization voltage to the pixel driving circuit; The heterogeneous circuit region includes a reference heterogeneous circuit region and an initialization heterogeneous circuit region; The first source-drain metal layer is provided with a reference voltage cross-line in the reference heterogeneous circuit region, so that two adjacent reference voltage traces are electrically connected. The first source-drain metal layer is provided with an initialization voltage cross-over line for electrically connecting two adjacent initialization voltage wires in the initialization heterogeneous circuit area; At least one reference heterogeneous circuit area is arranged between two adjacent initialization heterogeneous circuit areas along the row direction.

14. The display panel of claim 3, wherein, The initialization voltage wires include a first initialization voltage wire for loading a first initialization voltage, a second initialization voltage wire for loading a second initialization voltage, and a third initialization voltage wire for loading a third initialization voltage; the initialization heterogeneous circuit areas include a first initialization heterogeneous circuit area provided with a first initialization voltage cross-over line in the first source-drain metal layer, a second initialization heterogeneous circuit area provided with a second initialization voltage cross-over line in the first source-drain metal layer, and a third initialization heterogeneous circuit area provided with a third initialization voltage cross-over line in the first source-drain metal layer; The first initialization voltage cross-over line electrically connects two adjacent first initialization voltage wires, the second initialization voltage cross-over line electrically connects two adjacent second initialization voltage wires, and the third initialization voltage cross-over line electrically connects two adjacent third initialization voltage wires; In the initialization heterogeneous circuit areas arranged in the same row, the first initialization heterogeneous circuit area, the second initialization heterogeneous circuit area, the third initialization heterogeneous circuit area, and the second initialization heterogeneous circuit area are arranged in a periodic sequence.

15. The display panel of claim 3, wherein, The initialization voltage wires include a first initialization voltage wire for loading a first initialization voltage, a second initialization voltage wire for loading a second initialization voltage, and a third initialization voltage wire for loading a third initialization voltage; the initialization heterogeneous circuit areas include a first initialization heterogeneous circuit area provided with a first initialization voltage cross-over line in the first source-drain metal layer, a second initialization heterogeneous circuit area provided with a second initialization voltage cross-over line in the first source-drain metal layer, and a third initialization heterogeneous circuit area provided with a third initialization voltage cross-over line in the first source-drain metal layer; The first initialization voltage cross-over line electrically connects two adjacent first initialization voltage wires, the second initialization voltage cross-over line electrically connects two adjacent second initialization voltage wires, and the third initialization voltage cross-over line electrically connects two adjacent third initialization voltage wires; In every two rows of initialization heterogeneous circuit areas, the initialization heterogeneous circuit areas in one of the rows are arranged in a periodic sequence of the first initialization heterogeneous circuit area, the second initialization heterogeneous circuit area, the third initialization heterogeneous circuit area, and the second initialization heterogeneous circuit area; The initialization heterogeneous circuit areas in the other row of the two rows are arranged in a periodic sequence of the third initialization heterogeneous circuit area, the second initialization heterogeneous circuit area, the first initialization heterogeneous circuit area, and the second initialization heterogeneous circuit area.

16. The display panel of claim 1, wherein, The voltage wires include reference voltage wires arranged in the first source-drain metal layer and initialization voltage wires arranged in the transistor layer; the reference voltage wires are used for loading reference voltages, and the initialization voltage wires are used for loading initialization voltages to the pixel driving circuit; The heterogeneous circuit regions include reference heterogeneous circuit regions and initialization heterogeneous circuit regions. The first source-drain metal layer is provided with reference voltage cross-over lines in the reference heterogeneous circuit regions, the reference voltage cross-over lines electrically connecting two adjacent reference voltage wires. The first source-drain metal layer is provided with initialization voltage cross-over lines in the initialization heterogeneous circuit regions, the initialization voltage cross-over lines electrically connecting two adjacent initialization voltage wires.

17. The display panel of claim 1, wherein, The voltage wires include initialization voltage wires provided in the transistor layer, the initialization voltage wires being used to load initialization voltage to the pixel driving circuit. The circuit regions are provided with initialization voltage transfer structures in the first source-drain metal layer, the initialization voltage transfer structures being electrically connected with the initialization voltage wires and the thin film transistors through vias, so that the initialization voltage is loaded to the pixel driving circuit. The heterogeneous circuit regions include initialization heterogeneous circuit regions; the first source-drain metal layer is provided with initialization voltage cross-over lines in the initialization heterogeneous circuit regions, two ends of the initialization voltage cross-over lines being electrically connected with two adjacent initialization voltage transfer structures in the same column.

18. The display panel according to any one of claims 1 to 17, wherein The display panel further includes a second planarization layer, a third source-drain metal layer and a third planarization layer which are sequentially stacked on a side of the second source-drain metal layer away from the first source-drain metal layer; the third source-drain metal layer is provided with a reference voltage grid; the pixel layer is provided on a side of the third planarization layer away from the second source-drain metal layer; a plurality of sub-pixels are arranged in the hollow holes of the reference voltage grid.

19. The display panel of claim 18, wherein, The reference voltage grid has first reference voltage line segments extending along the column direction. Along the row direction, the first reference voltage line segments are located between blue sub-pixels and red sub-pixels; a distance between the first reference voltage line segments and the blue sub-pixels is greater than a distance between the first reference voltage line segments and the red sub-pixels.

20. A display device comprising the display panel of any one of claims 1-19.

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