Frequency response compensation method and device

Abstract

Embodiments of the present disclosure provide a frequency response compensation method and device. The method comprises: a first software module extracts a data block from inputted raw data, and determines a power spectrum interpolation function on the basis of the data block, wherein the raw data is four-path optical channel power value data outputted by a first hardware module; a second software module determines a frequency response compensation coefficient on the basis of the power spectrum interpolation function and a determined filter coefficient, and determines a chip performance on the basis of the frequency response compensation coefficient; and when the chip performance is lower than a preset threshold, the second software module sends the frequency response compensation coefficient to a second hardware module, so as to perform frequency response compensation by means of the second hardware module.

Description

Frequency response compensation method and device

[0001] Cross-reference to related applications

[0002] This disclosure is based on and claims priority to Chinese Patent Application No. 202410682693.0, entitled “Frequency Response Compensation Method and Apparatus”, filed on May 29, 2024, and incorporates the entire contents of that patent application by reference. Technical Field

[0003] This disclosure relates to the field of communication transmission technology, and more specifically, to a frequency response compensation method and apparatus. Background Technology

[0004] With the development of various emerging services, users' demands for high speed, large capacity, high sensitivity, and long-distance transmission are increasing, making high-speed optical fiber communication one of the solutions. During signal transmission in an optical fiber link, the signal is affected by various effects such as loss, dispersion, and nonlinearity, leading to signal distortion and causing bit errors during decision-making at the receiving end.

[0005] To reduce bit errors in optical communication systems, equalization techniques based on digital signal processing algorithms are needed at the receiving end to compensate for various impairments and distortions in the transmission link. Existing technologies typically design hardware to calculate frequency response compensation coefficients, but this increases chip area and power consumption due to the large amount of data collected and the complexity of the implementation. Furthermore, it has limited applicability, requiring the design of multiple compensation schemes for various scenarios, which places high demands on the chip's hardware. Some existing solutions transmit the raw large dataset first, then use a script to send the calculated frequency response compensation coefficients to the chip. However, this process is inefficient, resulting in poor real-time compensation performance of the chip. Summary of the Invention

[0006] This disclosure provides a frequency response compensation method and apparatus to at least solve the problem that frequency response compensation, which is mostly performed through hardware in related technologies, requires more chip area and power consumption.

[0007] According to one embodiment of this disclosure, a frequency response compensation method is provided, comprising: a first software module extracting data blocks from input raw data and determining a power spectrum interpolation function based on the data blocks; wherein the raw data is power value data of four optical channels output by a first hardware module; a second software module determining frequency response compensation coefficients based on the power spectrum interpolation function and determined filter coefficients, and judging chip performance based on the frequency response compensation coefficients; if the chip performance is lower than a preset threshold, the second software module sending the frequency response compensation coefficients to a second hardware module for frequency response compensation by the second hardware module.

[0008] According to another embodiment of this disclosure, a frequency response compensation device is provided, comprising: a first hardware module, a second hardware module, a first software module, and a second software module; the first software module is configured to extract data blocks from input raw data and determine a power spectrum interpolation function based on the data blocks; wherein the raw data is four-channel optical power value data output by the first hardware module; the second software module is configured to determine frequency response compensation coefficients based on the power spectrum interpolation function and determined filter coefficients, and determine chip performance based on the frequency response compensation coefficients; the second software module is further configured to send the frequency response compensation coefficients to the second hardware module when the chip performance is lower than a preset threshold, so as to perform frequency response compensation through the second hardware module.

[0009] According to yet another embodiment of this disclosure, a computer-readable storage medium is also provided, wherein a computer program is stored therein, wherein the computer program is configured to perform the steps in any of the above method embodiments when it is run.

[0010] According to yet another embodiment of this disclosure, an electronic device is also provided, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.

[0011] According to yet another embodiment of this disclosure, a computer program product is also provided, including a computer program and instructions, wherein the computer program and instructions, when executed by a processor, implement the steps in any of the above method embodiments. Attached Figure Description

[0012] Figure 1 is a hardware structure block diagram of a computer terminal that operates a frequency response compensation method according to an embodiment of the present disclosure;

[0013] Figure 2 is a structural block diagram of a frequency response compensation system according to an embodiment of the present disclosure;

[0014] Figure 3 is a flowchart of a frequency response compensation method according to an embodiment of the present disclosure;

[0015] Figure 4 is a power spectrum comparison diagram between the frequency response compensation method according to the embodiments of the present disclosure and the frequency response compensation method in the prior art;

[0016] Figure 5 is an overall flowchart of the frequency response compensation method according to an embodiment of the present disclosure;

[0017] Figure 6 is a structural block diagram of a frequency response compensation device according to an embodiment of the present disclosure. Detailed Implementation

[0018] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings and examples.

[0019] It should be noted that the terms "first," "second," etc., in the specification, claims, and drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0020] The method embodiments provided in this application can be executed in a mobile terminal, computer terminal, or similar computing device. Taking a computer terminal as an example, FIG1 is a hardware structure block diagram of a computer terminal running the frequency response compensation method according to an embodiment of this disclosure. As shown in FIG1, the computer terminal may include one or more (only one is shown in FIG1) processors 102 (processor 102 may include, but is not limited to, processing devices such as microprocessors MCUs or programmable logic devices FPGAs) and a memory 104 for storing data. The computer terminal may also include a transmission device 106 for communication functions and an input / output device 108. Those skilled in the art will understand that the structure shown in FIG1 is only illustrative and does not limit the structure of the computer terminal. For example, the computer terminal may also include more or fewer components than shown in FIG1, or have a different configuration than shown in FIG1.

[0021] The memory 104 can be used to store computer programs, such as application software programs and modules, like the computer program corresponding to the frequency response compensation method in this embodiment. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, thereby implementing the above-described method. The memory 104 may include high-speed random access memory and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include memory remotely located relative to the processor 102, and these remote memories can be connected to a computer terminal via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0022] The transmission device 106 is used to receive or send data via a network. Specific examples of the network described above may include a wireless network provided by a communication provider for the computer terminal. In one example, the transmission device 106 includes a Network Interface Controller (NIC), which can connect to other network devices via a base station to communicate with the Internet. In another example, the transmission device 106 may be a Radio Frequency (RF) module used for wireless communication with the Internet.

[0023] In high-speed, long-distance optical transmission systems, high-speed DSP (Digital Signal Processor) chips utilize optical polarization demultiplexing technology to improve transmission efficiency. However, this technology introduces three factors that interfere with the signal during transmission: 1. Damage to the signal from analog devices such as photoelectric converters, electro-optic converters, and optical modems; 2. The influence of fiber chromaticity and dispersion; and 3. Crosstalk between the two polarization states. These factors introduce noise into the signal during transmission through the fiber optic link, preventing complete reproduction of the true input signal, leading to bit errors and performance degradation. Furthermore, this performance degradation becomes more pronounced with increasing bandwidth.

[0024] To compensate for various impairments and distortions in the transmission link, the following equalization techniques in optical communication systems can be used: dispersion compensation, optical polarization demultiplexing, dynamic equalization, orthogonal normalization, clock recovery, phase recovery, and frequency offset estimation.

[0025] To improve real-time compensation performance while saving chip area and power consumption, this disclosure provides a frequency response compensation system. Figure 2 is a structural block diagram of the frequency response compensation system according to an embodiment of this disclosure. As shown in Figure 2, the frequency response compensation system includes an ADC (Analog-to-Digital Converter) and a DSP chip. In addition to an IQ (In-phase and Quadrature) imbalance compensation module and a coarse equalization module, the DSP chip also includes two additional software modules: a power spectrum reporting module and a frequency response compensation module. By introducing two software modules, the first determines the frequency response compensation coefficient in software, which has advantages over determining the frequency response compensation coefficient in hardware, such as not occupying additional chip area, generating lower power consumption, greater software flexibility and freedom, and simpler and easier software implementation. The second is the introduction of a feedback mechanism. After the second software module determines the frequency response compensation coefficient, it first determines whether the obtained frequency response compensation coefficient improves chip performance. If it does, the obtained frequency response compensation coefficient is sent to the second hardware module; otherwise, the compensation mode and / or period of the software module is adjusted, and the frequency response compensation coefficient is determined based on the adjusted compensation mode and / or period. That is, the cycle of determining, judging, and adjusting the frequency response compensation coefficient is repeated.

[0026] The high-speed DSP chip mainly implements coherent modulation and demodulation, encoding and decoding, and framer functions. In this embodiment, the DSP chip mainly handles modulation and demodulation services, supporting functions such as framing and deframing, mapping and demapping, sampling and downsampling, and optical channel processing.

[0027] The IQ imbalance compensation module is configured to use the GSOP (Gram-Schmidt Orthogonal Procedure) algorithm to compensate for the IQ at the receiving end. This compensation is necessary because the project design involves the digital signal generated by the ADC (Analog-to-Digital Converter) being transmitted to the DSP chip. Due to imperfections in components such as the laser and mixer, IQ imbalance occurs at the receiving end, primarily manifested as unequal amplitudes and non-orthogonal phases between the I and Q digital signals.

[0028] The power spectrum reporting module is set to monitor the power value of the signal and send it to the CPU to compensate for the power value output by the IQ imbalance module. The CPU calculates the power spectrum data and designs the filter to calculate the frequency response compensation coefficient, and then sends it down to the coarse equalization module. The CPU includes the frequency response compensation module.

[0029] The function of the coarse equalization module is to eliminate signal distortion caused by channel linearity factors, such as CD (Chromatic Dispersion), which refers to the phenomenon that the phase velocity and group velocity of light change with frequency in a transparent medium, and factors such as optical filtering.

[0030] The frequency response compensation system described above can reduce noise while preserving the useful spectrum of the signal, thereby reducing the bit error rate at the receiver of the DSP chip and improving the optical signal-to-noise ratio tolerance.

[0031] This disclosure provides a frequency response compensation method for the frequency response compensation system described above. This method can effectively filter noise during digital signal transmission, improve the bit error rate and optical signal-to-noise ratio tolerance of the DSP chip receiver, and save the area and power consumption of the DSP chip, thereby improving the compensation performance of the DSP chip.

[0032] Figure 3 is a flowchart of a frequency response compensation method according to an embodiment of the present disclosure. As shown in Figure 3, the process includes the following steps:

[0033] In step S302, the first software module extracts data blocks from the input raw data and determines the power spectrum interpolation function based on the data blocks; wherein, the raw data is the power value data of the four optical channels output by the first hardware module. Functionally, the first software module is equivalent to the power spectrum reporting module in the aforementioned frequency response compensation system, and the first hardware module is functionally equivalent to the IQ imbalance compensation module in the aforementioned frequency response compensation system.

[0034] In this embodiment, the first software module is located after the first hardware module. The first software module uses the power value data (i.e., the raw data) output by the first hardware module to perform spectrum estimation, and uploads the estimated power spectral density (PSD) data to the second software module. The power value data has two polarization states, X and Y, and each polarization state is further divided into a real part (I path) and an imaginary part (Q path). Therefore, the power value data output by the first hardware module can be divided into four paths: XI, XQ, YI, and YQ, i.e., four optical channel power value data. Power spectral density, or simply power spectrum, is a function that measures the energy distribution of the spectral components of a signal or random process.

[0035] In step S302 of this embodiment, the first software module extracts data blocks from the input raw data and determines the power spectrum interpolation function based on the data blocks, including: extracting multiple data blocks from the power value data of the four optical channels according to a preset extraction interval, determining the power spectrum corresponding to the power value data of the four optical channels based on the data blocks, and performing linear interpolation processing on the power spectrum corresponding to the power value data of the four optical channels to obtain the power spectrum interpolation function.

[0036] In one embodiment, multiple data blocks are extracted from the power value data of each optical channel according to a preset extraction interval, and the power spectrum corresponding to the power value data of the four optical channels is determined based on the data blocks, including: an extraction step: extracting multiple data blocks from the power value data of each optical channel according to a preset extraction interval; a determination step: determining the power spectrum corresponding to the power value data of each optical channel in the current iteration based on the data blocks corresponding to the power value data of each optical channel; an update step: updating the power spectrum corresponding to the power value data of each optical channel based on the power spectrum corresponding to the power value data of each optical channel in the current iteration and the power spectrum corresponding to the power value data of each optical channel in the previous iteration; and a judgment step: determining whether the current iteration number meets a preset threshold by using a counter, and if the current iteration number does not meet the preset threshold, repeating the extraction step, the determination step, the update step, and the judgment step.

[0037] In one embodiment, determining the power spectrum corresponding to the power value data of each optical channel in the current iteration based on the data block corresponding to the power value data of each optical channel includes: for any optical channel power value data, performing a Fourier transform on each data block corresponding to the power value data of that optical channel, and performing a modulus-square value operation on each Fourier transform result; to obtain the power spectrum corresponding to the power value data of that optical channel.

[0038] The following example, using the power value of one optical channel (e.g., XI), illustrates the process of determining the power interpolation function. Assume the raw data (XI) output by the first hardware module is sig_iq, which is the input to the power spectrum reporting module. sig_iq is divided into multiple data blocks of length N for processing, each block corresponding to a different sequence number.

[0039] Step S1: The first software module extracts a portion of the data blocks sig_blk_1 to sig_blk_Nblk from the multiple data blocks corresponding to sig_iq according to a preset extraction interval. Here, Nblk is the quantity. The partial data blocks sig_blk_Nblk can be discontinuous or continuous. Here, "continuous" or "discontinuous" refers to the continuity or discontinuity of the corresponding sequence numbers of the data blocks.

[0040] By extracting a portion of the data for subsequent processing, CPU resources can be saved and power consumption reduced compared to processing all the data.

[0041] In this embodiment, different extraction intervals can be configured according to different usage scenarios, which means that different compensation schemes can be designed according to different scenarios, thus solving the problem of the limited application scenarios of hardware frequency response compensation methods.

[0042] In one embodiment, the preset extraction interval can be configured according to actual conditions, wherein the preset extraction interval is adjusted when at least one of the following conditions is met: the monitored optical performance degradation of the chip exceeds a first preset threshold; the monitored chip temperature exceeds a second preset threshold; or the monitored chip voltage exceeds a third preset threshold.

[0043] The software side (including the first and second software modules) monitors the DSP chip's status in real time. Based on the current degree of optical performance degradation, temperature, and voltage, it compensates for the DSP chip's receive-end bit error rate and optical signal-to-noise ratio tolerance in real time. By judging indicators such as the receive-end bit error rate and power, it adjusts the frequency response compensation period, mode, or data block extraction interval. For example, if the bit error rate decreases and the receive-end power increases, the software side automatically sends the frequency response compensation coefficient to the subsequent modules, and the period is slowed down; if the bit error rate and receive-end power do not improve, the software side does not send the frequency response compensation coefficient, the period is sped up, the compensation mode is changed, the filter coefficient is recalculated, and the judgment is made again.

[0044] In this embodiment, XI can be extracted multiple times for use in steps S2 and S3.

[0045] Step S2: For the data blocks sig_blk_1~sig_blk_Nblk extracted in step S1, determine multiple sets of power spectrum psd.

[0046] Specifically, a period consists of Nblk*N data blocks, where N is the data length and Nblk is the quantity. Let the first data block of length N be sig_blk_1 (the first data block), the second data block of length N be sig_blk_2 (the m-th data block), and the Nblk-th data block of length N be sig_blk_Nblk.

[0047] Perform an FFT transformation on sig_blk_1 and calculate the squared modulus of the FFT output data. sig_fft_blk_1 = fft(sig_blk_1); sig_blk_real_1 = abs(real(sig_fft_blk_1)); sig_blk_image_1 = abs(imag(sig_fft_blk_1)); sig_pow_blk_1 = sig_blk_real_1 2 +sig_blk_imag_1 2 ;

[0048] The calculation process for sig_blk_2 to sig_blk_Nblk data is the same as that for sig_blk_1, resulting in sig_pow_blk_2 to sig_pow_blk_Nblk respectively.

[0049] Average these Nblk data points and divide by N, i.e.: sig_avg=1 / (Nblk×N)(sig_pow_blk_1+sig_pow_blk_2+...+sig_pow_blk_Nblk).

[0050] In this embodiment, cnt is set as a period counter. For the multiple groups of sig_blk_1 to sig_blk_Nblk extracted in step S1, cnt = cnt + 1 is calculated for each sig_avg.

[0051] Step S3: Update the average value of the spectrum data PSD.

[0052] Specifically, the multiple sets of PSD data determined in step S2 are averaged to reduce the error caused by calculating a single set of PSD coefficients. Let the initial PSD value be N zeros. The PSD is then updated:

[0053] psd = psd' + 1 / (cnt + 1)(sig_avg - psd), where psd' is the power spectrum data before the update.

[0054] The initial default value of cnt is 0, and the maximum value of cnt is cnt_level (cnt_level is configurable). cnt will not increase after it reaches cnt_level, until the system issues a reset command and restores the default value.

[0055] Step S4: Linear difference of power spectrum PSD, determine the power spectrum interpolation function.

[0056] Specifically, let the power spectrum of the four signals after passing through the first software module be psd(4×nfft), where nfft is an array of data blocks reporting the length of the power spectrum.

[0057] Calculate the average of the four PSD values: psd_mean = mean(psd, 2);

[0058] Symmetrical addition of PSDs: PSD = PSD_mean(nfft / 2+1:end) + PSD_mean(nfft / 2:-1:1); PSD = PSD / mean(PSD(2:10));

[0059] The `fun_psd` function is obtained by interpolating the PSD, which is the power spectrum interpolation function. The independent variable is (0:nfft / 2-1) / nfft*4 / 3, used for linear interpolation.

[0060] fun_psd=griddedInterplant((0:nfft / 2*4 / 3,psd,”,”).

[0061] In step S304, the second software module determines the frequency response compensation coefficient based on the power spectrum interpolation function and the determined filter coefficients, and judges the chip performance based on the frequency response compensation coefficient. Functionally, the second software module is equivalent to the frequency response compensation module in the aforementioned frequency response compensation system.

[0062] Before step S304 in this embodiment, the method further includes: a second software module determining filter parameters based on the power spectrum interpolation function, and determining the filter coefficients through the filter corresponding to the filter parameters. The filter parameters include: sampling rate, single-sideband, frequency response, frequency, and amplitude, wherein the amplitude is determined based on the power spectrum interpolation function.

[0063] In one embodiment, designing a filter includes: assuming the filter parameters are a sampling rate of osr, Ns single-sideband points, a frequency response of f, and a frequency of ff = linspace(0, 0.4, 20); the amplitude is...

[0064] [ff,aa]=deal([ff.4999.5001],[aa db2mag(target_db)*[1 1] / sqrt(fun_psd(0.5))]).

[0065] Least squares FIR filter design: filter coefficients (impulse response):

[0066] An FIR filter is a fundamental component of a digital signal processing system; it refers to a filter with a finite unit impulse response length. Its purpose is to guarantee arbitrary amplitude-frequency characteristics while possessing strictly linear phase-frequency characteristics, and the unit sample response is of finite length.

[0067] Based on the above [ff,aa], determine the filter coefficients: fir_b=firls(16,[ff*1.5 0.9999 1],[aa 1 1]);

[0068] Perform a Fast Fourier Transform on the filter coefficients and take their absolute values ​​to obtain the Fourier transformed filter coefficients: fir_h_fft = fft(fir_b, N s ); fir_h_abs=abs(fir_h_fft); fir_h_abs=fir_h_abs(1:N s / 2+1).

[0069] In step 304 of this embodiment, the second software module determines the frequency response compensation coefficient based on the power spectrum interpolation function and the determined filter coefficients, including: performing Fourier transform processing on the filter coefficients to obtain the Fourier transformed filter coefficients; and determining the frequency response compensation coefficient based on the power spectrum interpolation function, the filter coefficients, and the Fourier transformed filter coefficients.

[0070] Since the compensation requires a 16th-order order, which is costly to implement in the time domain, this embodiment first calculates the frequency response compensation coefficients in the frequency domain, and then performs subsequent processing on the compensated target spectrum in the frequency domain. Specifically, the formulas involved in this process are as follows:

[0071] Frequency response compensation coefficient output: flt_h=abs(fft(flt_b,N s )).

[0072] In step S306, when the chip performance is lower than a preset threshold, the second software module sends the frequency response compensation coefficient to the second hardware module so that frequency response compensation can be performed by the second hardware module.

[0073] In this embodiment, after determining the frequency response compensation coefficient based on the above steps, the second software module first determines the current performance of the DSP chip and the performance of the DSP chip corresponding to the obtained frequency response compensation coefficient. If the current performance of the DSP chip is lower than a preset threshold, and the performance of the DSP chip corresponding to the obtained frequency response compensation coefficient is higher than the current performance of the DSP chip, then the second software module sends the obtained frequency response compensation coefficient flt_h to the second hardware module for frequency response compensation. If the current performance of the DSP chip is not lower than the preset threshold, the second software module does not send the obtained frequency response compensation coefficient, and continues to monitor the real-time input data and determine new frequency response compensation coefficients through the steps of the above frequency response compensation method.

[0074] The software module reads the same set of input data from the hardware module and, through the aforementioned frequency response compensation method, obtains the power spectrum of the output signal. Figure 4 is a comparison of the power spectrum of the frequency response compensation method according to the present disclosure embodiment and the frequency response compensation method in the prior art. As shown in Figure 4, it can be seen that the power spectrum value is improved after the frequency response compensation method of the present disclosure embodiment, which reduces noise while preserving the useful spectrum of the signal, thereby reducing the bit error rate at the receiver of the DSP chip and improving the optical signal-to-noise ratio tolerance.

[0075] Figure 5 is an overall flowchart of the frequency response compensation coefficient determination method according to an embodiment of the present disclosure. The method is applied to the frequency response compensation system shown in Figure 2. As shown in Figure 5, it specifically includes the following steps:

[0076] Step S501: The first hardware module inputs the power value data of four optical channels XI, XQ, YI, and YQ to the first software module.

[0077] In step S502, the first software module extracts Nblk*N data blocks of length from the input four optical channel power value data; wherein, with Nblk*N data lengths as one period, FFT transformation is performed on each data block.

[0078] Step S503: The first software module performs FFT transformation on each of the Nblk*N data sets.

[0079] Step S504: The first software module calculates and updates the average value of the power spectrum PSD corresponding to the power value data of the four optical channels.

[0080] In step S505, the first software module determines that cnt < cnt_level. If the number of iterations of the period counter has not reached cnt_level, it returns to step S502; if the number of iterations of the period counter reaches cnt_level, it proceeds to step S506.

[0081] In step S506, the first software module performs linear interpolation on the power spectrum psd corresponding to the power value data of the four optical channels to obtain the linear interpolation function.

[0082] Step S507: The second software module determines the filter coefficients based on the designed filter.

[0083] In step S508, the second software module determines the frequency response compensation coefficient based on the linear interpolation function and the determined filter coefficients.

[0084] The specific implementation process of each step from S501 to S508 can be referred to the above embodiment, and will not be repeated here.

[0085] The methods and systems described in the above embodiments of this disclosure have the following advantages:

[0086] 1. Save chip power consumption: Compared with hardware implementation, software directly uses the chip's processor to calculate frequency response compensation, without occupying extra chip area, and the chip generates lower power consumption.

[0087] Second, the mechanism is simple and easy to implement: Calculating the filter coefficients requires a large amount of data and complex functions. The software can improve the execution efficiency of the interface by calling the DSP's CMSIS library.

[0088] Third, it offers great flexibility and freedom: the frequency response compensation mechanism can be processed by an external FPGA or calculated in hardware circuits; software implementation allows for the design of multiple frequency response compensation mechanisms, selecting the most suitable mechanism for frequency response compensation in different application scenarios; however, implementing multiple frequency response compensation mechanisms in hardware is clearly not flexible enough.

[0089] IV. Real-time Chip Monitoring: The software can monitor the chip's status in real time, such as the degree of optical performance degradation, temperature, and voltage. It performs real-time compensation by controlling the frequency response compensation cycle and mode. The frequency response compensation cycle and mode are adjusted based on indicators such as the bit error rate and power at the receiving end. If the bit error rate decreases and the receiving end power increases, the software automatically sends the frequency response compensation coefficients to the subsequent modules, and the cycle is slowed down. If the bit error rate and receiving end power do not improve, the software does not send the frequency response compensation coefficients, speeds up the cycle, changes the compensation mode, and recalculates the filter coefficients.

[0090] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this disclosure, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of this disclosure.

[0091] This embodiment also provides a frequency response compensation device for implementing the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the term "module" can refer to a combination of software and / or hardware that performs a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, hardware implementations, or a combination of software and hardware, are also possible and contemplated.

[0092] Figure 6 is a structural block diagram of a frequency response compensation device according to an embodiment of the present disclosure. As shown in Figure 6, the frequency response compensation device 600 includes: a first hardware module 610, a second hardware module 620, a first software module 630, and a second software module 640.

[0093] The first software module 630 is configured to extract data blocks from the input raw data and determine the power spectrum interpolation function based on the data blocks; wherein, the raw data is the four-channel optical power value data output by the first hardware module 610;

[0094] The second software module 640 is configured to determine the frequency response compensation coefficient based on the power spectrum interpolation function and the determined filter coefficients, and to judge the chip performance based on the frequency response compensation coefficients.

[0095] The second software module 640 is further configured to send the frequency response compensation coefficient to the second hardware module 620 when the chip performance is lower than a preset threshold, so that frequency response compensation can be performed by the second hardware module 620.

[0096] The invention introduces a software processing method, in which the software directly uses the chip's processor to calculate frequency response compensation, without occupying additional chip area and generating lower power consumption. Compared with hardware implementation, it has more advantages for processing large-scale scenarios. Moreover, the software has greater flexibility and freedom, and can design multiple frequency response compensation mechanisms to select the most suitable mechanism for frequency response compensation in different usage scenarios.

[0097] It should be noted that the above modules can be implemented by software or hardware. For the latter, they can be implemented in the following ways, but are not limited to: all the above modules are located in the same processor; or, the above modules are located in different processors in any combination.

[0098] Embodiments of this disclosure also provide a computer-readable storage medium storing a computer program configured to perform the steps in any of the above method embodiments when executed.

[0099] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0100] Embodiments of this disclosure also provide an electronic device including a memory and a processor, the memory storing a computer program and the processor being configured to run the computer program to perform the steps in any of the above method embodiments.

[0101] In one exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor and the input / output device is connected to the processor.

[0102] Specific examples in this embodiment can be found in the examples described in the above embodiments and exemplary implementations, and will not be repeated here.

[0103] Embodiments of this disclosure also provide a computer program product, which includes a computer program and instructions, wherein the computer program and instructions, when executed by a processor, implement the steps in any of the above method embodiments.

[0104] It is obvious to those skilled in the art that the modules or steps of this disclosure described above can be implemented using general-purpose computing devices. They can be centralized on a single computing device or distributed across a network of multiple computing devices. They can be implemented using computer-executable program code, and thus can be stored in a storage device for execution by a computing device. In some cases, the steps shown or described can be performed in a different order than those presented herein, or they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. Thus, this disclosure is not limited to any particular combination of hardware and software.

[0105] The above description is merely a preferred embodiment of this disclosure and is not intended to limit this disclosure. Various modifications and variations can be made to this disclosure by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A frequency response compensation method, comprising: a first software module extracts data blocks from input original data and determines a power spectrum interpolation function according to the data blocks; wherein the original data is four-path optical channel power value data output by a first hardware module; a second software module determines a frequency response compensation coefficient according to the power spectrum interpolation function and determined filter coefficients, and judges a chip performance according to the frequency response compensation coefficient; the second software module sends the frequency response compensation coefficient to a second hardware module for frequency response compensation by the second hardware module in a case where the chip performance is lower than a preset threshold.

2. The method of claim 1, wherein, the first software module extracts data blocks from input original data and determines a power spectrum interpolation function according to the data blocks, comprising: extracting a plurality of data blocks from the four-path optical channel power value data according to a preset extraction interval, and determining a power spectrum corresponding to the four-path optical channel power value data according to the data blocks; performing linear interpolation processing on the power spectrum corresponding to the four-path optical channel power value data to obtain the power spectrum interpolation function.

3. The method of claim 2, wherein, extracting a plurality of data blocks from each-path optical channel power value data according to a preset extraction interval, and determining a power spectrum corresponding to the four-path optical channel power value data according to the data blocks, comprising: an extraction step: extracting a plurality of data blocks from each-path optical channel power value data according to a preset extraction interval; a determination step: determining a power spectrum corresponding to each-path optical channel power value data in the current iteration according to the data blocks corresponding to each-path optical channel power value data; an update step: updating the power spectrum corresponding to each-path optical channel power value data according to the power spectrum corresponding to each-path optical channel power value data in the current iteration and the power spectrum corresponding to each-path optical channel power value data in the last iteration; a judgment step: judging whether the current iteration number meets a preset threshold by a counter, and repeatedly executing the extraction step, the determination step, the update step and the judgment step in a case where the current iteration number does not meet the preset threshold.

4. The method of claim 3, wherein, determining a power spectrum corresponding to each-path optical channel power value data in the current iteration according to the data blocks corresponding to each-path optical channel power value data, comprising: for any one-path optical channel power value data, respectively performing Fourier transform on each data block corresponding to the one-path optical channel power value data, and performing modulus square value operation on each Fourier transform result obtained; obtaining a power spectrum corresponding to the one-path optical channel power value data.

5. The method of claim 1, wherein, before the second software module determines a frequency response compensation coefficient according to the power spectrum interpolation function and determined filter coefficients, the method further comprises: the second software module determines a filter parameter according to the power spectrum interpolation function, and determines the filter coefficients through a filter corresponding to the filter parameter.

6. The method of claim 5, wherein, the filter parameter comprises a sampling rate, a single sideband, a frequency response, a frequency and an amplitude, and the amplitude is determined according to the power spectrum interpolation function.

7. The method of claim 2, further comprising: adjusting the preset extraction interval in a case where at least one of the following conditions is met: the light performance of the chip monitored is found to be deteriorated beyond a first preset threshold value; the temperature of the chip monitored is found to be beyond a second preset threshold value; the voltage of the chip monitored is found to be beyond a third preset threshold value.

8. The method of claim 1, wherein, The second software module determines a frequency response compensation coefficient according to the power spectrum interpolation function and the determined filter coefficient, including: performing Fourier transform processing on the filter coefficient to obtain a Fourier transformed filter coefficient; determining the frequency response compensation coefficient according to the power spectrum interpolation function, the filter coefficient and the Fourier transformed filter coefficient.

9. A frequency response compensation device, comprising: The first hardware module, the second hardware module, the first software module and the second software module; The first software module is configured to extract a data block from the inputted original data and determine a power spectrum interpolation function according to the data block; wherein the original data is the four-channel optical channel power value data outputted by the first hardware module. The second software module is configured to determine a frequency response compensation coefficient according to the power spectrum interpolation function and the determined filter coefficient, and judge the chip performance according to the frequency response compensation coefficient. The second software module is further configured to send the frequency response compensation coefficient to the second hardware module to perform frequency response compensation by the second hardware module when the chip performance is lower than a preset threshold value.

10. A computer-readable storage medium storing a computer program, wherein, The computer program is executed by a processor to realize the steps of the method in any one of claims 1 to 8. 11.An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor executes the computer program to realize the steps of the method in any one of claims 1 to 8. 12.A computer program product comprising a computer program, instructions, wherein the computer program, instructions are executed by a processor to realize the steps of the method in any one of claims 1 to 8.

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