Digital signal processing method and system based on FPGA mixed use data format

Abstract

The invention discloses a digital signal processing method and system based on an FPGA mixed use data format, and relates to the field of digital signal processing. The method solves the problems that in the prior art, an optimization method combining fixed-point number operation and floating-point number operation is lacked to solve the problems that at present, signal operation is usually conducted through fixed-point number operation, the dynamic range of the fixed-point number operation is small, and errors of obtained results are large. The module receives radar signals of 32 channels and divides the radar signals into four groups; performing maximum power spectral density comparison on the eight channels in each group, and finally performing inter-group comparison to select a signal with the maximum power spectral density in the 32 channels; and sending the signal to an FPGA for calculation, calculating the signal-to-noise ratio of the signal by using a mixed data format method, comparing the signal-to-noise ratio with a preset minimum signal-to-noise ratio threshold value, if the signal-to-noise ratio is greater than the threshold value, outputting the signal for subsequent processing, otherwise, not outputting a result.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of digital signal processing, in particular to a digital signal processing method and system based on mixed use of data formats of FPGA. BACKGROUND

[0002] In radar reconnaissance, the analysis of target radar signals is indispensable, but various calculations are required in the analysis process, and the calculation amount is very large. Floating-point operation is a method with large dynamic range and fine calculation result, but the floating-point resources on FPGA hardware devices are relatively scarce. Taking Fast Fourier Transform (FFT) as an example, if an 8-point FFT operation of single-precision floating-point number is performed, 12 complex multiplications and 24 complex additions are required. However, since the inputs of the multiplier and the adder in the FPGA are 24 bits and 18 bits, 24 multipliers and 48 adders are required for an 8-point FFT calculation, which is a very large consumption of FPGA resources.

[0003] Therefore, fixed-point operation is usually used for signal operation at present, which greatly saves hardware resources, but the dynamic range represented by fixed-point number is small, especially in some division operations, such as calculating the average value and the signal-to-noise ratio, the error of the result is large.

[0004] In the case of superposition of signals with large amplitude and signals with small amplitude, the use of fixed-point operation will not only lose accuracy, but also cause the loss of small signals in superposition, which will further cause errors in the results of subsequent calculations. This is unacceptable for reconnaissance and detection radar application scenarios. The simulation results are shown in Figure 1

[0005] In this simulation, the frequencies of two sinusoidal signals are set to 50Hz and 120Hz respectively, and the amplitudes are greatly different. Then the FFT calculation is performed on the signal obtained by superimposing the two sinusoidal signals converted into 32-bit signed fixed-point numbers and single-precision floating-point numbers respectively, and the frequency spectrum diagram is shown above. It can be seen that when the superimposed signal is converted into 32-bit signed fixed-point number, the signal with small amplitude is directly lost, and only the signal with large amplitude can be seen in the frequency spectrum diagram, while when converted into single-precision floating-point number, all information of the superimposed signal is retained.

[0006] ​In summary, there is an urgent need to provide a calculation optimization method to combine fixed-point number operation and floating-point number operation to solve the problem that fixed-point number operation is usually used for signal operation at present, which greatly saves hardware resources, but the dynamic range that can be represented by fixed-point number is small, especially in some division operations, such as calculating average value, calculating signal-to-noise ratio, etc., the error of the obtained result is large. In the case of superposition of signals with large amplitude and signals with small amplitude, the use of fixed-point number operation not only loses accuracy, but also causes the loss of small signals superimposed, which further causes errors in the results of subsequent calculations and other problems. SUMMARY

[0007] In order to solve the problem that there is no optimization method combining fixed-point number operation and floating-point number operation in the prior art, the present application provides a digital signal processing method and system based on mixed use of data formats of FPGA.

[0008] To solve the above technical problems, the present application is realized by the following technical scheme: Scheme one, the present application provides a digital signal processing method based on mixed use of data formats of FPGA, which is realized based on a multi-channel power spectrum density and signal-to-noise ratio maximum detection module, and the method comprises: Step 1, 32 channels of the multi-channel power spectrum density and signal-to-noise ratio maximum detection module are divided into 4 groups; Step 2, the maximum power spectrum density of each group of 8 channels is compared, and finally the maximum power spectrum density signal in 32 channels is selected by inter-group comparison; Step 3, the signal is sent into FPGA for calculation, and the signal-to-noise ratio of the signal is calculated by using the method of mixed use of data formats, and compared with a preset minimum signal-to-noise ratio threshold value, and if the signal-to-noise ratio is greater than the threshold value, the signal is output, otherwise no output result is output.

[0009] Further, a preferred embodiment is provided, and step 1 of the multi-channel power spectrum density and signal-to-noise ratio maximum detection module further comprises the step of converting fixed-point data into floating-point data, i.e. Step 1.1, input signal peak value data and noise peak value data, and convert the signal peak value data and the noise peak value data into floating-point; Step 1.2, splice the signal peak value data and the noise peak value data converted into floating-point in step 1 into 64-bit data in the signal processing channel and the noise processing channel respectively, and output the floating-point number.

[0010] Further, a preferred embodiment is provided, the signal peak data and the noise peak data input in step 1.1 are converted by high-bit zero padding expansion into 64-bit format.

[0011] Further, a preferred embodiment is provided, the signal processing channel and the noise processing channel in step 1.2 share the same control timing.

[0012] Further, a preferred embodiment is provided, the method for sending the signal into the FPGA for calculation in step 3 is calculated by the fast Fourier transform method and is obtained by the clipping operation.

[0013] Further, a preferred embodiment is provided, the method for calculating the signal-to-noise ratio of the maximum power spectral density signal in step 3 is:

[0014] wherein, is the signal power, is the noise power.

[0015] Further, a preferred embodiment is provided, the output result in step 3 is obtained by using MATLAB for visualization.

[0016] Scheme two, a digital signal processing system based on mixed use of data format of FPGA, the system is based on multi-channel power spectral density and signal-to-noise ratio maximum detection module is realized, the system comprises: The input module is used for dividing the 32 channels of the multi-channel power spectral density and signal-to-noise ratio maximum detection module into 4 groups; The data comparison module is used for comparing the maximum power spectral density of each group of 8 channels, and finally comparing between groups to select the signal with the maximum power spectral density in the 32 channels; The output module is used for sending the signal into the FPGA for calculation, using the method of mixed use of data format to calculate the signal-to-noise ratio of the signal and compare with the preset minimum signal-to-noise ratio threshold value, greater than the threshold value, then output the signal, otherwise no output result.

[0017] Scheme three, a computer readable storage medium, the computer readable storage medium stores a computer program, the computer program is executed by the processor to realize the steps of the method of scheme one.

[0018] Scheme four, a computer device, comprising a memory and a processor, the memory stores a computer program, when the processor runs the computer program stored in the memory, the processor executes the method of scheme one.

[0019] The beneficial effects of the present application are: The FPGA-based digital signal processing method and system using mixed data formats provided by the application adopts a combination of fixed-point number operation and floating-point number operation, and converts the fixed-point number into a floating-point number for signal calculation and analysis. Compared with the prior art, the application has higher calculation accuracy with less hardware resource consumption and a larger signal dynamic range.

[0020] The application has high universality and wide application scenarios, and is also applicable to reconnaissance and detection radar digital signal processing and other application scenarios. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 It is a simulation result diagram of fixed-point number operation in the prior art.

[0022] Figure 2 It is a flowchart of the FPGA-based digital signal processing method using mixed data formats according to the first embodiment.

[0023] Figure 3 It is a diagram of the amplitude of each noise point according to the first embodiment.

[0024] Figure 4 It is a diagram of the signal-to-noise ratio comparison of different methods when the noise amplitude is about 0 according to the first embodiment.

[0025] Figure 5 It is a diagram of the signal-to-noise ratio comparison of different methods when the noise amplitude is about 0 according to the first embodiment. DETAILED DESCRIPTION

[0026] To make the purpose, technical scheme and advantages of the embodiments of the application clearer, the technical scheme of the embodiments of the application will be described clearly and completely below with reference to the drawings in the embodiments of the application. Obviously, the described embodiments are part of the embodiments of the application, rather than all the embodiments of the application.

[0027] In the first embodiment, a FPGA-based digital signal processing method using mixed data formats is provided, which is realized based on a multi-channel power spectral density and signal-to-noise ratio maximum detection module. The method comprises the following steps: Step 1: The 32 channels of the multi-channel power spectral density and signal-to-noise ratio maximum detection module are divided into 4 groups. Step 2: The maximum power spectral density of each group of 8 channels is compared, and finally the maximum power spectral density signal in the 32 channels is selected through inter-group comparison. Step 3, the signal is sent into FPGA for calculation, the signal-to-noise ratio of the signal is calculated by using the method of mixed use of data format, and is compared with the preset minimum signal-to-noise ratio threshold value, and the signal is output if it is greater than the threshold value, otherwise no output result is output.

[0028] Embodiment two, the embodiment is further limited to the digital signal processing method based on FPGA mixed use of data format of embodiment one, the step 1.1, the signal peak data and the noise peak data are inputted, and the signal peak data and the noise peak data are converted into floating point data. Step 1.1, input signal peak data and noise peak data, and convert signal peak data and noise peak data into floating point; Step 1.2, the signal peak data and the noise peak data converted into floating point in step 1 are spliced into 64-bit data in the signal processing channel and the noise processing channel respectively, and the floating point number is outputted.

[0029] Embodiment three, the embodiment is further limited to the digital signal processing method based on FPGA mixed use of data format of embodiment two, the signal peak data and the noise peak data inputted in step 1.1 are expanded to 64-bit format by high-bit zero padding for conversion.

[0030] Embodiment four, the embodiment is further limited to the digital signal processing method based on FPGA mixed use of data format of embodiment two, the signal processing channel and the noise processing channel share the same control timing in step 1.2.

[0031] Embodiment five, the embodiment is further limited to the digital signal processing method based on FPGA mixed use of data format of embodiment one, the method of sending the signal into FPGA for calculation in step 3 is calculated by fast Fourier transform method and is subjected to bit clipping operation.

[0032] Embodiment six, the embodiment is further limited to the digital signal processing method based on FPGA mixed use of data format of embodiment one, the method for calculating the signal-to-noise ratio of the maximum power spectral density signal in step 3 is:

[0033] Wherein, The signal power is, The noise power is.

[0034] Embodiment seven, the embodiment is further limited to the digital signal processing method based on FPGA mixed use of data format of embodiment one, the output result in step 3 is visualized by using MATLAB.

[0035] Embodiment eight, the embodiment proposes a digital signal processing system based on mixed use of data format of FPGA, the system is realized based on multi-channel power spectral density and signal-to-noise ratio maximum detection module, the system comprises: Input module, for dividing 32 channels of the multi-channel power spectral density and signal-to-noise ratio maximum detection module into 4 groups; Data comparison module, for comparing the maximum power spectral density of each group of 8 channels, and finally comparing between groups to select the signal with the maximum power spectral density in 32 channels; Output module, for sending the signal into FPGA for calculation, using a mixed use of data format method to calculate the signal-to-noise ratio of the signal and compare it with a preset minimum signal-to-noise ratio threshold value, greater than the threshold value, output the signal, otherwise no output result.

[0036] Embodiment nine, the embodiment is a further explanation of the above-mentioned embodiments one to eight, specifically including the following contents: Referring to Figures 1 to 5 This embodiment designs a module for converting fixed-point numbers to floating-point numbers, which can be used in scenarios involving signal operations. This module is currently used in a multi-channel power spectral density and signal-to-noise ratio maximum detection unit in a signal processing system. The unit divides 32 channels into 4 groups, receives 8 channels of radar signals at a time, pre-processes the signals after receiving, adds a certain time delay to the signals for synchronization control, compares the maximum power spectral density of each group of 8 channels, calculates the signal-to-noise ratio of the signal with the maximum power spectral density, compares between groups to select the signal with the maximum signal-to-noise ratio in 32 channels, compares the signal-to-noise ratio with a preset minimum signal-to-noise ratio threshold value, and outputs the signal for subsequent processing if the signal-to-noise ratio is greater than the minimum threshold value, otherwise no output result. The signal-to-noise ratio is calculated as follows: wherein is the signal power, is the noise power. The single 8-channel signal-to-noise ratio comparison block diagram of the module is shown in Figure 2 .

[0037] The module designed in this embodiment is used for signal-to-noise ratio calculation in the unit. The module uses a local floating-point resource calling method. Floating-point number operations are used when calculating the signal-to-noise ratio, and fixed-point number calculations are used for the rest of the calculation process. The conversion process of the module from fixed-point number to floating-point number is as follows.

[0038]

[0039] Wherein ch08_max_psd_value and ch08_max_psd_noise are the signal power value and the noise power value of the signal with the largest power spectral density in the 8 channels, they are a 32-bit fixed point number and a 44-bit fixed point number, which are input variables of the module, and the output variables after conversion of the module are 32-bit floating point numbers sig_float and noise_float, which are used to calculate the signal-to-noise ratio of the signal in the subsequent. When calculating the signal-to-noise ratio, floating point operation is used because the noise power received by the hardware receiving device connected in front of the module in actual application is very small, and the FPGA performs bit truncation operation when performing signal FFT operation to save resources while ensuring accuracy, prevent data overflow, which makes the noise power even smaller. Therefore, if fixed-point calculation is used all the time, the noise power will be 0, which will lead to the inability to calculate the signal-to-noise ratio, and local calling of floating point resources can solve this problem with very small resource consumption.

[0040] In the experiment of the embodiment, a sinusoidal signal is added with a noise amplitude adjustable Gaussian white noise, and the signal-to-noise ratio is set to 30dB. The noise-added signal is sent into the FPGA for 1024-point FFT operation, and the amplitude average value of 100 noise points in the frequency spectrum is taken as the noise amplitude used for calculating the signal-to-noise ratio. Fixed-point operation and floating-point operation are used respectively in the process of taking the noise amplitude average value. Finally, the difference of the signal-to-noise ratios obtained by the two kinds of operations is compared and visualized using MATLAB. The amplitude values of the noise points selected in the experiment are as shown in Figure 3 , and the experimental results are as shown in Figure 4 .

[0041] From the experimental results, it can be seen that when the noise amplitude average value is converted to a fixed point number, the calculated signal-to-noise ratio is larger, because the loss of noise amplitude by fixed-point operation is larger, the noise power is smaller than the actual true value, and the error of the calculated signal-to-noise ratio is also larger.

[0042] When the noise amplitude size is adjusted to be around 0 to simulate the actual situation after fixed-point truncation under large signal-to-noise ratio, the experimental results are as shown in Figure 5 .

[0043] From Figure 5 , it can be found that fixed-point operation will directly calculate the noise amplitude as 0, and then cannot correctly calculate the signal-to-noise ratio.

[0044] Those skilled in the art can understand that the above description is only the preferred embodiment of the present application, and the features described in various embodiments of the present disclosure and / or claims can be combined or combined, even if such combination or combination is not explicitly described in the present disclosure. It is not intended to limit the present application, although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent replacement for part of the technical features, any modification, equivalent replacement, improvement, etc. within the spirit and principles of the present application shall be included in the protection scope of the present application.

[0045] Although preferred embodiments of the present application have been described, those skilled in the art can make further changes and modifications to these embodiments once they know the basic inventive concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application. Obviously, those skilled in the art can make various modifications and changes to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and changes of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application also intends to include these modifications and changes.

Claims

1. A method for processing a digital signal using a mixed data format based on an FPGA, characterized by, The method is realized based on a multi-channel power spectrum density and signal-to-noise ratio maximum detection module, and the method comprises the following steps: Step 1, 32 channels of the multi-channel power spectrum density and signal-to-noise ratio maximum detection module are divided into 4 groups; Step 2, the maximum power spectrum density of each group of 8 channels is compared, and finally the maximum power spectrum density signal in the 32 channels is selected through inter-group comparison; Step 3, the signal is sent into FPGA for calculation, the signal-to-noise ratio of the signal is calculated by using a mixed data format method, and compared with a preset minimum signal-to-noise ratio threshold value, if greater than the threshold value, the signal is output, otherwise no output result.

2. The method of claim 1, wherein the method is a method of processing a digital signal using a mixed data format based on an FPGA, and In step 1, the multi-channel power spectrum density and signal-to-noise ratio maximum detection module further comprises a step of converting fixed-point data into floating-point data, namely, Step 1.1, input signal peak value data and noise peak value data, and convert the signal peak value data and the noise peak value data into floating-point; Step 1.2, splice the signal peak value data and the noise peak value data converted into floating-point in step 1 into 64-bit data in the signal processing channel and the noise processing channel respectively, and output the floating-point number.

3. The method of claim 2, wherein the method is a method of processing a digital signal using a mixed data format based on an FPGA, characterized by, The signal peak value data and the noise peak value data input in step 1.1 are expanded into 64-bit format through high-bit zero padding for conversion.

4. The method of claim 2, wherein the data format of the mixed use of the FPGA is based on, In step 1.2, the signal processing channel and the noise processing channel share the same control timing.

5. The method of claim 1, wherein the method is a method of processing a digital signal using a mixed data format based on an FPGA, and the method further comprises: In step 3, the method for sending the signal into FPGA for calculation is obtained through fast Fourier transform method and bit clipping operation. ​ 6. The method of claim 1, wherein the method is a method of processing a digital signal using a mixed data format based on an FPGA, and In step 3, the method for calculating the signal-to-noise ratio of the maximum power spectrum density signal is: wherein, is the signal power, is the noise power.

7. The method of claim 1, wherein the method is a method of processing a digital signal using a mixed data format based on an FPGA, and the method further comprises: In step 3, the output result is visualized by using MATLAB. ​ 8. A digital signal processing system using mixed data formats based on FPGA, characterized by, The system is realized based on a multi-channel power spectrum density and signal-to-noise ratio maximum detection module, and the system comprises: An input module for dividing 32 channels of the multi-channel power spectrum density and signal-to-noise ratio maximum detection module into 4 groups; A data comparison module for comparing the maximum power spectrum density of each group of 8 channels, and finally selecting the maximum power spectrum density signal in the 32 channels through inter-group comparison; An output module for sending the signal into FPGA for calculation, calculating the signal-to-noise ratio of the signal by using a mixed data format method, and comparing with a preset minimum signal-to-noise ratio threshold value, if greater than the threshold value, outputting the signal, otherwise no output result.

9. A computer storage medium having stored thereon a computer program, characterized in that The computer program is executed by the processor to realize the method of any one of claims 1-7.

10. A computer device, comprising: Comprise: A memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor executes the program to realize the method of any one of claims 1-7. Comprise: A memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor executes the program to realize the method of any one of claims 1-7.

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