Display control circuit and method, display substrate, and display device

Abstract

The present disclosure provides a display control circuit and method, a display substrate, and a display device. The display control circuit (100) comprises: at least two shift register circuits and a pixel circuit (13), wherein the at least two shift register circuits include a first shift register (11) and a second shift register (12); the pixel circuit (13) comprises an initialization sub-circuit (130), a storage sub-circuit (131), a drive sub-circuit (132), and a data write sub-circuit (133); a control end of the initialization sub-circuit (130) is connected to a first output end of the first shift register (11), a control end of the data write sub-circuit (133) is connected to a first output end of the second shift register (12), and a shielding sub-circuit is designed in at least one shift register.

Description

Display control circuit, method, display substrate and display device Cross-reference to Related Applications

[0001] This application claims priority to Chinese Patent Application No. 202410677208.0, filed May 29, 2024, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0002] The present disclosure belongs to the technical field of display control, and in particular relates to a display control circuit, method, display substrate and display device. BACKGROUND

[0003] Local refresh refers to refreshing a certain dynamic area (such as an animation) on the screen at a high frequency and refreshing a certain static area (such as text) at a low frequency, thereby achieving the purpose of reducing power consumption. Currently, the local refresh technology is mostly used on LTPO (Low Temperature Polycrystalline Oxide) pixel circuits, but there is a problem of high cost in using the local refresh technology on the LTPO pixel circuit. SUMMARY

[0004] Embodiments of the present application provide a display control circuit, method, display substrate and display device, which can implement local refresh based on an LTPS pixel circuit, thereby reducing the implementation cost of the local refresh technology.

[0005] Other characteristics and advantages of the present application will become apparent from the following detailed description, or will be learned by practice of the present application.

[0006] According to a first aspect of the embodiments of the present application, a display control circuit is provided, comprising: at least two groups of shift register circuits, including a first group of shift register circuits and a second group of shift register circuits; the first group of shift register circuits comprises a plurality of first shift registers arranged in cascade, and the second group of shift register circuits comprises a plurality of second shift registers arranged in cascade; a pixel circuit comprising an initialization sub-circuit, a storage sub-circuit, a driving sub-circuit and a data writing sub-circuit, the initialization sub-circuit is connected with a first node, the storage sub-circuit is connected with the first node and a second node respectively, the data writing sub-circuit is connected with the second node, and the driving sub-circuit is connected with the first node; wherein a control end of the initialization sub-circuit is connected with a first output end of the first shift register, and a control end of the data writing sub-circuit is connected with a first output end of the second shift register; the first shift register and the second shift register comprise a shift register sub-circuit, and at least one of the first shift register and the second shift register further comprises a shielding sub-circuit connected with the shift register sub-circuit; the shift register sub-circuit is configured to output a cascade signal based on an input signal; and an output end of the shielding sub-circuit serves as the first output end and is configured to output a control signal based on a shielding signal, the control signal is a first level when the shielding signal is a first level, and the control signal is the same as the cascade signal when the shielding signal is a second level, wherein the first level is different from the second level.

[0007] In some embodiments, the pixel circuit further comprises a compensation sub-circuit, a first end of the compensation sub-circuit is connected with the first node, configured to write a compensation voltage to the first node, a second end is connected with an output end of the driving sub-circuit, and a control end is connected with the first output end of the second shift register; and the first shift register and the second shift register comprise the shielding sub-circuit, and the control signal output by the shielding sub-circuit is a row scanning signal.

[0008] In some embodiments, the driving mode of the first shift register and the second shift register is double-side driving.

[0009] In some embodiments, the at least two groups of shift register circuits further comprise a third group of shift register circuits, the third group of shift register circuits comprising a plurality of third shift registers arranged in cascade; the initialization sub-circuit comprises a first sub-circuit and a second sub-circuit, an input terminal of the first sub-circuit being configured to receive an initialization voltage signal, an output terminal of the first sub-circuit being connected to a third node, a control terminal of the first sub-circuit being connected to an output terminal of the third shift register, an input terminal of the second sub-circuit being connected to the third node, an output terminal of the second sub-circuit being connected to the first node, and a control terminal of the second sub-circuit being connected to a first output terminal of the first shift register; and the second sub-circuit is further configured to write a compensation voltage to the first node in a compensation phase.

[0010] In some embodiments, the first shift register comprises the shielding sub-circuit, the control signal output by the shielding sub-circuit being a light-emitting control signal; and a shift register sub-circuit in the second shift register is further configured to output a row scanning signal to a control terminal of the data writing sub-circuit.

[0011] In some embodiments, the first shift register and the second shift register comprise the shielding sub-circuit; the shielding sub-circuit in the first shift register outputs the control signal as a light-emitting control signal; and the shielding sub-circuit in the second shift register outputs the control signal as a row scanning signal.

[0012] In some embodiments, the first shift register and the third shift register are driven in a single-side driving mode, and the second shift register is driven in a double-side driving mode.

[0013] In some embodiments, the pixel circuit further comprises a compensation sub-circuit, a first terminal of the compensation sub-circuit being connected to the first node, a second terminal of the compensation sub-circuit being connected to an output terminal of the driving sub-circuit, and a control terminal of the compensation sub-circuit being connected to a first output terminal of the second shift register; the second shift register comprises a shielding sub-circuit, the shielding sub-circuit outputting the control signal as a row scanning signal; and the initialization sub-circuit is connected to a first output terminal of the first shift register and a first output terminal of a second shift register of a previous stage, respectively, and is configured to write the initialization voltage to the first node under control of a control signal output by the first output terminal of the first shift register and a control signal output by the first output terminal of the second shift register of the previous stage.

[0014] In some embodiments, the initialization sub-circuit comprises a third sub-circuit and a fourth sub-circuit, an input terminal of the third sub-circuit is configured to receive an initialization voltage signal, an output terminal of the third sub-circuit is connected with an input terminal of the fourth sub-circuit, and an output terminal of the fourth sub-circuit is connected with the first node; a control terminal of one of the third sub-circuit and the fourth sub-circuit is connected with the first output terminal of the first shift register, and a control terminal of the other is connected with the first output terminal of the second shift register of the previous stage.

[0015] In some embodiments, the initialization sub-circuit comprises a third sub-circuit and a fourth control sub-circuit, an input terminal of the third sub-circuit is configured to receive an initialization voltage signal, an output terminal of the third sub-circuit is connected with the first node, a control terminal of the third sub-circuit is connected with an output terminal of the fourth sub-circuit, an input terminal of the fourth sub-circuit is connected with the first output terminal of the second shift register of the previous stage, and a control terminal of the fourth sub-circuit is connected with the first output terminal of the first shift register.

[0016] In some embodiments, the driving mode of the first shift register is single-side driving or double-side driving, and the driving mode of the second shift register is double-side driving.

[0017] In some embodiments, the at least two groups of shift register circuits further include a third group of shift register circuits, a fourth group of shift register circuits, and a fifth group of shift register circuits, the third group of shift register circuits including a plurality of third shift registers arranged in cascade, the fourth group of shift register circuits including a plurality of fourth shift registers arranged in cascade, and the fifth group of shift register circuits including a plurality of fifth shift registers arranged in cascade; the data writing sub-circuit includes a fifth sub-circuit and a sixth sub-circuit, an input terminal of the fifth sub-circuit being configured to receive a data voltage signal, an output terminal of the fifth sub-circuit being connected to the second node, and a control terminal of the fifth sub-circuit being connected to a first output terminal of the second shift register, an input terminal of the sixth sub-circuit being configured to receive an initialization voltage signal, an output terminal of the sixth sub-circuit being connected to the second node, and a control terminal of the sixth sub-circuit being connected to an output terminal of the third shift register; the initialization sub-circuit includes a seventh sub-circuit, an eighth sub-circuit, and a ninth sub-circuit, an input terminal of the seventh sub-circuit being configured to receive the initialization voltage signal, an output terminal of the seventh sub-circuit being connected to a fourth node, and a control terminal of the seventh sub-circuit being connected to an output terminal of the fourth shift register, an input terminal of the eighth sub-circuit being connected to the fourth node, an output terminal of the eighth sub-circuit being connected to a third node, and a control terminal of the eighth sub-circuit being connected to an output terminal of the fifth shift register, an input terminal of the ninth sub-circuit being connected to the third node, an output terminal of the ninth sub-circuit being connected to the first node, and a control terminal of the ninth sub-circuit being connected to the first output terminal of the first shift register; the first shift register includes a shielding sub-circuit, the control signal output by the shielding sub-circuit being a light-emitting control signal; the eighth sub-circuit is further configured to write a light-emitting control voltage from the fourth node to the light-emitting element in a light-emitting stage; and the ninth sub-circuit is further configured to write a compensation voltage to the first node in a compensation stage.

[0018] In some embodiments, the transistors in the pixel circuit are low-temperature polysilicon transistors.

[0019] According to a second aspect of the embodiments of the present disclosure, a display substrate is provided, including a substrate and a display control circuit as described in the first aspect, the display control circuit being arranged on one side of the substrate.

[0020] According to a third aspect of the embodiments of the present disclosure, a display control method is provided, applied to the display substrate as described in the second aspect, and including: determining a first display area and a second display area of the display substrate; writing a first level to a shielding signal input terminal of a shielding sub-circuit in a shift register corresponding to the first display area; and writing a second level to the shielding signal input terminal of the shielding sub-circuit in the shift register corresponding to the second display area, the first level being different from the second level.

[0021] According to a fourth aspect of the embodiments of the present disclosure, a display device is provided, including the display substrate as described in the second aspect.

[0022] In the present disclosure, at least two groups of shift register circuits and pixel circuits are arranged in the display control circuit, wherein the at least two groups of shift register circuits include a first shift register and a second shift register, the pixel circuit includes an initialization sub-circuit, a storage sub-circuit, a driving sub-circuit and a data writing sub-circuit, the control end of the initialization sub-circuit is connected to the first output end of the first shift register, the control end of the data writing sub-circuit is connected to the first output end of the second shift register, and a shielding sub-circuit is designed in at least one shift register. The above display control circuit design can realize local refresh based on the LTPS pixel circuit, and the implementation cost of the local refresh technology is reduced.

[0023] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0024] The accompanying drawings, which are incorporated into and form part of the specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the disclosure. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained from these drawings without creative labor for those skilled in the art. In the drawings:

[0025] FIG. 1 shows a circuit block diagram of a display control circuit according to some embodiments of the present disclosure;

[0026] FIG. 2 shows a circuit structure diagram of an LTPS 7T1C pixel circuit in the related art;

[0027] FIG. 3 shows a circuit structure diagram of an LTPS 7T1C pixel circuit that can be refreshed at a full screen low frequency;

[0028] FIG. 4 shows a circuit structure diagram of an LTPS 8T1C pixel circuit that can be refreshed at a full screen low frequency;

[0029] FIG. 5 shows an exemplary circuit structure diagram of a shift register including a shielding sub-circuit in FIG. 1;

[0030] FIG. 6 shows a timing diagram of the shift register in FIG. 5 at normal output;

[0031] FIG. 7 shows a timing diagram of the shift register in FIG. 5 at shielding output;

[0032] FIG. 8 shows a circuit structure diagram of the shift register in FIG. 5 driving the 8T1C pixel circuit in FIG. 4;

[0033] FIG. 9 shows a timing diagram of the shift register in FIG. 5 driving the 8T1C pixel circuit in FIG. 4;

[0034] Fig. 10 shows an exemplary detailed schematic of the display control circuit of Fig. 1;

[0035] Fig. 11 shows an exemplary circuit configuration of the pixel circuit of Fig. 10;

[0036] Fig. 12 shows an exemplary timing chart for driving the pixel circuit of Fig. 11;

[0037] Fig. 13 shows an exemplary arrangement schematic of the display control circuit of Fig. 10;

[0038] Fig. 14 shows another exemplary timing chart for driving the pixel circuit of Fig. 11;

[0039] Fig. 15 shows another exemplary detailed schematic of the display control circuit of Fig. 1;

[0040] Fig. 16 shows an exemplary circuit configuration of the pixel circuit of Fig. 15;

[0041] Fig. 17 shows an exemplary arrangement schematic of the display control circuit of Fig. 15;

[0042] Fig. 18 shows an exemplary timing chart for driving the pixel circuit of Fig. 16;

[0043] Fig. 19 shows another exemplary detailed schematic of the display control circuit of Fig. 1;

[0044] Fig. 20 shows an exemplary circuit configuration of the pixel circuit of Fig. 19;

[0045] Fig. 21 shows another exemplary timing chart for driving the pixel circuit of Fig. 16;

[0046] Fig. 22 shows an exemplary timing chart for driving the pixel circuit of Fig. 20;

[0047] Fig. 23 shows another exemplary detailed schematic of the display control circuit of Fig. 1;

[0048] Fig. 24 shows an exemplary circuit configuration of the pixel circuit of Fig. 23;

[0049] Fig. 25 shows another exemplary circuit configuration of the pixel circuit of Fig. 23;

[0050] Fig. 26 shows another exemplary circuit configuration of the pixel circuit of Fig. 23;

[0051] Fig. 27 shows an exemplary timing chart for driving the pixel circuit of Fig. 23;

[0052] Fig. 28 shows an exemplary arrangement of the display control circuit of Fig. 23;

[0053] Fig. 29 shows another exemplary detail of the display control circuit of Fig. 1;

[0054] Fig. 30 shows an exemplary circuit structure of the pixel circuit of Fig. 29;

[0055] Fig. 31 shows a structure of a display substrate according to some embodiments of the present disclosure; and

[0056] Fig. 32 shows a flowchart of a display control method according to some embodiments of the present disclosure.

[0057] BRIEF DESCRIPTION OF DRAWINGS 20 - display substrate; 200 - substrate; 100 - display control circuit; 11 - first shift register, 12 - second shift register, 12' - upper-stage second shift register, 13 - pixel circuit, 130 - initialization sub-circuit, 1301-1309 - first to ninth sub-circuits, 131 - storage sub-circuit, 132 - drive sub-circuit, 133 - data write sub-circuit, 134 - compensation sub-circuit, 14 - third shift register, 15 - fourth shift register, 16 - fifth shift register, N1-N9 - first to ninth nodes, EL - drive light emitting element, T1-T22 - first to twenty-second transistors, Cst - first capacitor, C2-C5 - second to fifth capacitors. DETAILED DESCRIPTION

[0058] Exemplary embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the drawings, it is understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure can be thoroughly understood and the scope of the present disclosure can be accurately conveyed to those skilled in the art.

[0059] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the same meaning as those commonly understood by one of ordinary skill in the art to which the present disclosure belongs. The terms "first", "second", and similar terms are used herein merely to distinguish one element from another, and are not intended to imply any order or sequence in time. The terms "comprises", "comprising", "includes", "including" and the like are not intended to exclude a combination of elements or a combination of steps. The terms "coupled", "connected", and the like are not intended to limit to a direct connection or a mechanical connection, but can include an electrical connection, whether direct or indirect. The terms "upper", "lower", "left", "right", and the like are used herein merely to indicate relative positions, and are not intended to limit the position of the described objects.

[0060] It should also be noted that the source and the drain of the transistors used in the embodiments of the present disclosure can be symmetrical in structure, so that the source and the drain can be physically indistinguishable. In the embodiments of the present disclosure, in order to distinguish the transistors, in addition to the gate as the control electrode, one of the electrodes is directly described as the first electrode and the other electrode is directly described as the second electrode, so that the first electrode and the second electrode of all or part of the transistors in the embodiments of the present disclosure can be interchangeable as needed.

[0061] In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits the detailed description of some known functions and known components.

[0062] The exemplary embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings, and the present disclosure is not limited to these specific embodiments.

[0063] Figure 1 shows a circuit block diagram of a display control circuit according to some embodiments of the present disclosure. As shown in Figure 1, the display control circuit includes at least two groups of shift register circuits, including a first group of shift register circuits and a second group of shift register circuits; the first group of shift register circuits includes a plurality of first shift registers 11 arranged in cascade, and the second group of shift register circuits includes a plurality of second shift registers 12 arranged in cascade; a pixel circuit 13 includes an initialization sub-circuit 130, a storage sub-circuit 131, a driving sub-circuit 132, and a data writing sub-circuit 133, the initialization sub-circuit 130 is connected to a first node N1, the storage sub-circuit 131 is connected to the first node N1 and a second node N2 respectively, the data writing sub-circuit 133 is connected to the second node N2, and the driving sub-circuit 132 is connected to the first node N1; wherein a control terminal of the initialization sub-circuit 130 is connected to a first output terminal of the first shift register 11, and a control terminal of the data writing sub-circuit 133 is connected to a first output terminal of the second shift register 12; the first shift register 11 and the second shift register 12 include a shift register sub-circuit, and at least one of the first shift register 11 and the second shift register 12 further includes a masking sub-circuit connected to the shift register sub-circuit; the shift register sub-circuit is configured to output a cascade signal (carry) based on an input signal (such as GSTV or a carry output by a shift register sub-circuit of a previous stage); the masking sub-circuit has an output terminal as the first output terminal, and is configured to output a control signal based on a masking signal (SU1 or SU2); in a case where the masking signal is at a first level, the control signal is at the first level; and in a case where the masking signal is at a second level, the control signal is the same as the cascade signal.

[0064] In some embodiments, the display control circuit can be applied to a display substrate, such as an active-matrix organic light-emitting diode (AMOLED) display substrate.

[0065] In some embodiments, the light emitting element EL can be a light emitting diode, which can be an organic light emitting diode (OLED) or a quantum dot light emitting diode (QLED), etc., and the present disclosure is not limited thereto. The light emitting element EL can use light emitting materials of different colors to emit light of different colors, thereby realizing color display.

[0066] In some embodiments, the initialization sub-circuit 130 is configured to write an initialization voltage to the first node N1, the data writing sub-circuit 133 is configured to write a data voltage from the second node N2 to the storage sub-circuit 131, and the driving sub-circuit 132 is configured to drive the light emitting element EL to emit light under the control of the voltage of the first node N1.

[0067] It should be noted that the pixel circuit 13 is an LTPS (Low Temperature Poly-Silicon) pixel circuit, and all the transistors in the pixel circuit are P-type thin film transistors, so that the local refresh technology is realized at low cost.

[0068] It can be understood that, for the first stage shift register sub-circuit in the shift register circuit, since there is no upper stage shift register sub-circuit output cascade signal, it is necessary to write an input signal GSTV, and for other stage shift register sub-circuits, the cascade signal output by the upper stage shift register sub-circuit can be used as the GSTV to realize driving.

[0069] It should be further noted that, in the embodiments of the present disclosure, the first level can be an effective level for turning on the transistor, and the second level can be an invalid level for turning off the transistor. Taking the transistor as a P-type thin film transistor, for example, the first level is a high level, and the P-type thin film transistor is turned off, and the second level is a low level, and the P-type thin film transistor is turned on. When the shielding signal is at a high level, the control signal is at a high level, and the shielding function of the shielding sub-circuit takes effect, and at this time, the corresponding display area will be refreshed at a low frequency; and when the second level is at a low level, the control signal is the same as the cascade signal, and the shielding function of the shielding sub-circuit does not take effect, and at this time, the corresponding display area is normally refreshed.

[0070] FIG. 2 shows a circuit structure diagram of an LTPS 7T1C pixel circuit in the related art. All the transistors in the circuit are P-type low temperature poly-silicon transistors. As shown in FIG. 2, the first transistor T1, the second transistor T2, the fourth transistor T4, and the seventh transistor T7 are controlled by a group of Gate GOA (Gate scan driving) circuits, and the Reset is generally the Gate GOA signal of the previous row, that is, while data is written in the current row, the first node N1 and the fourth node N4 of the next row are reset, and the fifth transistor T5 and the sixth transistor T6 are controlled by a group of EM GOA (EM driving) circuits. Under the circuit architecture, in order to ensure that the screen does not flicker at a low frequency, the second node N2 and the fourth node N4 need to be reset during the frame maintaining stage, but since the first transistor T1, the second transistor T2, the fourth transistor T4, and the seventh transistor T7 share a group of Gate GOA circuits, when the second node N2 and the fourth node N4 are reset, the second transistor T2 will also be turned on, which is equivalent to another data write, so the circuit architecture cannot switch from a high frequency to a low frequency.

[0071] FIG. 3 shows a circuit structure diagram of LTPS 7T1C pixel circuit which can refresh the full screen at low frequency. As shown in FIG. 3, the fourth transistor T4 and the seventh transistor T7 are controlled by a set of EM GOA circuit, the first transistor T1 and the second transistor T2 are controlled by a set of Gate GOA circuit, and the fifth transistor T5 and the sixth transistor T6 are controlled by a set of EM GOA circuit. Under this circuit architecture, when the second node N2 and the fourth node N4 are reset in the holding frame stage, the second transistor T2 is turned off, which can solve the problem of screen flicker at low frequency, so this circuit architecture can realize low frequency refresh of the full screen area.

[0072] FIG. 4 shows a circuit structure diagram of LTPS 8T1C pixel circuit which can refresh the full screen at low frequency. As shown in FIG. 4, by adding the eighth transistor T8 connected to the second node N2 in the circuit, the hysteresis of the third transistor T3 can be improved, and the reset of the second node N2 is completed by the initialization voltage Vinit3. The seventh transistor T7 and the eighth transistor T8 are controlled by a set of EM GOA circuit, the first transistor T1, the second transistor T2 and the fourth transistor T4 are controlled by a set of Gate GOA circuit, and the fifth transistor T5 and the sixth transistor T6 are controlled by a set of EM GOA circuit. This circuit architecture can also realize low frequency refresh of the full screen area.

[0073] The LTPS 7T1C pixel circuit shown in FIG. 3 and the LTPS 8T1C pixel circuit shown in FIG. 4 can both realize low-frequency refresh of the full-screen area, but cannot realize low-frequency refresh of a local area. In order to realize local refresh, the embodiments of the present disclosure add a shielding subunit in the GOA circuit, and shield data writing of a part of the area through the shielding subunit to realize low-frequency refresh of the part of the area. FIG. 5 shows an exemplary circuit structure diagram of a shift register containing a shielding subcircuit in FIG. 1. As shown in FIG. 5, taking the shift register as the first shift register for example, the shift register includes a shift register subcircuit 110 and a shielding subcircuit 111, wherein the shift register subcircuit 110 can be a Gate GOA circuit, including a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, a sixteenth transistor T16, a second capacitor C2 and a third capacitor C3, wherein the first electrode of the ninth transistor T9 is configured to receive a GSTV signal, the second electrode is connected with a fifth node N5, and the gate electrode is configured to receive a GCK signal; the first electrode of the tenth transistor T10 is connected with a sixth node N6, the second electrode is configured to receive a GCK signal, and the gate electrode is connected with the fifth node N5; the first electrode of the eleventh transistor T11 is configured to receive a VGL signal, the second electrode is connected with the sixth node N6, and the gate electrode is configured to receive a GCK signal; the first end of the second capacitor C2 is configured to receive a VGH signal, and the second end is connected with the sixth node N6; the gate electrode of the twelfth transistor T12 is connected with the sixth node N6, the first electrode is configured to receive a VGH signal, and the second electrode is connected with the first end of the third capacitor C3 and the first electrode of the thirteenth transistor T13, serving as an output end of the Gate GOA and outputting a cascade signal; the second electrode of the thirteenth transistor T13 is configured to output a GCB signal, and the gate electrode is connected with a seventh node N7; the first electrode of the fourteenth transistor T14 is configured to receive a VGH signal, the second electrode is connected with the first electrode of the fifteenth transistor T15 through an eighth node N8, and the gate electrode is connected with the sixth node N6; the second electrode of the fifteenth transistor T15 is connected with the fifth node N5, and the gate electrode is configured to receive a GCB signal; the first electrode of the sixteenth transistor T16 is connected with the fifth node N5, the second electrode is connected with the seventh node N7, and the gate electrode is configured to receive a VGL signal.

[0074] The shielding unit 111 can include a seventeenth transistor T17, an eighteenth transistor T18, a nineteenth transistor T19, a twentieth transistor T20, a twenty-first transistor T21, a twenty-second transistor T22, a fourth capacitor C4, and a fifth capacitor C5. The gate of the seventeenth transistor T17 is connected to the sixth node N6, the first electrode is configured to receive a VGH signal, and the second electrode is connected to the first terminal of the fourth capacitor C4 and the first electrode of the eighteenth transistor T18, serving as an output terminal of the shielding unit 111, and outputting a control signal Gout. The second electrode of the eighteenth transistor T18 is configured to output a GCB signal, and the gate is connected to the ninth node N9. The first electrode of the nineteenth transistor T19 is configured to receive a VGH signal, the second electrode is connected to the ninth node N9 via the first and second electrodes of the twentieth transistor T20, and the gate is connected to the sixth node N6. The gate of the twentieth transistor T20 is configured to receive a GCB signal. The first electrode of the twenty-first transistor T21 is connected to the seventh node N7, the second electrode is connected to the ninth node N9 via the fifth capacitor C5, and the gate is configured to receive a VGL signal. The first electrode of the twenty-second transistor T22 is configured to receive a shielding signal SU, the second electrode is connected to the ninth node N9, and the gate is connected to the second electrode of the twenty-first transistor T21.

[0075] wherein GSTV is a row driving clock signal, carry is a cascade signal, Gout is a control signal, GCK is a first gate clock signal, GCB is a second gate clock signal, VGH is a high voltage level, VGL is a low voltage level, VGH is a voltage for closing a gate for a P-type low-temperature polysilicon crystal, and VGL is a voltage for opening the gate.

[0076] It can be understood that, in the circuit of the shift register, the shift register sub-circuit 110 is configured to output a cascade signal carry to a next stage of shift register sub-circuit, and the shielding unit 111 is configured to output a control signal Gout to a display area, and the cascade signal and the control signal do not interfere with each other. In some areas, the shielding signal is set to a first voltage level, so that the second transistor T2 and the fourth transistor T4 in the pixel circuit are turned off, and thus the area is kept at a low refresh frequency.

[0077] The circuit of the shift register is based on the 8T2C shift register sub-circuit 110 and further includes the 6T2C shielding unit 111. In the implementation process, the shielding unit 111 is not limited to the 6T2C circuit design, and more thin film transistors and capacitors can be added to enhance the output capacity or improve the function of the shielding unit 111. The shift register sub-circuit 110 is not limited to 8T2C, and the shielding unit 111 can be added to 12T3C, 16T3C, and other circuits.

[0078] Fig. 6 shows a timing diagram of the shift register in Fig. 5 in normal output. In Fig. 6, SU is the mask signal. As shown in Fig. 6, when GSTV is low, GCK is low, and GCB is high, for the shift sub-circuit, the ninth transistor T9 and the eleventh transistor T11 are turned on, the sixth node N6 and the seventh node N7 are set low, and the twelfth transistor T12 and the thirteenth transistor T13 are turned on, so that the carry signal is high. For the mask sub-circuit, the sixth node N6 is set low, the sixteenth transistor T16 is turned on, the Gout signal is high, the seventh node N7 is set low, the seventeenth transistor T17 is turned on, the seventh node N7 is set low, the twenty-second transistor T22 is turned on, and the mask signal SU is written into the ninth node N9. Since the mask signal is low at this time, the eighteenth transistor T18 is turned on, the GCB is output, and the GCB is high, so the Gout signal is still high.

[0079] Fig. 7 shows a timing diagram of the shift register in Fig. 5 in mask output. As shown in Fig. 7, when GSTV is high, GCK is high, and GCB is low, for the shift sub-circuit, the ninth transistor T9 and the eleventh transistor T11 are turned off, the seventh node N7 and the fifth node N5 maintain the state of the previous time, which is low, so the tenth transistor T10 is turned on, the GCK is written into the sixth node N6, which is high, and the twelfth transistor T12 is turned off. The seventh node N7 is low, so that the thirteenth transistor T13 is turned on, and the GCB is output. At this time, the carry signal is low. For the mask sub-circuit, the sixth node N6 is high, the seventeenth transistor T17 is turned off, the seventh node N7 is low, the twenty-second transistor T22 is turned on, and the mask signal SU is written in. At this time, whether the eighteenth transistor T18 is turned on or not depends on the high or low of the mask signal SU. If the mask signal SU is low, the eighteenth transistor T18 is normally turned on, the GCB is output, and the Gout is low, as shown in Fig. 6. If the mask signal SU is high, the eighteenth transistor T18 is turned off, the Gout is maintained by the fourth capacitor C4, and the high output is achieved, as shown in Fig. 7, so that the mask function is realized.

[0080] If the local refresh design is based on the LTPS 8T1C pixel circuit, a shielding sub-circuit is added in the shift register sub-circuit, and a circuit structure diagram obtained is shown in FIG. 8. If the second transistor T2, the fourth transistor T4 and the first transistor T1 are still controlled by the same set of GOA circuits, the first node N1 of the next row is refreshed at the same time of the reset of the current row, and in this case, two phenomena can occur according to the area where the low-frequency refresh area is located. The first phenomenon is that if the upper half of the screen is a high-frequency refresh area and the lower half of the screen is a low-frequency refresh area, the first node N1 of the first row of the low-frequency refresh area is refreshed, and then a bright line can appear at the boundary between the high-frequency refresh area and the low-frequency refresh area. The second phenomenon is that if the upper half of the screen is a low-frequency refresh area and the lower half of the screen is a high-frequency refresh area, the first node N1 of the first row of the high-frequency refresh area is not refreshed due to no data writing in the low-frequency refresh area, and then a picture abnormality can appear. Referring to a timing diagram shown in FIG. 9, the shielding is performed by the SU in the nth row, but the refresh of the first node N1 of the nth row is determined by the data writing in the n-1th row, and thus cannot be shielded. Therefore, in the local refresh design of the LTPS pixel circuit, the key point is that the influence of the previous row on the current row cannot be associated, or the associated influence can be shielded through special design.

[0081] Through the design of the display control circuit in the embodiments of the present disclosure, the local refresh can be implemented based on the LTPS pixel circuit, the implementation cost of the local refresh technology is reduced, and through the control of the data writing of the second node and the refresh of the first node by different sets of shift registers, the data writing of the current row will not affect the refresh of the first node N1 of the next row, and thus the normal display of the picture in the local refresh process is ensured.

[0082] FIG. 10 shows an example detailed schematic diagram of the display control circuit in FIG. 1. As shown in FIG. 10, the pixel circuit further includes a compensation sub-circuit 134, a first end of the compensation sub-circuit 134 is connected with the first node N1, for writing a compensation voltage to the first node N1, a second end is connected with the output end of the driving sub-circuit 132, and a control end is connected with the first output end of the second shift register 12; the first shift register 11 and the second shift register 12 include a shielding sub-circuit, and the control signal output by the shielding sub-circuit is a row scanning signal.

[0083] Fig. 11 shows an exemplary circuit structure diagram of the pixel circuit in Fig. 10. In combination with Fig. 10 and Fig. 11, in some embodiments, the initialization sub-circuit 130 can include a first transistor T1, the storage sub-circuit 131 can include a first capacitor Cst, the compensation sub-circuit 134 can include a second transistor T2, the driving sub-circuit 132 can include a third transistor T3, and the data writing sub-circuit 133 can include a fourth transistor T4. In a specific implementation process, the pixel circuit 13 can further include a first light-emitting control sub-circuit (not shown in the figure) and a second light-emitting control sub-circuit (not shown in the figure), the first light-emitting control sub-circuit includes a fifth transistor T5, the second light-emitting control sub-circuit includes a sixth transistor T6, the initialization sub-circuit 130 can further include a seventh transistor T7, and the data writing sub-circuit 133 can further include an eighth transistor T8. The gate of the first transistor T1 is controlled by the first shift register 11, the gates of the second transistor T2 and the fourth transistor T4 are controlled by the second shift register 12, the gates of the fifth transistor T5 and the sixth transistor T6 can be controlled by a shift register EM1, and the gates of the seventh transistor T7 and the eighth transistor T8 can be controlled by a shift register EM2.

[0084] It should be noted that the sub-circuits of the pixel circuit in Fig. 10 are not limited to the above design, and the number of thin film transistors can be reduced, or more thin film transistors and capacitors can be added to enhance the output capability of the sub-circuits.

[0085] Fig. 12 shows an exemplary timing diagram for driving the pixel circuit in Fig. 11. As shown in Fig. 12, at the nth row, the shielding signal SU2 of the shielding sub-circuit of the second shift register is switched to high level, which can shield the data writing of the nth row, and the shielding signal SU1 of the shielding sub-circuit of the first shift register can be switched to high level 1H (H is the time length required for refreshing one row of pixels by the data signal) in advance, shielding the refresh of the first node N1 of the nth row, so as to ensure the normal display of the picture at the junction of the high-frequency refresh area and the low-frequency refresh area.

[0086] Fig. 13 shows an exemplary arrangement diagram of the display control circuit in Fig. 10. As shown in Fig. 13, the driving mode of the first shift register (Gate1+SU1) and the second shift register (Gate2+SU2) can be double-side driving, and the driving mode of the shift register EM1 and the shift register EM2 can be single-side driving, which can reduce the frame size. In other embodiments, the driving mode of the four shift registers can be double-side driving, which can increase the frame size, but can ensure the improvement of the uniformity of the display brightness.

[0087] Fig. 14 shows another exemplary timing diagram for driving the pixel circuit in Fig. 11. As shown in Fig. 14, the driving principle of the pixel circuit in Fig. 11 is that the shielding signal SU1 and the shielding signal SU2 are high at the beginning of the nth row, and are maintained low before the (n-1)th row. If the base frequency is 120 Hz, the control signal and the cascade signal are the same before the (n-1)th row, the shielding effect does not take effect, and each frame is refreshed, so the refresh frequency before the (n-1)th row is 120 Hz. From the nth row, the control signal is high, the shielding effect takes effect, which is equivalent to refreshing one frame and keeping one frame, so the refresh frequency from the nth row is 60 Hz.

[0088] Fig. 15 shows another exemplary detailed schematic diagram of the display control circuit in Fig. 1. As shown in Fig. 15, the at least two groups of shift register circuits further include a third group of shift register circuits, the third group of shift register circuits including a plurality of third shift registers 14 arranged in cascade; the initialization sub-circuit includes a first sub-circuit 1301 and a second sub-circuit 1302, the input terminal of the first sub-circuit 1301 being configured to receive an initialization voltage signal Vinit1, the output terminal of the first sub-circuit 1301 being connected with the third node N3, and the control terminal of the first sub-circuit 1301 being connected with the output terminal of the third shift register 14, the input terminal of the second sub-circuit 1302 being connected with the third node N3, the output terminal of the second sub-circuit 1302 being connected with the first node N1, and the control terminal of the second sub-circuit 1302 being connected with the first output terminal of the first shift register 11; the second sub-circuit 1302 is further configured to write a compensation voltage to the first node N1 in a compensation stage. The first shift register 11 includes a shielding sub-circuit 111, and the control signal output by the shielding sub-circuit 111 is a light-emitting control signal; the shift register sub-circuit 120 in the second shift register 12 is further configured to output a row scanning signal to the control terminal of the data writing sub-circuit 133.

[0089] Fig. 16 shows an exemplary circuit structure diagram of the pixel circuit in Fig. 15. In combination with Fig. 15 and Fig. 16, in some embodiments, the first sub-circuit 1301 can include a first transistor T1, the second sub-circuit 1302 can include a second transistor T2, the storage sub-circuit 131 can include a first capacitor Cst, the driving sub-circuit 132 can include a third transistor T3, and the data writing sub-circuit 133 can include a fourth transistor T4. In a specific implementation process, the pixel circuit 13 can further include a first light-emitting control sub-circuit (not shown in the figure) and a second light-emitting control sub-circuit (not shown in the figure), the first light-emitting control sub-circuit includes a fifth transistor T5, the second light-emitting control sub-circuit includes a sixth transistor T6, the initialization sub-circuit 130 can further include a seventh transistor T7, and the data writing sub-circuit 133 can further include an eighth transistor T8. The gate of the first transistor T1 is controlled by the third shift register 14, the gate of the second transistor T2 is controlled by the first shift register 11, the gate of the fourth transistor T4 is controlled by the second shift register 12, the gates of the fifth transistor T5 and the sixth transistor T6 can be controlled by a shift register EM1, and the gates of the seventh transistor T7 and the eighth transistor T8 can be controlled by a shift register EM2.

[0090] It can be understood that, in order to achieve the refresh of the first node N1, the initialization voltage signal Vinit1 needs to open the first transistor T1 and the second transistor T2 at the same time, and in the architecture of the pixel circuit, the data writing of the current row will not affect the next row. Since the first transistor T1 and the second transistor T2 are controlled by different shift registers, the initialization voltage signal Vinit1 cannot reset the first node N1 when the second transistor T2 is shielded, and therefore the gate of the first transistor T1 does not need to be controlled by a shielding sub-circuit.

[0091] Fig. 17 shows an exemplary arrangement diagram of the display control circuit in Fig. 15. In combination with Fig. 15 to Fig. 17, EM4+SU corresponds to the first shift register 11, Gate corresponds to the second shift register 12, and EM3 corresponds to the third shift register 14. The driving mode of the first shift register and the third shift register is single-side driving, and the driving mode of the second shift register is double-side driving.

[0092] Fig. 18 shows an exemplary timing diagram for driving the pixel circuit in Fig. 16. As shown in Fig. 18, at the nth row, the shielding signal SU of the shielding sub-circuit of the first shift register is switched to high level, which can shield the refresh of the first node N1 of the nth row, so as to ensure the normal display of the picture at the junction of the high-frequency refresh area and the low-frequency refresh area.

[0093] Fig. 19 shows another exemplary detailed schematic diagram of the display control circuit in Fig. 1. As shown in Fig. 19, the at least two groups of shift register circuits further include a third group of shift register circuits including a plurality of third shift registers 14 arranged in cascade; the initialization sub-circuit 130 includes a first sub-circuit 1301 and a second sub-circuit 1302, an input terminal of the first sub-circuit 1301 is configured to receive an initialization voltage signal, an output terminal of the first sub-circuit 1301 is connected with the third node N3, and a control terminal of the first sub-circuit 1301 is connected with an output terminal of the third shift register 14; an input terminal of the second sub-circuit 1302 is connected with the third node N3, an output terminal of the second sub-circuit 1302 is connected with the first node N1, and a control terminal of the second sub-circuit 1302 is connected with a first output terminal of the first shift register 11; the second sub-circuit 1302 is further configured to write a compensation voltage to the first node N1 in a compensation stage. The first shift register 11 and the second shift register 12 include a shielding sub-circuit; the shielding sub-circuit 111 in the first shift register 11 outputs a light emission control signal as the control signal; and the shielding sub-circuit 121 in the second shift register 12 outputs a row scanning signal as the control signal.

[0094] Fig. 20 shows an exemplary circuit structure diagram of the pixel circuit in Fig. 19. Fig. 20 has the same pixel circuit architecture as Fig. 16, except that a shielding sub-circuit is added to the second shift register 12 to realize shielding control of the gate of the fourth transistor T4. Fig. 21 shows another exemplary timing diagram for driving the pixel circuit in Fig. 16, and Fig. 22 shows an exemplary timing diagram for driving the pixel circuit in Fig. 20. As can be seen from Figs. 21 and 22, through this design, in the holding frame stage of the low-frequency refresh area, the data voltage will not refresh the second node N2, while in the holding frame stage in Fig. 16, the data voltage will refresh to the second node N2, affecting the source potential of the third transistor T3, so the circuit structure shown in Fig. 20 can have an advantage in low-frequency display effect, but inevitably brings an increase in the frame.

[0095] Fig. 23 shows another exemplary detailed schematic diagram of the display control circuit in Fig. 1. As shown in Fig. 23, the pixel circuit 13 further includes a compensation sub-circuit 134, a first end of the compensation sub-circuit 134 is connected with the first node N1, configured to write a compensation voltage to the first node N1, a second end of the compensation sub-circuit 134 is connected with an output terminal of the driving sub-circuit 132, and a control terminal of the compensation sub-circuit 134 is connected with a first output terminal of the second shift register 12; the second shift register 12 includes a shielding sub-circuit 121, and the shielding sub-circuit 121 outputs a row scanning signal as the control signal; the initialization sub-circuit 130 is connected with the first output terminal of the first shift register 11 and the first output terminal of the second shift register 12' of the previous stage, respectively, and is configured to write an initialization voltage to the first node N1 under control of the control signal outputted by the first output terminal of the first shift register 11 and the control signal outputted by the first output terminal of the second shift register 12' of the previous stage.

[0096] In some embodiments, the initialization sub-circuit 130 includes a third sub-circuit 1303 and a fourth sub-circuit 1304, an input terminal of the third sub-circuit 1303 is configured to receive an initialization voltage signal, an output terminal of the third sub-circuit 1303 is connected with an input terminal of the fourth sub-circuit 1304, and an output terminal of the fourth sub-circuit 1304 is connected with the first node N1; a control terminal of one of the third sub-circuit 1303 and the fourth sub-circuit 1304 is connected with the first output terminal of the first shift register 11, and a control terminal of the other one is connected with the first output terminal of the second shift register 12’ of the previous stage.

[0097] FIGS. 24 and 25 show two exemplary circuit structure diagrams of the pixel circuit in FIG. 23. As shown in FIG. 24, the third sub-circuit 1303 can include a first transistor T1, the fourth sub-circuit 1304 can include a ninth transistor T9, the storage sub-circuit 131 can include a first capacitor Cst, the compensation sub-circuit 134 can include a second transistor T2, the driving sub-circuit 132 can include a third transistor T3, and the data writing sub-circuit 133 can include a fourth transistor T4. In a specific implementation process, the pixel circuit 13 can further include a first light-emitting control sub-circuit (not shown in the figure) and a second light-emitting control sub-circuit (not shown in the figure), the first light-emitting control sub-circuit includes a fifth transistor T5, the second light-emitting control sub-circuit includes a sixth transistor T6, the initialization sub-circuit 130 can further include a seventh transistor T7, and the data writing sub-circuit 133 can further include an eighth transistor T8. A gate of the first transistor T1 is controlled by the second shift register 12’ of the previous stage, a gate of the second transistor T2 and a gate of the fourth transistor T4 are controlled by the second shift register 12, a gate of the ninth transistor T9 is controlled by the first shift register 11, a gate of the fifth transistor T5 and a gate of the sixth transistor T6 are controlled by the shift register M1, and a gate of the seventh transistor T7 and a gate of the eighth transistor T8 are controlled by the shift register M2.

[0098] The difference between FIG. 25 and FIG. 24 is that the ninth transistor T9 is arranged at a source or a drain of the first transistor T1, respectively, and in FIG. 25, the third sub-circuit 1303 includes the ninth transistor T9, and the fourth sub-circuit 1304 includes the first transistor T1.

[0099] In some embodiments, the initialization sub-circuit 130 includes a third sub-circuit 1303 and a fourth control sub-circuit 1304, an input terminal of the third sub-circuit 1303 is configured to receive an initialization voltage signal, an output terminal of the third sub-circuit 1303 is connected with the first node N1, a control terminal of the third sub-circuit 1303 is connected with an output terminal of the fourth sub-circuit 1304, an input terminal of the fourth sub-circuit 1304 is connected with the first output terminal of the second shift register 12’ of the previous stage, and a control terminal of the fourth sub-circuit 1304 is connected with the first output terminal of the first shift register 11.

[0100] Fig. 26 shows another exemplary circuit structure of the pixel circuit in Fig. 23. As shown in Fig. 26, the third sub-circuit 1303 can include the first transistor T1, and the fourth sub-circuit 1304 can include the ninth transistor T9, and the gate of the first transistor T1 is controlled by the ninth transistor T9. The difference between Fig. 26 and Fig. 24 is that the ninth transistor T9 is arranged at the gate of the first transistor T1.

[0101] The three pixel circuits above respectively add the ninth transistor T9 at the drain, source and gate of the first transistor T1 to control whether the initialization voltage Vinit1 is written into the first transistor T1. Under the three circuit architectures, the first transistor T1, the second transistor T2 and the fourth transistor T4 are controlled by the second shift register 12, and whether the first node N1 is refreshed is controlled by the ninth transistor T9. In the low-frequency refresh area, the ninth transistor T9 can be turned off to ensure that the first node N1 is not refreshed.

[0102] Fig. 27 shows an exemplary timing diagram for driving the pixel circuit in Fig. 23. As shown in Fig. 27, at the nth row, the shielding signal SU of the shielding sub-circuit of the second shift register is switched to high level, and the signal output by the first shift register is switched to high level 1H in advance, so that the refresh of the first node N1 and the data writing of the second node N2 of the nth row can be shielded, thereby ensuring the normal display of the picture at the junction of the high-frequency refresh area and the low-frequency refresh area.

[0103] Fig. 28 shows an exemplary arrangement of the display control circuit in Fig. 23. In combination with Figs. 23 to 28, EM3 corresponds to the first shift register, Gate+SU corresponds to the second shift register, EM1 corresponds to the shift register connected with the fifth transistor T5 and the sixth transistor T6, EM2 corresponds to the shift register connected with the seventh transistor T7 and the eighth transistor T8, the driving mode of the first shift register is double-side driving, the driving mode of the second shift register is double-side driving, and the driving mode of the shift register M1 and the shift register M2 is single-side driving. Of course, other driving modes can also be used. In order to ensure the uniformity of the screen display brightness, the driving mode of the second shift register must be double-side driving, and the other shift registers can be selected as double-side driving and single-side driving according to actual needs.

[0104] Fig. 29 shows another exemplary detailed schematic diagram of the display control circuit in Fig. 1. As shown in Fig. 29, the at least two groups of shift register circuits further include a third group of shift register circuits, a fourth group of shift register circuits and a fifth group of shift register circuits, the third group of shift register circuits including a plurality of third shift registers 14 arranged in cascade, the fourth group of shift register circuits including a plurality of fourth shift registers 15 arranged in cascade, and the fifth group of shift register circuits including a plurality of fifth shift registers 16 arranged in cascade; the data writing sub-circuit 133 includes a fifth sub-circuit 1331 and a sixth sub-circuit 1332, the fifth sub-circuit 1331 having an input terminal for receiving a data voltage signal Vdata, an output terminal connected to the second node N2, and a control terminal connected to a first output terminal of the second shift register 12, and the sixth sub-circuit 1332 having an input terminal for receiving an initialization voltage signal Vinit3, an output terminal connected to the second node N2, and a control terminal connected to an output terminal of the third shift register 14; the initialization sub-circuit 130 includes a seventh sub-circuit 1307, an eighth sub-circuit 1308 and a ninth sub-circuit 1309, the seventh sub-circuit 1307 having an input terminal for receiving the initialization voltage signal Vinit2, an output terminal connected to the fourth node N4, and a control terminal connected to an output terminal of the fourth shift register 15, the eighth sub-circuit 1308 having an input terminal connected to the fourth node N4, an output terminal connected to the third node N3, and a control terminal connected to an output terminal of the fifth shift register 16, and the ninth sub-circuit 1309 having an input terminal connected to the third node N3, an output terminal connected to the first node N1, and a control terminal connected to a first output terminal of the first shift register 11; the first shift register 11 includes a masking sub-circuit 111, and the control signal outputted by the masking sub-circuit 111 is a light emission control signal; the eighth sub-circuit 1308 is further configured to write a light emission control voltage from the fourth node N4 to the light emitting element in a light emission stage; and the ninth sub-circuit 1309 is further configured to write a compensation voltage to the first node N1 in a compensation stage.

[0105] FIG. 30 shows an exemplary circuit structure diagram of the pixel circuit in FIG. 29. As shown in FIG. 30, the fifth sub-circuit 1331 can include the fourth transistor T4, the sixth sub-circuit 1332 can include the eighth transistor T8, the storage sub-circuit 131 can include the first capacitor Cst, the driving sub-circuit 132 can include the third transistor T3, the seventh sub-circuit 1307 can include the seventh transistor T7, the eighth sub-circuit 1308 can include the sixth transistor T6, and the ninth sub-circuit 1309 can include the second transistor T2. In a specific implementation process, the pixel circuit 13 can further include a light-emitting control sub-circuit (not shown in the figure), which includes the fifth transistor T5. The gate of the second transistor T2 is controlled by the first shift register 11, the gate of the fourth transistor T4 is controlled by the second shift register 12, and the gates of the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are all controlled by different shift registers.

[0106] It can be understood that, by controlling the fifth transistor T5 and the sixth transistor T6 by different shift registers, the second transistor T2, the sixth transistor T6, and the seventh transistor T7 can be set to be turned on at the same time in the timing, and the first node N1 is reset by the initialization voltage Vinit2. In addition, by also controlling the seventh transistor T7 and the eighth transistor T8 by different shift registers, the seventh transistor T7 and the eighth transistor T8 can be prevented from being turned on at the same time, causing the initialization voltage Vinit2 and the initialization voltage Vinit3 to be short-circuited. This circuit architecture can also achieve that the first row of the low-frequency refresh area does not perform refresh of the first node N1, and the pixel circuit has fewer thin film transistors but more shift registers.

[0107] It should be noted that the pixel circuit in the present disclosure can be designed based on a low-frequency LTPS 8T1C pixel circuit or a low-frequency LTPS 7T1C pixel circuit, and a person skilled in the art can also design it based on other low-frequency LTPS pixel circuits according to actual needs.

[0108] FIG. 31 is a structural schematic diagram of a display substrate 20 according to some embodiments of the present disclosure. As shown in FIG. 31, the display substrate 20 includes a substrate 200 and a display control circuit 100 provided by any of the embodiments above, and the display control circuit 100 is arranged on one side of the substrate 200. The display control circuit 100 can include shift register circuits 1-n and a pixel circuit 13, the shift register circuits 1-n are connected with the pixel circuit 13, the pixel circuit 13 is connected with a light-emitting element EL, and the light-emitting element EL is controlled to emit light.

[0109] FIG. 32 shows a flow chart of a display control method according to some embodiments of the present disclosure. As shown in FIG. 32, the display control method is applied to the display substrate provided above, and the method can include the following steps:

[0110] Step S101, determining a first display area and a second display area of the display substrate;

[0111] Step S102, writing a first level to the shielding signal input end of the shielding sub-circuit in the shift register corresponding to the first display area; and

[0112] Step S103, writing a second level to the shielding signal input end of the shielding sub-circuit in the shift register corresponding to the second display area, wherein the first level is different from the second level.

[0113] The first display area refers to a display area requiring low-frequency refresh, and the second display area refers to a display area requiring high-frequency refresh. The specific positions and specific quantities of the first display area and the second display area on the display substrate are not limited in the embodiments of the present disclosure.

[0114] Suppose the shift register corresponding to the first display area is in the nth row, then before the nth row, the shielding signal written to the shielding sub-circuit is the second level (for example, low level), and at the nth row, the shielding signal written to the shielding sub-circuit is switched to the first level (for example, high level), thereby realizing high-frequency refresh of the second display area and low-frequency refresh of the first display area.

[0115] Taking FIG. 12 as an example, at the nth row, the shielding signal SU2 of the shielding sub-circuit of the second shift register is switched to high level, the data written to the nth row can be shielded, the shielding signal SU1 of the shielding sub-circuit of the first shift register can be switched to high level 1H in advance, and the refresh of the first node N1 of the nth row is shielded, so as to ensure the normal display of the picture at the junction of the high-frequency refresh area and the low-frequency refresh area.

[0116] Taking FIG. 18 as an example, at the nth row, the shielding signal SU of the shielding sub-circuit of the first shift register is switched to high level, the refresh of the first node N1 of the nth row can be shielded, so as to ensure the normal display of the picture at the junction of the high-frequency refresh area and the low-frequency refresh area.

[0117] The present disclosure also provides a display device including the display substrate 20 described above. In some embodiments, the display device can be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, a wearable device, etc., and the embodiments of the present disclosure are not limited in this regard.

[0118] In addition, those skilled in the art should understand that the above discussion of any embodiment is merely exemplary in nature and is not intended to imply that the scope of the disclosure is limited to these examples; the above embodiments or technical features among different embodiments can also be combined, the steps can be implemented in any order, and there are many other changes of different aspects of one or more embodiments of the disclosure as described above, which are not provided in details for the sake of brevity.

[0119] While the preferred embodiments of the disclosure have been described, additional variations and modifications can be made to the embodiments by those skilled in the art once they learn of the basic inventive concepts. Therefore, the appended claims are intended to encompass within their scope all possible variations and modifications of the preferred embodiments.

Claims

1. A display control circuit, comprising: at least two groups of shift register circuits, including a first group of shift register circuits and a second group of shift register circuits; the first group of shift register circuits includes a plurality of first shift registers arranged in cascade, and the second group of shift register circuits includes a plurality of second shift registers arranged in cascade; a pixel circuit including an initialization sub-circuit, a storage sub-circuit, a driving sub-circuit and a data writing sub-circuit, the initialization sub-circuit is connected to a first node, the storage sub-circuit is connected to the first node and a second node respectively, the data writing sub-circuit is connected to the second node, and the driving sub-circuit is connected to the first node; wherein a control terminal of the initialization sub-circuit is connected to a first output terminal of the first shift register, and a control terminal of the data writing sub-circuit is connected to a first output terminal of the second shift register; the first shift register and the second shift register include a shift register sub-circuit, and at least one of the first shift register and the second shift register further includes a shielding sub-circuit connected to the shift register sub-circuit; the shift register sub-circuit is configured to output a cascade signal based on an input signal; and an output terminal of the shielding sub-circuit serves as the first output terminal and is configured to output a control signal based on a shielding signal, the control signal is a first level when the shielding signal is a first level, and the control signal is the same as the cascade signal when the shielding signal is a second level, wherein the first level is different from the second level.

2. The display control circuit of claim 1, wherein the pixel circuit further includes a compensation sub-circuit, a first terminal of the compensation sub-circuit is connected to the first node and configured to write a compensation voltage to the first node, a second terminal is connected to an output terminal of the driving sub-circuit, and a control terminal is connected to the first output terminal of the second shift register; and the first shift register and the second shift register include the shielding sub-circuit, and the control signal output by the shielding sub-circuit is a row scanning signal.

3. The display control circuit according to claim 2, wherein The driving mode of the first shift register and the second shift register is double-side driving.

4. The display control circuit of claim 1, wherein the at least two groups of shift register circuits further include a third group of shift register circuits, and the third group of shift register circuits includes a plurality of third shift registers arranged in cascade; the initialization sub-circuit includes a first sub-circuit and a second sub-circuit, an input terminal of the first sub-circuit is configured to receive an initialization voltage signal, an output terminal is connected to a third node, and a control terminal is connected to an output terminal of the third shift register, an input terminal of the second sub-circuit is connected to the third node, an output terminal is connected to the first node, and a control terminal is connected to the first output terminal of the first shift register; and the second sub-circuit is further configured to write a compensation voltage to the first node in a compensation phase.

5. The display control circuit of claim 4, wherein The first shift register comprises the shielding sub-circuit, and the control signal output by the shielding sub-circuit is a light-emitting control signal. The shift register sub-circuit in the second shift register is further configured to output a row scanning signal to a control end of the data writing sub-circuit.

6. The display control circuit of claim 4, wherein, The first shift register and the second shift register comprise the shielding sub-circuit. The control signal output by the shielding sub-circuit in the first shift register is a light-emitting control signal. The control signal output by the shielding sub-circuit in the second shift register is a row scanning signal.

7. The display control circuit according to claim 4, wherein The driving mode of the first shift register and the third shift register is single-side driving, and the driving mode of the second shift register is double-side driving.

8. The display control circuit of claim 1, wherein, The pixel circuit further comprises a compensation sub-circuit, a first end of the compensation sub-circuit is connected with the first node, the compensation sub-circuit is configured to write a compensation voltage to the first node, a second end of the compensation sub-circuit is connected with the output end of the driving sub-circuit, and a control end of the compensation sub-circuit is connected with a first output end of the second shift register. The second shift register comprises a shielding sub-circuit, and the control signal output by the shielding sub-circuit is a row scanning signal. The initialization sub-circuit is connected with a first output end of the first shift register and a first output end of a second shift register of a previous stage, respectively, and is configured to write the initialization voltage to the first node under control of a control signal output by the first output end of the first shift register and a control signal output by the first output end of the second shift register of the previous stage.

9. The display control circuit of claim 8, wherein, The initialization sub-circuit comprises a third sub-circuit and a fourth sub-circuit, an input end of the third sub-circuit is configured to receive an initialization voltage signal, an output end of the third sub-circuit is connected with an input end of the fourth sub-circuit, and an output end of the fourth sub-circuit is connected with the first node. A control end of one of the third sub-circuit and the fourth sub-circuit is connected with the first output end of the first shift register, and a control end of the other is connected with the first output end of the second shift register of the previous stage.

10. The display control circuit of claim 8, wherein, The initialization sub-circuit comprises a third sub-circuit and a fourth control sub-circuit, an input end of the third sub-circuit is configured to receive an initialization voltage signal, an output end of the third sub-circuit is connected with the first node, a control end of the third sub-circuit is connected with an output end of the fourth sub-circuit, an input end of the fourth sub-circuit is connected with the first output end of the second shift register of the previous stage, and a control end of the fourth sub-circuit is connected with the first output end of the first shift register. The driving mode of the first shift register is single-side driving or double-side driving, and the driving mode of the second shift register is double-side driving.

11. The display control circuit according to any one of claims 8 to 10, wherein 12. The display control circuit of claim 1, wherein, ​ The at least two groups of shift register circuits further include a third group of shift register circuits, a fourth group of shift register circuits and a fifth group of shift register circuits, the third group of shift register circuits includes a plurality of third shift registers arranged in cascade, the fourth group of shift register circuits includes a plurality of fourth shift registers arranged in cascade, and the fifth group of shift register circuits includes a plurality of fifth shift registers arranged in cascade; The data writing sub-circuit includes a fifth sub-circuit and a sixth sub-circuit, the fifth sub-circuit has an input end for receiving a data voltage signal, an output end connected with the second node, and a control end connected with a first output end of the second shift register, and the sixth sub-circuit has an input end for receiving an initialization voltage signal, an output end connected with the second node, and a control end connected with an output end of the third shift register; The initialization sub-circuit includes a seventh sub-circuit, an eighth sub-circuit and a ninth sub-circuit, the seventh sub-circuit has an input end for receiving an initialization voltage signal, an output end connected with a fourth node, and a control end connected with an output end of the fourth shift register, the eighth sub-circuit has an input end connected with the fourth node, an output end connected with a third node, and a control end connected with an output end of the fifth shift register, and the ninth sub-circuit has an input end connected with the third node, an output end connected with the first node, and a control end connected with a first output end of the first shift register; The first shift register includes a shielding sub-circuit, and the control signal output by the shielding sub-circuit is a light-emitting control signal; The eighth sub-circuit is further configured to write a light-emitting control voltage from the fourth node to the light-emitting element in a light-emitting stage; and The ninth sub-circuit is further configured to write a compensation voltage to the first node in a compensation stage.

13. The display control circuit according to any one of claims 1 to 12, wherein The transistors in the pixel circuit are all low-temperature polysilicon transistors.

14. A display substrate, comprising: a substrate substrate, and the display control circuit in any one of claims 1-13, which is arranged on one side of the substrate substrate.

15. A display control method applied to the display substrate in claim 14, the method comprising: determining a first display area and a second display area of the display substrate; writing a first level to a shielding signal input end of a shielding sub-circuit in a shift register corresponding to the first display area; and writing a second level to the shielding signal input end of the shielding sub-circuit in the shift register corresponding to the second display area, wherein the first level is different from the second level.

16. A display device comprising the display substrate in claim 15. ​

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