Display panel and display device

Abstract

The present disclosure provides a display panel and a display device. The display panel comprises data signal lines and power signal lines extending in a column direction, wherein the data signal lines are located in each column of first sub-pixel areas, and the power signal lines are located in each column of first sub-pixel areas and each column of virtual sub-pixel areas. The display panel further comprises a main power signal line located in a peripheral area and provided on at least one side of a display area, and power signal transfer lines extending in a row direction. In the first sub-pixel areas, some of the power signal lines are connected to each other by means of a same power signal transfer line, some of the power signal lines are connected to the main power signal line by means of a same power signal transfer line, some of the power signal lines are separately connected to the main power signal line by means of different power signal transfer lines, and at least one end of each of the remaining power signal lines is connected to the main power signal line. In the virtual sub-pixel areas, at least one end of each power signal line is connected to the main power signal line.

Description

Display panel and display device

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 202410703284.4, filed on May 31, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure belongs to the field of display technology, specifically relating to a display panel and display device. Background Technology

[0004] Organic light-emitting diodes (OLEDs) are optical devices that use organic solid-state semiconductors as light-emitting materials. Due to their advantages such as simple fabrication process, low cost, low power consumption, high brightness, and wide operating temperature range, they have broad application prospects. Summary of the Invention

[0005] This disclosure aims to at least solve one of the technical problems existing in the prior art, and provides a display panel and display device.

[0006] In a first aspect, embodiments of this disclosure provide a display panel having a first display area, a second display area, and a peripheral area; the first display area surrounds the second display area, and the peripheral area surrounds the first display area; the first display area includes: a first sub-pixel area and a virtual sub-pixel area; each column of the virtual sub-pixel area is located between a first M columns of first sub-pixel areas and a second M columns of first sub-pixel areas, and the first M columns of first sub-pixel areas and the second M columns of first sub-pixel areas are adjacent to each other; the second display area includes: a second sub-pixel area; wherein, the display panel includes: a pixel driving circuit and a light-emitting device; the first sub-pixel area is provided with a portion of the pixel driving circuit and a portion of the light-emitting device; the virtual sub-pixel area is provided with only the other portion of the pixel driving circuit; the second sub-pixel area is provided with only the other portion of the light-emitting device; the display panel further includes: a data signal line and a power signal line extending along a column direction; the data signal line is located in each column of the first sub-pixel area; the power signal line is located in each column of the first sub-pixel area and each column of the virtual sub-pixel area;

[0007] The display panel further includes: a main power signal line located in the peripheral area and disposed on at least one side of the display area, and a power signal adapter cable extending along the row direction;

[0008] In the first sub-pixel region, some of the power signal lines are interconnected via the same power signal adapter cable; some of the power signal lines are connected to the main power signal line via the same power signal adapter cable; some of the power signal lines are connected to the main power signal line via different power signal adapter cables; and at least one end of some of the power signal lines is connected to the main power signal line.

[0009] In the virtual sub-pixel area, at least one end of the power signal line is connected to the main power signal line.

[0010] In some embodiments, the number of power signal lines in the same column of virtual sub-pixel areas is two; and

[0011] Two power signal lines in the same column of virtual sub-pixel area are connected to each other through the same power signal adapter cable, or connected to the main power signal line through the same power signal adapter cable.

[0012] In some embodiments, the number of power signal lines in the same column of virtual sub-pixel areas is two; and

[0013] The two power signal lines in the same column of virtual sub-pixel area are connected to each other through the same power signal adapter cable, or are connected to the main power signal line through two power signal adapter cables respectively.

[0014] In some embodiments, the display panel further includes: a first auxiliary initialization signal line and a second auxiliary initialization signal line extending along the column direction; the first auxiliary initialization signal line and the second auxiliary initialization signal line are respectively located in the virtual sub-pixel areas of different columns; the display panel further includes: a first main initialization signal line and a second main initialization signal line located in the peripheral area and extending along the column direction, and a first initialization signal adapter line and a second initialization signal adapter line extending along the row direction;

[0015] Some of the first auxiliary initialization signal lines are connected to each other via the same first initialization signal adapter cable, and some of the first auxiliary initialization signal lines are connected to the first main initialization signal line via the first initialization signal adapter cable; and

[0016] Some of the second auxiliary initialization signal lines are connected to each other through the same second initialization signal adapter cable, and some of the second auxiliary initialization signal lines are connected to the second main initialization signal line through the second initialization signal adapter cable.

[0017] In some embodiments, a first initialization signal adapter cable and a second initialization signal adapter cable are provided between adjacent power signal adapter cables.

[0018] In some embodiments, a first initialization signal adapter or a second initialization signal adapter is provided between adjacent power signal adapters.

[0019] In some embodiments, the display panel includes: a first source-drain conductive layer, a second source-drain conductive layer, and a third source-drain conductive layer stacked together;

[0020] The first source-drain conductive layer includes: the power signal adapter cable, the first initialization signal adapter cable, and the second initialization signal adapter cable;

[0021] The second source / drain conductive layer includes: the data signal line; and

[0022] The third source / drain conductive layer includes: the power signal line, the first auxiliary initialization signal line, and the second auxiliary initialization signal line.

[0023] In some embodiments, the display panel further includes: fan-out signal lines extending along the column direction and data signal adapter lines extending along the row direction; and

[0024] The fan-out signal line is located in the first sub-pixel area away from the peripheral area, and is connected to the data signal line close to the peripheral area through the data signal adapter.

[0025] In some embodiments, in the first sub-pixel area of ​​the same column, the fan-out signal line and the power signal line are located on the same straight line and are disconnected from each other.

[0026] In some embodiments, the first sub-pixel region in each M columns and the virtual sub-pixel region in each column are alternately arranged.

[0027] In some embodiments, M equals 4.

[0028] In some embodiments, the pixel driving circuit includes: a data writing transistor, a threshold compensation transistor, a first light-emitting control transistor, a second light-emitting control transistor, a first reset transistor, a second reset transistor, a driving transistor, and a storage capacitor.

[0029] In some embodiments, the drain of the second light-emitting control transistor is connected to the anode of the light-emitting device, and the cathode of the light-emitting device is connected to the second power signal line.

[0030] In some embodiments, the power signal line, the main power signal line, and the power signal adapter cable constitute the second power signal line.

[0031] In some embodiments, the second power signal line provides a low-level signal.

[0032] In some embodiments, the length direction of the power signal adapter cable intersects both the length direction of the power signal line and the length direction of the main power signal line.

[0033] In some embodiments, the pixel driving circuit includes: a data writing transistor, a threshold compensation transistor, a first light-emitting control transistor, a second light-emitting control transistor, a first reset transistor, a second reset transistor, a driving transistor, and a storage capacitor; the source of the first reset transistor is connected to a first initialization signal line, and the source of the second reset transistor is connected to a second initialization signal line.

[0034] In some embodiments, the first auxiliary initialization signal line, the first main initialization signal line, and the first initialization signal adapter line are connected together to form the first initialization signal line; and the second auxiliary initialization signal line, the second main initialization signal line, and the second initialization signal adapter line are connected together to form the second initialization signal line.

[0035] In a second aspect, embodiments of this disclosure provide a display device, wherein the display device includes a display panel provided according to any embodiment of the first aspect described above.

[0036] In some embodiments, the display device further includes: a sensor; the sensor is disposed corresponding to the second sub-pixel area and is located on the backlight side of the light-emitting device in the second sub-pixel area. Attached Figure Description

[0037] Figure 1 is a schematic diagram of the structure of the display panel provided in an embodiment of this disclosure.

[0038] Figure 2 is a schematic diagram of a defective display panel provided in an embodiment of this disclosure.

[0039] Figure 3 is a schematic diagram of the pixel driving circuit in the display panel provided in the embodiment of this disclosure.

[0040] Figure 4 is a partial enlarged schematic diagram of the structure of the first type of display panel provided in the embodiments of this disclosure.

[0041] Figure 5 is a partial enlarged schematic diagram of the structure of the second type of display panel provided in the embodiments of this disclosure.

[0042] Figure 6 is a partial enlarged schematic diagram of the structure of the third type of display panel provided in the embodiments of this disclosure.

[0043] Figure 7 is a partial enlarged schematic diagram of the structure of the fourth type of display panel provided in the embodiments of this disclosure.

[0044] Figure 8 is a partial enlarged schematic diagram of the structure of the fifth type of display panel provided in the embodiments of this disclosure.

[0045] Figure 9 is a partial enlarged schematic diagram of the structure of the sixth type of display panel provided in the embodiments of this disclosure.

[0046] Figure 10 is a partial enlarged schematic diagram of the structure of the seventh type of display panel provided in the embodiments of this disclosure.

[0047] Figures 11a to 11e are schematic diagrams of the structure of each conductive layer in the display panel provided in the embodiments of this disclosure. Detailed Implementation

[0048] To enable those skilled in the art to better understand the technical solutions of this disclosure, the disclosure will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0049] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding the presence of other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0050] With the continuous development of display technology, in order to achieve a higher screen-to-body ratio (i.e., the ratio of the screen display area to the total front area of ​​the display panel), the current main technology used is under-display camera (e.g., Full Display with Camera, FDC) to eliminate the camera hole of the front-facing camera in the display panel and place the front-facing camera inside the display panel. Generally, FDC technology is implemented by changing the pixel arrangement. That is, the pixel driving circuit of the pixel unit corresponding to the camera area is arranged in an array with the pixel driving circuit of other normal pixel units, while the light-emitting devices of the pixel units corresponding to the camera area are placed directly above the camera (i.e., the camera is located on the non-light-emitting side of these light-emitting devices).

[0051] Figure 1 is a schematic diagram of the structure of a display panel provided in an embodiment of this disclosure. As shown in Figure 1, the display panel has a first display area AA1, a second display area AA2, and a peripheral area BB. The first display area AA1 surrounds the second display area AA2, and the peripheral area BB surrounds the first display area AA1. The first display area AA1 includes a first sub-pixel area P1 and a virtual sub-pixel area P; the second display area AA2 includes a second sub-pixel area P2. The first sub-pixel area P1 and the virtual sub-pixel area P are arranged in an array, and each column of virtual sub-pixel area P is located between the first M columns of first sub-pixel areas P1 and the second M columns of first sub-pixel areas P1, and the first M columns of first sub-pixel areas P1 and the second M columns of first sub-pixel areas P1 are adjacent to each other. For example, Figure 1 shows that M equals 4, but the embodiments of this disclosure are not limited to this.

[0052] The first sub-pixel area P1 is a normal sub-pixel area, containing part of a pixel driving circuit and part of a light-emitting device. The pixel driving circuit drives the light-emitting device to emit light. The virtual sub-pixel area P is an inserted sub-pixel area, containing only the other part of the pixel driving circuit and no light-emitting device; it does not emit light. The second sub-pixel area P2 corresponds to the sub-pixel area of ​​sensors such as cameras (for example, the second sub-pixel area P2 is located directly above the camera or other sensor). It contains only the other part of the light-emitting device and no pixel driving circuit. It emits light under the drive of the pixel driving circuit in the virtual sub-pixel area P. Generally, it is transparent to allow light to pass through, avoiding interference with the operation of the camera or other sensors below.

[0053] In Figure 1 above, the first sub-pixel area P1 and the virtual sub-pixel area P in the display panel are set in a 4:1 ratio, that is, every four columns of the first sub-pixel area P1 and every one column of the virtual sub-pixel area P are alternately set. It is understood that the first sub-pixel area P1 and the virtual sub-pixel area P in the display panel can also be set in a 2:1, 8:1, or 16:1 ratio. In other words, M can be equal to 2, 4, 8, 16, etc. Furthermore, the inventors of this disclosure have found that if an 8:1 or 16:1 scheme is used, the distance between the light-emitting device of the second sub-pixel area P2 and the pixel driving circuit of the first sub-pixel area P1 is relatively large, and the connections between these light-emitting devices and these pixel driving circuits (e.g., indium tin oxide (ITO) traces) are long, resulting in larger capacitance. This will make it difficult to light up the second display area AA2 and degrade the image quality. On the other hand, in 2:1 or 4:1 design schemes, as the number of sub-pixels whose pixel arrangement needs to be changed increases, the pixel layout space becomes smaller and smaller. Therefore, in conventional product designs using 2:1 or 4:1 designs, the initialization signal line Vinit and other traces cannot be designed in a mesh pattern, resulting in a horizontal mura problem at the second display area AA2 position under low brightness, as shown in Figure 2. Therefore, in one embodiment of this disclosure, a 4:1 setting (i.e., M equals 4) will be used as an example for explanation. It should be understood that the 4:1 (i.e., M equals 4) embodiment of this disclosure at least avoids the problems caused by the large distance between the light-emitting device of the second sub-pixel area P2 and the pixel driving circuit of the first sub-pixel area P1, as described above, and the horizontal mura problem caused by the inability to use a mesh pattern for the initialization signal line Vinit and other traces.

[0054] Specifically, in conventional product designs using a 2:1 or 4:1 aspect ratio, as the number of virtual sub-pixel areas P that require altering the pixel arrangement increases, the limited space in the display panel severely restricts the width of signal traces such as power and initialization lines. This results in reduced trace width, increased resistance, and a higher risk of heat generation and signal trace burn-in under high brightness conditions. Simultaneously, under low brightness conditions, horizontal stripes (as shown in Figure 2) can easily appear around the second sub-pixel area P2, affecting the image quality.

[0055] In order to at least solve one of the above-mentioned technical problems, other embodiments of this disclosure provide a display panel and a display device. The display panel and display device provided in the embodiments of this disclosure will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0056] In a first aspect, embodiments of this disclosure provide a display panel, the structure of which can be referred to as FIG1. ​​The display panel has a first display area AA1, a second display area AA2, and a peripheral area BB. The first display area AA1 surrounds the second display area AA2, and the peripheral area BB surrounds the first display area AA1. The first display area AA1 includes: a first sub-pixel area P1 and a virtual sub-pixel area P. Each column of virtual sub-pixel areas P is located between the first M columns of first sub-pixel areas P1 and the second M columns of first sub-pixel areas P1, and the first M columns of first sub-pixel areas P1 and the second M columns of first sub-pixel areas P1 are adjacent to each other. The second display area AA2 includes: a second sub-pixel area P2. The display panel includes: a pixel driving circuit (as shown in FIG3) and a light-emitting device (OLED as shown in FIG3). The specific circuit connection structure of the two will be described in detail in the following description.

[0057] The first sub-pixel area P1 is the normal sub-pixel area, which contains a pixel driving circuit and a light-emitting device. The pixel driving circuit drives the light-emitting device to emit light. The virtual sub-pixel area P is the inserted sub-pixel area, which only contains a pixel driving circuit and does not contain a light-emitting device; therefore, it does not emit light. The second sub-pixel area P2 corresponds to the sub-pixel area of ​​sensors such as cameras. It only contains a light-emitting device and does not contain a pixel driving circuit. It emits light under the drive of the pixel driving circuit in the virtual sub-pixel area P. Generally, it is transparent to allow light to pass through, thus avoiding interference with the operation of the cameras or other sensors below.

[0058] A pixel driving circuit may include multiple transistors (represented by T) and at least one capacitor (represented by C). For example, a pixel driving circuit may be a 3T1C (i.e., including 3 transistors and 1 capacitor) structure, a 7T1C (i.e., including 7 transistors and 1 capacitor) structure, a 5T1C (i.e., including 5 transistors and 1 capacitor) structure, an 8T1C (i.e., including 8 transistors and 1 capacitor) structure, or an 8T2C (i.e., including 8 transistors and 2 capacitors) structure, etc.

[0059] In some embodiments, the light-emitting device can be a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), or a micro-LED (including any of mini-LED or micro-LED). For example, the light-emitting device can be an OLED, which emits red, green, blue, or white light under the drive of its corresponding pixel driving circuit. The color of the light emitted by the light-emitting device can be determined as needed.

[0060] In some embodiments, the light-emitting device may include an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting device may be connected to a corresponding pixel driving circuit, as shown in FIG3. However, the embodiments of this disclosure are not limited thereto.

[0061] Figure 3 is a schematic diagram of the pixel driving circuit in the display panel provided in an embodiment of this disclosure. The pixel driving circuit in this embodiment is illustrated using a 7T1C structure as an example. However, the embodiments of this disclosure are not limited thereto.

[0062] In some embodiments, as shown in FIG3, the pixel driving circuit may include six switching transistors (T1, T2, T4 to T7), a driving transistor T3, and a storage capacitor Cst. The six switching transistors are a data writing transistor T4, a threshold compensation transistor T2, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a first reset transistor T1, and a second reset transistor T7. The light-emitting device OLED may include an anode, a cathode, and an organic light-emitting layer disposed between the anode and the cathode.

[0063] In some embodiments, the driving transistor and the six switching transistors can be P-type transistors or N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the processing difficulty of the display substrate, and improve product yield. In some possible implementations, the driving transistor and the six switching transistors may include both P-type and N-type transistors.

[0064] In some embodiments, the driving transistor and the six switching transistors can be low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs), oxide thin-film transistors (OPTs), or a combination of both. The active layer of the LTPS TFT is made of low-temperature polycrystalline silicon (LTPS), while the active layer of the OPT TFT is made of oxide semiconductor. LTPS TFTs offer advantages such as high mobility and fast charging, while OPT TFTs offer advantages such as low leakage current. Integrating LTPS TFTs and OPTs onto a single display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate leverages the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0065] In some embodiments, as shown in FIG3, the first node N1 is the connection point between the first capacitor plate of the storage capacitor Cst, the drain of the first reset transistor T1, the gate of the driving transistor T3, and the source of the threshold compensation transistor T2; the second node N2 is the connection point between the drain of the first light-emitting control transistor T5, the drain of the data writing transistor T4, and the source of the driving transistor T3; the third node N3 is the connection point between the drain of the driving transistor T3, the drain of the threshold compensation transistor T2, and the source of the second light-emitting control transistor T6; and the fourth node N4 is the connection point between the drain of the second light-emitting control transistor T6, the drain of the second reset transistor T7, and the anode of the light-emitting device OLED.

[0066] As shown in Figure 3, the gate of data writing transistor T4 is connected to the scan signal line Gate, the source of data writing transistor T4 is connected to the data signal line Data, and the drain of data writing transistor T4 is connected to the second node N2. The gate of threshold compensation transistor T2 is connected to the scan signal line Gate, the source of threshold compensation transistor T2 is connected to the first node N1, and the drain of threshold compensation transistor T2 is connected to the third node N3. The gate of the first light-emitting control transistor T5 is connected to the light-emitting control line EM, the source of the first light-emitting control transistor T5 is connected to the first power supply signal line VDD, and the drain of the first light-emitting control transistor T5 is connected to the second node N2. The gate of the second light-emitting control transistor T6 is connected to the light-emitting control line EM, the source of the second light-emitting control transistor T6 is connected to the third node N3, and the drain of the second light-emitting control transistor T6 is connected to the fourth node N4. The gate of the first reset transistor T1 is connected to the first reset control line Vref1, the source of the first reset transistor T1 is connected to the first initialization signal line Vinit1, and the drain of the first reset transistor T1 is connected to the first node N1. The gate of the second reset transistor T7 is connected to the second reset control line Vref2, the source of the second reset transistor T7 is connected to the second initialization signal line Vinit2, and the drain of the second reset transistor T7 is connected to the fourth node N4. The first capacitor plate of the storage capacitor Cst is connected to the first node N1, and the second capacitor plate of the storage capacitor Cst is connected to the first power supply signal line VDD. The anode of the light-emitting device OLED is connected to the fourth node N4, and the cathode is connected to the second power supply signal line VSS.

[0067] The operation of the pixel driving circuit shown in Figure 3 will be explained below. The explanation will take the example where all the transistors in the pixel driving circuit shown in Figure 3 are P-type transistors.

[0068] During a single frame display period, the operation of the pixel driving circuit can include: a first stage S1, a second stage S2, and a third stage S3.

[0069] The first stage, S1, is called the reset stage. The first reset control signal provided by the first reset control line Vref1 is a low-level signal, turning on the first reset transistor T1. The first initialization signal provided by the first initialization signal line Vinit1 is provided to the first node N1 to initialize N1 and clear the original data voltage in the storage capacitor Cst. The second reset control signal provided by the second reset control line Vref2 is a low-level signal, turning on the second reset transistor T7. The second initialization signal provided by the second initialization signal line Vinit2 is provided to the anode of the OLED to initialize the anode and clear its internal pre-stored voltage. The scan signal provided by the scan signal line Gate is a high-level signal, and the light emission control signal provided by the light emission control line EM is a high-level signal, turning off the data writing transistor T4, the threshold compensation transistor T2, the first light emission control transistor T5, the second light emission control transistor T6, and the second reset transistor T7. During this stage, the OLED does not emit light.

[0070] The second stage, S2, is called the data writing stage or threshold compensation stage. The scan signal provided by the scan signal line Gate is a low-level signal, while the first reset control signal provided by the first reset control line Vref1 and the light emission control signal provided by the light emission control line EM are both high-level signals. The data signal line Data outputs a data signal. During this stage, because the first capacitor plate of the storage capacitor Cst is at a low level, the driving transistor T3 is turned on. The low-level scan signal turns on the threshold compensation transistor T2 and the data writing transistor T4. The turn-on of the threshold compensation transistor T2 and the data writing transistor T4 allows the data signal output by the data signal line Data to be supplied to the first node N1 via the second node N2, the turned-on driving transistor T3, the third node N3, and the turned-on threshold compensation transistor T2. The difference between the data signal output by the data signal line Data and the threshold voltage of the driving transistor T3 is charged into the storage capacitor Cst. The voltage of the first capacitor plate of the storage capacitor Cst (i.e., the first node N1) is Vdata - |Vth|, where Vdata is the data voltage output by the data signal line Data, and Vth is the threshold voltage of the driving transistor T3. The first reset control signal provided by the first reset control line Vref1 is a high-level signal, causing the first reset transistor T1 to turn off. The light emission control signal EM provided by the light emission control line EM is a high-level signal, causing the first light emission control transistor T5 and the second light emission control transistor T6 to turn off.

[0071] The third stage, S3, is called the light-emitting stage. The light-emitting control signal provided by the light-emitting control line EM is a low-level signal, while the scan signal provided by the scan signal line Gate and the first reset control signal provided by the first reset control line Vref1 are high-level signals. The low-level light-emitting control signal provided by the light-emitting control line EM turns on the first light-emitting control transistor T5 and the second light-emitting control transistor T6. The first power signal output from the first power signal line VDD provides driving current to the anode of the OLED device through the turned-on first light-emitting control transistor T5, driving transistor T3, and second light-emitting control transistor T6, driving the OLED device to emit light.

[0072] Figure 4 is a partial enlarged schematic diagram of the structure of the first type of display panel provided in this embodiment. Its overall structure can be seen in Figure 1, which is an enlarged schematic diagram of the lower left corner of the display panel shown in Figure 1. In the following description, the enlarged schematic diagram of the lower left corner of the display panel under different conditions will be used as an example. As shown in Figure 4, the display panel further includes: a data signal line Data and a power signal line ELVSS1 extending along the column direction; the data signal line Data is located in each column's first sub-pixel area P1 (i.e., each column's first sub-pixel area P1 has a data signal line Data); the power signal line ELVSS1 is located in each column's first sub-pixel area P1 and each column's virtual sub-pixel area P (i.e., each column's first sub-pixel area P1 has a power signal line ELVSS1, and each column's virtual sub-pixel area P has a power signal line ELVSS1); the display panel further includes: a main power signal line ELVSS2 located in the peripheral area BB and disposed on at least one side of the first display area AA1, and a power signal line ELVSS2 extending along the row direction... The extended power signal adapter cable ELVSS3; in the first sub-pixel area P1, some power signal lines ELVSS1 are interconnected through the same power signal adapter cable ELVSS3, some power signal lines ELVSS1 are connected to the main power signal line ELVSS2 through the same power signal adapter cable ELVSS3, some power signal lines ELVSS1 are connected to the main power signal line ELVSS2 through different power signal adapter cables ELVSS3, and at least one end of some power signal lines ELVSS1 is connected to the main power signal line ELVSS2; in the virtual sub-pixel area P, at least one end of the power signal line ELVSS1 is connected to the main power signal line ELVSS2. It should be understood that, as understood by those skilled in the art, the solid black dot at the intersection of two signal lines in Figure 4 indicates that the two signal lines are electrically connected at the solid black dot.

[0073] The data signal line Data shown in Figure 4 is the same as the data signal line Data in the circuit structure shown in Figure 3, which can provide a data signal. The power signal line ELVSS1, the main power signal line ELVSS2, and the power signal adapter line ELVSS3 shown in Figure 4 can be connected together to form the second power signal line VSS in the circuit structure shown in Figure 3, which can provide a second power signal, i.e., a low-level signal.

[0074] The power signal line ELVSS1 is located in the first sub-pixel area P1 of each column and in the virtual sub-pixel area P of each column. It extends along the column direction and can provide a second power signal to the pixel driving circuit in the first sub-pixel area P1 so that the light-emitting device therein can emit light and realize the display function.

[0075] The main power signal line ELVSS2 is located in the peripheral area BB and is disposed on at least one side of the first display area AA1. The main power signal line ELVSS2 may be disposed only on one side of the first display area AA1; for example, it may extend along the column direction. Alternatively, it may be disposed around the perimeter of the first display area AA1; for example, it may form a loop around the entire first display area AA1. In this embodiment, to increase its trace width, the main power signal line ELVSS2 will be described as forming a loop.

[0076] The power signal adapter cable ELVSS3 can extend along the row direction, meaning that the extension direction (i.e., the length direction) of the power signal adapter cable ELVSS3 intersects with the extension directions of both the power signal line ELVSS1 and the main power signal line ELVSS2, allowing different power signal lines ELVSS1 and ELVSS2 to be connected together. The black dots in the diagram represent the connection points between different signal traces.

[0077] In the display panel provided in this embodiment, the power signal line ELVSS1, the main power signal line ELVSS2, and the power signal adapter line ELVSS3 can be connected together to form a mesh structure, increasing the trace width of the second power signal line VSS. This reduces the resistance of the second power signal line VSS, preventing excessive heat generation in high-brightness conditions and thus preventing the risk of burning the second power signal line VSS. Consequently, the display effect and lifespan of the display panel can be improved. Simultaneously, it avoids the appearance of horizontal stripe defects around the second sub-pixel area P2 as shown in Figure 2 in low-brightness conditions, further improving the display effect of the display panel.

[0078] Referring again to Figure 4, the display panel also includes: a fanout signal line Fanout1 extending along the column direction and a data signal adapter line Fanout2 extending along the row direction; the fanout signal line Fanout1 is located in the first sub-pixel area P1 far from the peripheral area BB, and is connected to the data signal line Data near the peripheral area BB through the data signal adapter line Fanout2.

[0079] The data signal lines Data in the display panel can be divided into parts near the perimeter area BB and parts far from the perimeter area BB. For example, the data signal lines Data in the middle area of ​​the display panel are far from the perimeter area BB, while the data signal lines Data in the two side areas are near the perimeter area BB.

[0080] Data signal lines (Data) far from the peripheral area BB are normally configured, extending along the column direction. Data signal lines (Data) close to the peripheral area BB, while extending along the column direction, can also be led outwards away from the peripheral area BB via data signal adapter line Fanout2, connecting to the fanout signal line Fanout1 located in the first sub-pixel area P1 far from the peripheral area BB. This eliminates the need for a fanout signal line Fanout1 to be set up in the directly opposite peripheral area BB for the data signal lines (Data). This reduces the routing area of ​​the fanout signal line Fanout1 in the peripheral area BB (i.e., the area of ​​the fanout region), thereby reducing the bezel of the display panel, improving the screen-to-body ratio, and enhancing the display effect.

[0081] Referring to Figure 4, in the first sub-pixel area P1 of the same column, the fanout signal line Fanout1 and the power signal line ELVSS1 are located on the same straight line and are disconnected from each other.

[0082] In practical applications, the length of the power signal line ELVSS1 in the column direction of the first sub-pixel area P1 where the fanout signal line Fanout1 needs to be set can be reduced to leave routing space for the fanout signal line Fanout1, avoiding excessive routing density and interference between adjacent signal lines. Simultaneously, the fanout signal line Fanout1 and the power signal line ELVSS1 are located on the same straight line and disconnected from each other to prevent short circuits. During fabrication, the fanout signal line Fanout1 and the power signal line ELVSS1 can be made using the same process and materials; simply cutting the same signal line is sufficient to form both, thus reducing process steps, lowering process difficulty, and saving fabrication costs.

[0083] Figure 5 is a partial enlarged schematic diagram of the structure of the second type of display panel provided in the embodiment of this disclosure. As shown in Figure 5, there are two power signal lines ELVSS1 in the same column of virtual sub-pixel area P. The two power signal lines ELVSS1 in the same column of virtual sub-pixel area P are connected to each other through the same power signal adapter ELVSS3, or connected to the main power signal line ELVSS2 through the same power signal adapter ELVSS3.

[0084] Two power signal lines ELVSS1 in the same column of virtual sub-pixel area P are interconnected through the same power signal adapter cable ELVSS3, or connected to the main power signal line ELVSS2 through the same power signal adapter cable ELVSS3. In this way, power signal lines ELVSS1, main power signal lines ELVSS2, and power signal adapter cable ELVSS3 can be connected together to form a grid structure, increasing the trace width of the second power signal line VSS. This reduces the resistance of the second power signal line VSS, avoiding excessive heat generation under high brightness conditions, thus preventing the risk of burning the second power signal line VSS, and improving the display effect and lifespan of the display panel. Simultaneously, it avoids the appearance of horizontal stripes (as shown in Figure 2) around the second sub-pixel area P2 under low brightness conditions, further improving the display effect of the display panel.

[0085] Figure 6 is a partial enlarged schematic diagram of the structure of the third type of display panel provided in the embodiment of this disclosure. As shown in Figure 6, there are two power signal lines ELVSS1 in the same column of virtual sub-pixel area P. The two power signal lines ELVSS1 in the same column of virtual sub-pixel area P are connected to each other through the same power signal adapter ELVSS3, or are connected to the main power signal line ELVSS2 through two power signal adapters ELVSS3 respectively.

[0086] The difference between the display panel shown in Figure 6 and the display panel shown in Figure 5 is that in the display panel shown in Figure 5, two adjacent power signal lines ELVSS1 can be connected to the main power signal line ELVSS2 through the same power signal adapter cable ELVSS3. However, in the display panel shown in Figure 6, two adjacent power signal lines ELVSS1 are connected to the main power signal line ELVSS2 through different power signal adapter cables ELVSS3. This reduces the number of connection points on the same power signal adapter cable ELVSS3 and avoids the distance between adjacent connection points on the same power signal adapter cable ELVSS3 being too close, which could cause the corresponding connection vias to be too large and short-circuit the second power signal line VSS with other signal traces, affecting the display effect.

[0087] Figure 7 is a partial enlarged schematic diagram of the structure of the fourth type of display panel provided in the embodiments of the present disclosure, and Figure 8 is a partial enlarged schematic diagram of the structure of the fifth type of display panel provided in the embodiments of the present disclosure. As shown in Figures 7 and 8, the display panel further includes: a first auxiliary initialization signal line Init11 and a second auxiliary initialization signal line Init21 extending along the column direction; the first auxiliary initialization signal line Init11 and the second auxiliary initialization signal line Init21 are respectively located in virtual sub-pixel areas P of different columns; the display panel further includes: a first main initialization signal line Init12 and a second main initialization signal line Init22 located in the peripheral area BB and extending along the column direction, and a first main initialization signal line Init12 extending along the row direction. An initialization signal adapter cable Init13 and a second initialization signal adapter cable Init23 are provided; some of the first auxiliary initialization signal lines Init11 are connected to each other through the same first initialization signal adapter cable Init13, and some of the first auxiliary initialization signal lines Init11 are connected to the first main initialization signal line Init12 through the first initialization signal adapter cable Init13; some of the second auxiliary initialization signal lines Init21 are connected to each other through the same second initialization signal adapter cable Init23, and some of the second auxiliary initialization signal lines Init21 are connected to the second main initialization signal line Init22 through the second initialization signal adapter cable Init23.

[0088] The first auxiliary initialization signal line Init11, the first main initialization signal line Init12, and the first initialization signal adapter line Init13 shown in Figures 7 and 8 can be connected together to form the first initialization signal line Vinit1 in the circuit structure shown in Figure 3, which can provide the first initialization signal. The second auxiliary initialization signal line Init21, the second main initialization signal line Init22, and the second initialization signal adapter line Init23 can be connected together to form the second initialization signal line Vinit2 in the circuit structure shown in Figure 3, which can provide the second initialization signal.

[0089] The first auxiliary initialization signal line Init11, the first main initialization signal line Init12, and the first initialization signal adapter line Init13 can be connected together to form a mesh structure, increasing the trace width of the first initialization signal line Vinit1. This reduces the resistance of Vinit1, preventing excessive heat generation under high brightness conditions and thus avoiding the risk of burning Vinit1. Consequently, it improves the display effect and lifespan of the display panel. Simultaneously, it avoids the appearance of horizontal stripes around the second sub-pixel area P2 under low brightness conditions, as shown in Figure 2, further enhancing the display panel's performance.

[0090] Similarly, the second auxiliary initialization signal line Init21, the second main initialization signal line Init22, and the second initialization signal adapter line Init23 can be connected together to form a mesh structure, increasing the trace width of the second initialization signal line Vinit2. This reduces the resistance of Vinit2, preventing excessive heat generation in high-brightness conditions and thus preventing the risk of burning Vinit2, thereby improving the display effect and lifespan of the display panel. Simultaneously, it avoids the appearance of horizontal stripes around the second sub-pixel area P2 in low-brightness conditions, as shown in Figure 2, further improving the display effect of the display panel.

[0091] The difference between the display panel shown in Figure 8 and the display panel shown in Figure 7 is that the display panel in Figure 7 does not have a separate fanout signal line Fanout1, while the display panel in Figure 8 has a fanout signal line Fanout1 in the middle area of ​​the display panel. The data signal line Data near the peripheral area BB extends along the column direction and can also be led out in the direction away from the peripheral area BB through the data signal adapter line Fanout2, and connected to the fanout signal line Fanout1 set in the first sub-pixel area P1 away from the peripheral area BB. This means that the data signal line Data near the peripheral area BB does not need to be led out by setting a fanout signal line Fanout1 in the peripheral area BB directly opposite it. This can reduce the routing area of ​​the fanout signal line Fanout1 in the peripheral area BB (i.e., the area of ​​the fanout area), thereby reducing the bezel of the display panel, which is beneficial to improving the screen ratio of the display panel and improving the display effect.

[0092] Referring to Figures 7 and 8, a first initialization signal adapter cable Init13 or a second initialization signal adapter cable Init23 is provided between adjacent power signal adapter cables ELVSS3.

[0093] Along the column direction, the signal traces are arranged as follows: power signal adapter ELVSS3, first initialization signal adapter Init13, second initialization signal adapter Init23, and power signal adapter ELVSS3. This allows the second power signal line VSS, the first initialization signal line Vinit1, and the second initialization signal line Vinit2 to form a mesh structure, increasing the trace width of these lines. This reduces their resistance, preventing excessive heat generation under high brightness conditions and thus mitigating the risk of burn-in to the second power signal line VSS, first initialization signal line Vinit1, and second initialization signal line Vinit2. This, in turn, improves the display panel's display performance and lifespan. Simultaneously, it avoids the appearance of horizontal stripes (as shown in Figure 2) around the second sub-pixel area P2 under low brightness conditions, further enhancing the display panel's performance.

[0094] Figure 9 is a partial enlarged schematic diagram of the structure of the sixth type of display panel provided in the present disclosure embodiment, and Figure 10 is a partial enlarged schematic diagram of the structure of the seventh type of display panel provided in the present disclosure embodiment. As shown in Figures 9 and 10, a first initialization signal transfer line Init13 or a second initialization signal transfer line Init23 is provided between adjacent power signal transfer lines ELVSS3.

[0095] Along the column direction, the signal traces are arranged as follows: power signal adapter ELVSS3, first initialization signal adapter Init13, power signal adapter ELVSS3, second initialization signal adapter Init23, power signal adapter ELVSS3. This allows the second power signal line VSS, the first initialization signal line Vinit1, and the second initialization signal line Vinit2 to form a mesh structure, increasing the trace width of these lines. This reduces their resistance, preventing excessive heat generation under high brightness conditions and thus mitigating the risk of burn-in to the second power signal line VSS, first initialization signal line Vinit1, and second initialization signal line Vinit2. This, in turn, improves the display panel's display performance and lifespan. Simultaneously, it avoids the appearance of horizontal stripes around the second sub-pixel area P2 under low brightness conditions, as shown in Figure 2, further enhancing the display panel's performance.

[0096] Furthermore, compared to the display panels shown in Figures 7 and 8 above, the signal routing method used in the display panels shown in Figures 9 and 10 can increase the number of power signal adapter cables ELVSS3 and the number of connection points in the second power signal line VSS, thereby further reducing the resistance of the second power signal line VSS.

[0097] It should be noted that the display panel shown in Figure 10 differs from the display panel shown in Figure 9 in that the display panel in Figure 9 does not have a separate fanout signal line Fanout1, while the display panel in Figure 10 has a fanout signal line Fanout1 in the middle area of ​​the display panel. The data signal line Data near the peripheral area BB extends along the column direction and can also be led out in the direction away from the peripheral area BB through the data signal adapter line Fanout2, and connected to the fanout signal line Fanout1 set in the first sub-pixel area P1 away from the peripheral area BB. This means that the data signal line Data near the peripheral area BB does not need to be led out by the fanout signal line Fanout1 in the peripheral area BB directly opposite it. This reduces the routing area of ​​the fanout signal line Fanout1 in the peripheral area BB (i.e., the area of ​​the fanout area), thereby reducing the bezel of the display panel, which is beneficial to improving the screen ratio of the display panel and improving the display effect.

[0098] Figures 11a to 11e are schematic diagrams of the structures of various conductive layers in the display panel provided in the embodiments of this disclosure. The conductive layers shown in Figures 11a to 11e are a first gate conductive layer (Gate1), a second gate conductive layer (Gate2), a first source-drain conductive layer (SD1), a second source-drain conductive layer (SD2), and a third source-drain conductive layer (SD3), respectively. The first gate conductive layer (Gate1) mainly includes the gates of each thin-film transistor in the pixel driving circuit, the first electrode plate of the storage capacitor, scan signal lines, and other structures. The second gate conductive layer (Gate2) mainly includes the second electrode plate of the storage capacitor, and other structures. The first source-drain conductive layer (SD1) mainly includes the source and drain electrodes of each thin-film transistor in the pixel driving circuit, as well as the aforementioned power signal transfer line (ELVSS3), the first initialization signal transfer line (Init13), and the second initialization signal transfer line (Init23), and other structures. The second source-drain conductive layer (SD2) mainly includes data signal lines, and other structures. The third conductive layer (SD3) mainly includes the power signal line (ELVSS1), the first auxiliary initialization signal line (Init11), and the second auxiliary initialization signal line (Init21), and other structures.

[0099] Secondly, embodiments of this disclosure provide a display device, which includes a display panel as provided in any of the above embodiments. The display device further includes: a sensor (not shown in the figures); the sensor is disposed corresponding to a second sub-pixel area P2 (for example, the sensor may be disposed directly below the second sub-pixel area P2), and is located on the backlight side of the light-emitting device of the second sub-pixel area P2. This display device can be, for example, any product with a display function such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or in-vehicle device. Other essential components of this display device are understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting this disclosure.

[0100] It is understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of this disclosure, and this disclosure is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and substance of this disclosure, and these modifications and improvements are also considered to be within the scope of protection of this disclosure.

Claims

1. A display panel having a first display area, a second display area, and a peripheral area; the first display area surrounding the second display area, and the peripheral area surrounding the first display area; the first display area comprising: The first sub-pixel area and the virtual sub-pixel area; each column of the virtual sub-pixel area is located between the first M column first sub-pixel area and the second M column first sub-pixel area, and the first M column first sub-pixel area and the second M column first sub-pixel area are adjacent to each other; The second display area includes a second sub-pixel area; wherein the display panel includes a pixel driving circuit and a light-emitting device; the first sub-pixel area is provided with a portion of the pixel driving circuit and a portion of the light-emitting device; the virtual sub-pixel area is provided with only the other portion of the pixel driving circuit; the second sub-pixel area is provided with only the other portion of the light-emitting device; the display panel further includes a data signal line and a power signal line extending along the column direction; the data signal line is located in each column of the first sub-pixel area; the power signal line is located in each column of the first sub-pixel area and each column of the virtual sub-pixel area; The display panel further includes: a main power signal line located in the peripheral area and disposed on at least one side of the first display area, and a power signal adapter cable extending along the row direction; In the first sub-pixel region, some of the power signal lines are interconnected via the same power signal adapter cable; some of the power signal lines are connected to the main power signal line via the same power signal adapter cable; some of the power signal lines are connected to the main power signal line via different power signal adapter cables; and at least one end of some of the power signal lines is connected to the main power signal line. In the virtual sub-pixel area, at least one end of the power signal line is connected to the main power signal line.

2. The display panel according to claim 1, wherein, In the same column of the virtual sub-pixel area, the number of power signal lines is two; and Two power signal lines in the same column of virtual sub-pixel area are connected to each other through the same power signal adapter cable, or connected to the main power signal line through the same power signal adapter cable.

3. The display panel according to claim 1, wherein, In the same column of the virtual sub-pixel area, the number of power signal lines is two; and The two power signal lines in the same column of virtual sub-pixel area are connected to each other through the same power signal adapter cable, or are connected to the main power signal line through two power signal adapter cables respectively.

4. The display panel according to claim 1, wherein, The display panel further includes: a first auxiliary initialization signal line and a second auxiliary initialization signal line extending along the column direction; the first auxiliary initialization signal line and the second auxiliary initialization signal line are respectively located in the virtual sub-pixel areas of different columns; the display panel further includes: a first main initialization signal line and a second main initialization signal line located in the peripheral area and extending along the column direction, and a first initialization signal adapter line and a second initialization signal adapter line extending along the row direction; Some of the first auxiliary initialization signal lines are connected to each other via the same first initialization signal adapter cable, and some of the first auxiliary initialization signal lines are connected to the first main initialization signal line via the first initialization signal adapter cable; and Some of the second auxiliary initialization signal lines are connected to each other through the same second initialization signal adapter cable, and some of the second auxiliary initialization signal lines are connected to the second main initialization signal line through the second initialization signal adapter cable.

5. The display panel according to claim 4, wherein, A first initialization signal adapter cable and a second initialization signal adapter cable are provided between adjacent power signal adapter cables.

6. The display panel according to claim 4, wherein, A first initialization signal adapter or a second initialization signal adapter is provided between adjacent power signal adapters.

7. The display panel according to claim 4, wherein, The display panel includes: a first source / drain conductive layer, a second source / drain conductive layer and a third source / drain conductive layer stacked together; The first source-drain conductive layer includes: the power signal adapter cable, the first initialization signal adapter cable, and the second initialization signal adapter cable; The second source / drain conductive layer includes: the data signal line; and The third source / drain conductive layer includes: the power signal line, the first auxiliary initialization signal line, and the second auxiliary initialization signal line.

8. The display panel according to any one of claims 1 to 7, wherein, The display panel further includes: fan-out signal lines extending along the column direction and data signal adapter lines extending along the row direction; and The fan-out signal line is located in the first sub-pixel area away from the peripheral area, and is connected to the data signal line close to the peripheral area through the data signal adapter.

9. The display panel according to claim 8, wherein, In the first sub-pixel area of ​​the same column, the fan-out signal line and the power signal line are located on the same straight line and are disconnected from each other.

10. The display panel according to claim 1, wherein, The first sub-pixel area in each M column and the virtual sub-pixel area in each column are alternately set.

11. The display panel according to claim 1 or 10, wherein, M equals 4.

12. The display panel according to any one of claims 1 to 11, wherein, The pixel driving circuit includes: a data writing transistor, a threshold compensation transistor, a first light-emitting control transistor, a second light-emitting control transistor, a first reset transistor, a second reset transistor, a driving transistor, and a storage capacitor.

13. The display panel according to claim 12, wherein, The drain of the second light-emitting control transistor is connected to the anode of the light-emitting device, and the cathode of the light-emitting device is connected to the second power signal line.

14. The display panel according to claim 13, wherein, The power signal line, the main power signal line, and the power signal adapter cable constitute the second power signal line.

15. The display panel according to claim 13 or 14, wherein, The second power signal line provides a low-level signal.

16. The display panel according to any one of claims 1 to 15, wherein, The length direction of the power signal adapter cable intersects with both the length direction of the power signal line and the length direction of the main power signal line.

17. The display panel according to claim 4, wherein, The pixel driving circuit includes: a data writing transistor, a threshold compensation transistor, a first light-emitting control transistor, a second light-emitting control transistor, a first reset transistor, a second reset transistor, a driving transistor, and a storage capacitor; the source of the first reset transistor is connected to a first initialization signal line, and the source of the second reset transistor is connected to a second initialization signal line.

18. The display panel according to claim 17, wherein, The first auxiliary initialization signal line, the first main initialization signal line, and the first initialization signal adapter line are connected together to form the first initialization signal line; and the second auxiliary initialization signal line, the second main initialization signal line, and the second initialization signal adapter line are connected together to form the second initialization signal line.

19. A display device, wherein, The display device includes a display panel according to any one of claims 1 to 18.

20. The display device according to claim 19, wherein, The display device further includes a sensor; the sensor is disposed corresponding to the second sub-pixel area and is located on the backlight side of the light-emitting device in the second sub-pixel area.

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