Display device

Abstract

The present invention provides a display device including: a substrate including a display area and a peripheral area outside the display area, the substrate foldable about a folding axis extending in a first direction across the display area; a plurality of pixels arranged in the display area; a first voltage line arranged in the peripheral area; a plurality of second voltage lines arranged in the display area and electrically connected to the first voltage line and the plurality of pixels; a sensing line arranged adjacent to the folding axis in the display area; and a connection line arranged in the peripheral area and electrically connected to the sensing line, wherein the sensing line includes a first end portion and a second end portion, the first end portion is electrically connected to the first voltage line, and the second end portion is electrically connected to the connection line.

Description

display device

[0001] The present invention relates to a display device, and more specifically, to a display device having a display panel that can be folded or unfolded.

[0002] As display devices that visually display electrical signals evolve, a variety of display devices with superior characteristics, such as thinness, weight reduction, and low power consumption, are being introduced. For example, active research and development is underway on display devices with foldable or unfoldable display panels.

[0003] Some embodiments of the present invention relate to a display device, for example, a display device having a display panel that can be folded or unfolded.

[0004] When a display panel is folded or unfolded, the area where an image is displayed may expand or contract. Furthermore, the brightness, color coordinates, etc. of pixels may change in the area where the display panel is bent. The present invention aims to provide a display device that detects deformation of a display panel to control the area where an image is displayed and compensate for the brightness, color coordinates, etc. of pixels. However, these tasks are exemplary and the scope of the present invention is not limited thereby.

[0005] According to one aspect of the present invention, a display device is provided, comprising: a substrate including a display area and a peripheral area outside the display area, the substrate being foldable about a folding axis extending in a first direction across the display area; a plurality of pixels arranged in the display area; a first voltage line arranged in the peripheral area; a plurality of second voltage lines arranged in the display area and electrically connected to the first voltage line and the plurality of pixels; a sensing wire arranged adjacent to the folding axis in the display area; and a connecting wire arranged in the peripheral area and electrically connected to the sensing wire, wherein the sensing wire includes a first end and a second end, the first end being electrically connected to the first voltage line, and the second end being electrically connected to the connecting wire.

[0006] In one embodiment, the sensing wire may have a meandering shape.

[0007] In one embodiment, the sensing wiring may include a wiring portion having a first width and a pattern portion having a second width greater than the first width.

[0008] In one embodiment, each of the plurality of pixels includes a pixel circuit including transistors and a light-emitting diode electrically connected to the pixel circuit, and the light-emitting diode may include a pixel electrode, a counter electrode disposed on the pixel electrode, and a light-emitting layer disposed between the pixel electrode and the counter electrode.

[0009] In one embodiment, the pixel circuit may include a driving transistor electrically connecting a power line and the pixel electrode, a data writing transistor electrically connecting a data line and the driving transistor, and a first initialization transistor electrically connecting one of the plurality of second voltage lines and a gate of the driving transistor.

[0010] In one embodiment, the pixel circuit may include a driving transistor electrically connecting a power line and the pixel electrode, a data writing transistor electrically connecting a data line and the driving transistor, and a second initialization transistor electrically connecting one of the second voltage lines and the pixel electrode.

[0011] In one embodiment, the first voltage line may be a first power voltage line electrically connected to the power line or a second power voltage line electrically connected to the counter electrode.

[0012] In one embodiment, the second voltage lines extend in a second direction intersecting the first direction, and the display device may further include a plurality of third voltage lines extending in the first direction and electrically connected to the plurality of second voltage lines.

[0013] In one embodiment, the sensing wire may be directly connected to one of the plurality of second voltage lines or one of the plurality of third voltage lines.

[0014] In one embodiment, the sensing wire may include a material that is stretchable and whose resistance changes with the length of the stretch.

[0015] In one embodiment, the sensing wiring may include conductive nanoparticles and an elastomer.

[0016] In one embodiment, the display device further includes a display driving circuit that drives the plurality of pixels and a sensing circuit that is electrically connected to the connection wiring and configured to detect a folding state by comparing a measured voltage of the sensing wiring with a reference voltage, and the display driving circuit may include a data driving unit configured to supply a data signal to the plurality of pixels, a gate driving unit configured to supply a scan signal to the plurality of pixels, a timing control unit configured to control operation timing of the data driving unit and the gate driving unit using a vertical synchronization signal, and a voltage generating unit configured to supply the reference voltage and the first voltage.

[0017] In one embodiment, the sensing circuit may include a memory storing a lookup table, a comparator comparing the measured voltage with the reference voltage and outputting a first value when the measured voltage is less than or equal to the reference voltage and outputting a second value when the measured voltage is greater than the reference voltage, a first controller configured to detect the folding state based on an output value of the comparator and generate sensing data including the folding state, and a second controller configured to generate a display control signal for controlling the plurality of pixels based on the lookup table and the sensing data.

[0018] In one embodiment, the first controller may be configured to output a voltage control signal that changes the reference voltage based on an output value of the comparator.

[0019] In one embodiment, the sensing circuit may further include a switch unit configured to electrically connect the sensing wire and the input terminal of the comparator during an on-voltage period of the switch control signal, and electrically separate the sensing wire and the input terminal of the comparator during an off-voltage period of the switch control signal.

[0020] In one embodiment, the on voltage period of the switch control signal may overlap with the on voltage period of the vertical synchronization signal.

[0021] In one embodiment, the display control signal may include an image control signal configured to rearrange the image displayed by the plurality of pixels according to the folding state.

[0022] In one embodiment, the display control signal may include an image quality control signal configured to compensate for color coordinates or luminance of the plurality of pixels according to the folding state.

[0023] According to another aspect of the present invention, a display device includes a substrate including a display area and a peripheral area outside the display area, and foldable around a first folding axis and a second folding axis extending in a first direction across the display area, a plurality of pixels arranged in the display area, a first voltage line arranged in the peripheral area, a plurality of second voltage lines arranged in the display area and electrically connected to the first voltage line and the plurality of pixels, a first sensing wire arranged adjacent to the first folding axis in the display area, a second sensing wire arranged adjacent to the second folding axis in the display area, a first connection wire arranged in the peripheral area and electrically connected to the first sensing wire, and a second connection wire arranged in the peripheral area and electrically connected to the second sensing wire, wherein a first end of the first sensing wire is electrically connected to the first voltage line and a second end of the first sensing wire is electrically connected to the first connection wire, and A display device is provided, wherein a first end of a second sensing wire is electrically connected to the first voltage line, and a second end of the second sensing wire is electrically connected to the second connection wire.

[0024] In one embodiment, the display device may further include a display driving circuit configured to drive the plurality of pixels using a vertical synchronization signal, and a sensing circuit electrically connected to the first connection wire and the second connection wire, and configured to detect a folding state of the substrate by comparing a measurement voltage of the first sensing wire with a first reference voltage and comparing a measurement voltage of the second sensing wire with a second reference voltage during an on voltage period of the vertical synchronization signal.

[0025] Other aspects, features and advantages other than those described above will become apparent from the following drawings, claims and detailed description of the invention.

[0026] According to one embodiment of the present invention, as described above, a display device capable of detecting deformation of a display panel can be implemented. Of course, the scope of the present invention is not limited by these effects.

[0027] The above-mentioned and other aspects, features, and advantages of the embodiments of the present disclosure will become more apparent when the detailed description of the invention is considered in conjunction with the accompanying drawings.

[0028] FIGS. 1A, 1B, and 1C are perspective views schematically illustrating an electronic device according to one embodiment of the present invention.

[0029] FIG. 2 is a drawing schematically illustrating a part of an electronic device according to one embodiment of the present invention.

[0030] FIG. 3 is a plan view schematically illustrating a portion of a display device according to one embodiment of the present invention.

[0031] FIGS. 4A, 4B, and 4C are each an equivalent circuit diagram of one pixel included in a display device according to one embodiment of the present invention.

[0032] FIG. 5 is a cross-sectional view schematically illustrating a portion of a display device according to one embodiment of the present invention.

[0033] FIG. 6 is a plan view schematically illustrating a portion of a display device according to one embodiment of the present invention.

[0034] FIG. 7a and FIG. 7b are each a plan view schematically illustrating a portion of a display device according to one embodiment of the present invention.

[0035] FIG. 8 is a plan view schematically illustrating a portion of a display device according to one embodiment of the present invention.

[0036] FIGS. 9A, 9B, and 9C are each a plan view schematically illustrating a portion of a sensing line according to one embodiment of the present invention.

[0037] FIGS. 10A, 10B, and 10C are each a cross-sectional view schematically illustrating a portion of a display device according to one embodiment of the present invention.

[0038] FIG. 11 is a diagram schematically showing a sensing circuit included in a display device according to one embodiment of the present invention.

[0039] FIG. 12 is a drawing schematically showing a method for driving a display device according to one embodiment of the present invention.

[0040] FIG. 13 is a timing diagram for explaining the operation timing of a vertical synchronization signal and a sensing control signal according to one embodiment of the present invention.

[0041] FIG. 14 is a drawing for explaining the folding state of a display device and the measurement voltage of a sensing line according to one embodiment of the present invention.

[0042] FIGS. 15A and 15B are perspective views schematically illustrating an electronic device according to one embodiment of the present invention.

[0043] FIG. 16 is a plan view schematically illustrating a display device according to one embodiment of the present invention.

[0044] FIG. 17 and FIG. 18 are perspective views schematically illustrating an electronic device according to one embodiment of the present invention.

[0045] The present invention is capable of various modifications and embodiments. Specific embodiments are illustrated in the drawings and described in detail in the detailed description. The effects and features of the present invention, as well as the methods for achieving them, will become clearer with reference to the embodiments described in detail below, along with the drawings. However, the present invention is not limited to the embodiments disclosed below and can be implemented in various forms.

[0046] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. When describing with reference to the drawings, identical or corresponding components are given the same reference numerals and redundant descriptions thereof will be omitted.

[0047] In this specification, the terms first, second, etc. are not used in a limiting sense, but are used for the purpose of distinguishing one component from another.

[0048] In this specification, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0049] In this specification, terms such as “include” or “have” mean that a feature or component described in the specification exists, and do not preclude the possibility that one or more other features or components may be added.

[0050] In this specification, when it is said that a part such as a film, region, or component is on or above another part, it includes not only the case where it is directly on top of the other part, but also the case where another film, region, component, etc. is interposed in between.

[0051] In this specification, when it is said that a film, region, component, etc. are connected, it includes cases where the films, regions, components, etc. are directly connected, and / or cases where other films, regions, components, etc. are interposed between the films, regions, components, etc. and are indirectly connected. For example, when it is said in this specification that a film, region, component, etc. are electrically connected, it refers to cases where the films, regions, components, etc. are directly electrically connected, and / or cases where other films, regions, components, etc. are interposed between them and are indirectly electrically connected.

[0052] In this specification, “A and / or B” refers to the case where it is A, or B, or both A and B. And, “at least one of A and B” refers to the case where it is A, or B, or both A and B.

[0053] In this specification, the x-direction, y-direction, and z-direction are not limited to directions along the three axes on the orthogonal coordinate system, and can be interpreted in a broad sense that includes them. For example, the x-direction, y-direction, and z-direction may be orthogonal to each other, but may also refer to different directions that are not orthogonal to each other.

[0054] In this specification, when we say “planar”, it means when the target portion is viewed from above (e.g., when viewed in a direction perpendicular to the upper surface of the substrate), and when we say “cross-sectional”, it means when the target portion is viewed from the side in a cross-section cut vertically.

[0055] In this specification, when a first component is said to "overlap" a second component, it means that the first component is positioned above or below the second component so that at least a portion of the first component overlaps the second component in a plane.

[0056] In this specification, "ON" used in connection with a device state may refer to an activated state of the device, and "OFF" may refer to a deactivated state of the device. "ON" used in connection with a signal received by a device may refer to a signal that activates the device, and "OFF" may refer to a signal that deactivates the device. A device may be activated by a high-level voltage or a low-level voltage. For example, a P-channel transistor (P-type transistor) is activated by a low-level voltage, and an N-channel transistor (N-type transistor) is activated by a high-level voltage. Therefore, it should be understood that the "ON" voltages for P-type transistors and N-type transistors are opposite (lower versus higher) voltage levels.

[0057] In some embodiments of this specification, where implementations are otherwise feasible, specific process sequences may be performed in a different order than described. For example, two processes described in succession may be performed substantially simultaneously, or in a reverse order from the described order.

[0058] For convenience of explanation, the sizes of components in the drawings may be exaggerated or reduced. For example, the sizes and thicknesses of each component shown in the drawings are arbitrarily indicated for convenience of explanation, and thus the present invention is not necessarily limited to what is shown.

[0059] FIGS. 1A, 1B, and 1C are perspective views schematically illustrating an electronic device according to one embodiment of the present invention.

[0060] Fig. 1a is a perspective view showing an electronic device (1A) folded at an angle of approximately 90 degrees, Fig. 1b is a perspective view showing an electronic device (1A) folded, and Fig. 1c is a perspective view showing an electronic device (1A) completely unfolded.

[0061] Referring to FIGS. 1A, 1B, and 1C, an electronic device (1A) according to an embodiment of the present invention may include a display device (50) and a housing (90). The display device (50) may include a main display area (MDA) on which an image is displayed, a sub display area (SDA), and a peripheral area (PA) disposed around the main display area (MDA). Pixels (P) having display elements may be disposed in the main display area (MDA) and the sub display area (SDA). At this time, the pixels (P) may be disposed spaced apart from each other according to a predetermined arrangement in each of the main display area (MDA) and the sub display area (SDA). The area of ​​the main display area (MDA) may be larger than the area of ​​the sub display area (SDA). In one embodiment, the sub display area (SDA) may be omitted. The display device (50) may provide an image by using light emitted from pixels (P) disposed in the main display area (MDA) and the sub display area (SDA). The peripheral area (PA) may be a kind of non-display area where pixels (P) are not placed.

[0062] A housing (90) may form the exterior of an electronic device (1A). The housing (90) may include plastic, metal, or the like. The housing (90) may include a first portion (91) and a second portion (92) that support a display device (50). The housing (90) may have a hinge (HG) between the first portion (91) and the second portion (92). The electronic device (1A) may be folded or unfolded near the hinge (HG).

[0063] For example, the main display area (MDA) may include a first main display area (MDA1) located in a first part (91) of the housing (90) and a second main display area (MDA2) located in a second part (92) of the housing (90). A folding axis (FAX) overlapping with a hinge (HG) may be located between the first main display area (MDA1) and the second main display area (MDA2). The display device (50) may be folded or unfolded based on the folding axis (FAX).

[0064] As illustrated in FIGS. 1A and 1B, the first main display area (MDA1) and the second main display area (MDA2) can be folded (in-folding) to face each other with respect to the folding axis (FAX). In another embodiment, the first main display area (MDA1) and the second main display area (MDA2) can be folded so as not to face each other with respect to the folding axis (FAX). For example, the first main display area (MDA1) and the second main display area (MDA2) can be folded so as to face outward, respectively.

[0065] The electronic device (1A) can display different images in each display area depending on the folding state. As illustrated in Fig. 1b, when the electronic device (1A) is completely folded, the user can only use the sub-display area (SDA) located on the outside. In this case, the electronic device (1A) can display an image only in the sub-display area (SDA) without displaying an image in the main display area (MDA). When the electronic device (1A) is partially folded as illustrated in Fig. 1a, the first main display area (MDA1) and the second main display area (MDA2) can display different images. When the electronic device (1A) is completely unfolded as illustrated in Fig. 1c, the image can be displayed by extending across the entire first main display area (MDA1) and the second main display area (MDA2). The electronic device (1A) can detect a change in the folding state and automatically control the image.

[0066] Referring to FIGS. 1A, 1B, and 1C, the electronic device (1A) is a device that displays a moving image or a still image, and may be a portable electronic device such as a mobile phone, a smart phone, a tablet personal computer (PC), a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation device, an Ultra Mobile PC (UMPC), etc., as well as a television, a laptop, a monitor, a billboard, an Internet of Things (IOT) device, etc.

[0067] In addition to the display device (50), the electronic device (1A) may include a processor, memory, an input module, an audio module, a communication module, a camera module, a battery module, etc. within the housing (90). At least one of these components may be omitted or added. In one embodiment, some of these components may be integrated into the display device (50).

[0068] FIG. 2 is a drawing schematically illustrating a part of an electronic device according to one embodiment of the present invention.

[0069] Referring to FIG. 2, an electronic device may include a display device (50). The display device (50) may include a display unit (11) and a display driving circuit (DDV) configured to drive the display unit (11). The display driving circuit (DDV) may include a gate driving unit (12), a data driving unit (13), a timing control unit (14), and a voltage generation unit (15).

[0070] The display unit (11) can be placed in the main display area (MDA). Although FIG. 2 only shows the display unit (11) placed in the main display area (MDA, see FIG. 1a), the display device (50) may further include a sub-display unit (not shown) placed in the sub-display area (SDA, see FIG. 1b).

[0071] The display unit (11) may include pixels (P), such as a pixel (Pij) located in the i-th row and the j-th column. Although FIG. 2 illustrates one pixel (P) in the display unit (11), a person skilled in the art can understand that the display unit (11) includes an appropriate number of pixels according to its design and size. In one embodiment, the display device (50) may have one or more display units (11). For ease of understanding, only one pixel (Pij) is illustrated in the display unit (11) of FIG. 2, but mХn pixels (P) may be arranged, for example, in a matrix form (or array). Here, i is a natural number greater than or equal to 1 and less than or equal to m, and j is a natural number greater than or equal to 1 and less than or equal to n.

[0072] In FIG. 2, for illustrative purposes, a pixel (P) employing a pixel circuit including two transistors and one capacitor is described. However, the present invention is not only applicable to a pixel (P) employing this specific pixel circuit, but can also be equally applied to other pixel circuits, for example, a pixel (P) employing a pixel circuit including three transistors and one capacitor, a pixel (P) employing a pixel circuit including seven transistors and one capacitor, etc.

[0073] Pixels (P) are connected to scan lines (SL_1 to SL_m), data lines (DL_1 to DL_n), and a first power line (PL). For example, a pixel (Pij) located in the i-th row and the j-th column can be connected to a scan line (SL_i), a data line (DL_j), and a first power line (PL).

[0074] The data lines (DL_1 to DL_n) may extend in the column direction of the pixels (P) (hereinafter, pixel column direction) and be connected to the pixels (P) located in the same column. The scan lines (SL_1 to SL_m) may extend in the row direction of the pixels (P) (hereinafter, pixel row direction) and be connected to the pixels (P) located in the same row.

[0075] The first power line (PL) extends in the direction of the pixel column and may be provided in multiple numbers. Each of the first power lines (PL) may be connected to pixels (P) located in the same column.

[0076] Each of the scan lines (SL_1 to SL_m) transmits scan signals (Sn_1 to Sn_m) output from the gate driver (12) to the pixels (P) in the same row. Each of the data lines (DL_1 to DL_n) transmits data signals (Dm_1 to Dm_n) output from the data driver (13) to the pixels (P) in the same column. The pixel (Pij) located in the i-th row and the j-th column receives the scan signal (Sn_i) and the data signal (Dm_j).

[0077] The first power line (PL) transmits the first power voltage (VDD) output from the voltage generator (15) to the pixels (P).

[0078] A pixel (Pij) includes a driving transistor and a storage capacitor that control the amount of current flowing to the display element based on a display element and a data signal (Dm_j). The data signal (Dm_j) is output from a data driving unit (13) and received by the pixel (Pij) through a data line (DL_j). The display element may be, for example, an organic light-emitting diode. By causing the display element to emit light with a brightness corresponding to the amount of current received from the driving transistor, the pixel (Pij) can express a grayscale corresponding to the data signal (Dm_j). In the present specification, each pixel (P) may correspond to a part of a unit pixel capable of displaying full color, for example, a subpixel.

[0079] The voltage generation unit (15) can generate voltages required for driving pixels (Pij). For example, the voltage generation unit (15) can generate a first power voltage (VDD, driving voltage) and a second power voltage (VSS, common voltage). The level of the first power voltage (VDD) can be higher than the level of the second power voltage (VSS).

[0080] The voltage generator (15) can generate a first initialization voltage and a second initialization voltage and provide them to the pixels (P). The first initialization voltage can be applied to a gate of a driving transistor to initialize the gate of the driving transistor. The second initialization voltage can be applied to a pixel electrode (e.g., an anode) of a display element to initialize the pixel electrode. The voltage generator (15) can generate a sustain voltage and provide it to the pixels (P). The sustain voltage can be applied to one electrode of a storage capacitor. The first power supply voltage (VDD), the second power supply voltage (VSS), the first initialization voltage, the second initialization voltage, and the sustain voltage may be DC voltages whose direction and magnitude are maintained constant. In one embodiment, the first initialization voltage, the second initialization voltage, and the sustain voltage may be omitted.

[0081] In addition, the voltage generation unit (15) can generate a turn-on voltage and a turn-off voltage for controlling the switching transistor of the pixel (Pij) and provide them to the gate driver (12). When the turn-on voltage is applied to the gate of the switching transistor, the switching transistor can be turned on, and when the turn-off voltage is applied to the gate of the switching transistor, the switching transistor can be turned off. The voltage generation unit (15) can also generate gamma reference voltages and provide them to the data driver (13).

[0082] The timing control unit (14) can control the pixels (P) of the display unit (11) by controlling the operation timing of the gate driver (12) and the data driver (13). The pixels (P) of the display unit (11) receive a new data signal (Dm) for each frame period, and can display an image corresponding to the image source data (RGB) of one frame by emitting light with a brightness corresponding to the data signal (Dm).

[0083] The timing control unit (14) receives image source data (RGB) and a control signal (CONT) from the outside. The timing control unit (14) can convert the image source data (RGB) into image data (DATA) based on the characteristics of the display unit (11) and pixels (P). The timing control unit (14) can provide the image data (DATA) to the data driving unit (13).

[0084] The control signal (CONT) may include a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a data enable signal, a clock signal, etc. The vertical synchronization signal (Vsync) may define the start of a section (hereinafter, a frame period) in which image data (DATA) constituting one frame is written. The horizontal synchronization signal (Hsync) may define the start of a section in which image data constituting a horizontal line image displayed through one pixel row is written. The timing control unit (14) may control the operation timing of the gate driver (12) and the data driver (13) using the control signal (CONT). The timing control unit (14) may count the data enable signals of the horizontal scanning period to determine the frame period. The image data (DATA) includes luminance information of the pixels (P). The luminance may be a fixed number, for example, 1024 (=2 10 ), 256(=2 8 ) or 64(=2 6 ) can have gray levels.

[0085] The timing control unit (14) can generate control signals including a gate timing control signal (GDC) for controlling the operation timing of the gate driver (12) and a data timing control signal (DDC) for controlling the operation timing of the data driver (13). In one embodiment, the timing control unit (14) can generate a switch control signal for controlling the operation timing of a sensing circuit that detects a folding state using a vertical synchronization signal (Vsync).

[0086] The gate timing control signal (GDC) may include a gate start pulse, a gate shift clock, a gate output enable signal, etc. The gate start pulse is supplied to the gate driver (12) that generates the first scan signal at the start of the scanning period. The gate shift clock is a clock signal commonly input to the gate driver (12) and is a clock signal for shifting the gate start pulse. The gate output enable signal controls the output of the gate driver (12).

[0087] The data timing control signal may include a source start pulse, a source sampling clock, a source output enable signal, etc. The source start pulse controls the data sampling start time of the data driving unit (13) and is provided to the data driving unit (13) at the start time of the scanning period. The source sampling clock is a clock signal that controls the data sampling operation within the data driving unit (13) based on the rising or falling edge. The source output enable signal controls the output of the data driving unit (13). Meanwhile, the source start pulse supplied to the data driving unit (13) may be omitted depending on the data transmission method.

[0088] The gate driver (12) sequentially generates scan signals (Sn_1 to Sn_m) in response to a gate timing control signal (GDC) supplied from a timing controller (14) using a turn-on voltage or a turn-off voltage provided from a voltage generator (15). The gate driver (12) may include a plurality of transistors and may be formed together with pixels (P) through a thin film process. For example, the gate driver (12) may be mounted in the peripheral area (PA) of the display panel in the form of an ASG (Amorphous Silicon TFT Gate driver circuit) or an OSG (Oxide Semiconductor TFT Gate driver circuit).

[0089] The data driving unit (13) samples and latches the image data (DATA) supplied from the timing control unit (14) in response to the data timing control signal (DDC) supplied from the timing control unit (14) and converts it into data of a parallel data system. When converting into data of a parallel data system, the data driving unit (13) converts the image data (DATA) into a gamma reference voltage and converts it into data signals (Dm_1 to Dm_n) in analog form. The data driving unit (13) provides the data signals (Dm_1 to Dm_n) to the pixels (P) through the data lines (DL_1 to DL_n). The pixels (P) receive the data signals (Dm_1 to Dm_n) in response to the scan signals (Sn_1 to Sn_m).

[0090] FIG. 3 is a plan view schematically illustrating a portion of a display device according to one embodiment of the present invention.

[0091] Referring to FIG. 3, the display device (50) may include a display panel (DP), a circuit board (PCB), and a flexible film (FFC) connecting the display panel (DP) and the circuit board (PCB). Although FIG. 3 illustrates only one display panel (DP), in one embodiment, the display device (50) may further include a sub-display panel (not shown) including a sub-display area (SDA, see FIG. 1b).

[0092] A display panel (DP) may include a main display area (MDA) in which a plurality of pixels (P) are positioned, and a peripheral area (PA) positioned outside the main display area (MDA). This can be understood as meaning that the substrate (100) included in the display panel (DP) has the main display area (MDA) and the peripheral area (PA). In one embodiment, the display panel (DP) may be a flexible display panel that can be bent, folded, or rolled.

[0093] The substrate (100) may include various materials having flexible or bendable properties. For example, the substrate (100) may include a polymer resin such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate. In one embodiment, the substrate (100) may have a multilayer structure. For example, the substrate (100) may include two layers including a polymer resin and a barrier layer including an inorganic material interposed between the layers.

[0094] A plurality of pixels (P) may be arranged in the main display area (MDA). The pixels (P) may include a display element such as an organic light-emitting diode and a pixel circuit electrically connected to the display element. Each display element may emit red, green, blue, or white light. Each pixel (P) may be electrically connected to external circuits and wires arranged in the peripheral area (PA).

[0095] A gate driver (12, see FIG. 2), a data driver (13), and wires may be arranged in the peripheral area (PA). The gate driver (12) may include a first gate driver (3a) located on the left side (-x direction) of the peripheral area (PA) with respect to the main display area (MDA) and a second gate driver (3b) located on the right side (+x direction) of the peripheral area (PA). The first gate driver (3a) may transmit scan signals to pixels (P) located on the left side with respect to an imaginary center line that bisects the main display area (MDA) through scan lines (SL). The second gate driver (3b) may transmit scan signals to pixels located on the right side with respect to an imaginary center line that bisects the main display area (MDA) through scan lines (SL). In one embodiment, either the first gate driver (3a) or the second gate driver (3b) may be omitted.

[0096] The data driver (13) can transmit data signals to pixels (P) via data lines (DL). In one embodiment, the data driver (13) may be a display driver IC (DDI). In another embodiment, the data driver (13) may be a touch and display driver IC (TDDI). The data driver (13) may be mounted in a peripheral area (PA) adjacent to an edge of the substrate (100).

[0097] The wires arranged in the peripheral area (PA) may include a first power voltage line (6) and a second power voltage line (7). The first power voltage line (6) may be arranged to extend in the first direction (x direction) from the lower side (-y direction) of the peripheral area (PA) based on the main display area (MDA).

[0098] The second power voltage line (7) may be arranged in the peripheral area (PA) to surround a portion of the main display area (MDA). The second power voltage line (7) may have a loop shape with one end open, extending along the boundary of the main display area (MDA).

[0099] The peripheral area (PA) may include a first pad area (PDA1) in which a plurality of pads are positioned. The plurality of pads are exposed and not covered by an insulating layer, and may be electrically connected to a flexible film (FFC). That is, the pads of the flexible film (FFC) may be electrically connected to the pads of the display panel (DP).

[0100] For reference, FIG. 3 can be understood as a plan view showing the appearance of the display device (50) during the manufacturing process. In the final electronic device (1A), a portion of the display panel (DP) may be bent to minimize or reduce the area of ​​the non-display area. For example, the peripheral area (PA) includes a bending area (BA) located between the main display area (MDA) and the first pad area (PDA1), and the substrate (100) may be bent in the bending area (BA). When the surface of the display panel (DP) that displays an image is referred to as the front surface, and the surface facing the front surface is referred to as the back surface, a portion of the peripheral area (PA), a flexible film (FFC), and a circuit board (PCB) may be located on the back surface of the display panel (DP).

[0101] A control circuit and a voltage generation unit (15, see FIG. 2) that control the overall operation of a display device (50) may be mounted on a circuit board (PCB). The circuit board (PCB) may be a printed circuit board. The circuit board (PCB) may include a second pad area (PDA2) on which a plurality of pads are positioned. The plurality of pads may be exposed without being covered by an insulating layer and may be electrically connected to a flexible film (FFC). That is, pads of the flexible film (FFC) may be electrically connected to pads of the circuit board (PCB).

[0102] The control signal generated in the control circuit and the voltage generated in the voltage generation unit (15) can be transmitted to the first gate driver (3a), the second gate driver (3b), the data driver (13), and wires through the flexible film (FFC). For example, the voltage generation unit (15) can transmit the first power voltage (VDD, see FIG. 2) to the first power voltage line (6) and transmit the second power voltage (VSS, see FIG. 2) to the second power voltage line (7) through the corresponding pads.

[0103] In one embodiment, a sensing circuit (FSC) may be mounted on a circuit board (PCB). The sensing circuit (FSC) is electrically connected to a sensing wire (not shown) arranged on a display panel (DP), and can detect a folding state of the display panel (DP) by utilizing changes in the electrical characteristics of the sensing wire, and transmit a control signal according to the folding state to a display driving circuit (DDV).

[0104] The flexible film (FFC) may be a flexible printed circuit board (PCB) or a flexible cable. If the flexible film (FFC) is a flexible PCB, the sensing circuit (FSC) may be mounted on the flexible film (FFC). In another embodiment, the sensing circuit (FSC) may be mounted on a peripheral area (PA) of the display panel (DP). The sensing circuit (FSC) may also be provided as an integral part of the data driver (13).

[0105] FIGS. 4A, 4B, and 4C are each an equivalent circuit diagram of one pixel included in a display device according to one embodiment of the present invention.

[0106] Referring to FIG. 4A, a pixel (P, see FIG. 3) may include a display element (ED) and a pixel circuit (PC) electrically connected to the display element (ED). The pixel circuit (PC) may include a first transistor (T1), a second transistor (T2), and a storage capacitor (Cst). The pixel circuit (PC) may be electrically connected to a signal line and a voltage line. The signal line may include a gate line such as a first scan line (SL1) and a data line (DL), and the voltage line may include a first power line (PL) that transmits a first power voltage (VDD).

[0107] The second transistor (T2) may be electrically connected to the first scan line (SL1) and the data line (DL). The first scan line (SL1) may provide a first scan signal (GW) to a gate electrode of the second transistor (T2). The second transistor (T2) may be a switching transistor that is turned on or off according to the first scan signal (GW) input from the first scan line (SL1). The second transistor (T2) may be electrically connected to the first transistor (T1) and may transmit a data signal (Dm) input from the data line (DL) to the first transistor (T1).

[0108] The storage capacitor (Cst) is electrically connected to the second transistor (T2) and the first power line (PL), and can store a voltage corresponding to the difference between the voltage received from the second transistor (T2) and the first power voltage (VDD) supplied by the first power line (PL).

[0109] The first transistor (T1) is a driving transistor and can control a driving current flowing through the display element (ED). The first transistor (T1) can be connected to a first power line (PL) and a storage capacitor (Cst). The first transistor (T1) can control a driving current flowing from the first power line (PL) to the display element (ED) in response to a voltage value stored in the storage capacitor (Cst). The display element (ED) can emit light having a predetermined brightness by the driving current. A pixel electrode (anode) of the display element (ED) can be electrically connected to the first transistor (T1), and a counter electrode (cathode) can be electrically connected to a second power voltage line (7, see FIG. 3) that supplies a second power voltage (common power voltage) (VSS).

[0110] Although FIG. 4A illustrates that the pixel circuit (PC) includes two transistors and one storage capacitor, in other embodiments, the pixel circuit (PC) may include three or more transistors. Furthermore, the pixel circuit (PC) may further include additional components without departing from the technical spirit of the present invention.

[0111] Referring to FIG. 4B, the pixel circuit (PC) may include a first transistor (T1), a second transistor (T2), a third transistor (T3), a fourth transistor (T4), a fifth transistor (T5), a sixth transistor (T6), a seventh transistor (T7), and a storage capacitor (Cst). The pixel circuit (PC) is electrically connected to signal lines and voltage lines. The signal lines may include gate lines such as a first scan line (SL1), a second scan line (SL2), a third scan line (SL3), and an emission control line (EML), and a data line (DL). The voltage lines may include a first initialization voltage line (VIL1), a second initialization voltage line (VIL2), and a first power line (PL).

[0112] The first power line (PL) can transmit a first power voltage (VDD) to the first transistor (T1). The first initialization voltage line (VIL1) can transmit a first initialization voltage (Vint) that initializes the first transistor (T1) to the pixel circuit (PC). The second initialization voltage line (VIL2) can transmit a second initialization voltage (Vaint) that initializes the first electrode of the display element (ED) to the pixel circuit (PC).

[0113] The first transistor (T1) may be electrically connected to the first power line (PL) via the fifth transistor (T5) and may be electrically connected to the display element (ED) via the sixth transistor (T6). The first transistor (T1) functions as a driving transistor, and receives a data signal (Dm) according to the switching operation of the second transistor (T2) and supplies a driving current to the display element (ED).

[0114] The second to seventh transistors (T2 to T7) may be switching transistors that are turned on or off depending on the gate-source voltage or gate voltage.

[0115] The second transistor (T2) is a data writing transistor and is electrically connected to the first scan line (SL1) and the data line (DL). The second transistor (T2) is electrically connected to the first power line (PL) via the fifth transistor (T5). The second transistor (T2) is turned on in response to the first scan signal (GW) received through the first scan line (SL1) and performs a switching operation to transmit the data signal (Dm) transmitted to the data line (DL) to the first node (N1).

[0116] The third transistor (T3) is electrically connected to the first scan line (SL1) and is electrically connected to the display element (ED) via the sixth transistor (T6). The third transistor (T3) can be turned on in response to the first scan signal (GW) received through the first scan line (SL1) to diode-connect the first transistor (T1).

[0117] The fourth transistor (T4) is a first initialization transistor and is electrically connected to the third scan line (SL3) and the first initialization voltage line (VIL1). The fourth transistor (T4) is turned on according to the third scan signal (GI) received through the third scan line (SL3) and transmits the first initialization voltage (Vint) from the first initialization voltage line (VIL1) to the gate electrode of the first transistor (T1) to initialize the voltage of the gate electrode of the first transistor (T1). The third scan signal (GI) may correspond to the first scan signal of another pixel circuit arranged in the previous row of the corresponding pixel circuit (PC).

[0118] The fifth transistor (T5) may be a motion control transistor, and the sixth transistor (T6) may be a light emission control transistor. The fifth transistor (T5) and the sixth transistor (T6) are electrically connected to the light emission control line (EML), and are turned on simultaneously according to the light emission control signal (EM) transmitted through the light emission control line (EML), thereby forming a current path so that a driving current can flow from the first power line (PL) in the direction of the display element (ED).

[0119] The seventh transistor (T7) is a second initialization transistor and can be electrically connected to the second scan line (SL2), the second initialization voltage line (VIL2), and the sixth transistor (T6). The seventh transistor (T7) is turned on according to the second scan signal (GB) transmitted through the second scan line (SL2), and can transmit the second initialization voltage (Vaint) from the second initialization voltage line (VIL2) to the pixel electrode of the display element (ED) to initialize the pixel electrode of the display element (ED).

[0120] The storage capacitor (Cst) includes a first capacitor electrode (CE1) and a second capacitor electrode (CE2). The first capacitor electrode (CE1) is electrically connected to the gate electrode of the first transistor (T1), and the second capacitor electrode (CE2) is electrically connected to the first power line (PL). The storage capacitor (Cst) can maintain the voltage applied to the gate electrode of the first transistor (T1) by storing and maintaining a voltage corresponding to the difference between the voltages at both ends of the first power line (PL) and the gate electrode of the first transistor (T1). Although FIG. 4B exemplarily illustrates various components of the pixel circuit (PC), the pixel circuit (PC) may further include additional components or omit some components within the scope of the technical idea of ​​the present invention.

[0121] Referring to FIG. 4c, the pixel circuit (PC) may include a first transistor (T1), a second transistor (T2), a third transistor (T3), a fourth transistor (T4), a fifth transistor (T5), a sixth transistor (T6), a seventh transistor (T7), an eighth transistor (T8), a ninth transistor (T9), a storage capacitor (Cst), and an auxiliary capacitor (Ca).

[0122] The pixel circuit (PC) is electrically connected to signal lines and voltage lines. The signal lines may include gate lines such as a first scan line (SL1), a second scan line (SL2), a third scan line (SL3), and an emission control line (EML), and a data line (DL). The voltage lines may include first and second initialization voltage lines (VIL1, VIL2), a sustain voltage line (VSL), and a first power line (PL).

[0123] The first power line (PL) can transmit a first power voltage (VDD) to the first transistor (T1). The first initialization voltage line (VIL1) can transmit a first initialization voltage (Vint) for initializing the first transistor (T1) to the pixel circuit (PC). The second initialization voltage line (VIL2) can transmit a second initialization voltage (Vaint) for initializing the first electrode of the display element (ED) to the pixel circuit (PC). The sustain voltage line (VSL) can provide a sustain voltage (VSUS) to the second node (N2), for example, the second capacitor electrode (CE2) of the storage capacitor (Cst), during the initialization period and the data writing period.

[0124] The first transistor (T1) may be electrically connected to the first power line (PL) via the fifth transistor (T5) and the eighth transistor (T8), and may be electrically connected to the display element (ED) via the sixth transistor (T6). The first transistor (T1) functions as a driving transistor, and may receive a data signal (Dm) according to the switching operation of the second transistor (T2) to supply a driving current to the display element (ED).

[0125] The second to ninth transistors (T2 to T9) may be switching transistors that are turned on or off depending on the gate-source voltage or gate voltage.

[0126] The second transistor (T2) is electrically connected to the first scan line (SL1) and the data line (DL), and is electrically connected to the first power line (PL) via the fifth transistor (T5) and the eighth transistor (T8). The second transistor (T2) is turned on in response to the first scan signal (GW) received through the first scan line (SL1) and performs a switching operation to transmit the data signal (Dm) transmitted to the data line (DL) to the first node (N1).

[0127] The third transistor (T3) is electrically connected to the first scan line (SL1) and is electrically connected to the display element (ED) via the sixth transistor (T6). The third transistor (T3) is turned on in response to the first scan signal (GW) received through the first scan line (SL1), thereby diode-connecting the first transistor (T1), thereby compensating for the threshold voltage of the first transistor (T1).

[0128] The fourth transistor (T4) is electrically connected to the third scan line (SL3) and the first initialization voltage line (VIL1), and is turned on in response to the third scan signal (GI) transmitted through the third scan line (SL3) to transmit the first initialization voltage (Vint) from the first initialization voltage line (VIL1) to the gate electrode of the first transistor (T1) to initialize the voltage of the gate electrode of the first transistor (T1). The third scan signal (GI) may correspond to the first scan signal of another pixel circuit arranged in the previous row of the corresponding pixel circuit (PC).

[0129] The fifth transistor (T5), the sixth transistor (T6), and the eighth transistor (T8) are electrically connected to the emission control line (EML), and are simultaneously turned on in response to the emission control signal (EM) transmitted through the emission control line (EML), thereby forming a current path so that a driving current can flow from the first power line (PL) in the direction of the display element (ED).

[0130] The seventh transistor (T7) is a second initialization transistor and can be electrically connected to the second scan line (SL2), the second initialization voltage line (VIL2), the sixth transistor (T6), and the display element (ED). The seventh transistor (T7) is turned on in response to the second scan signal (GB) transmitted through the second scan line (SL2) and transmits the second initialization voltage (Vaint) from the second initialization voltage line (VIL2) to the first electrode of the display element (ED), thereby initializing the pixel electrode of the display element (ED).

[0131] The ninth transistor (T9) may be electrically connected to the second scan line (SL2), the second capacitor electrode (CE2) of the storage capacitor (Cst), and the sustain voltage line (VSL). The ninth transistor (T9) is turned on according to the second scan signal (GB) transmitted through the second scan line (SL2), and may transmit the sustain voltage (VSUS) to the second node (N2), for example, the second capacitor electrode (CE2) of the storage capacitor (Cst), during the initialization section and the data writing section.

[0132] The eighth transistor (T8) and the ninth transistor (T9) may be electrically connected to a second node (N2), for example, a second capacitor electrode (CE2) of a storage capacitor (Cst), respectively. In some embodiments, the eighth transistor (T8) may be turned off and the ninth transistor (T9) may be turned on in an initialization period and a data writing period, and the eighth transistor (T8) may be turned on and the ninth transistor (T9) may be turned off in an emission period. Since the sustain voltage (VSUS) is transmitted to the second node (N2) in the initialization period and the data writing period, the uniformity of the luminance (e.g., LRU, Long Range Uniformity) of the display device according to the voltage drop of the first power line (PL) may be improved.

[0133] The storage capacitor (Cst) includes a first capacitor electrode (CE1) and a second capacitor electrode (CE2). The first capacitor electrode (CE1) is electrically connected to the gate electrode of the first transistor (T1), and the second capacitor electrode (CE2) is electrically connected to the eighth transistor (T8) and the ninth transistor (T9).

[0134] The auxiliary capacitor (Ca) can be electrically connected to the sixth transistor (T6), the sustain voltage line (VSL), and the pixel electrode of the display element (ED). The auxiliary capacitor (Ca) stores and maintains a voltage corresponding to a voltage difference between the pixel electrode of the display element (ED) and the sustain voltage line (VSL) while the seventh transistor (T7) and the ninth transistor (T9) are turned on, thereby preventing or reducing a problem in which black luminance increases when the sixth transistor (T6) is turned off.

[0135] The first power supply voltage (VDD), the second power supply voltage (VSS), the first initialization voltage (Vint), the second initialization voltage (Vaint), and the sustain voltage (VSUS) are voltages supplied to the pixel circuit (PC), and may be DC voltages whose direction and magnitude are maintained constant. Although Fig. 4c exemplarily illustrates various components of the pixel circuit (PC), the pixel circuit (PC) may further include additional components or some components may be omitted within the scope of the technical idea of ​​the present invention.

[0136] FIG. 5 is a cross-sectional view schematically illustrating a portion of a display device according to one embodiment of the present invention.

[0137] Referring to FIG. 5, the display device (50) may include a substrate (100), a display layer (200), an encapsulation layer (300), and an input sensing layer (400). The display layer (200) may include a pixel circuit (PC) arranged in a display area (DA) and a display element (ED) electrically connected to the pixel circuit (PC). The pixel circuit (PC) may include a first transistor (T1), a third transistor (T3), and a storage capacitor (Cst).

[0138] The buffer layer (201) may include an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride, and may include a single-layer or multi-layer structure including the aforementioned inorganic insulating material. The buffer layer (201) may block the penetration of impurities from the substrate (100) and provide a flat base surface to components on the buffer layer (201).

[0139] A first semiconductor layer (A1) of a first transistor (T1) may be disposed on a buffer layer (201). The first semiconductor layer (A1) may include a silicon-based semiconductor material, such as amorphous silicon, polysilicon, etc. The first semiconductor layer (A1) may include a channel region (C1) and a first region (B1) and a second region (D1) disposed on both sides of the channel region (C1). The first region (B1) and the second region (D1) are regions that include impurities at a higher concentration than the channel region (C1), and one of the first region (B1) and the second region (D1) may be a source region and the other may be a drain region.

[0140] A first gate insulating layer (203) may be disposed on the first semiconductor layer (A1). The first gate insulating layer (203) may include an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride, and may include a single-layer or multi-layer structure including the aforementioned inorganic insulating material.

[0141] The first transistor (T1) may include a gate electrode (hereinafter referred to as a first gate electrode, GE1) overlapping the channel region (C1) of the first semiconductor layer (A1). The first gate electrode (GE1) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like, and may include a single-layer or multi-layer structure including the aforementioned materials.

[0142] The storage capacitor (Cst) may include a first capacitor electrode (CE1) and a second capacitor electrode (CE2) that overlap each other. In one embodiment, the first capacitor electrode (CE1) of the storage capacitor (Cst) may include a first gate electrode (GE1). In other words, the first gate electrode (GE1) may include the first capacitor electrode (CE1). For example, the first gate electrode (GE1) and the first capacitor electrode (CE1) of the storage capacitor (Cst) may be formed integrally.

[0143] A first interlayer insulating layer (205) may be disposed between the first capacitor electrode (CE1) and the second capacitor electrode (CE2) of the storage capacitor (Cst). The first interlayer insulating layer (205) may include an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride, and may include a single-layer or multi-layer structure including the aforementioned inorganic insulating material.

[0144] The second capacitor electrode (CE2) of the storage capacitor (Cst) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may include a single-layer or multi-layer structure including the aforementioned material.

[0145] A second interlayer insulating layer (207) may be disposed on the storage capacitor (Cst). The second interlayer insulating layer (207) may include an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride, and may include a single-layer or multi-layer structure including the aforementioned inorganic insulating material.

[0146] The semiconductor layer (hereinafter, referred to as the third semiconductor layer, A3) of the third transistor (T3) may be disposed on the second interlayer insulating layer (207). The third semiconductor layer (A3) may include an oxide-based semiconductor material. For example, the third semiconductor layer (A3) may be formed of a Zn oxide-based material, such as Zn oxide, In—Zn oxide, Ga—In—Zn oxide, etc. In some embodiments, the third semiconductor layer (A3) may be an IGZO (In—Ga—Zn—O), ITZO (In—Sn—Zn—O), or IGTZO (In—Ga—Sn—Zn—O) semiconductor containing a metal such as indium (In), gallium (Ga), or tin (Sn) in ZnO.

[0147] The third semiconductor layer (A3) may include a channel region (C3) and a first region (B3) and a second region (D3) arranged on both sides of the channel region (C3). One of the first region (B3) and the second region (D3) may be a source region and the other may be a drain region.

[0148] The third transistor (T3) may include a gate electrode (hereinafter referred to as the third gate electrode, GE3) overlapping the channel region (C3) of the third semiconductor layer (A3). The third gate electrode (GE3) may have a dual gate structure including a lower gate electrode (G3A) disposed below the third semiconductor layer (A3) and an upper gate electrode (G3B) disposed above the channel region (C3).

[0149] The lower gate electrode (G3A) may be disposed on the same layer as the second capacitor electrode (CE2) of the storage capacitor (Cst). For example, the lower gate electrode (G3A) may be disposed between the first interlayer insulating layer (205) and the second interlayer insulating layer (207). The lower gate electrode (G3A) may include the same material as the second capacitor electrode (CE2) of the storage capacitor (Cst).

[0150] The upper gate electrode (G3B) may be disposed on the third semiconductor layer (A3) with the second gate insulating layer (209) interposed therebetween. The second gate insulating layer (209) may include an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride, and may include a single-layer or multi-layer structure including the aforementioned inorganic insulating material.

[0151] The third interlayer insulating layer (210) may be disposed on the upper gate electrode (G3B). The third interlayer insulating layer (210) may include an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride, and may include a single-layer or multi-layer structure including the aforementioned inorganic insulating material.

[0152] A first organic insulating layer (211), a second organic insulating layer (212), and a third organic insulating layer (213) may be sequentially laminated on the third interlayer insulating layer (210). The first organic insulating layer (211), the second organic insulating layer (212), and the third organic insulating layer (213) may include an organic insulating material. The organic insulating material may include acrylic, BCB (Benzocyclobutene), polyimide, or HMDSO (Hexamethyldisiloxane). Some of the first organic insulating layer (211), the second organic insulating layer (212), and the third organic insulating layer (213) may be omitted.

[0153] Conductive layers may be disposed between the third interlayer insulating layer (210) and the first organic insulating layer (211), between the first organic insulating layer (211) and the second organic insulating layer (212), and between the second organic insulating layer (212) and the third organic insulating layer (213). The conductive layers may include signal lines and / or connection electrodes that electrically connect the pixel circuit (PC) and the display element (ED). For example, a data line (DL) and a first power line (PL) may be disposed between the second organic insulating layer (212) and the third organic insulating layer (213). Each of the conductive layers may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like, and may include a single-layer or multi-layer structure including the aforementioned material. In one embodiment, each of the data line (DL) and the first power line (PL) may have a three-layer structure of titanium layer / aluminum layer / titanium layer.

[0154] The display element (ED) may be disposed on the third organic insulating layer (213). In one embodiment, the display element (ED) may be an organic light-emitting diode including a pixel electrode (221), a counter electrode (223), and an intermediate layer (222) disposed between the pixel electrode (221) and the counter electrode (223).

[0155] The pixel electrode (221) may include a reflective film including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound thereof. In another embodiment, the pixel electrode (221) may further include a conductive oxide layer on and / or below the aforementioned reflective film. The conductive oxide layer may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and / or aluminum zinc oxide (AZO). In one embodiment, the pixel electrode (221) may have a three-layer structure of ITO layer / Ag layer / ITO layer.

[0156] The bank layer (215) may be disposed on the pixel electrode (221). The bank layer (215) may include an opening that overlaps the pixel electrode (221), but may cover the edge of the pixel electrode (221). The bank layer (215) may include an organic insulating material such as polyimide.

[0157] The intermediate layer (222) includes a light-emitting layer (222b). The intermediate layer (222) may include a first functional layer (222a) disposed below the light-emitting layer (222b) and / or a second functional layer (222c) disposed above the light-emitting layer (222b). The light-emitting layer (222b) may include a polymer or low-molecular organic material that emits light of a predetermined color. The first functional layer (222a) may be a hole transport layer. Alternatively, the first functional layer (222a) may include a hole injection layer and a hole transport layer. The second functional layer (222c) may include an electron transport layer (ETL) and / or an electron injection layer (EIL).

[0158] The counter electrode (223) may be formed of a conductive material having a low work function. For example, the counter electrode (223) may include a (semi-)transparent layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or an alloy thereof. Alternatively, the counter electrode (223) may further include a layer such as ITO, IZO, ZnO, or In2O3 on the (semi-)transparent layer including the aforementioned material.

[0159] The light-emitting layer (222b) can be formed by patterning so as to overlap the pixel electrode (221) through the opening of the bank layer (215). On the other hand, the first functional layer (222a), the second functional layer (222c), and the counter electrode (223) can cover the entire display area (DA).

[0160] A spacer (217) may be formed on the bank layer (215). The spacer (217) may be formed together with the bank layer (215) in the same process, or may be formed individually in separate processes. In one embodiment, the spacer (217) may include an organic insulating material such as polyimide. Alternatively, the bank layer (215) may include an organic insulating material including a light-blocking dye, and the spacer (217) may include an organic insulating material such as polyimide.

[0161] The display element (ED) may be covered with an encapsulating layer (300). The encapsulating layer (300) may include at least one organic encapsulating layer and at least one inorganic encapsulating layer. In one embodiment, FIG. 4 illustrates that the encapsulating layer (300) includes a first inorganic encapsulating layer (310), a second inorganic encapsulating layer (330), and an organic encapsulating layer (320) interposed therebetween.

[0162] The first inorganic sealing layer (310) and the second inorganic sealing layer (330) may include one or more inorganic materials selected from the group consisting of aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride. The first inorganic sealing layer (310) and the second inorganic sealing layer (330) may be a single layer or multiple layers including the aforementioned materials. The organic sealing layer (320) may include a polymer-based material. Examples of the polymer-based material include acrylic resins, epoxy resins, polyimides, and polyethylene. In one embodiment, the organic sealing layer (320) may include acrylate.

[0163] The input sensing layer (400) may be disposed on the encapsulating layer (300). The input sensing layer (400) may include touch electrodes (TE) disposed in the display area (DA) and at least one touch insulating layer. In this regard, FIG. 5 illustrates that the input sensing layer (400) includes a first touch insulating layer (410) on a second inorganic encapsulating layer (330), a first conductive line (420) on the first touch insulating layer (410), a second touch insulating layer (430) on the first conductive line (420), a second conductive line (440) on the second touch insulating layer (430), and a third touch insulating layer (450) on the second conductive line (440).

[0164] The first touch insulating layer (410), the second touch insulating layer (430), and the third touch insulating layer (450) may each include an inorganic insulating material and / or an organic insulating material. As an example, the first touch insulating layer (410) and the second touch insulating layer (430) may include an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride, and the third touch insulating layer (450) may include an organic insulating material. At least one of the first touch insulating layer (410), the second touch insulating layer (430), and the third touch insulating layer (450) may extend from the display area (DA) to the peripheral area (PA).

[0165] The touch electrode (TE) of the input sensing layer (400) may include a structure in which a first conductive wire (420) and a second conductive wire (440) are connected. Alternatively, the touch electrode (TE) may include either the first conductive wire (420) or the second conductive wire (440), in which case the second touch insulating layer (430) may be omitted.

[0166] The first conductive wire (420) and the second conductive wire (440) may each include aluminum (Al), copper (Cu), and / or titanium (Ti), and may be formed as a single layer or multiple layers including the aforementioned materials. For example, the first conductive wire (420) and the second conductive wire (440) may each have a three-layer structure of titanium layer / aluminum layer / titanium layer.

[0167] FIG. 6 is a plan view schematically illustrating a portion of a display device according to one embodiment of the present invention.

[0168] Referring to FIG. 6, a display device according to an embodiment of the present invention may include a display panel (DP). The display panel (DP) may include a main display area (MDA) and a peripheral area (PA) outside the main display area (MDA). Since the components of the display panel (DP) are arranged on a substrate (100), it can be said that the substrate (100) includes the main display area (MDA) and the peripheral area (PA).

[0169] The display panel (DP) can be folded or unfolded around a folding axis (FAX) extending in a first direction (x direction) across the main display area (MDA). The main display area (MDA) can be divided into a first main display area (MDA1) and a second main display area (MDA2) based on the folding axis (FAX). The first main display area (MDA1) and the second main display area (MDA2) can be folded to face each other based on the folding axis (FAX). Alternatively, the first main display area (MDA1) and the second main display area (MDA2) can be folded to face outward, respectively, based on the folding axis (FAX).

[0170] The main display area (MDA) may include a folding area (FA) adjacent to the folding axis (FAX). The folding area (FA) is an area that expands or contracts when the display device is folded or unfolded, and may be a portion of the first main display area (MDA1) and a portion of the second main display area (MDA2). The folding area (FA) may be an area where stress due to deformation of the display panel (DP) is concentrated.

[0171] A sensing wire (SSL) may be arranged in the folding area (FA). The sensing wire (SSL) is arranged adjacent to the folding axis (FAX) and may extend approximately in a first direction (x direction). That is, the sensing wire (SSL) may extend entirely along the first direction (x direction), but may partially extend in another direction to have a meandering shape. In one embodiment, the sensing wire (SSL) may be arranged to overlap the folding axis (FAX) on a plane. The electrical characteristics of the sensing wire (SSL), for example, resistance, may change when the display panel (DP) is folded or unfolded.

[0172] In one embodiment, the sensing wire (SSL) may include a stretchable conductive material whose resistance changes depending on the length of the stretch. The sensing wire (SSL) may include a material having stretchability, conductivity, and linearity. Here, linearity means that when the sensing wire (SSL) is stretched or contracted, the change in the electrical characteristics of the sensing wire (SSL) is proportional to the elongation of the sensing wire (SSL).

[0173] The sensing wire (SSL) may include conductive nanoparticles and an elastomer. The conductive nanoparticles may be reduced graphene oxide (rGO), graphene, carbon nanotubes, metal nanoparticles, metal nanowires, conductive polymer particles, or mixtures thereof. The elastomer may be a silicone-based elastomer such as polydimethylsiloxane, a styrene-based elastomer, an olefin-based elastomer, polyurethane, or a mixture thereof. In one embodiment, the elastomer may be a polymer nanofiber. The polymer nanofiber may include polyurethane, polystyrene-block-poly(ethylene butylene)-block-polystyrene, polystyrene, or polyvinyl chloride. The sensing wire (SSL) may have a composite elastomer structure including a conductive nanoparticle layer and an elastomer layer. The sensing wiring (SSL) may include an elastomer layer mixed with a conductive nanoparticle layer or an elastomer layer coated with conductive nanoparticles.

[0174] In one embodiment, the gauge factor of the sensing wire (SSL) may be about 10 GF to about 1,000 GF. If the gauge factor of the sensing wire (SSL) is less than 10 GF, changes in the electrical characteristics of the sensing wire (SSL) may not be measured when the display panel (DP) is folded or unfolded. If the gauge factor of the sensing wire (SSL) is greater than 1,000 GF, even a slight deformation of the display panel (DP) may cause a large change in the electrical characteristics of the sensing wire (SSL), which may reduce the sensing resolution.

[0175] A first power voltage line (6), a second power voltage line (7), a first voltage line (8), a connection wire (SCL), a data driver (13), and pads (PD) may be arranged in the peripheral area (PA). The first power voltage line (6) may be arranged to extend in the first direction (x direction) from the lower side (-y direction) of the peripheral area (PA) with respect to the main display area (MDA). The second power voltage line (7) may be arranged in the peripheral area (PA) to surround a part of the main display area (MDA). For example, the second power voltage line (7) may have a loop shape with one end open and extending along the boundary of the main display area (MDA). The connection wire (SCL) may extend in the second direction (y direction) along the boundary of the main display area (MDA) and may be arranged on one side of the peripheral area (PA).

[0176] The first voltage line (8) may include a first-first voltage line (8a) and a first-second voltage line (8b). The first-first voltage line (8a) and the first-second voltage line (8b) are respectively arranged on opposite sides of the peripheral area (PA) with the main display area (MDA) therebetween, and may extend in the second direction (y direction). In another embodiment, the first voltage line (8) may be arranged on only one side of the peripheral area (PA). For example, one of the first-first voltage line (8a) and the first-second voltage line (8b) may be omitted. In yet another embodiment, the first voltage line (8) may further include a first-third voltage line connecting the first-first voltage line (8a) and the first-second voltage line (8b). In this case, the first voltage line (8) may have a loop shape with one end open and extending along the boundary of the main display area (MDA).

[0177] A plurality of second voltage lines (VL) are arranged in the main display area (MDA) and can electrically connect the first voltage line (8) and the pixels (P, see FIG. 3). For example, each of the second voltage lines (VL) can extend from the 1-1 voltage line (8a) through the main display area (MDA) to the 1-2 voltage line (8b). The second voltage lines (VL) can be voltage lines that are electrically connected to the pixels (P) arranged in the same row and transmit a DC voltage to each pixel circuit (PC, see FIG. 4c).

[0178] Each of the first power supply voltage line (6), the second power supply voltage line (7), the first voltage line (8), and the connecting wire (SCL) can be electrically connected to a corresponding pad (PD). As described with reference to Fig. 3, the pads (PD) are electrically connected to pads of a flexible film (FFC), and the flexible film (FFC) can be electrically connected to a circuit board (PCB).

[0179] Each of the first power supply voltage line (6), the second power supply voltage line (7), and the first voltage line (8) can be electrically connected to a voltage generation unit (15, see FIG. 2) located on a circuit board (PCB) through a corresponding pad (PD). The first power supply voltage line (6) can receive a first power supply voltage (VDD, see FIG. 2) from the voltage generation unit (15). The second power supply voltage line (7) can receive a second power supply voltage (VSS, see FIG. 2) from the voltage generation unit (15). The first voltage line (8) can receive a DC voltage from the voltage generation unit (15). Here, the DC voltage may be any one of a first initialization voltage (Vint, see FIG. 4b), a second initialization voltage (Vaint, see FIG. 4b), and a sustain voltage (VSUS, see FIG. 4c) supplied to the pixel circuit (PC).

[0180] In one embodiment, the first voltage line (8) may receive the first initialization voltage (Vint) from the voltage generator (15). At this time, the second voltage lines (VL) may be configured to correspond to the first initialization voltage line (VIL1, see FIG. 4b) that transmits the first initialization voltage (Vint) to pixel circuits (PC) located in the same row. In another embodiment, the first voltage line (8) may receive the second initialization voltage (Vaint) from the voltage generator (15). At this time, the second voltage lines (VL) may be the second initialization voltage lines (VIL2, see FIG. 4b) that transmit the second initialization voltage (Vaint) to pixel circuits (PC) located in the same row. In yet another embodiment, the first voltage line (8) may receive the sustain voltage (VSUS) from the voltage generator (15). At this time, the second voltage lines (VL) may be sustain voltage lines (VSL, see Fig. 4c) that transmit sustain voltages (VSUS) to pixel circuits (PC) located in the same row.

[0181] The sensing wire (SSL) may include a first end and a second end. The first end of the sensing wire (SSL) may be electrically connected to a first voltage line (8), and the second end may be electrically connected to a connection wire (SCL). In one embodiment, the first end of the sensing wire (SSL) may be electrically connected to a first-first voltage line (8a) on the left side (-x direction) of the peripheral area (PA) with respect to the main display area (MDA). At this time, the second end of the sensing wire (SSL) may be electrically connected to a connection wire (SCL) located on the right side (+x direction) of the peripheral area (PA). In another embodiment, the first end of the sensing wire (SSL) may be connected to a first-second voltage line (8b) on the right side (+x direction) of the peripheral area (PA) with respect to the main display area (MDA). At this time, the second end of the sensing wire (SSL) may be electrically connected to the connecting wire (SCL) located on the left side (-x direction) of the peripheral area (PA). In another embodiment, the first end of the sensing wire (SSL) may be electrically connected to any one of the second voltage lines (VL) in the main display area (MDA). That is, the sensing wire (SSL) may receive a sensing driving voltage through the first voltage line (8) or the second voltage line (VL) electrically connected to the first voltage line (8).

[0182] The connecting wire (SCL) can be electrically connected to a sensing circuit (FSC, see Fig. 3) via a corresponding pad (PD). The sensing circuit (FSC) can be configured to measure changes in electrical characteristics of the sensing wire (SSL), detect a folding state of the display panel (DP), and generate a display control signal for controlling pixels (P) based on the detected folding state.

[0183] The sensing circuit (FSC) can be configured to compare the measured voltage of the sensing wire (SSL) with a reference voltage to detect the folding state of the display panel (DP) and generate a display control signal that controls the pixels (P) according to the folding state of the display panel (DP).

[0184] Since the sensing wire (SSL) receives the sensing drive voltage from the first voltage line (8) that transmits the DC voltage to the pixel (P), separate wiring and circuitry for transmitting the sensing drive voltage to the sensing wire (SSL) can be omitted. Accordingly, the area required by the folding detection sensor for detecting the folding state of the display panel (DP) can be reduced. In addition, by simplifying the structure of the folding detection sensor, the manufacturing cost can be reduced.

[0185] FIG. 7a and FIG. 7b are each a plan view schematically illustrating a portion of a display device according to one embodiment of the present invention.

[0186] The display device illustrated in Fig. 7a is similar to that illustrated in Fig. 6, but differs in that it further includes third voltage lines (VLa). The display device illustrated in Fig. 7b is similar to that illustrated in Fig. 6, but differs in that the sensing wire (SSL) is electrically connected to the second power voltage line (7). Below, descriptions of identical or similar components will be omitted, and the differences will be primarily described.

[0187] Referring to FIG. 7A, a display device may include a display panel (DP). The display panel (DP) may extend in a second direction (y direction) and may further include a plurality of third voltage lines (VLa) arranged in a main display area (MDA). In the main display area (MDA), the second voltage lines (VL) and the third voltage lines (VLa) may intersect each other to form a mesh structure. In the main display area (MDA), the second voltage lines (VL) and the third voltage lines (VLa) may be electrically connected to each other to prevent or reduce a voltage drop of a DC voltage.

[0188] A first end of the sensing wire (SSL) may be electrically connected to a first voltage line (8), and a second end may be electrically connected to a connecting wire (SCL). The first end of the sensing wire (SSL) may be electrically connected to a first-first voltage line (8a) on the left side (-x direction) of the peripheral area (PA) with respect to the main display area (MDA). The second end of the sensing wire (SSL) may be electrically connected to a connecting wire (SCL) located on the right side (+x direction) of the peripheral area (PA). In another embodiment, the first end of the sensing wire (SSL) may be electrically connected to a second voltage line (VL) or a third voltage line (VLa) in the main display area (MDA).

[0189] That is, the sensing wiring (SSL) can be supplied with a sensing driving voltage through the first voltage line (8), the second voltage line (VL), or the third voltage line (VLa). As described above, the sensing driving voltage can be any one of the first initialization voltage (Vint, see Fig. 4b), the second initialization voltage (Vaint, see Fig. 4b), and the sustain voltage (VSUS, see Fig. 4c).

[0190] Referring to FIG. 7b, the display panel (DP) may further include second power lines (VSSL) extending in a first direction (x direction) from the main display area (MDA) and first auxiliary power lines (VSSLa) extending in a second direction (y direction) from the main display area (MDA). In the main display area (MDA), the second power lines (VSSL) and the first auxiliary power lines (VSSLa) may intersect each other to form a mesh structure. In the main display area (MDA), the second power lines (VSSL) and the first auxiliary power lines (VSSLa) may be electrically connected, and the second power lines (VSSL) or the first auxiliary power lines (VSSLa) may be electrically connected to a counter electrode (223, see FIG. 5) of a display element (ED, see FIG. 4a). The mesh structure formed by the second power lines (VSSL) and the first auxiliary power line (VSSLa) can prevent or reduce the voltage drop of the second power voltage (VSS, see FIG. 2).

[0191] A first end of the sensing wire (SSL) may be electrically connected to a second power voltage line (7), and a second end may be electrically connected to a connection wire (SCL). In another embodiment, the first end of the sensing wire (SSL) may be electrically connected to a second power line (VSSL) or a first auxiliary power line (VSSLa) in the main display area (MDA). A second end of the sensing wire (SSL) may be electrically connected to a connection wire (SCL) located in a peripheral area (PA). The sensing wire (SSL) may receive a sensing driving voltage through the second power voltage line (7), the second power line (VSSL), or the first auxiliary power line (VSSLa). At this time, the sensing driving voltage transmitted to the sensing wire (SSL) may be a second power voltage (VSS, see FIG. 2).

[0192] In another embodiment, a first end of the sensing wire (SSL) may be electrically connected to a first power voltage line (6) or a first power line (PL, see FIG. 2), and a second end of the sensing wire (SSL) may be electrically connected to a connection wire (SCL). In this case, the sensing driving voltage transmitted to the sensing wire (SSL) may be a first power voltage (VDD, see FIG. 2).

[0193] FIG. 8 is a plan view schematically illustrating a portion of a display device according to one embodiment of the present invention.

[0194] Referring to FIG. 8, a display device may include a display panel (DP). The display panel (DP) may be folded or unfolded around a folding axis (FAX) extending in a second direction (y direction) across a main display area (MDA). The main display area (MDA) may be divided into a first main display area (MDA1) and a second main display area (MDA2) based on the folding axis (FAX). The first main display area (MDA1) may be located to the left (-x direction) based on the folding axis (FAX), and the second main display area (MDA2) may be located to the right (+x direction) based on the folding axis (FAX). The first main display area (MDA1) and the second main display area (MDA2) may be folded to face each other based on the folding axis (FAX). Alternatively, the first main display area (MDA1) and the second main display area (MDA2) can be folded to face outward based on the folding axis (FAX).

[0195] The main display area (MDA) may include a folding area (FA) adjacent to the folding axis (FAX). The folding area (FA) is an area that expands or contracts when the display device is folded or unfolded, and may be a portion of the first main display area (MDA1) and a portion of the second main display area (MDA2). The folding area (FA) may extend in the second direction (y direction).

[0196] The first voltage line (8) may include a first-first voltage line (8a), a first-second voltage line (8b), and a first-third voltage line (8c) connecting the first-first voltage line (8a) and the first-second voltage line (8b), which are arranged on both sides of the peripheral area (PA) with the main display area (MDA) in between. The first-first voltage line (8a) may extend in the second direction (y direction) from the left side (-x direction) of the peripheral area (PA), the first-second voltage line (8b) may extend in the second direction (y direction) from the right side (+x direction) of the peripheral area (PA), and the first-third voltage line (8c) may extend in the first direction (x direction) from the upper side (+y direction) of the peripheral area (PA). That is, the first voltage line (8) may have a loop shape with one end open, which extends along the boundary of the main display area (MDA).

[0197] A plurality of second voltage lines (VL) are arranged in the main display area (MDA) and can electrically connect the first voltage line (8) and the pixels (P, see FIG. 3). For example, each of the second voltage lines (VL) can extend from the 1-1 voltage line (8a) through the main display area (MDA) to the 1-2 voltage line (8b). The second voltage lines (VL) can be voltage lines that are electrically connected to the pixels (P) arranged in the same row and transmit a DC voltage to each pixel circuit (PC, see FIG. 4c).

[0198] The sensing wire (SSL) may be arranged in the folding area (FA). The sensing wire (SSL) may be arranged adjacent to the folding axis (FAX) and may extend in a second direction (y direction) approximately parallel to the folding axis (FAX). In one embodiment, the sensing wire (SSL) may be arranged to overlap the folding axis (FAX) on a plane. The electrical characteristics, for example, resistance, of the sensing wire (SSL) may change when the display panel (DP) is folded or unfolded.

[0199] The sensing wire (SSL) may include a first end and a second end. The first end of the sensing wire (SSL) may be electrically connected to a first voltage line (8), and the second end may be electrically connected to a connection wire (SCL). In one embodiment, the first end of the sensing wire (SSL) may be electrically connected to a first-third voltage line (8c) at an upper side (+y direction) of a peripheral area (PA) with respect to the main display area (MDA). At this time, the second end of the sensing wire (SSL) may be electrically connected to a connection wire (SCL) located at a lower side (-y direction) of the peripheral area (PA). In another embodiment, the first end of the sensing wire (SSL) may be electrically connected to any one of the second voltage lines (VL) in the main display area (MDA). That is, the sensing wiring (SSL) can receive a sensing driving voltage through the first voltage line (8) or the second voltage line (VL) electrically connected to the first voltage line (8).

[0200] Fig. 8 illustrates that the sensing wire (SSL) is electrically connected to the first voltage line (8), but the present invention is not limited thereto. The first end of the sensing wire (SSL) may be electrically connected to the first power voltage line (6, see Fig. 3) or the second power voltage line (7, see Fig. 3).

[0201] FIGS. 9A, 9B, and 9C are each a plan view schematically illustrating a portion of a sensing line according to one embodiment of the present invention. FIGS. 9A, 9B, and 9C are each an enlarged view of area B of FIG. 6.

[0202] Referring to Fig. 9a, the sensing wire (SSL) may have a meandering shape on a plane. The sensing wire (SSL) may have an approximate "S" shape. For example, the sensing wire (SSL) may include two round portions (RP) and a connecting portion (SP) connecting the two round portions (RP). Each of the two round portions (RP) may have an approximate arc shape. The connecting portion (SP) may have an approximate straight shape. In Fig. 9a, the connecting portion (SP) extends in a direction orthogonal to the extension direction of the folding axis (FAX), but the present invention is not limited thereto. The connecting portion (SP) may also extend in a direction oblique to the extension direction of the folding axis (FAX).

[0203] Referring to FIG. 9B, the sensing wire (SSL) may include horizontal wires extending in a direction parallel to the extension direction of the folding axis (FAX) and vertical wires extending in a direction orthogonal to the extension direction of the folding axis (FAX). The horizontal wires and the vertical wires are arranged alternately, so that the sensing wire (SSL) may have an approximately rectangular wave shape on a plane. In other embodiments, the sensing wire (SSL) may have various shapes, such as a sine wave shape or a triangular wave shape, on a plane.

[0204] Referring to FIG. 9c, the sensing wiring (SSL) may include wiring portions (LP) extending along the folding axis (FAX) and pattern portions (PT) arranged between the wiring portions (LP). In one embodiment, the pattern portion (PT) may have an approximately rectangular shape in a plan view. In this case, the wiring portion (LP) may have a first width (w1) in a direction perpendicular to the extension direction of the folding axis (FAX), and the pattern portion (PT) may have a second width (w2) greater than the first width (w1) in a direction perpendicular to the extension direction of the folding axis (FAX). In a plan view, the pattern portion (PT) may have another polygonal, circular, elliptical, or irregular shape.

[0205] In one embodiment, the pattern portion (PT) may have a meandering shape on a plane. For example, the sensing wire (SSL) may have a meandering pattern portion (PT) between linear wire portions (LP). Accordingly, the sensing wire (SSL) may have a partially meandering shape.

[0206] FIGS. 10A, 10B, and 10C are each a cross-sectional view schematically illustrating a portion of a display device according to one embodiment of the present invention.

[0207] Referring to FIGS. 10A, 10B, and 10C, a display panel of a display device (50) may include a substrate (100), a display layer (200), an encapsulation layer (300), and an input sensing layer (400). The display layer (200) may include a pixel circuit (PC) arranged in a display area (DA) and a display element (ED) electrically connected to the pixel circuit (PC).

[0208] A display layer (200) may be disposed on a substrate (100). The display layer (200) includes a buffer layer (201), and a pixel circuit (PC) may be disposed on the buffer layer (201). The pixel circuit (PC) may include a first transistor (T1) and a third transistor (T3). The first transistor (T1) may be a silicon-based semiconductor thin film transistor including a silicon-based semiconductor layer, and the third transistor (T3) may be an oxide-based semiconductor thin film transistor including an oxide-based semiconductor layer.

[0209] A display element (ED) electrically connected to the pixel circuit (PC) may be arranged on the pixel circuit (PC). The display element (ED) may be an organic light-emitting diode including a pixel electrode (221), a counter electrode (223), and an intermediate layer (222) arranged between the pixel electrode (221) and the counter electrode (223).

[0210] The display layer (200) may include a plurality of insulating layers, for example, a first gate insulating layer (203), a first interlayer insulating layer (205), a second interlayer insulating layer (207), a second gate insulating layer (209), a third interlayer insulating layer (210), a first organic insulating layer (211), a second organic insulating layer (212), a third organic insulating layer (213), and a bank layer (215). Conductive layers may be arranged between the plurality of insulating layers. A first conductive layer including a gate electrode of a first transistor (T1) may be disposed between the first gate insulating layer (203) and the first interlayer insulating layer (205), a second conductive layer including a lower gate electrode (G3A, see FIG. 5) of a third transistor (T3) may be disposed between the first interlayer insulating layer (205) and the second interlayer insulating layer (207), and a third conductive layer including an upper gate electrode (G3B, see FIG. 5) of a third transistor (T3) may be disposed between the second gate insulating layer (209) and the third interlayer insulating layer (210). A fourth conductive layer, a fifth conductive layer, and a sixth conductive layer including connection electrodes and wirings may be disposed between the third interlayer insulating layer (210) and the first organic insulating layer (211), between the first organic insulating layer (211) and the second organic insulating layer (212), and between the second organic insulating layer (212) and the third organic insulating layer (213). A seventh conductive layer including a pixel electrode (221) may be disposed between the third organic insulating layer (213) and the bank layer (215).

[0211] The second voltage line (VL) may be included in any one of the conductive layers included in the display layer (200). In this regard, FIGS. 10A to 10C illustrate that the second voltage line (VL) is included in the fourth conductive layer disposed between the third interlayer insulating layer (210) and the first organic insulating layer (211), but the present invention is not limited thereto. The position of the second voltage line (VL) may vary depending on the design of the pixel circuit (PC).

[0212] The sensing wire (SSL) may be arranged adjacent to the folding axis (FAX). The sensing wire (SSL) may be arranged to overlap the folding axis (FAX) on a plane. In one embodiment, the sensing wire (SSL) may be arranged on the display layer (200), but may be arranged in a different layer from the second voltage line (VL). In this regard, FIG. 10A illustrates that the second voltage line (VL) is arranged between the third interlayer insulating layer (210) and the first organic insulating layer (211), and the sensing wire (SSL) is arranged between the first organic insulating layer (211) and the second organic insulating layer (212), but the present invention is not limited thereto.

[0213] In one embodiment, the sensing wire (SSL) may be arranged on the same layer as the second voltage line (VL). For example, as illustrated in FIG. 10b, the sensing wire (SSL) and the second voltage line (VL) may be arranged between the third interlayer insulating layer (210) and the first organic insulating layer (211). In this way, the sensing wire (SSL) is arranged on the display layer (200), but the design may be varied as needed.

[0214] In one embodiment, the sensing wire (SSL) may be disposed between the encapsulation layer (300) and the input detection layer (400). For example, as illustrated in FIG. 10c, the sensing wire (SSL) may be disposed between the second inorganic encapsulation layer (330) and the first touch insulating layer (410). In another embodiment, the sensing wire (SSL) may be disposed between the first touch insulating layer (410) and the second touch insulating layer (430), or between the second touch insulating layer (430) and the third touch insulating layer (450).

[0215] FIG. 11 is a diagram schematically showing a sensing circuit included in a display device according to one embodiment of the present invention.

[0216] Referring to FIG. 11, a display device (50) may include a display panel (DP) and a sensing circuit (FSC). A first voltage line (8) and a sensing wire (SSL) may be arranged on the display panel (DP). The first voltage line (8) may be an external voltage line that transmits a first voltage (V1) to pixels (P, see FIG. 3). The first voltage (V1) may be a sensing driving voltage and may be a DC voltage supplied to the pixel circuit. For example, the first voltage (V1) may be a first initialization voltage (Vint, see FIG. 4b), a second initialization voltage (Vaint, see FIG. 4b), a sustain voltage (VSUS, see FIG. 4c), etc.

[0217] The sensing wire (SSL) can be electrically connected to the first voltage line (8) and the sensing circuit (FSC). A first end of the sensing wire (SSL) can be electrically connected to the first voltage line (8), and a second end can be electrically connected to the sensing circuit (FSC) via a connection wire (SCL, see FIG. 6). In one embodiment, the first end of the sensing wire (SSL) can be electrically connected to a first power voltage line (6, see FIG. 6) or a second power voltage line (7, see FIG. 6), and a second end can be electrically connected to the sensing circuit (FSC) via the connection wire (SCL).

[0218] The sensing circuit (FSC) may include a switch unit (71), a comparator (73), a sensing controller (75, first controller), a compensation controller (77, second controller), and a memory (79).

[0219] The switch unit (71) can selectively electrically connect the sensing wire (SSL) and the comparator (73) according to the switch control signal (SCs). The switch unit (71) can electrically connect the sensing wire (SSL) and the comparator (73) during a period in which the switch control signal (SCs) is supplied with an on voltage (hereinafter, an on voltage period), and the switch unit (71) can electrically separate the sensing wire (SSL) and the comparator (73) during a period in which the switch control signal (SCs) is supplied with an off voltage (hereinafter, an off voltage period). The sensing wire (SSL) electrically separated from the comparator (73) can be maintained in a floating state. In one embodiment, the switch unit (71) can electrically connect the sensing wire (SSL) and the comparator (73) during a vertical blank time, which is an on voltage period of a vertical synchronization signal (Vsync, see FIG. 2). The sensing circuit (FSC) measures the measurement voltage (Vsen) of the sensing wire (SSL) only during the vertical blank period, thereby minimizing noise caused by driving pixels and enabling more accurate detection of the folding state.

[0220] The comparator (73) may include a first input terminal, a second input terminal, and an output terminal. The first input terminal of the comparator (73) may receive a reference voltage (Vref) from a voltage generation unit (15, see FIG. 2), and the second input terminal may receive a measurement voltage (Vsen) from the sensing wire (SSL) when the switch unit (71) electrically connects the sensing wire (SSL) and the comparator (73). The comparator (73) may compare the reference voltage (Vref) and the measurement voltage (Vsen) and output an output value corresponding to a larger voltage between the two voltages to the output terminal. For example, the comparator (73) may output a first value to the sensing controller (75) when the measurement voltage (Vsen) is less than or equal to the reference voltage (Vref), and may output a second value to the sensing controller (75) when the measurement voltage (Vsen) is greater than the reference voltage (Vref).

[0221] Here, the reference voltage (Vref) is the measurement voltage (Vsen) of the sensing wire (SSL) at the point where the display panel (DP) is folded or unfolded, and the image displayed to the user needs to be rearranged or the color coordinates or brightness of the pixels need to be compensated. The value may be measured in advance during the manufacturing process and stored in the memory (79).

[0222] The sensing controller (75) can be configured to detect the folding state of the display panel (DP) based on the output value of the comparator (73) and generate sensing data (SCD) including the folding state. For example, when the output value of the comparator (73) is a first value, the sensing controller (75) can determine that the folding state of the display panel (DP) is a folded state and generate sensing data (SCD) including the same. When the output value of the comparator (73) is a second value, the sensing controller (75) can determine that the folding state of the display panel (DP) is an unfolded state and generate sensing data (SCD) including the same. The sensing controller (75) can determine that the folding state of the display panel (DP) has changed when the output value of the comparator (73) changes, for example, from a first value to a second value or from the second value to a first value.

[0223] The memory (79) can store lookup tables for compensating the color coordinates or brightness of pixels according to the reference voltage (Vref) and the folding state of the display panel (DP). The memory (79) can store the measured voltage (Vsen) value for a certain period of time.

[0224] In one embodiment, the folding state may be divided into several stages depending on the angle at which the display panel (DP) is folded. In this case, a plurality of reference voltages (Vref) corresponding to each stage of the folding state may be stored in the memory (79). The sensing controller (75) may output a voltage control signal (STs) configured to change the stage of the folding state when the comparator (73) outputs a first value, and cause the voltage generator (15) to output the reference voltage (Vref) corresponding to the stage. The voltage generator (15) may change the reference voltage (Vref) according to the voltage control signal (STs). In one embodiment, the sensing controller (75) may detect the operating state of the display panel (DP) based on a change in the value of the measured voltage (Vsen) to determine whether the display panel (DP) is unfolded or folded. In addition, the sensing controller (75) may detect a folding speed at which the display panel (DP) is unfolded or folded based on a change in the value of the measured voltage (Vsen) over a predetermined period of time. The sensing data (SCD) may include the operating status and / or folding speed of the display panel (DP).

[0225] The compensation controller (77) can be configured to generate display control signals (FCs) based on sensing data (SCD) and a lookup table stored in memory (79).

[0226] The display control signals (FCs) may include image control signals configured to rearrange images displayed by pixels according to the folding state of the display panel (DP). For example, when the display panel (DP) is fully unfolded, the images may be rearranged so that one image is displayed to extend across the entire first main display area (MDA1, see FIG. 1C) and the second main display area (MDA2, see FIG. 1C). When the display panel (DP) is out-folded, the images may be rearranged so that the first main display area (MDA1) and the second main display area (MDA2) display different screens. When the display panel (DP) is fully in-folded, the main display area (MDA) may not display an image, and the image may be displayed in the sub display area (SDA, see FIG. 1B).

[0227] The display control signals (FCs) may include image quality control signals configured to compensate for color coordinates and / or luminance of pixels according to the folding state of the display panel (DP). For example, when the display panel (DP) is out-folded, the folding area (FA, see FIG. 6) may increase and the color coordinates and / or luminance of pixels located in the folding area (FA) may change. The compensation controller (77) compensates for the color coordinates and / or luminance of pixels based on the sensing data (SCD) and the lookup table, so that the display device (50) can display a high-quality image.

[0228] The display device (50) may further include a mechanism for folding or unfolding the display panel (DP). In this case, the compensation controller (77) may be configured to generate a mechanism control signal for controlling the mechanism based on sensing data (SCD). For example, even when a user applies a small amount of force to fold or unfold the display device (50), the mechanism may completely fold or unfold the display panel (DP) according to the mechanism control signal.

[0229] Since the comparator (73) quickly compares the two input voltages and outputs the result, the sensing circuit (FSC) can quickly determine the folding state of the display panel (DP) using the output value of the comparator (73), and can rearrange the image or compensate for the color coordinates and / or brightness of the pixels according to the folding state.

[0230] Figure 12 is a schematic diagram illustrating a method for driving a display device according to one embodiment of the present invention. While Figure 12 illustrates various steps (or operations) of the method for driving a display device, the present invention is not limited thereto. According to some embodiments of the present invention, the method for driving a display device may further include additional dynamics within the technical scope of the present invention.

[0231] FIG. 13 is a timing diagram for explaining the operation timing of a vertical synchronization signal and a sensing control signal according to one embodiment of the present invention.

[0232] Referring to FIGS. 11 and 12 together, a method of driving a display device may include a voltage sensing step (S101), a voltage comparison step (S102), an image quality control step (S103), and an image control step (S104).

[0233] In the voltage sensing step (S101), the switch unit (71) can selectively electrically connect the sensing wire (SSL) and the comparator (73) according to the switch control signal (SCs). During the on voltage period of the switch control signal (SCs), the switch unit (71) can electrically connect the sensing wire (SSL) and the comparator (73), and during the off voltage period of the switch control signal (SCs), the switch unit (71) can electrically separate the sensing wire (SSL) and the comparator (73). The sensing wire (SSL) electrically separated from the comparator (73) can be maintained in a floating state.

[0234] Referring to Fig. 13, the on-voltage period of the switch control signal (SCs) may overlap with the on-voltage period of the vertical synchronization signal (Vsync). As described above, the vertical synchronization signal (Vsync) is a reference signal indicating the start or end of a frame. The data enable signal (DE) is a signal indicating a section where there is actual valid image data within one line time.

[0235] The first period (t1) is the on-voltage period of the vertical synchronization signal (Vsync), which can be expressed as a vertical blank period, which is a period during which there is no on-voltage pulse of the data enable signal (DE). The second period (t2) is the off-voltage period of the vertical synchronization signal (Vsync), which can be expressed as a display active time, which is a period during which the on-voltage pulse of the data enable signal (DE) is output at a predetermined interval (e.g., a preset interval).

[0236] The third period (t3) may overlap with the first period (t1) as the on-voltage period of the switch control signal (SCs). That is, the sensing circuit (FSC) may measure the measurement voltage (Vsen) of the sensing wire (SSL) during the vertical blank period. During the second period (t2), the transistors of the pixel circuit (PC, see FIGS. 4A to 4C) may be electrically connected to the second voltage line (VL, see FIG. 6). Therefore, the voltage of the sensing wire (SSL) may change during the second period (t2). The sensing circuit (FSC) may measure the measurement voltage (Vsen) of the sensing wire (SSL) only during the vertical blank period, thereby minimizing or reducing noise caused by driving of pixels and detecting the folding state more accurately.

[0237] In the voltage comparison step (S102), the sensing circuit (FSC) compares the measured voltage (Vsen) with the reference voltage (Vref), and if the measured voltage (Vsen) is smaller or larger than the reference voltage (Vref), the sensing circuit (FSC) determines that the folding state of the display panel (DP) is a folded state, and if the measured voltage (Vsen) is larger than the reference voltage (Vref), the sensing circuit (FSC) can determine that the folding state of the display panel (DP) is an unfolded state. The sensing circuit (FSC) can detect the folding speed, the operating state, etc. based on the change in the measured voltage (Vsen) value. If the folding state of the display panel (DP) changes, the sensing circuit (FSC) can perform the image quality control step (S103) and / or the image control step (S104), and if the folding state of the display panel (DP) does not change and is maintained, the voltage sensing step (S101) can be repeatedly performed.

[0238] In the image quality control step (S103), the sensing circuit (FSC) can generate an image quality control signal configured to compensate for the color coordinates and / or luminance of pixels based on the folding state and the lookup table stored in the memory, and transmit the signal to the display driving circuit (DDV, see FIG. 2).

[0239] In the image control step (S104), the sensing circuit (FSC) can generate an image control signal configured to rearrange the image displayed by the pixels based on the folding state, and transmit the signal to the display driving circuit (DDV). Depending on the folding state, the image quality control step (S103) and the image control step (S104) can be performed simultaneously or sequentially. Depending on the folding state, either the image quality control step (S103) or the image control step (S104) can be omitted.

[0240] FIG. 14 is a drawing schematically illustrating a folding state of a display device and a measurement voltage of a sensing line according to one embodiment of the present invention.

[0241] Referring to FIGS. 11 and 14 together, a first voltage (V1) may be supplied to a first voltage line (8) electrically connected to a sensing wire (SSL). The first voltage (V1) may be a sensing driving voltage and may be a voltage supplied to a pixel circuit (PC, see FIGS. 4b and 4c). The first voltage (V1) may be a first initialization voltage (Vint, see FIG. 4b), a second initialization voltage (Vaint, see FIG. 4b), a sustain voltage (VSUS, see FIG. 4c), etc. The first voltage (V1) may be maintained at a constant value while the measurement voltage (Vsen) of the sensing wire (SSL) is measured.

[0242] When the display panel (DP) is fully unfolded, the measured voltage (Vsen) may have a voltage value slightly lower than the first voltage (V1). As the display panel (DP) is folded, the measured voltage (Vsen) of the sensing wire (SSL) decreases, and when the display panel (DP) is fully folded, the measured voltage (Vsen) of the sensing wire (SSL) may have the lowest value. As the display panel (DP) is unfolded from the folded state, the measured voltage (Vsen) of the sensing wire (SSL) may increase again.

[0243] The reference voltage (Vref) is the measurement voltage (Vsen) of the sensing wire (SSL) at the point when the display panel (DP) is folded or unfolded, requiring rearrangement of the image displayed to the user or compensation for the color coordinates or brightness of the pixels. Its value may be measured and determined in advance during the manufacturing process. The reference voltage (Vref) may be equal to or greater than the lowest value of the measurement voltage (Vsen), and less than the highest value of the measurement voltage (Vsen).

[0244] In one embodiment, the folding state of the display panel (DP) may be divided into several stages depending on the folding angle. In this case, the reference voltage (Vref) value may be stored in memory for each stage of the folding state, and the sensing circuit (FSC) may change the reference voltage (Vref) for comparison with the measurement voltage (Vsen) for each stage. The sensing circuit (FSC) may detect the folding state of the display panel (DP) by comparing the measurement voltage (Vsen) of the sensing wire (SSL) with the reference voltage (Vref) for each stage.

[0245] FIGS. 15A and 15B are perspective views schematically illustrating an electronic device according to one embodiment of the present invention, respectively, and FIG. 16 is a plan view schematically illustrating a display device according to one embodiment of the present invention.

[0246] Referring to FIGS. 15A and 15B, an electronic device (1B) according to an embodiment of the present invention may include a display device (50) and a housing (90). The display device (50) may include a display area (DA) where an image is displayed and a peripheral area (PA) disposed around the display area (DA). Pixels having display elements may be disposed in the display area (DA). The display device (50) may provide an image using light emitted from pixels disposed in the display area (DA). The peripheral area (PA) may be a type of non-display area where no pixels are disposed.

[0247] A housing (90) can form the exterior of an electronic device (1B). The housing (90) can include a first portion (91), a second portion (92), and a third portion (93) that support a display device (50). The housing (90) can have a first hinge (HG1) between the first portion (91) and the second portion (92), and a second hinge (HG2) between the second portion (92) and the third portion (93). The electronic device (1B) can be folded or unfolded near the first hinge (HG1) and the second hinge (HG2).

[0248] For example, the display area (DA) may include a first display area (DA1) located in a first part (91) of the housing (90), a second display area (DA2) located in a second part (92) of the housing (90), and a third display area (DA3) located in a third part (93) of the housing (90). A first folding axis (FAX1) overlapping with a first hinge (HG1) may be located between the first display area (DA1) and the second display area (DA2), and a second folding axis (FAX2) overlapping with a second hinge (HG2) may be located between the second display area (DA2) and the third display area (DA3). The display device (50) may be folded or unfolded based on the first folding axis (FAX1) and the second folding axis (FAX2).

[0249] As illustrated in FIG. 15B, the first display area (DA1) and the second display area (DA2) can be folded to face each other based on the first folding axis (FAX1), and the second display area (DA2) and the third display area (DA3) can be folded to face outward based on the second folding axis (FAX2). The display area (DA) may include a first folding area (FA1) adjacent to the first folding axis (FAX1) and a second folding area (FA2) adjacent to the second folding axis (FAX2). The first folding area (FA1) and the second folding area (FA2) are areas that expand or contract when the electronic device (1B) is folded or unfolded, and may be areas where stress due to deformation of the display device (50) is concentrated.

[0250] As illustrated in Fig. 15b, when the electronic device (1B) is in a fully folded state, the user can only use the third display area (DA3) located on the outside. In this case, the electronic device (1B) can display an image only in the third display area (DA3) without displaying an image in the first display area (DA1) and the second display area (DA2). As illustrated in Fig. 15a, when the electronic device (1B) is in a fully unfolded state, an image can be displayed by extending it over the entire first display area (DA1), the second display area (DA2), and the third display area (DA3). The electronic device (1B) can detect a change in the folding state and automatically control the image.

[0251] Referring to FIG. 16, a display device according to one embodiment of the present invention may include a display panel (DP). The display panel (DP) may include a display area (DA) and a peripheral area (PA) outside the display area (DA).

[0252] The display panel (DP) can be folded or unfolded about a first folding axis (FAX1) and a second folding axis (FAX2) extending in a first direction (x direction) across the display area (DA). The display area (DA) can be divided into a first display area (DA1), a second display area (DA2), and a third display area (DA3) by the first folding axis (FAX1) and the second folding axis (FAX2). The first display area (DA1) and the second display area (DA2) can be folded to face each other based on the first folding axis (FAX1), and the second display area (DA2) and the third display area (DA3) can be folded to face outward based on the second folding axis (FAX2).

[0253] The display area (DA) may include a first folding area (FA1) adjacent to the first folding axis (FAX1) and a second folding area (FA2) adjacent to the second folding axis (FAX2). The first folding area (FA1) is an area that expands or contracts when the display device is folded or unfolded around the first folding axis (FAX1), and may be a part of the first display area (DA1) and a part of the second display area (DA2). The second folding area (FA2) is an area that expands or contracts when the display device is folded or unfolded around the second folding axis (FAX2), and may be a part of the second display area (DA2) and a part of the third display area (DA3). The first folding area (FA1) and the second folding area (FA2) may be areas where stress due to deformation of the display panel (DP) is concentrated.

[0254] A first sensing wire (SSL1) may be arranged in a first folding area (FA1), and a second sensing wire (SSL2) may be arranged in a second folding area (FA2). The first sensing wire (SSL1) may be arranged adjacent to a first folding axis (FAX1) and may extend in a direction parallel to the first folding axis (FAX1). The second sensing wire (SSL2) may be arranged adjacent to a second folding axis (FAX2) and may extend in a direction parallel to the second folding axis (FAX2). Each of the first sensing wire (SSL1) and the second sensing wire (SSL2) may extend entirely along the first direction (x direction), but may partially extend in another direction to have a winding shape. In one embodiment, the first sensing wire (SSL1) may be arranged to overlap the first folding axis (FAX1) on a plane, and the second sensing wire (SSL2) may be arranged to overlap the second folding axis (FAX2) on a plane.

[0255] The electrical characteristics, such as resistance, of the first sensing wire (SSL1) may change when the display panel (DP) is folded or unfolded around the first folding axis (FAX1). The electrical characteristics of the second sensing wire (SSL2) may change when the display panel (DP) is folded or unfolded around the second folding axis (FAX2).

[0256] In one embodiment, each of the first sensing wire (SSL1) and the second sensing wire (SSL2) may include a conductive material that is stretchable and whose resistance changes depending on the stretching length. Each of the first sensing wire (SSL1) and the second sensing wire (SSL2) may include a material having stretchability, conductivity, and linearity. Each of the first sensing wire (SSL1) and the second sensing wire (SSL2) may include conductive nanoparticles and an elastomer. In one embodiment, the gauge factor of each of the first sensing wire (SSL1) and the second sensing wire (SSL2) may be about 10 GF to about 1,000 GF.

[0257] A first power voltage line (6), a second power voltage line (7), a first voltage line (8), a connection wire (SCL), a data driver (13), and pads (PD) may be arranged in the peripheral area (PA). The first power voltage line (6) may be arranged to extend in the first direction (x direction) from the lower side (-y direction) of the peripheral area (PA) with respect to the main display area (MDA). The second power voltage line (7) may be arranged in the peripheral area (PA) to surround a part of the main display area (MDA). For example, the second power voltage line (7) may have a loop shape with one end open and extending along the boundary of the main display area (MDA). The connection wire (SCL) may extend in the second direction (y direction) along the boundary of the main display area (MDA) and may be arranged on one side of the peripheral area (PA).

[0258] The first voltage line (8) may include a first-first voltage line (8a) and a first-second voltage line (8b). The first-first voltage line (8a) and the first-second voltage line (8b) are respectively arranged on both sides of the peripheral area (PA) with the main display area (MDA) therebetween, and may extend in the second direction (y direction). In one embodiment, one of the first-first voltage line (8a) and the first-second voltage line (8b) may be omitted. In another embodiment, the first voltage line (8) may further include a first-third voltage line connecting the first-first voltage line (8a) and the first-second voltage line (8b).

[0259] A plurality of second voltage lines (VL) are arranged in the main display area (MDA) and can electrically connect the first voltage line (8) and the pixels (P, see Fig. 3). The second voltage lines (VL) can be voltage lines that are electrically connected to the pixels (P) arranged in the same row and transmit a DC voltage to each pixel circuit (PC, see Fig. 4c).

[0260] Each of the first power supply voltage line (6), the second power supply voltage line (7), and the first voltage line (8) can be electrically connected to a voltage generation unit (15, see FIG. 2) located on a circuit board (PCB) through a corresponding pad (PD). The first power supply voltage line (6) can receive a first power supply voltage (VDD, see FIG. 2) from the voltage generation unit (15). The second power supply voltage line (7) can receive a second power supply voltage (VSS, see FIG. 2) from the voltage generation unit (15). The first voltage line (8) can receive a DC voltage from the voltage generation unit (15). Here, the DC voltage may be any one of a first initialization voltage (Vint, see FIG. 4b), a second initialization voltage (Vaint, see FIG. 4b), and a sustain voltage (VSUS, see FIG. 4c) supplied to the pixel circuit (PC).

[0261] Each of the first sensing wire (SSL1) and the second sensing wire (SSL2) may include a first end and a second end. The first end of each of the first sensing wire (SSL1) and the second sensing wire (SSL2) may be electrically connected to the first voltage line (8). The second end of the first sensing wire (SSL1) may be electrically connected to the first connection wire (SCL1), and the second end of the second sensing wire (SSL2) may be electrically connected to the second connection wire (SCL2).

[0262] In another embodiment, the first end of each of the first sensing wire (SSL1) and the second sensing wire (SSL2) may be electrically connected to one of the second voltage lines (VL) in the display area (DA). That is, each of the first sensing wire (SSL1) and the second sensing wire (SSL2) may receive a sensing driving voltage through the first voltage line (8) or the second voltage line (VL) electrically connected to the first voltage line (8).

[0263] Each of the first connection wire (SCL1) and the second connection wire (SCL2) may be electrically connected to a sensing circuit (FSC, see FIG. 3) via a corresponding pad (PD). The sensing circuit (FSC) may be configured to measure changes in electrical characteristics of each of the first sensing wire (SSL1) and the second sensing wire (SSL2), detect a folding state of the display panel (DP), and generate a display control signal for controlling pixels (P) based on the detected folding state.

[0264] The sensing circuit (FSC) may be configured to compare a first measurement voltage of a first sensing wire (SSL1) with a first reference voltage of the first sensing wire (SSL1), and determine that the display panel (DP) is folded about the first folding axis (FAX1) when the first measurement voltage is equal to or less than the first reference voltage. Similarly, the sensing circuit (FSC) may be configured to compare a second measurement voltage of a second sensing wire (SSL2) with a second reference voltage of the second sensing wire (SSL2), and determine that the display panel (DP) is folded about the second folding axis (FAX2) when the second measurement voltage is equal to or less than the second reference voltage.

[0265] Here, the first reference voltage may be a measurement voltage of the first sensing wire (SSL1) at a point in time when the display panel (DP) is folded or unfolded around the first folding axis (FAX1) to rearrange the image displayed to the user or when compensation for the color coordinates or luminance of the pixels is required, and its value may be measured in advance during the manufacturing process and stored in the memory of the sensing circuit (FSC). The second reference voltage may be a measurement voltage of the second sensing wire (SSL2) at a point in time when the display panel (DP) is folded or unfolded around the second folding axis (FAX2) to rearrange the image displayed to the user or when compensation for the color coordinates or luminance of the pixels is required, and its value may be measured in advance during the manufacturing process and stored in the memory of the sensing circuit (FSC). The sensing circuit (FSC) may be configured to generate a display control signal for controlling the pixels according to the folding state of the display panel (DP).

[0266] FIG. 15A, FIG. 15B and FIG. 16 illustrate a case where the electronic device (1B) has two hinges and the display panel (DP) is folded or unfolded about the first folding axis (FAX1) and the second folding axis (FAX2), but the present invention is not limited thereto. The electronic device (1B) has a plurality of hinges, and the display panel (DP) can be folded or unfolded about the plurality of folding axes. In this case, the same number of sensing wires as the number of folding axes of the display panel (DP) may be provided and arranged to overlap each of the folding axes. The sensing circuit (FSC) may compare the measured voltage of each sensing wire with the reference voltage of each sensing wire to detect the folding state of the display panel (DP) and generate a display control signal according to the folding state.

[0267] FIGS. 17 and 18 are perspective views schematically illustrating an electronic device including a display device according to one embodiment of the present invention.

[0268] Referring to FIG. 17, the electronic device (1C) may include a main display area (MDA), a sub display area (SDA), and a peripheral area (PA). Pixels having display elements may be arranged in the main display area (MDA) and the sub display area (SDA). The area of ​​the main display area (MDA) may be different from the area of ​​the sub display area (SDA). For example, the area of ​​the main display area (MDA) may be larger than the area of ​​the sub display area (SDA). The peripheral area (PA) may be a non-display area in which pixels are not arranged.

[0269] A housing (90) may form the exterior of an electronic device (1C). The housing (90) may include a first portion (91) and a second portion (92) that support a display device (50). The area of ​​the first portion (91) may be different from the area of ​​the second portion (92). The housing (90) may have a hinge (HG) between the first portion (91) and the second portion (92). The electronic device (1C) may be folded or unfolded near the hinge (HG).

[0270] The main display area (MDA) may be located in the first part (91) of the housing (90), and the sub display area (SDA) may be located in the second part (92) of the housing (90). A folding axis (FAX) overlapping with a hinge (HG) may be located between the main display area (MDA) and the sub display area (SDA). The electronic device (1C) may be folded or unfolded based on the folding axis (FAX). When the electronic device (1C) is unfolded, the entire display area including the main display area (MDA) and the sub display area (SDA) may have a shape roughly like the alphabet "L" on a plane.

[0271] The display area (DA) may include a folding area (FA) adjacent to the folding axis (FAX). The display device may include a sensing wire arranged in the folding area (FA). The sensing wire may be arranged adjacent to the folding axis (FAX). For example, the sensing wire may be arranged to overlap the folding axis (FAX) on a plane. The sensing circuit may be configured to measure a change in the electrical characteristics of the sensing wire to detect a folding state of the electronic device (1C) and generate a display control signal for controlling pixels based on the detected folding state.

[0272] Referring to FIG. 18, the electronic device (1D) may include a display area (DA) and a peripheral area (PA). At least a portion of the electronic device (1D) may be bent or unfolded. In one embodiment, the housing (90) may be designed such that the curvatures of each portion are the same or different when the electronic device (1D) is bent. For example, as illustrated in FIG. 18, the housing (90) may be designed such that a portion of the electronic device (1D) is bent more than another portion so that the electronic device (1D) can stand without falling over. The housing (90) may maintain a bent or unfolded state of at least a portion of the electronic device (1D).

[0273] A display device included in an electronic device (1D) may include sensing wires arranged in a display area (DA). The sensing wires may be arranged at predetermined intervals in the display area (DA). In one embodiment, the sensing wires may be arranged more densely in a portion where the display device is bent with a smaller radius of curvature. A sensing circuit may be configured to measure a change in the electrical characteristics of each of the sensing wires to detect a bending state of the electronic device (1D), and generate a display control signal to compensate for color coordinates and / or brightness of pixels or rearrange an image displayed to a user based on the detected state.

[0274] While the present invention has been described with reference to the embodiments illustrated in the drawings, these are merely exemplary, and those skilled in the art will appreciate that various modifications and equivalent alternative embodiments are possible. Therefore, the true scope of technical protection of the present invention should be determined by the technical spirit of the appended claims.

Claims

A substrate comprising a display area and a peripheral area outside the display area, the substrate being foldable around a folding axis extending in a first direction across the display area; A plurality of pixels arranged in the above display area; A first voltage line arranged in the above peripheral area; A plurality of second voltage lines arranged in the above display area and electrically connected to the first voltage line and the plurality of pixels; A sensing wire arranged adjacent to the folding axis in the above display area; and A connecting wire disposed in the above peripheral area and electrically connected to the sensing wire; A display device, wherein the sensing wiring includes a first end and a second end, the first end being electrically connected to the first voltage line, and the second end being electrically connected to the connecting wiring. In the first paragraph, The above sensing wiring has a winding shape, a display device. In the first paragraph, A display device, wherein the sensing wiring includes a wiring portion having a first width and a pattern portion having a second width greater than the first width. In the first paragraph, Each of the plurality of pixels includes a pixel circuit including transistors and a light-emitting diode electrically connected to the pixel circuit, A display device, wherein the light-emitting diode includes a pixel electrode, a counter electrode disposed on the pixel electrode, and a light-emitting layer disposed between the pixel electrode and the counter electrode. In paragraph 4, The above pixel circuit is, A driving transistor electrically connecting the power line and the pixel electrode; A data write transistor electrically connecting the data line and the driving transistor; and A display device, comprising: a first initialization transistor electrically connecting one of the plurality of second voltage lines to the gate of the driving transistor. In paragraph 4, The above pixel circuit is, A driving transistor electrically connecting the power line and the pixel electrode; A data write transistor electrically connecting the data line and the driving transistor; and A display device comprising a second initialization transistor electrically connecting one of the second voltage lines and the pixel electrode. In paragraph 4, A display device, wherein the first voltage line is a first power voltage line electrically connected to the power line or a second power voltage line electrically connected to the counter electrode. In the first paragraph, The above second voltage lines extend in a second direction intersecting the first direction, A display device further comprising a plurality of third voltage lines extending in the first direction and electrically connected to the plurality of second voltage lines. In paragraph 8, A display device in which the sensing wiring is directly connected to one of the plurality of second voltage lines or one of the plurality of third voltage lines. In the first paragraph, A display device in which the sensing wire is elastic and includes a material whose resistance changes according to the elastic length. In Article 10, A display device, wherein the sensing wiring comprises conductive nanoparticles and an elastomer. In the first paragraph, A display driving circuit for driving the plurality of pixels; and Further comprising a sensing circuit electrically connected to the above connecting wire and configured to detect a folding state by comparing a measured voltage of the sensing wire with a reference voltage; The above display driving circuit is, A data driving unit configured to supply a data signal to the plurality of pixels; A gate driver configured to supply a scan signal to the plurality of pixels; A timing control unit configured to control the operation timing of the data driving unit and the gate driving unit using a vertical synchronization signal; and A display device comprising a voltage generator configured to supply the reference voltage and the first voltage. In paragraph 12, The above sensing circuit, Memory that stores the lookup table; A comparator that compares the measured voltage with the reference voltage and outputs a first value based on whether the measured voltage is less than or equal to the reference voltage, and outputs a second value based on whether the measured voltage is greater than the reference voltage; A first controller configured to detect the folding state based on the output value of the comparator and generate sensing data including the folding state; and A display device comprising a second controller configured to generate a display control signal for controlling the plurality of pixels based on the lookup table and the sensing data. In Article 13, A display device, wherein the first controller is configured to output a voltage control signal that changes the reference voltage based on the output value of the comparator. In Article 13, A display device, wherein the sensing circuit further includes a switch unit configured to electrically connect the sensing wire and the input terminal of the comparator during the on-voltage period of the switch control signal and electrically separate the sensing wire and the input terminal of the comparator during the off-voltage period of the switch control signal. In Article 15, A display device in which the on voltage period of the above switch control signal overlaps with the on voltage period of the above vertical synchronization signal. In Article 13, A display device, wherein the display control signal includes an image control signal configured to rearrange the image displayed by the plurality of pixels according to the folding state. In Article 13, A display device, wherein the display control signal includes an image quality control signal configured to compensate for color coordinates or luminance of the plurality of pixels according to the folding state. A substrate including a display area and a peripheral area outside the display area, the substrate being foldable about a first folding axis and a second folding axis extending in a first direction across the display area; A plurality of pixels arranged in the above display area; A first voltage line arranged in the above peripheral area; A plurality of second voltage lines arranged in the above display area and electrically connected to the first voltage line and the plurality of pixels; A first sensing wire arranged adjacent to the first folding axis in the above display area; A second sensing wire arranged adjacent to the second folding axis in the above display area; A first connecting wire arranged in the above peripheral area and electrically connected to the first sensing wire; and A second connecting wire disposed in the peripheral area and electrically connected to the second sensing wire; The first end of the first sensing wire is electrically connected to the first voltage line, and the second end of the first sensing wire is electrically connected to the first connection wire. A display device, wherein the first end of the second sensing wire is electrically connected to the first voltage line and the second end of the second sensing wire is electrically connected to the second connection wire. In Article 19, A display driving circuit configured to drive the plurality of pixels using a vertical synchronization signal; and A display device further comprising a sensing circuit electrically connected to the first connecting wire and the second connecting wire, configured to detect a folding state of the substrate by comparing the measured voltage of the first sensing wire with a first reference voltage and comparing the measured voltage of the second sensing wire with a second reference voltage during the on voltage period of the vertical synchronization signal.

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