Array substrate, display panel, and display device

Abstract

An array substrate, a display panel, and a display device. The array substrate comprises: a substrate (1); a plurality of first active patterns (20); a first insulating layer (3) provided with a plurality of first via holes (K1); a first metal layer (M1), located on the side of the first insulating layer (3) away from a first active layer (2) and comprising a plurality of first metal lines (M10), wherein the first metal lines (M10) are electrically connected to second portions (22) through the first via holes (K1); and a first conductive layer (D1), located on the side of the first metal layer (M1) away from the first insulating layer (3), insulated from the first metal layer (M1), and comprising a plurality of conductive portions (D10) and a plurality of first shielding portions (D11) located in a pixel region (AA), wherein the conductive portions (D10) are insulated from the first shielding portions (D11), the conductive portions (D10) are electrically connected to third portions (23), and the orthographic projections of the first shielding portions (D11) on the substrate (1) cover the orthographic projections of the first via holes (K1) on the substrate (1).

Description

Array substrate, display panel and display device TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to an array substrate, a display panel and a display device. BACKGROUND

[0002] High resolution (Pixels Per Inch, PPI) display technology is an important research direction in the field of display technology in recent years. With the popularity of electronic devices and the rapid development of network applications, people's requirements for image clarity and accuracy are constantly improving, and higher requirements are put forward for display technology. High-resolution display products have better immersive display experience, and have wide application in near-eye display products.

[0003] SUMMARY

[0004] The present application provides an array substrate, a display panel and a display device. The array substrate comprises:

[0005] a substrate;

[0006] a first active layer located on one side of the substrate, comprising a plurality of first active patterns located in the pixel region; the first active pattern comprises a first part, a second part connected to one end of the first part, and a third part connected to the other end of the first part;

[0007] a first insulating layer located on the side of the first active layer away from the substrate, having a plurality of first vias;

[0008] a first metal layer located on the side of the first insulating layer away from the first active layer, comprising a plurality of first metal lines; the first metal lines are electrically connected to the second part through the first vias;

[0009] a first conductive layer located on the side of the first metal layer away from the first insulating layer, comprising a plurality of conductive parts located in the pixel region and a plurality of first shielding parts; the projection of the conductive part on the substrate does not overlap with the projection of the first shielding part on the substrate; the conductive part is electrically connected to the third part; the projection of the first shielding part on the substrate covers the projection of the first via on the substrate.

[0010] In a possible implementation, the width of the first shielding part in the direction perpendicular to the extension direction of the first metal line is greater than the width of the first via in the direction perpendicular to the extension direction of the first metal line.

[0011] In a possible implementation, a width of the first shielding portion in a direction perpendicular to the extending direction of the first metal line is greater than a width of the second portion in the direction perpendicular to the extending direction of the first metal line.

[0012] In a possible implementation, at the first via position, the first metal line comprises a first metal portion, a second metal portion, and a third metal portion; the first metal portion covers a bottom of the first via; the second metal portion is located on a side of the first metal portion in a direction perpendicular to the extending direction of the first metal line and extends along a sidewall of the first via; and the third metal portion is located on another side of the first metal portion in the direction perpendicular to the extending direction of the first metal line and extends along the sidewall of the first via.

[0013] In a possible implementation, in a direction from the substrate to the first conductive layer, a thickness of at least one of the second metal portion and the third metal portion in a direction perpendicular to the extending direction of the first metal line gradually decreases.

[0014] In a possible implementation, a maximum thickness of the second metal portion in a direction perpendicular to the substrate is the same as a maximum thickness of the third metal portion in the direction perpendicular to the substrate; and a maximum length of the second metal portion in a direction perpendicular to the extending direction of the first metal line is equal to a maximum length of the third metal portion in the direction perpendicular to the extending direction of the first metal line.

[0015] In a possible implementation, the second metal portion only covers a sidewall on one side of the first via; and the third metal portion only covers a sidewall on another side of the first via.

[0016] In a possible implementation, the second metal portion covers all of the sidewall of the first via on one side of the first metal line and covers a portion of a surface of the first insulating layer away from the substrate; and the third metal portion covers all of the sidewall of the first via on another side of the first metal line and covers a portion of the surface of the first insulating layer away from the substrate.

[0017] In a possible implementation, a maximum thickness of the second metal portion in a direction perpendicular to the substrate is less than a maximum thickness of the third metal portion in the direction perpendicular to the substrate; and a maximum length of the second metal portion in a direction perpendicular to the extending direction of the first metal line is less than a maximum length of the third metal portion in the direction perpendicular to the extending direction of the first metal line.

[0018] In a possible implementation, the first via comprises a first sidewall and a second sidewall; and the first sidewall and the second sidewall are respectively located on two sides of the first metal portion.

[0019] The second metal portion covers part of the first sidewall; the third metal portion covers part of the second sidewall; and the area of the second metal portion covering the first sidewall is less than the area of the third metal portion covering the second sidewall.

[0020] In a possible implementation, the first via includes: a first sidewall, and a second sidewall; wherein the first sidewall and the second sidewall are respectively located on two sides of the first metal portion along a direction perpendicular to the extending direction of the first metal line;

[0021] The second metal portion covers part of the first sidewall; the third metal portion covers all of the second sidewall, and covers part of the first insulating layer on the periphery of the second sidewall away from the surface of the substrate on the side facing away from the substrate.

[0022] In a possible implementation, the first conductive layer and the first metal layer have a second insulating layer therebetween; the second insulating layer includes: a first insulating portion, and a second insulating portion located on the periphery of the first insulating portion; the first insulating portion in the orthographic projection of the substrate overlaps the first via in the orthographic projection of the substrate.

[0023] In a possible implementation, the first insulating portion and the second insulating portion are in an integral connection structure.

[0024] In a possible implementation, at least one side of the second insulating portion in the direction perpendicular to the extending direction of the first metal line has a first gap between the first insulating portion and the second insulating portion.

[0025] In a possible implementation, the orthographic projection of the first gap and the second metal portion on the substrate is located on the same side of the orthographic projection of the first metal portion on the substrate.

[0026] In a possible implementation, at the position of the first via, the first gap extends from the surface of the second insulating layer on the side facing away from the substrate to the bottom of the first via.

[0027] In a possible implementation, at the position of the first via, the first gap extends from the surface of the second insulating layer on the side facing away from the substrate to the first metal line.

[0028] In a possible implementation, the first shielding portion covers the first insulating portion, covers part of the second insulating portion on the periphery of the first insulating portion, and fills at least part of the first gap.

[0029] In a possible implementation, the first insulating part is a first recessed part recessed toward the substrate side at positions corresponding to the first metal part, and is a first protruded part protruded away from the substrate side at positions corresponding to the second metal part and the third metal part.

[0030] In a possible implementation, a distance between the first protruded part and the substrate is greater than a distance between the second insulating part and the substrate.

[0031] In a possible implementation, the first shielding part has a second recessed part at positions corresponding to the first recessed part, and has a second protruded part at positions corresponding to the first protruded part.

[0032] In a possible implementation, a line width of the first metal line is less than a width of the first via in a direction perpendicular to an extension direction of the first metal line.

[0033] In a possible implementation, a minimum distance in a first direction between a projection of an outer edge of the first shielding part on the substrate and a projection of an outer edge of the first via on the substrate is greater than 0.52 μm.

[0034] In a possible implementation, the array substrate further includes: a second conductive layer located on a side of the first conductive layer away from the first metal layer; the second conductive layer includes: a plurality of first electrodes located in the pixel area;

[0035] The first electrode is electrically connected to the third part through the conductive part.

[0036] In a possible implementation, the array substrate further includes: a second metal layer located between the first active layer and the first metal layer, and a third metal layer located on a side of the first active layer toward the substrate;

[0037] The second metal layer includes: a plurality of second metal lines extending in a first direction; the third metal layer includes: a plurality of shielding patterns; a projection of the shielding pattern on the substrate covers a projection of the first via on the substrate.

[0038] In a possible implementation, a projection of the shielding pattern on the substrate covers a projection of the first shielding part on the substrate.

[0039] In a possible implementation, the first metal line extends in a second direction;

[0040] The first part comprises a first sub-part extending along the second direction, and a second sub-part connected with the first sub-part and extending along a third direction; the second part is connected to an end of the second sub-part away from the first sub-part, and the third part is connected to an end of the first sub-part away from the second sub-part.

[0041] In a possible implementation, the first metal line comprises first sub-metal parts and second sub-metal parts arranged alternately along the second direction; the first sub-metal parts and the second sub-metal parts extend in different directions.

[0042] The second sub-metal part overlaps the first via in the orthographic projection of the substrate; the first part extends in the same direction as the first sub-metal part.

[0043] In a possible implementation, the array substrate further comprises a third signal line and a fourth signal line in the peripheral area; the third signal line is in the same layer as the first metal line; the fourth signal line is provided with a third insulating layer between the third signal line; the third insulating layer is provided with a plurality of second vias; the third signal line is electrically connected through the second vias.

[0044] The first conductive layer further comprises a plurality of second shielding parts; the second shielding parts cover the second vias in the orthographic projection of the substrate.

[0045] In a possible implementation, the array substrate further comprises a second active layer on a side of the first active layer facing the substrate, a driving source electrode on a side of the second active layer away from the substrate, a driving drain electrode, and a driving gate electrode.

[0046] The material of the first active layer comprises a metal oxide; and the material of the second active layer comprises low-temperature polysilicon.

[0047] The display panel provided in the embodiments of the present disclosure comprises the array substrate provided in the embodiments of the present disclosure, and further comprises a counter substrate arranged opposite to the array substrate.

[0048] The display device provided in the embodiments of the present disclosure comprises the display panel provided in the embodiments of the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0049] FIG. 1 is a schematic top view of an array substrate provided in the embodiments of the present disclosure;

[0050] FIG. 2A is a schematic top view of an array substrate provided in the embodiments of the present disclosure;

[0051] Figure 2B is a schematic diagram of the single film layer of the third metal layer in Figure 2A;

[0052] Figure 2C is a schematic diagram of the first active layer in Figure 2A;

[0053] Figure 2D is a schematic diagram of a single film layer of the second metal layer in Figure 2A;

[0054] Figure 2E is a schematic diagram of the single film layer of the first metal layer in Figure 2A;

[0055] Figure 2F is a schematic diagram of a single film layer of the first conductive layer in Figure 2A;

[0056] Figure 2G is a schematic diagram of a single film layer of the second conductive layer in Figure 2A;

[0057] Figure 2H is a schematic diagram of the cross section along the dashed line f in Figure 2A;

[0058] Figure 2I is a third top view of the array substrate provided in the embodiment of this disclosure;

[0059] Figure 3A is a schematic diagram of the array substrate after the third conductive layer is superimposed on Figure 2A;

[0060] Figure 3B is a schematic diagram of a single film layer of the third conductive layer in Figure 3A;

[0061] Figure 4A is one of the actual morphological diagrams corresponding to the dashed line width S1 in Figure 2H;

[0062] Figure 4B is a schematic diagram showing the extension of the second gap J2 to the bottom of the first through hole K1;

[0063] Figure 4C is a schematic diagram of Figure 4A after the first shielding part D11 is covered;

[0064] Figure 4D is the second schematic diagram of the actual morphology corresponding to the dashed line width S1 in Figure 2H;

[0065] Figure 4E is the third schematic diagram of the actual morphology corresponding to the dashed line width S1 in Figure 2H;

[0066] Figure 4F is the fourth schematic diagram of the actual morphology corresponding to the dashed line width S1 in Figure 2H;

[0067] Figure 5A is the fifth schematic diagram of the actual morphology corresponding to the dashed line width S1 in Figure 2H;

[0068] Figure 5B is a schematic diagram of Figure 5A after the first shielding part D11 is covered;

[0069] Figure 5C is the sixth schematic diagram of the actual morphology corresponding to the dashed line width S1 in Figure 2H;

[0070] Figure 5D is the seventh schematic diagram of the actual morphology corresponding to the dashed line width S1 in Figure 2H;

[0071] FIG. 5E is a view of FIG. 5D after covering the first shield portion;

[0072] FIG. 6A is a view of FIG. 2H at a line width S1 of a dashed line;

[0073] FIG. 6B is a view of FIG. 6A after covering a first shield portion D11;

[0074] FIG. 7 is a plan view of an array substrate according to an embodiment of the present disclosure;

[0075] FIG. 8 is a cross-sectional view of an array substrate according to an embodiment of the present disclosure;

[0076] FIG. 9 is a cross-sectional view of an array substrate according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0077] The present disclosure can be implemented in various forms. One of ordinary skill in the art can readily understand that the mode and content can be changed into one or more forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the content described in the following embodiments. Embodiments in the present disclosure and features in the embodiments can be combined with each other as long as there is no conflict.

[0078] In the drawings, the size, the thickness, or the region of one or more constituent elements can be exaggerated for clarity. Thus, one embodiment of the present disclosure is not limited to what is described in the following embodiments but can include any changes, equivalents, or substitutes of the configurations. Additionally, some of the components in the drawings are shown as being exaggerated in size for illustrative purposes.

[0079] In the present specification, ordinal terms, such as "first", "second", and "third", are used merely to avoid confusion with one another, and do not limit the number or the order of the constituent elements. "A plurality of" can include two or more.

[0080] In the present specification, terms indicating directions or positional relationships, such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", and "outer", are used to describe the positional relationships of constituent elements with reference to the drawings for the convenience of explanation of the present specification and simplification of the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus cannot be construed as limiting the present disclosure. The positional relationships of the constituent elements are appropriately changed depending on the directions in which the constituent elements are described. Therefore, the terms are not limited to those described in the specification, and can be appropriately replaced depending on the situation.

[0081] In this specification, unless otherwise explicitly specified and limited, the terms "mount", "connected", "connection" are to be interpreted broadly. For example, it can be fixed connection, or detachable connection, or integral connection; it can be mechanical connection, or electrical connection; it can be direct connection, or indirect connection through intermediate parts, or internal connection of two elements. For those skilled in the art, the meaning of the above terms in the present disclosure can be understood according to the circumstances.

[0082] In this specification, "electrically connected" includes the case where the constituent elements are connected through an element having some electrical effect. The "element having some electrical effect" is not particularly limited as long as it can transmit an electrical signal between the connected constituent elements. Examples of the "element having some electrical effect" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having one or more functions.

[0083] In this specification, a transistor refers to an element including at least three terminals of a gate electrode (gate), a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (a drain electrode terminal, a drain region, or a drain) and the source electrode (a source electrode terminal, a source region, or a source), and current can flow through the drain electrode, the channel region, and the source electrode. In the present disclosure, the channel region refers to a region where current mainly flows.

[0084] In addition, the gate of the transistor can be referred to as a control electrode. In the case of using a transistor with opposite polarity or in the case where the direction of current flow in a circuit is changed, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" can be interchanged.

[0085] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than or equal to -10° and less than or equal to 10°, and thus can include a state where the angle is greater than or equal to -5° and less than or equal to 5°. In addition, "perpendicular" refers to a state where the angle formed by two straight lines is greater than or equal to 80° and less than or equal to 100°, and thus can include a state where the angle is greater than or equal to 85° and less than or equal to 95°.

[0086] In this specification, a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon, etc. are not strictly so, and can be an approximate triangle, a rectangle, a trapezoid, a pentagon, or a hexagon, etc. There can be some small deformation due to tolerance, there can be a rounded corner, an arc edge, and deformation, etc.

[0087] In this specification, "film" and "layer" can be interchanged. For example, "conductive layer" can be changed to "conductive film". Similarly, "insulating film" can be changed to "insulating layer".

[0088] In the present specification, "about", "approximately", "substantially" mean not to be strictly limited to the boundary, and to allow a range of process and measurement errors. In the present specification, "substantially the same" can be a case where the exponential value is within 10% of each other.

[0089] For a high PPI display panel, usually part of the active pattern is electrically connected to the pixel electrode through the transfer electrode, and another part of the active pattern is electrically connected to the data line through the via. Due to the smaller line width and aperture of the high PPI display panel, the coverage of the insulating layer above the via can be poor, for example, there can be a gap around the via. When etching to form the transfer electrode, the etching liquid can enter the gap, causing corrosion of the data line in the hole, and even corrosion of the oxide active pattern connected to the data line, resulting in display panel display problems such as bright spots, dark lines, and the like.

[0090] Therefore, the array substrate provided by the embodiments of the present disclosure is provided, as shown in FIG. 1, FIG. 2A-2H, wherein FIG. 1 is a top view of the array substrate provided by the embodiments of the present disclosure, FIG. 2A is a top view of the array substrate provided by the embodiments of the present disclosure, FIG. 2B is a single film layer diagram of the third metal layer in FIG. 2A, FIG. 2C is a single film layer diagram of the first active layer in FIG. 2A, FIG. 2D is a single film layer diagram of the second metal layer in FIG. 2A, FIG. 2E is a single film layer diagram of the first metal layer in FIG. 2A, FIG. 2F is a single film layer diagram of the first conductive layer in FIG. 2A, FIG. 2G is a single film layer diagram of the second conductive layer in FIG. 2A, and FIG. 2H is a cross-sectional view along the dashed line f in FIG. 2A, having a pixel area AA and a peripheral area BB located outside the pixel area AA, wherein it comprises:

[0091] a substrate 1;

[0092] a first active layer 2 located on one side of the substrate 1, comprising: a plurality of first active patterns 20 located in the pixel area AA; the first active pattern 20 comprises: a first part 21, a second part 22 connected to one end of the first part 21, and a third part 23 connected to the other end of the first part 21; optionally, as shown in FIG. 2C, the first part 21 comprises: a first sub-part 211 extending in the second direction Y, and a second sub-part 212 connected to the first sub-part 211 and extending in the third direction Z; the second part 22 is connected to one end of the second sub-part 212 away from the first sub-part 211, and the third part 23 is connected to one end of the first sub-part 211 away from the second sub-part 212;

[0093] a first insulating layer 3 located on the side of the first active layer 2 away from the substrate 1, having a plurality of first vias K1;

[0094] The first metal layer M1 is located on the side of the first insulating layer 3 away from the first active layer 2, and includes: a plurality of first metal lines M10; the first metal line M10 is electrically connected with the second part 22 through the first via K1; optionally, the first metal line M10 can be a data line, and the first metal layer M1 can be a layer where the data line is located; specifically, the pixel region AA can have a plurality of first transistors, and the second part 22 can be used as the first transistor first electrode at the position overlapping the first metal line M10; the second part 22 can be turned on at the position overlapping the first metal line M11, realizing the electrical connection between the first transistor and the data line.

[0095] The first conductive layer D1 is located on the side of the first metal layer M1 away from the first insulating layer 3, and includes: a plurality of conductive parts D10 located in the pixel region AA and a plurality of first shielding parts D11, the conductive part D10 is in the orthographic projection of the substrate 1, and the first shielding part D11 is in the orthographic projection of the substrate 1 and does not overlap each other; the conductive part D10 is electrically connected with the third part 23; optionally, as shown in FIG. 2A and FIG. 2H, the conductive part D10 can be electrically connected with the third part 23 through the third via K3; the conductive part D10 can be further electrically connected with the first electrode D20 through the fourth via K4, and the first electrode D20 can be a pixel electrode; the first shielding part D11 is in the orthographic projection of the substrate 1, covering the orthographic projection of the first via K1 in the substrate 1. Specifically, the first conductive layer D1 can be a transparent conductive layer, and the conductive part D10 can be used as the first transistor second electrode to turn on the first active pattern 20 and the first electrode D20; specifically, the conductive part D10 can be in the orthographic projection of the substrate 1 in the shape of a rectangle.

[0096] In the embodiments of the present disclosure, the first conductive layer D1 includes: a plurality of conductive parts D10 and a plurality of first shielding parts D11, the first shielding part D11 is in the orthographic projection of the substrate 1, covering the orthographic projection of the first via K1 in the substrate 1, by adding the shielding of the first shielding part D11 to the position of the first via K1, the etching liquid for etching the conductive part D10 is effectively prevented from entering the first via K1 through the hole edge gap of the first via K1 to corrode the first metal line M10 and the first active pattern 20, thereby causing related defects such as bright spots and bright-dark lines; moreover, since the first shielding part D11 is usually used with the conductive part D10, the conductive part D10 usually uses transparent material, which is transparent in the visible light wavelength range, so that the use of the first shielding part D11 does not affect the transmittance of the entire display panel.

[0097] In the related art, on a high-resolution LTPO structure display panel, the first metal line M10 needs to be extremely thin, as shown in FIG. 1, the line width a4 of the first metal line M10 is smaller than the size a2 of the first via K1, then the film layer above the first via K1 has poor coverage of the first via K1, and a broken gap problem occurs, for example, as shown in FIG. 4A, the second insulating layer 4 has a first gap J1 at the position of the first via K1; and the conductive part D10 above the second insulating layer 4 adopts a transparent material (for example, indium tin oxide), and generally adopts a wet etching method during etching. Since the etching liquid is an acidic solution, when the second insulating layer 4 has poor coverage and the first gap J1 occurs at the position of the first via K1, the etching liquid can enter the first via K1 through the first gap J1, thereby corroding the first metal line M10 (optionally, the first metal line M10 can include a plurality of sub-metal layers arranged in a stack, for example, can include a first sub-metal layer M01, a second sub-metal layer M02 and a third sub-metal layer M03 arranged in a stack, wherein the material of the first sub-metal layer M01 can be titanium or molybdenum, the material of the second sub-metal layer M02 can be aluminum, and the material of the third sub-metal layer M03 can be titanium or molybdenum; optionally, the first metal line M10 can also be a single layer of metal or alloy, for example, when the first metal line M10 is a single layer of metal, the material of the first metal line M10 can be molybdenum; when the first metal line M10 is an alloy, the material of the first metal line M10 can be WMo alloy) and the first active pattern 20 below the first metal line M10, which will cause the resistance of the first metal line M10 to be large, and even cause a broken problem; in addition, the acidic etching liquid and the first active pattern 20 of the oxide (for example, indium gallium zinc oxide) react chemically, for example, causing Zn to be precipitated, thereby causing the electrical characteristics of the oxide transistor to be negatively biased, resulting in related electrical properties such as bright spots and other related malfunctions. In the embodiments of the present disclosure, as shown in FIG. 4C, by covering the first shielding part D11 at the position of the first via K1, the first shielding part D11 shields the position of the first via K1, effectively avoiding the etching liquid from entering the first via K1 through the hole edge gap of the first via K1, thereby avoiding the corrosion of the etching liquid to the first metal line M10 and / or the first active pattern 20, and thereby improving the related malfunctions such as bright spots and bright and dark lines caused by corrosion of the first metal line M10 and / or the first active pattern 20.

[0098] In a possible implementation, as shown in FIG. 1, the minimum distance a5 between the outer edge of the first shielding part D11 in the orthographic projection of the substrate 1 and the outer edge of the first via K1 in the orthographic projection of the substrate 1 in the direction perpendicular to the extension direction of the first metal line M10 is greater than 0.52 μm.

[0099] In a possible implementation, the first shielding portion D11 is generally designed as a square shape or a circle shape in design. In order to ensure complete shielding, the size of the first shielding portion D11 and the alignment deviation need to be considered; in the embodiment of the present disclosure, the minimum distance a5 between the outer edge of the first shielding portion D11 in the orthographic projection of the substrate 1 and the outer edge of the first via K1 in the orthographic projection of the substrate 1 in the first direction X is greater than 0.52 μm, which can ensure the effective shielding of the first shielding portion D11 to the first via K1 within the range considering the influence factors of the alignment deviation. Taking the size CDC of the first via K1 as 1.5 μm for example, the first error tolerance value CDA in the first direction X is 0.6 μm, the second error tolerance value CDB in the second direction Y is 0.6 μm, and the alignment deviation OVL is 0.3 μm, so the size of the single-sided shielding required is Therefore, the size of the first shielding portion D11 needs to be CD = CDC + 2*CD1 = 2.54 μm.

[0100] In a possible implementation, referring to FIG. 1, the width a1 of the first shielding portion D11 in the direction perpendicular to the extension direction of the first metal line M10 is greater than the width a2 of the first via K1 in the direction perpendicular to the extension direction of the first metal line M10. In this way, sufficient coverage of the first shielding portion D11 to the first via K1 is achieved.

[0101] In a possible implementation, referring to FIG. 1, the width a1 of the first shielding portion D11 in the direction perpendicular to the extension direction of the first metal line M10 is greater than the width a3 of the second portion 22 in the direction perpendicular to the extension direction of the first metal line M10.

[0102] In a possible implementation, referring to FIGS. 4A-4C, wherein FIG. 4A is one of the corresponding actual topography schematic diagrams of FIG. 2H at the line width S1, FIG. 2H is one of the schematic diagrams of the array substrate, FIG. 4B is a schematic diagram in which the second gap J2 extends to the bottom of the first via K1, and FIG. 4C is a schematic diagram in which the first shielding portion D11 covers the first via K1, the first metal line M10 at the position of the first via K1 includes: a first metal portion M11, a second metal portion M12, and a third metal portion M13; the first metal portion M11 covers the bottom of the first via K1; the second metal portion M12 is located on the side of the first metal portion M11 along the direction perpendicular to the extension direction of the first metal line M10 and extends along the sidewall of the first via K1; and the third metal portion M13 is located on the other side of the first metal portion M11 along the direction perpendicular to the extension direction of the first metal line M10 and extends along the sidewall of the first via K1.

[0103] In a possible implementation, as shown in FIG. 4A, the thickness c1 of at least one of the second metal portion M12 and the third metal portion M13 in the direction perpendicular to the extending direction of the first metal line M10 (for example, the first metal line M10 extends along the first direction X, and the direction perpendicular to the extending direction of the first metal line M10 is the direction perpendicular to the first direction X) gradually decreases in the direction from the substrate 1 to the first conductive layer D1. That is, as shown in FIG. 4A, the thickness c1 of the second metal portion M12 in the direction perpendicular to the extending direction of the first metal line M10 gradually decreases in the direction from the bottom to the top, forming a sharp angle.

[0104] In a possible implementation, as shown in FIG. 4A, the maximum thickness d11 of the second metal portion M12 in the direction perpendicular to the substrate 1 is the same as the maximum thickness d12 of the third metal portion M13 in the direction perpendicular to the substrate 1; and the maximum length d13 of the second metal portion M12 in the direction perpendicular to the extending direction of the first metal line M10 is equal to the maximum length d14 of the third metal portion M13 in the direction perpendicular to the extending direction of the first metal line M10.

[0105] In a possible implementation, as shown in FIG. 4A, the maximum thickness d11 of the second metal portion M12 in the direction perpendicular to the substrate 1 is greater than the maximum depth d20 of the first via K1 in the direction perpendicular to the substrate 1. In a possible implementation, the maximum thickness d11 of the second metal portion M12 in the direction perpendicular to the substrate 1 can be equal to the maximum depth d20 of the first via K1 in the direction perpendicular to the substrate 1. In a possible implementation, the maximum thickness d11 of the second metal portion M12 in the direction perpendicular to the substrate 1 is less than the maximum depth d20 of the first via K1 in the direction perpendicular to the substrate 1.

[0106] In a possible implementation, as shown in FIG. 4A, the second metal portion M12 only covers the sidewall on one side of the first via K1; and the third metal portion M13 only covers the sidewall on the other side of the first via K1. For example, as shown in FIG. 4A, the second metal portion M12 only covers the left sidewall of the first via K1; and the third metal portion M13 only covers the right sidewall of the first via K1. That is, as shown in FIG. 4A, the second metal portion M12 does not climb to the upper surface of the first insulating layer 3 on the left side of the first via K1; and the third metal portion M13 does not climb to the upper surface of the first insulating layer 3 on the right side of the first via K1.

[0107] In a possible implementation, as shown in FIG. 6A, the second metal portion M12 covers all of the first sidewall of the first via K1 on one side of the first metal line M10, and covers part of the surface of the first insulating layer 3 on the side away from the substrate 1; the third metal portion M13 covers all of the first sidewall of the first via K1 on the other side of the first metal line M10, and covers part of the surface of the first insulating layer 3 on the side away from the substrate 1. Specifically, in combination with FIG. 6A, the first via K1 includes: a first sidewall K11, and a second sidewall K12; the first sidewall K11 and the second sidewall K12 are respectively on two sides of the first metal portion M11 perpendicular to the extension direction of the first metal line M10; as shown in FIG. 6A, the second metal portion M12 covers all of the first sidewall K11, and covers part of the surface of the first insulating layer 3 on the side away from the substrate 1 around the first sidewall K11; the third metal portion M13 covers all of the second sidewall K12, and covers part of the surface of the first insulating layer 3 on the side away from the substrate 1.

[0108] In a possible implementation, as shown in FIG. 6A, the line width of the first metal line M10 in the first direction X can be greater than the width of the first via K1 in the first direction X, so that by widening the line width of the first metal line M10 at the position of the first via K1 (the first metal line M10 can still be made thinner at positions other than the first via K1), the second insulating layer 4 can be prevented from being broken at the position of the first via K1, and the etching liquid can be prevented from corroding the first metal line M10 and / or the first active pattern 20 along the gap of the breakage.

[0109] In a possible implementation, due to actual process reasons, the relative position of the first metal line M10 and the first via K1 can be offset, causing the climbing height of the first metal line M10 to be different on different sides of the first via K1. For example, as shown in FIG. 4E and FIG. 5A, the maximum height of the second metal portion M12 and the third metal portion M13 on both sides of the first metal portion M11 in the direction perpendicular to the substrate 1 can be different, and the maximum length in the direction perpendicular to the extension direction of the first metal line M10 can also be different. For example, as shown in FIG. 4E and FIG. 5A, the maximum thickness d11 of the second metal portion M12 in the direction perpendicular to the substrate 1 is less than the maximum thickness d12 of the third metal portion M13 in the direction perpendicular to the substrate 1; and the maximum length d13 of the second metal portion M12 in the direction perpendicular to the extension direction of the first metal line M10 is less than the maximum length d14 of the third metal portion M13 in the direction perpendicular to the extension direction of the first metal line M10.

[0110] In a possible implementation, as shown in FIG. 4E, the first via K1 includes a first sidewall K11 and a second sidewall K12; the first sidewall K11 and the second sidewall K12 are respectively located at two sides of the first metal portion M11; the second metal portion M12 covers part of the first sidewall K11; the third metal portion M13 covers part of the second sidewall K12; and the area of the second metal portion M12 covering the first sidewall K11 is smaller than the area of the third metal portion M13 covering the second sidewall K12. That is, although the relative position between the first metal line M10 and the first via K1 can be offset, the second metal portion M12 and the third metal portion M13 have not climbed onto the upper surface of the part of the first insulating layer 3 surrounding the first via K1.

[0111] In a possible implementation, as shown in FIG. 5A, the first via K1 includes a first sidewall K11 and a second sidewall K12; the first sidewall K11 and the second sidewall K12 are respectively located at two sides of the first metal portion M11; the second metal portion M12 covers part of the first sidewall K11; the third metal portion M13 covers the entire second sidewall K12 and covers part of the upper surface of the first insulating layer surrounding the second sidewall K12 away from the substrate 1. That is, the relative position between the first metal line M10 and the first via K1 can be offset, and the third metal portion M13 climbs onto the upper surface of the part of the first insulating layer 3 surrounding the first via K1.

[0112] In a possible implementation, as shown in FIGS. 2H and 4A-4E, the first conductive layer D1 and the first metal layer M1 have a second insulating layer 4 therebetween; the second insulating layer 4 includes a first insulating portion 41 and a second insulating portion 42 located at the periphery of the first insulating portion 41; the first insulating portion 41 is overlapped with the first via K1 in the projection of the substrate 1; optionally, the part of the second insulating layer 4 corresponding to the first via K1 can be the first insulating portion 41, and the part of the second insulating layer 4 other than the first insulating portion 41 can be the second insulating portion 42.

[0113] In a possible implementation, as shown in FIGS. 4A-4C, at least one side of the second insulating portion 42 perpendicular to the extending direction of the first metal line M10 has a first gap J1 with the first insulating portion 41. In a possible implementation, as shown in FIG. 4B, both sides of the second insulating portion 42 perpendicular to the extending direction of the first metal line M10 have a first gap J1 with the first insulating portion 41. In a possible implementation, as shown in FIG. 5D, one side of the second insulating portion 42 perpendicular to the extending direction of the first metal line M10 has a first gap J1 with the first insulating portion 41. That is, due to the extremely thin line of the first metal line M10, the coverage of the second insulating layer 4 at the location of the first via K1 is not good, thereby causing the first gap J1 between the first insulating portion 41 and the second insulating portion 42.

[0114] In a possible implementation, as shown in FIG. 5D, the first gap J1 and the second metal portion M12 are located on the same side of the first metal portion M11 in the orthographic projection of the substrate 1. For example, as shown in FIG. 5D, the first gap J1 and the second metal portion M12 are located on the left side of the first metal portion M11 in the orthographic projection of the substrate 1. That is, when the relative position of the first metal line M10 and the first via K1 is offset, the first gap J1 can be located on the opposite side of the offset direction. For example, as shown in FIG. 5D, the first metal line M10 is offset to the right relative to the center of the first via K1, which causes the second insulating portion 42 on the left side of the first via K1 to have the first gap J1 with the first insulating portion 41.

[0115] In a possible implementation, as shown in FIG. 4A, at the location of the first via K1, the first gap J1 extends from the surface of the second insulating layer 4 away from the substrate 1 to the first metal line M10.

[0116] In a possible implementation, as shown in FIG. 4B, at the location of the first via K1, the first gap J1 extends from the surface of the second insulating layer 4 away from the substrate 1 to the bottom of the first via K1. That is, there is also a gap between the first metal line M10 and the sidewall of the first via K1.

[0117] In a possible implementation, as shown in FIG. 4C, the first shielding portion D11 covers the first insulating portion 41, covers part of the second insulating portion 42 around the first insulating portion 41, and fills at least part of the first gap J1. In a possible implementation, the first shielding portion D11 fills all of the first gap J1; in another possible implementation, the first shielding portion D11 can also fill part of the first gap J1.

[0118] In a possible implementation, as shown in FIG. 4D, FIG. 5A-5B, FIG. 6A-6B, there can be no first gap J1 between the first insulating part 41 and the second insulating part 42, that is, the first insulating part 41 and the second insulating part 42 are integrally connected, and the first insulating layer 4 is a continuous structure at the first via K1 and the periphery.

[0119] In a possible implementation, as shown in FIG. 4F, FIG. 5D, FIG. 5E, where FIG. 5E is a schematic view of FIG. 5D after covering the first shielding part, there can be only one side with the first gap J1 between the first insulating part 41 and the second insulating part 42.

[0120] In a possible implementation, as shown in FIG. 4C, FIG. 5B, FIG. 6B, the first shielding part D11 covers the first insulating part 41 and part of the second insulating part 42 around the first insulating part 41.

[0121] In a possible implementation, as shown in FIG. 5B, the first metal line M10 can include a plurality of sub-metal layers arranged in a stack, for example, can include a first sub-metal layer M01, a second sub-metal layer M02 and a third sub-metal layer M03 arranged in a stack in turn, the material of the first sub-metal layer M01 can be titanium or molybdenum, the material of the second sub-metal layer M02 can be aluminum, and the material of the third sub-metal layer M03 can be titanium or molybdenum; at the edge position of the first metal line M10, the second sub-metal layer M02 is recessed relative to the first sub-metal layer M01 and / or the third sub-metal layer M03, that is, there is an aluminum over-etching situation; in a possible implementation, as shown in FIG. 5C, at the edge position of the first metal line M10, the second sub-metal layer M02 is substantially flush with the first sub-metal layer M01 and / or the third sub-metal layer M03, that is, there can be no aluminum over-etching situation.

[0122] In a possible implementation, as shown in FIG. 4A, the first insulating part 41 has a first recessed part 410 recessed toward one side of the substrate 1 at a position corresponding to the first metal part M11, and has a first protruding part 420 protruding away from one side of the substrate 1 at positions corresponding to the second metal part M12 and the third metal part M13.

[0123] In a possible implementation, as shown in FIG. 4A, the maximum distance between the first protruding part 420 and the substrate 1 is greater than the maximum distance between the second insulating part 42 and the substrate 1.

[0124] In a possible implementation, as shown in FIG. 4C, the first shielding part D11 has a second recessed part D111 at a position corresponding to the first recessed part 410, and has a second protruding part D112 at a position corresponding to the first protruding part 420.

[0125] In a possible manner, referring to FIG. 2A and FIG. 2H, the array substrate further includes: a second conductive layer D2 located on a side of the first conductive layer D1 away from the first metal layer M1; the second conductive layer D2 includes: a plurality of first electrodes D20 located in the pixel area AA; the first electrode D20 is electrically connected with the third part 23 through the conductive part D10; in a possible manner, the material of the conductive part D10 can be the same as the material of the first electrode D20.

[0126] In a possible implementation, the first electrode D20 is a pixel electrode, and the second conductive layer D2 can be a layer in which the pixel electrode is located. In a possible implementation, the second conductive layer D2 can be a pixel electrode layer; in a possible implementation, the second conductive layer D2 can be a transparent electrode layer; in a possible implementation, the material of the second conductive layer D2 can include: a metal oxide. For example, one or a combination of indium tin oxide, indium-doped zinc oxide (AZO), fluorine-doped tin oxide (AZO), aluminum-doped zinc oxide (AZO), and indium-doped cadmium oxide.

[0127] In a possible implementation, referring to FIG. 2I, the array substrate further includes: a second metal layer M2 located between the first active layer 2 and the first metal layer M1, and a third metal layer M3 located on a side of the first active layer 2 facing the substrate 1; the second metal layer M2 includes: a plurality of second metal lines M20 extending along the first direction X; the third metal layer M3 includes: a plurality of shielding patterns M33; the shielding pattern M33 has a projection on the substrate 1 covering a projection of the first via K1 on the substrate 1. In the embodiment of the present disclosure, the array substrate further includes the plurality of shielding patterns M33, and the light shielding at the position of the first via K1 can be implemented.

[0128] In a possible implementation, referring to FIG. 2A, the shielding pattern M33 has a projection on the substrate 1 covering a projection of the first shielding part D11 on the substrate 1.

[0129] In a possible implementation, the second metal line M20 can be a gate line.

[0130] In a possible implementation, referring to FIG. 2A and FIG. 2H, the third metal layer M3 further includes: a third metal line M30 extending along the first direction X; the third metal line M30 has a projection on the substrate 1 covering a projection of the second metal line M20 on the substrate 1. Optionally, the third metal line M30 has a projection on the substrate 1 covering a part of a projection of the first active pattern 20 on the substrate 1, so as to avoid external light from irradiating the channel region of the first active pattern 20 and affecting the transistor characteristics.

[0131] In a possible implementation, the first shielding portion D11 has a rectangular, circular, elliptical, triangular, trapezoidal, pentagonal, hexagonal or octagonal shape in the orthographic projection of the substrate 1.

[0132] In a possible implementation, the shielding pattern M33 has a rectangular, circular, elliptical, triangular, trapezoidal, pentagonal, hexagonal or octagonal shape in the orthographic projection of the substrate 1.

[0133] In a possible implementation, the first shielding portion D11 has a shape similar to the shielding pattern M33 in the orthographic projection of the substrate 1, for example, both are rectangular; or for example, both are circular.

[0134] In a possible implementation, referring to FIG. 2A, the first metal line M10 extends along the second direction Y. That is, the first metal line M10 is a straight line extending along the second direction Y.

[0135] In a possible implementation, referring to FIG. 7, the first metal line M10 includes: first sub-metal portions M1a and second sub-metal portions M1b arranged alternately along the second direction Y; the first sub-metal portions M1a and the second sub-metal portions M1b have different extension directions; the second sub-metal portions M1b have an orthographic projection on the substrate 1 that overlaps with an orthographic projection of the first via K1 on the substrate 1; the first portion 21 has an extension direction that is the same as that of the first sub-metal portions M1a. That is, the first metal line M10 can also be a broken line. When the first metal line M10 is a broken line, the extension direction of the first portion 21 can be the same as that of the first sub-metal portions M1a.

[0136] In a possible implementation, referring to FIG. 8, the array substrate further includes: a third signal line M13 and a fourth signal line M14 in the peripheral area BB; the third signal line M13 is in the same layer as the first metal line M10; the fourth signal line M14 has a third insulating layer between the third signal line M13, the third insulating layer having a plurality of second vias K2; the third signal line M13 is electrically connected through the second vias K2; the first conductive layer D1 further includes: a plurality of second shielding portions D12; the second shielding portions D12 have an orthographic projection on the substrate 1 that covers an orthographic projection of the second vias K2 on the substrate. In the embodiments of the present disclosure, for the third signal line M13 in the peripheral area BB that is in the same layer as the first metal line M10, when the third signal line M13 is to be electrically connected to the fourth signal line M14 through the second vias K2, the second shielding portions D12 can also be arranged at positions of the second vias K2 to avoid the etching liquid corroding the third signal line M13 through the periphery of the second vias K2, thereby preventing the third signal line M13 from being adversely affected.

[0137] In a possible implementation, referring to FIGS. 3A-3B and 8, the array substrate further includes: a third conductive layer D3 on the side of the second conductive layer D2 away from the substrate 1, and a fourth metal layer M4 on the side of the third conductive layer D3 away from the substrate 1; the third conductive layer D3 can be a common electrode layer, and the fourth metal layer M4 can be in direct contact with the third conductive layer D3 to reduce the resistance of the third conductive layer D3; the fourth metal layer M4 can include: a plurality of light-shielding patterns M40, which can include first light-shielding patterns extending along the first direction X and second light-shielding patterns extending along the second direction Y, wherein the first light-shielding patterns can overlap the second metal lines M20 in the orthographic projection of the substrate 1, and the second light-shielding patterns can overlap the first metal lines M10 in the orthographic projection of the substrate 1.

[0138] In a possible implementation, referring to FIG. 8, the array substrate further includes: a buffer layer 11 on the side of the substrate 1, a first gate insulating layer 12 on the side of the buffer layer 11 away from the substrate 1, a first interlayer dielectric layer 13 on the side of the first gate insulating layer 12 away from the buffer layer 11, a second gate insulating layer 31 on the side of the first interlayer dielectric layer 13 away from the first gate insulating layer 12, and a second interlayer dielectric layer 32 on the side of the second gate insulating layer 31 away from the first interlayer dielectric layer 13, a third interlayer dielectric layer 14 on the side of the second interlayer dielectric layer 32 away from the second gate insulating layer 31, a planarization layer 15 on the side of the third interlayer dielectric layer 14 away from the second interlayer dielectric layer 32, and a passivation layer 16 on the side of the planarization layer 15 away from the third interlayer dielectric layer 14.

[0139] The first insulating layer 3 can include: the second gate insulating layer 31 and the second interlayer dielectric layer 32; and the second insulating layer 4 can include: the third interlayer dielectric layer 14.

[0140] In a possible implementation, referring to FIG. 9, the first electrode D20 can include a first sub-electrode D21 and a second sub-electrode D22; the first sub-electrode D21 is partially located at the bottom of the first via K1, partially located at the sidewall of the fourth via K4, and partially extends to the surface of the planarization layer 15 on the side away from the substrate 1; and the second sub-electrode D22 is located on the side of the first sub-electrode D21 away from the substrate 1 and is in direct contact with the part of the first sub-electrode D21 extending to the surface of the planarization layer 15 on the side away from the substrate 1.

[0141] In a possible implementation, referring to FIG. 9, the array substrate further includes: a filling portion 62 filled in the fourth via K4 to achieve planarization at the first electrode D20.

[0142] In a possible implementation, referring to FIG. 8 or FIG. 9, the array substrate further includes a first spacer 18 located on the side of the second conductive layer D2 away from the substrate 1.

[0143] In a possible implementation, referring to FIG. 8 or FIG. 9, the array substrate further includes a color filter layer located on the side of the second conductive layer D2 toward the substrate 1; the color filter layer includes a plurality of color resist 17, for example, can include red color resist, green color resist, and blue color resist. In the embodiment of the present disclosure, the array substrate further includes the color filter layer to avoid cross color between different sub-pixels, which can be applied to display products with a resolution of 1500 PPI or above.

[0144] In a possible implementation, the array substrate can also not be provided with the color filter layer, and the fourth metal layer M4 can be used to improve the cross color between different sub-pixels, so as to reduce the cross color level without increasing the black matrix.

[0145] In a possible implementation, referring to FIG. 8, the array substrate further includes a second active layer 5 located on the side of the first active layer 2 toward the substrate 1, a drive source-drain electrode 61 and a drive drain electrode 62 located on the side of the second active layer 5 away from the substrate 1, and a drive gate electrode 7. In a possible implementation, referring to FIG. 8, the drive source-drain electrode 61 and the drive drain electrode 62 can be of the same layer and the same material as the first metal trace M10, and the drive gate electrode 7 can be of the same layer and the same material as the third metal layer M3.

[0146] In a possible implementation, referring to FIG. 8, the array substrate further includes a first drive electrode M31, a second drive electrode M16, a third drive electrode D32, a fourth drive electrode M17, and a fifth drive electrode D31 located in the peripheral area BB, wherein the first drive electrode M31 and the second drive electrode M16 can be electrically connected through the second drive electrode M16, and the fourth drive electrode M17 and the fifth drive electrode D31 are electrically connected. Specifically, the first drive electrode M31 can serve as a first signal line, and the fourth drive electrode M17 can serve as a second signal line. The first signal line can include a signal line electrically connected to a gate drive circuit and / or a signal line electrically connected to a multiplexer; the second signal line can include a signal line electrically connected to a gate drive circuit and / or a signal line electrically connected to a multiplexer. The first signal line can include an initial signal line, a clock signal line, a reset signal line, or a light-emitting control line. The second signal line can include an initial signal line, a clock signal line, a reset signal line, or a light-emitting control line.

[0147] In a possible implementation, referring to FIG. 8, the material of the first active layer 2 includes a metal oxide, and the material of the second active layer 5 includes low-temperature polycrystalline silicon. In the embodiment of the present disclosure, the array substrate uses the LTPO (Low Temperature Polycrystalline Oxide) technology, integrates the LTPS (Low Temperature Poly-Silicon) and the Oxide (oxide) two TFTs (Thin Film Transistor), and can make the AR and VR products have high resolution (for example, more than 1000 PPI), high aperture ratio and high transmittance.

[0148] In a possible implementation, the material of the first active layer 2 includes a metal oxide semiconductor material, and the metal oxide semiconductor material can include any one or more of an amorphous indium gallium zinc oxide material (a-IGZO), zinc oxide nitride (ZnON), or indium zinc tin oxide (IZTO), indium gallium zinc oxide (IGZO), indium gallium oxide (IGO), indium gallium zinc tin oxide (IGZTO), indium zinc oxide (IZO), or a rare earth element doped metal oxide (RE-OS), where the rare earth element doped metal oxide can include a lanthanide doped metal oxide (Ln-OS). The crystallization state of the active layer material can be amorphous, partially crystalline or polycrystalline. In the embodiment of the present disclosure, the material of the first active layer 2 is a rare earth element doped metal oxide, and the first active layer 2 can have stable performance even if it is exposed to light, so that the display panel can further improve the aperture ratio without the need to set a light shielding layer in the pixel light transmission area. In the embodiment of the present disclosure, the first active layer 2 of the display area transistor can use an oxide active layer, that is, the thin film transistor of the oxide active layer has the advantages of low leakage current.

[0149] Based on the same inventive concept, the embodiment of the present disclosure further provides a display panel, which includes the array substrate provided by the embodiment of the present disclosure, and further includes an opposite substrate arranged opposite to the array substrate.

[0150] Based on the same inventive concept, the embodiment of the present disclosure further provides a display device, which includes the display panel provided by the embodiment of the present disclosure.

[0151] Although the preferred embodiments of the present application have been described, those skilled in the art can make further changes and modifications to the embodiments once they know the basic inventive concept. Therefore, the appended claims are intended to be interpreted as including all changes and modifications falling within the scope of the present application.

[0152] It will be apparent to those skilled in the art that various modifications and variations can be made to the present embodiments without departing from the spirit or scope of the present embodiments. Thus, it is intended that the present embodiments cover the modifications and variations of this application provided they come within the scope of the appended claims and their equivalents.

Claims

1. An array substrate having a pixel region and a peripheral region located at a periphery of the pixel region, wherein, The application relates to a substrate, a first active layer, a first insulating layer, a first metal layer, and a first conductive layer. The first active layer is located on one side of the substrate and comprises a plurality of first active patterns in the pixel region; each first active pattern comprises a first part, a second part connected to one end of the first part, and a third part connected to the other end of the first part. The first insulating layer is located on the side of the first active layer away from the substrate and has a plurality of first through holes. The first metal layer is located on the side of the first insulating layer away from the first active layer and comprises a plurality of first metal lines; the first metal lines are electrically connected to the second parts through the first through holes. The first conductive layer is located on the side of the first metal layer away from the first insulating layer and comprises a plurality of conductive parts in the pixel region and a plurality of first shielding parts; the conductive parts do not overlap with the first shielding parts in the projection of the substrate; the conductive parts are electrically connected to the third parts; the first shielding parts cover the first through holes in the projection of the substrate. The width of the first shielding part in the direction perpendicular to the extension direction of the first metal line is greater than the width of the first through hole in the direction perpendicular to the extension direction of the first metal line.

2. The array substrate of claim 1, wherein, The width of the first shielding part in the direction perpendicular to the extension direction of the first metal line is greater than the width of the second part in the direction perpendicular to the extension direction of the first metal line.

3. The array substrate of claim 2, wherein, The first metal line at the position of the first through hole comprises a first metal part, a second metal part, and a third metal part; the first metal part covers the bottom of the first through hole; the second metal part is located on the side of the first metal part in the direction perpendicular to the extension direction of the first metal line and extends along the sidewall of the first through hole; and the third metal part is located on the other side of the first metal part in the direction perpendicular to the extension direction of the first metal line and extends along the sidewall of the first through hole.

4. The array substrate of claim 2 or 3, wherein, In the direction from the substrate to the first conductive layer, the thickness of at least one of the second metal part and the third metal part in the direction perpendicular to the extension direction of the first metal line gradually decreases.

5. The array substrate of claim 4, wherein, The maximum thickness of the second metal part in the direction perpendicular to the substrate is the same as the maximum thickness of the third metal part in the direction perpendicular to the substrate; and the maximum length of the second metal part in the direction perpendicular to the extension direction of the first metal line is equal to the maximum length of the third metal part in the direction perpendicular to the extension direction of the first metal line.

6. The array substrate of claim 4 or 5, wherein, The second metal part only covers the sidewall on one side of the first through hole; and the third metal part only covers the sidewall on the other side of the first through hole.

7. The array substrate of claim 6, wherein, The second metal part covers all the sidewalls of the first through hole on one side of the first metal line and covers part of the surface of the first insulating layer away from the substrate; and the third metal part covers all the sidewalls of the first through hole on the other side of the first metal line and covers part of the surface of the first insulating layer away from the substrate.

8. The array substrate of claim 6, wherein, ​ 9. The array substrate of claim 4 or 5, wherein, The maximum thickness of the second metal portion in a direction perpendicular to the substrate is less than the maximum thickness of the third metal portion in a direction perpendicular to the substrate; and the maximum length of the second metal portion in a direction perpendicular to the extending direction of the first metal line is less than the maximum length of the third metal portion in a direction perpendicular to the extending direction of the first metal line.

10. The array substrate of claim 9, wherein, The first via includes a first sidewall and a second sidewall, wherein the first sidewall and the second sidewall are respectively located on two sides of the first metal portion. The second metal portion covers a portion of the first sidewall, and the third metal portion covers a portion of the second sidewall.

11. The array substrate of claim 9, wherein, The first via includes a first sidewall and a second sidewall, wherein the first sidewall and the second sidewall are respectively located on two sides of the first metal portion in a direction perpendicular to the extending direction of the first metal line. The second metal portion covers a portion of the first sidewall, and the third metal portion covers a portion of the second sidewall.

12. The array substrate of any of claims 4-11, wherein, The first conductive layer and the first metal layer have a second insulating layer therebetween; the second insulating layer includes a first insulating portion and a second insulating portion located at the periphery of the first insulating portion; the orthographic projection of the first insulating portion on the substrate overlaps the orthographic projection of the first via on the substrate.

13. The array substrate of claim 12, wherein, The first insulating portion and the second insulating portion are in an integral connection structure.

14. The array substrate of claim 12, wherein, At least one side of the second insulating portion in a direction perpendicular to the extending direction of the first metal line has a first gap with the first insulating portion.

15. The array substrate of claim 14, wherein, The orthographic projection of the first gap and the second metal portion on the substrate is located on the same side of the orthographic projection of the first metal portion on the substrate.

16. The array substrate of claim 14 or 15, wherein, At the position of the first via, the first gap extends from the surface of the second insulating layer away from the substrate to the bottom of the first via.

17. The array substrate of claim 14 or 15, wherein, At the position of the first via, the first gap extends from the surface of the second insulating layer away from the substrate to the first metal line.

18. The array substrate of any one of claims 14-17, wherein, The first shielding portion covers the first insulating portion, covers a portion of the second insulating portion at the periphery of the first insulating portion, and fills at least a portion of the first gap.

19. The array substrate of any one of claims 12-18, wherein, The first insulating portion has a first recessed portion recessed toward the substrate at a position corresponding to the first metal portion, and has a first protruding portion protruding away from the substrate at positions corresponding to the second metal portion and the third metal portion.

20. The array substrate of claim 19, wherein, The distance between the first protruding portion and the substrate is greater than the distance between the second insulating portion and the substrate.

21. The array substrate of claim 19 or 20, wherein, The first shielding portion has a second recessed portion at a position corresponding to the first recessed portion, and has a second protruding portion at a position corresponding to the first protruding portion.

22. The array substrate of any of claims 1-7, 8-21, wherein, The line width of the first metal line is less than the width of the first via in a direction perpendicular to the extending direction of the first metal line.

23. The array substrate of any of claims 1-22, wherein, The minimum distance between the outer edge of the first shielding portion and the outer edge of the first via in the first direction in the orthographic projection of the substrate is greater than 0.52 μm.

24. The array substrate of any of claims 1-23, wherein, The array substrate further comprises a second conductive layer on the side of the first conductive layer away from the first metal layer; the second conductive layer comprises a plurality of first electrodes in the pixel region; The first electrode is electrically connected to the third portion through the conductive portion.

25. The array substrate of any one of claims 1-24, wherein, The array substrate further comprises a second metal layer between the first active layer and the first metal layer, and a third metal layer on the side of the first active layer facing the substrate; The second metal layer comprises a plurality of second metal lines extending in a first direction; the third metal layer comprises a plurality of shielding patterns; the shielding patterns in the orthographic projection of the substrate cover the first via in the orthographic projection of the substrate.

26. The array substrate of claim 25, wherein, The shielding patterns in the orthographic projection of the substrate cover the first shielding portion in the orthographic projection of the substrate.

27. The array substrate of any of claims 1-26, wherein, The first metal lines extend in a second direction; The first portion comprises a first sub-portion extending in the second direction, and a second sub-portion connected to the first sub-portion and extending in a third direction; the second portion is connected to one end of the second sub-portion away from the first sub-portion, and the third portion is connected to one end of the first sub-portion away from the second sub-portion. The first metal lines comprise first sub-metal portions and second sub-metal portions arranged alternately in the second direction; the first sub-metal portions and the second sub-metal portions extend in different directions; 28. The array substrate of any of claims 1-27, wherein, The second sub-metal portions in the orthographic projection of the substrate overlap the first via in the orthographic projection of the substrate; the first portion extends in the same direction as the first sub-metal portions. The array substrate further comprises a third signal line and a fourth signal line in the peripheral region; the third signal line is in the same layer as the first metal lines; the fourth signal line has a third insulating layer between the third signal line; the third insulating layer has a plurality of second vias; 29. The array substrate of any of claims 1-28, wherein, The third signal line is electrically connected through the second vias; The first conductive layer further comprises a plurality of second shielding portions; The second shielding portions in the orthographic projection of the substrate cover the second vias in the orthographic projection of the substrate. The array substrate further comprises a second active layer on the side of the first active layer facing the substrate, a driving source electrode on the side of the second active layer away from the substrate, a driving drain electrode, and a driving gate electrode; 30. The array substrate of any of claims 1-29, wherein, The material of the first active layer comprises metal oxide; the material of the second active layer comprises low-temperature polysilicon. The array substrate as claimed in any one of claims 1-30, further comprising a counter substrate arranged opposite to the array substrate.

31. A display panel, wherein, The display panel as claimed in claim 31.

32. A display device comprising: ​

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