Display module and drive method therefor, and electronic device

Abstract

A display module (40) and a drive method therefor, and an electronic device (1), relating to the technical field of electronics, and being used for designing the display module (40) having low power consumption. When the display module (40) is designed, a drive circuit in the display module (40) is set to comprise a first drive sub-circuit (121I) and a second drive sub-circuit (121II) that can be independently driven. During partial display, gate start signals (STV) corresponding to the first drive sub-circuit (121I) and the second drive sub-circuit (121II) are independently input. A valid gate start signal is input into the first drive sub-circuit (121I), and an invalid gate start signal is input into the second drive sub-circuit (121II), so as to achieve independent driving of the first drive sub-circuit (121I) and the second drive sub-circuit (121II). On this basis, a clock signal corresponding to the first drive sub-circuit (121I) toggles at a normal frequency, and a clock signal corresponding to the second drive sub-circuit (121II) does not toggle or toggles at a reduced frequency, thus achieving different clock signal inputs, and reducing the power consumption of the display module.

Description

Display module, driving method thereof and electronic device

[0001] The present application claims priority to the Chinese patent application No. 202410726930.9, filed on June 5, 2024, and entitled "Display module, driving method thereof and electronic device", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the technical field of electronics, and in particular to a display module, a driving method thereof and an electronic device. BACKGROUND

[0003] With the diversification of the form and use scene of electronic devices, the size of the display module is gradually expanding. The larger the display module is, the more the display power consumption increases, which affects the overall endurance of the electronic device. Therefore, the demand for low power consumption of the display module has become a new design improvement point in the display field.

[0004] Therefore, how to design a low-power display module is a problem to be solved by those skilled in the art. SUMMARY

[0005] The present application provides a display module, a driving method thereof and an electronic device, which are used to design a low-power display module.

[0006] To achieve the above-mentioned purpose, the present application adopts the following technical solutions:

[0007] In a first aspect, the present application provides a display module, which includes a first driving circuit and a first display driving integrated circuit. The first driving circuit includes a plurality of cascaded first shift registers and a plurality of cascaded second shift registers. The plurality of cascaded first shift registers are used to output a gate scanning signal for controlling a first display partition, and the plurality of cascaded second shift registers are used to output a gate scanning signal for controlling a second display partition. The first display driving integrated circuit includes a first gate start signal terminal and a second gate start signal terminal. The first gate start signal terminal is coupled to the input terminal of the first stage first shift register, and the second gate start signal terminal is coupled to the input terminal of the first stage second shift register. The first gate start signal terminal and the second gate start signal terminal are located at different sides of the first display driving integrated circuit.

[0008] The display module provided by the embodiment of the present application comprises a first driving circuit, the first driving circuit comprises a first driving sub-circuit and a second driving sub-circuit, the first driving sub-circuit comprises a plurality of cascaded first shift registers, and the second driving sub-circuit comprises a plurality of cascaded second shift registers. The first driving sub-circuit is controlled by a first gate start signal provided by a first gate start signal terminal in the first display driving integrated circuit, and the second driving sub-circuit is controlled by a second gate start signal provided by a second gate start signal terminal in the first display driving integrated circuit, so that the first driving sub-circuit and the second driving sub-circuit are independently controlled in different zones, and the power consumption of the display module is reduced. The first gate start signal terminal and the second gate start signal terminal are located on different sides of the first display driving integrated circuit, the signal terminals on both sides of the first display driving integrated circuit can be utilized, the change of the existing layout design of the display module is small, and the difficulty of process implementation is reduced.

[0009] In a possible implementation, the first display driving integrated circuit further comprises a first data signal terminal, the first data signal terminal is coupled with the data line, and the first data signal terminal is arranged between the first gate start signal terminal and the second gate start signal terminal. By arranging the first gate start signal terminal and the second gate start signal terminal for providing the first gate start signal and the second gate start signal on both sides of the first data signal terminal, the signal terminals on both sides of the first display driving integrated circuit can be utilized, the change of the existing layout design of the display module is small, and the difficulty of process implementation is reduced.

[0010] In a possible implementation, the display module further comprises a plurality of connection lines, the plurality of connection lines and the data line are arranged in different layers; the input terminal of the first stage first shift register and the first gate start signal terminal are coupled through the connection line, and the input terminal of the first stage second shift register and the second gate start signal terminal are coupled through the connection line. By arranging the connection line and the data line in different layers, the jumper difficulty at the intersection position of the connection line and the data line can be reduced, and the preparation process is simplified.

[0011] In a possible implementation, the display module further comprises a shielding layer, the shielding layer is located between the data line and the plurality of connection lines. By arranging the shielding layer between the data line and the connection line, the signal of the data line is shielded, the coupling effect between the data line and the connection line can be reduced, and the noise on the connection line is reduced.

[0012] In a possible implementation, along the thickness direction of the display module, the plurality of connection lines are arranged on the side of the data line facing the first display driving integrated circuit. The data line is usually arranged in the same layer as the source and the drain of the transistor in the pixel circuit, and the connection line is arranged above the data line, so that the process change is reduced and the implementation difficulty is reduced.

[0013] In a possible implementation, the first driving circuit is located at a first side of the display module, the first display driving integrated circuit is located at a second side of the display module, and the second side intersects the first side; the first gate start signal end is closer to the first side than the second gate start signal end; the connection line coupled to the second gate start signal end includes a first segment, a second segment, and a third segment; the first segment is coupled to the second gate start signal end, the third segment is coupled to an input end of the first-stage second shift register, and the second segment is connected between the first segment and the third segment; the second segment is arranged on a side of the first display driving integrated circuit away from an edge of the display module, and the second segment intersects the data line. In the region on the side of the first display driving integrated circuit facing the pixel array, the wiring structure above the data line is simple. Therefore, the connection line is arranged in the region on the side of the first display driving integrated circuit facing the pixel array, and the process difficulty is low and the preparation cost is low.

[0014] In a possible implementation, the connection lines for transmitting low-level active signals are arranged adjacently, and the connection lines for transmitting high-level active signals are arranged adjacently. Because the signals of some gate start signal ends are high-level start signals, and the signals of some gate start signal ends are low-level start signals. Therefore, the connection lines for transmitting low-level active signals are arranged adjacently, and the connection lines for transmitting high-level active signals are arranged adjacently, to avoid cross arrangement, so that the spacing between the connection lines can be reduced, to reduce the layout area.

[0015] In a possible implementation, the spacing between adjacent connection lines is greater than or equal to ΔV / 0.5 um, and ΔV is the potential difference of signals on adjacent connection lines. This arrangement meets the requirement of weakening signal interference.

[0016] In a possible implementation, the display module further includes a second driving circuit, for example, the second driving circuit is located at the same side of the display module as the first driving circuit; the second driving circuit includes a plurality of cascaded third shift registers and a plurality of cascaded fourth shift registers; the plurality of cascaded third shift registers are configured to output gate scanning signals for controlling a first display subregion, and the plurality of cascaded fourth shift registers are configured to output gate scanning signals for controlling a second display subregion; the first display driving integrated circuit further includes a third gate start signal end and a fourth gate start signal end; the third gate start signal end is coupled to an input end of the first-stage third shift register, and the fourth gate start signal end is coupled to an input end of the first-stage fourth shift register. The display module can be provided with a plurality of driving circuits that can be controlled in subregions, to further save the power consumption of the display module.

[0017] In a possible implementation, the at least one first gate start signal terminal, the second gate start signal terminal, the third gate start signal terminal, and the fourth gate start signal terminal are located at different sides of the first display driving integrated circuit. The display module can include a plurality of driving circuits, and the correspondence between the plurality of driving circuits and the ports of the first display driving integrated circuit can be variously set.

[0018] In a possible implementation, the display module further includes a second display driving integrated circuit, and the second display driving integrated circuit is arranged side by side with the first display driving integrated circuit. The display module can be a display module including a plurality of display driving integrated circuits to meet various requirements.

[0019] In a possible implementation, the display module further includes a third driving circuit, the third driving circuit is located at a different side of the display module from the first driving circuit, the third driving circuit includes a plurality of cascaded fifth shift registers and a plurality of cascaded sixth shift registers, the plurality of cascaded fifth shift registers are configured to output gate scanning signals for controlling the first display sub-area, and the plurality of cascaded sixth shift registers are configured to output gate scanning signals for controlling the second display sub-area. The display module can be provided with driving circuits on multiple sides to meet the driving requirements of large screens.

[0020] In a possible implementation, the second display driving integrated circuit includes a fifth gate start signal terminal and a sixth gate start signal terminal, the fifth gate start signal terminal is coupled to an input terminal of a first-stage fifth shift register, and the sixth gate start signal terminal is coupled to an input terminal of a first-stage sixth shift register. The driving circuits located at different sides can be provided with start signals by display driving integrated circuits at different positions, and the layout of the display module is simplified.

[0021] In a possible implementation, the fifth gate start signal terminal and the sixth gate start signal terminal are located at different sides of the second display driving integrated circuit. In this way, the signal terminals at different positions of the second display driving integrated circuit can be utilized, the change to the existing layout design of the display module is small, and the process implementation difficulty is reduced.

[0022] In a possible implementation, the second display driving integrated circuit further includes a second data signal terminal, the second data signal terminal is coupled to a data line, and the second data signal terminal is arranged between the fifth gate start signal terminal and the sixth gate start signal terminal. In this way, the signal terminals on both sides of the second display driving integrated circuit can be utilized, the change to the existing layout design of the display module is small, and the process implementation difficulty is reduced.

[0023] In a possible implementation, the display module further includes a fourth driving circuit, the fourth driving circuit is located on the same side of the display module as the third driving circuit; the fourth driving circuit includes a plurality of cascaded seventh shift registers and a plurality of cascaded eighth shift registers; the plurality of cascaded seventh shift registers are configured to output a gate scanning signal for controlling the first display subregion, and the plurality of cascaded eighth shift registers are configured to output a gate scanning signal for controlling the second display subregion; the second display driving integrated circuit further includes a seventh gate start signal terminal and an eighth gate start signal terminal; the seventh gate start signal terminal is coupled to an input terminal of a first-stage seventh shift register, and the eighth gate start signal terminal is coupled to an input terminal of a first-stage eighth shift register. The display module can be provided with a plurality of subregion-controlled driving circuits, further reducing the power consumption of the display module.

[0024] In a possible implementation, the at least one fifth gate start signal terminal, the sixth gate start signal terminal, the seventh gate start signal terminal, and the eighth gate start signal terminal are located on different sides of the second display driving integrated circuit. Both sides of the display module can include a plurality of driving circuits, and the correspondence between the plurality of driving circuits and the ports in the first display driving integrated circuit and the second display driving integrated circuit can be variously set.

[0025] In a possible implementation, the first driving circuit and the third driving circuit are configured to transmit the same gate scanning signal. The first driving circuit and the third driving circuit can be configured to control the same type of transistor in the pixel circuit, and are suitable for various application scenarios.

[0026] In a possible implementation, the first driving circuit and the third driving circuit are configured to transmit different gate scanning signals. The first driving circuit and the third driving circuit can also be configured to control the same type of transistor in the pixel circuit, and are suitable for various application scenarios.

[0027] In a possible implementation, the display module further includes a power voltage terminal, and the first shift register and the second shift register are coupled to the power voltage terminal. In this way, the structure of the display module can be simplified.

[0028] In a possible implementation, the first display driving integrated circuit further includes a clock signal terminal, and the first shift register and the second shift register are coupled to the clock signal terminal. In this way, the structure of the display module can be simplified.

[0029] In a second aspect, the embodiment of the present application provides a display module, which comprises: a first driving circuit comprising a plurality of cascaded first shift registers and a plurality of cascaded second shift registers, the plurality of cascaded first shift registers being configured to output a gate scanning signal for controlling a first display partition, and the plurality of cascaded second shift registers being configured to output a gate scanning signal for controlling a second display partition; a second driving circuit, which is located at a different side of the display module from the first driving circuit, and comprises a plurality of cascaded third shift registers and a plurality of cascaded fourth shift registers, the plurality of cascaded third shift registers being configured to output a gate scanning signal for controlling the first display partition, and the plurality of cascaded fourth shift registers being configured to output a gate scanning signal for controlling the second display partition; a first display driving integrated circuit configured to provide a first gate start signal for a first-stage first shift register and a second gate start signal for a first-stage second shift register; and a second display driving integrated circuit configured to provide a third gate start signal for a first-stage third shift register and a fourth gate start signal for a first-stage fourth shift register.

[0030] The display module provided by the embodiment of the present application comprises the first driving circuit comprising the plurality of cascaded first shift registers and the plurality of cascaded second shift registers, and the plurality of cascaded first shift registers and the plurality of cascaded second shift registers are respectively controlled by the first gate start signal and the second gate start signal provided by the first display driving integrated circuit. The second driving circuit comprises the plurality of cascaded third shift registers and the plurality of cascaded fourth shift registers, and the plurality of cascaded third shift registers and the plurality of cascaded fourth shift registers are respectively controlled by the fifth gate start signal and the sixth gate start signal provided by the second display driving integrated circuit. The partition independent control of the first driving circuit and the second driving circuit is achieved, and even each driving circuit in the display module can be partitioned and independently controlled. The power consumption of the plurality of driving circuits in the display module can be saved, thereby greatly reducing the power consumption of the display module.

[0031] In a possible implementation, the first display driving integrated circuit comprises a first gate start signal terminal and a second gate start signal terminal; the first gate start signal terminal is coupled with an input terminal of the first-stage first shift register, and the second gate start signal terminal is coupled with an input terminal of the first-stage second shift register; and the first gate start signal terminal and the second gate start signal terminal are located at different sides of the first display driving integrated circuit. The first gate start signal terminal and the second gate start signal terminal are located at different sides of the first display driving integrated circuit, so that the signal terminals at both sides of the first display driving integrated circuit can be utilized, the change to the existing layout design of the display module is small, and the process implementation difficulty is reduced.

[0032] In a possible implementation, the second display driving integrated circuit includes a third gate start signal terminal and a fourth gate start signal terminal, the third gate start signal terminal is coupled with an input terminal of the first-stage third shift register, and the fourth gate start signal terminal is coupled with an input terminal of the first-stage fourth shift register; the third gate start signal terminal and the fourth gate start signal terminal are located at different sides of the second display driving integrated circuit. The third gate start signal terminal and the fourth gate start signal terminal are located at different sides of the second display driving integrated circuit, so that the signal terminals at both sides of the second display driving integrated circuit can be used, the change to the existing layout design of the display module is small, and the process implementation difficulty is reduced.

[0033] In a possible implementation, the display module further includes a third driving circuit; the third driving circuit is located at the same side of the display module as the first driving circuit; the third driving circuit includes a plurality of cascaded fifth shift registers and a plurality of cascaded sixth shift registers; the plurality of cascaded fifth shift registers are configured to output a gate scanning signal for controlling the first display sub-area, and the plurality of cascaded sixth shift registers are configured to output a gate scanning signal for controlling the second display sub-area; the first display driving integrated circuit is configured to provide a fifth gate start signal for the first-stage fifth shift register and a sixth gate start signal for the first-stage sixth shift register. The display module can be provided with a plurality of driving circuits that can be controlled in sub-areas, and the power consumption of the display module is further saved.

[0034] In a possible implementation, the first display driving integrated circuit further includes a fifth gate start signal terminal and a sixth gate start signal terminal, the fifth gate start signal terminal is coupled with an input terminal of the first-stage fifth shift register, and the sixth gate start signal terminal is coupled with an input terminal of the first-stage sixth shift register; at least one of the first gate start signal terminal, the second gate start signal terminal, the fifth gate start signal terminal, and the sixth gate start signal terminal is located at a different side of the first display driving integrated circuit. The display module can include a plurality of driving circuits, and the correspondence between the plurality of driving circuits and the ports in the first display driving integrated circuit can be diversified.

[0035] In a possible implementation, the display module further includes a fourth driving circuit, the fourth driving circuit is located at the same side of the display module as the second driving circuit; the fourth driving circuit includes a plurality of cascaded seventh shift registers and a plurality of cascaded eighth shift registers; the plurality of cascaded seventh shift registers are configured to output a gate scanning signal for controlling the first display sub-area, and the plurality of cascaded eighth shift registers are configured to output a gate scanning signal for controlling the second display sub-area; the second display driving integrated circuit is configured to provide a seventh gate start signal for the first-stage seventh shift register and an eighth gate start signal for the first-stage eighth shift register. The display module can be provided with a plurality of driving circuits that can be controlled in sub-areas, and the power consumption of the display module is further saved.

[0036] In a possible implementation, the second display driving integrated circuit further includes a seventh gate start signal terminal and an eighth gate start signal terminal; the seventh gate start signal terminal is coupled with an input terminal of the first-stage seventh shift register, and the eighth gate start signal terminal is coupled with an input terminal of the first-stage eighth shift register; the at least one third gate start signal terminal, the fourth gate start signal terminal, the seventh gate start signal terminal, and the eighth gate start signal terminal are located at different sides of the second display driving integrated circuit. The display module can include a plurality of driving circuits, and the correspondence between the plurality of driving circuits and the ports in the first display driving integrated circuit can be variously set.

[0037] In a possible implementation, the first driving circuit and the second driving circuit are configured to transmit the same gate scanning signal. The first driving circuit and the second driving circuit can be configured to control the same type of transistor in the pixel circuit, and are suitable for various application scenarios.

[0038] In a possible implementation, the first driving circuit and the second driving circuit are configured to transmit different gate scanning signals. The first driving circuit and the second driving circuit can also be configured to control the same type of transistor in the pixel circuit, and are suitable for various application scenarios.

[0039] In a third aspect, an electronic device is provided. The electronic device includes a driving controller and a display module, and the driving controller is coupled with the display module. The display module includes the display module of any one of the first aspect. Alternatively, the display module includes the display panel and the display driving integrated circuit of the second aspect.

[0040] In a possible implementation, the driving controller is configured to output an image signal to the display driving integrated circuit; the image signal includes coordinate information of a scanning start row and a scanning stop row, and a data signal.

[0041] In a fourth aspect, the embodiment of the present application provides a driving method of a display module. The display module comprises a first driving circuit and a first display driving integrated circuit. The first driving circuit comprises a plurality of cascaded first shift registers and a plurality of cascaded second shift registers. The driving method of the display module comprises: in a first time period of an image frame, a first-stage first shift register receives an opening signal of a first gate start signal terminal, an N-stage first shift register receives a signal of an output terminal of an (N-1)-stage first shift register; each first shift register receives a first clock signal of a first clock signal terminal; each first shift register outputs a scanning opening signal; N is an integer greater than 1; a frequency of the first clock signal is a first frequency. In a second time period of the image frame, a first-stage second shift register receives a closing signal of a second gate start signal terminal, an M-stage second shift register receives a signal of an output terminal of an (M-1)-stage second shift register; each second shift register receives a second clock signal of the first clock signal terminal or a fixed voltage signal; each second shift register outputs a scanning closing signal; M is an integer greater than 1; a frequency of the second clock signal is a second frequency, and the second frequency is less than the first frequency.

[0042] The driving method of the display module provided by the embodiment of the present application can reduce the driving power consumption of the display module in the local display scenario by closing the signal of the clock signal terminal or reducing the frequency of the signal of the clock signal terminal, and the effect of display power consumption optimization can be achieved.

[0043] In a possible implementation, the display module further comprises a second driving circuit, the second driving circuit comprises a plurality of cascaded third shift registers and a plurality of cascaded fourth shift registers. In the first time period, a first-stage third shift register receives an opening signal of a third gate start signal terminal, an O-stage third shift register receives a signal of an output terminal of an (O-1)-stage third shift register; each third shift register receives a third clock signal of a second clock signal terminal; each third shift register outputs a scanning opening signal; O is an integer greater than 1. In the second time period, a first-stage fourth shift register receives an opening signal of a fourth gate start signal terminal, a P-stage fourth shift register receives a signal of an output terminal of a (P-1)-stage fourth shift register; each fourth shift register receives a third clock signal of the second clock signal terminal; each fourth shift register outputs a scanning opening signal; P is an integer greater than 1. In the case that the display module comprises a plurality of driving circuits, the driving circuit can also be kept normal refreshing in the split-screen display. BRIEF DESCRIPTION OF DRAWINGS

[0044] FIG. 1 is a structural schematic diagram of an electronic device provided by an embodiment of the present application;

[0045] FIG. 2 is a topological structure schematic diagram of a pixel circuit provided by an embodiment of the present application;

[0046] FIG. 3A is a structural schematic diagram of a display module according to an embodiment of the present application;

[0047] FIG. 3B is a structural schematic diagram of an EOA according to an embodiment of the present application;

[0048] FIG. 3C is an output waveform diagram of an EOA and a GOA according to an embodiment of the present application;

[0049] FIG. 4A is a structural schematic diagram of a display module according to an embodiment of the present application;

[0050] FIG. 4B is a structural schematic diagram of an EOA according to an embodiment of the present application;

[0051] FIG. 4C is an output waveform diagram of an EOA and a GOA according to an embodiment of the present application;

[0052] FIG. 5 is a structural schematic diagram of a GOA according to an embodiment of the present application;

[0053] FIG. 6 is a structural schematic diagram of a display module according to an embodiment of the present application;

[0054] FIG. 7 is a structural schematic diagram of a display module according to an embodiment of the present application;

[0055] FIG. 8A and FIG. 8B are structural schematic diagrams of a display module according to an embodiment of the present application;

[0056] FIG. 9 is a sectional view along A1-A2 direction in FIG. 8B according to an embodiment of the present application;

[0057] FIG. 10A-FIG. 10E are structural schematic diagrams of a display module according to an embodiment of the present application;

[0058] FIG. 11A-FIG. 11C are structural schematic diagrams of a display module according to an embodiment of the present application;

[0059] FIG. 12A-FIG. 12B are structural schematic diagrams of a display module according to an embodiment of the present application;

[0060] FIG. 13A and FIG. 13B are structural schematic diagrams of a display module according to an embodiment of the present application;

[0061] FIG. 14 is a structural schematic diagram of a display module according to an embodiment of the present application;

[0062] FIG. 15A-FIG. 15D are display scene schematic diagrams according to an embodiment of the present application;

[0063] FIG. 16A-FIG. 16E are morphological schematic diagrams of a display panel according to an embodiment of the present application;

[0064] FIGS. 17A-17D are driving timing diagrams of a display panel according to an embodiment of the present application;

[0065] FIG. 18 is a signal transmission diagram in a partitioned display according to an embodiment of the present application;

[0066] FIG. 19 is a driving logic diagram in a partitioned display according to an embodiment of the present application. DETAILED DESCRIPTION

[0067] The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all of the embodiments of the present application.

[0068] Hereinafter, the terms "second", "first", and the like are only used for description convenience, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "second", "first", and the like can explicitly or implicitly include one or more of the features. In the description of the present application, unless otherwise specified, the meaning of "a plurality of" is two or more.

[0069] In addition, in the embodiments of the present application, the orientation terms such as "upper", "lower", "left", "right", and the like can include but not limited to the orientation defined by the relative placement of the components in the drawings. It should be understood that these directional terms can be relative concepts, which are used for relative description and clarification, and can be changed accordingly according to the change of the placement of the components in the drawings.

[0070] In the embodiments of the present application, unless otherwise specified and limited, the term "connection" should be understood in a broad sense, for example, "connection" can be fixed connection, or detachable connection, or integral; can be directly connected, or indirectly connected through an intermediate medium. In addition, the term "coupling" can be direct electrical connection, or indirect electrical connection through an intermediate medium. The term "contact" can be direct contact, or indirect contact through an intermediate medium.

[0071] In the embodiments of the present application, "and / or" describes the association relationship between the associated objects, which means that there can be three kinds of relationships, for example, A and / or B, which can represent the following three cases: A exists alone, A and B exist together, and B exists alone, where A and B can be singular or plural. The character " / " generally represents an "or" relationship between the associated objects before and after it.

[0072] Embodiments of the present application provide an electronic device, which may, for example, be a foldable electronic device. The electronic device may, for example, be a consumer electronic product, a home electronic product, a vehicle-mounted electronic product, or a financial electronic product. The consumer electronic product may, for example, be a mobile phone, a pad, a notebook computer, an e-reader, a personal computer (PC), a personal digital assistant (PDA), a desktop display, a smart wearable product (for example, a smart watch, a smart bracelet), a virtual reality (VR) electronic device, an augmented reality (AR) electronic device, a drone, and the like. The home electronic product may, for example, be a smart door lock, a television, a refrigerator, a charging household small appliance (for example, a soybean milk machine, a sweeping robot), and the like. The vehicle-mounted electronic product may, for example, be a vehicle-mounted navigation device, a vehicle-mounted DVD, and the like. The financial electronic product may, for example, be an ATM machine, a self-service electronic device, and the like.

[0073] Embodiments of the present application do not specially limit the specific form of the electronic device, and the following embodiments are exemplarily described by taking a mobile phone as an example.

[0074] FIG. 1 is a structural schematic diagram of an electronic device according to an embodiment of the present application.

[0075] As shown in FIG. 1, the electronic device 1 includes a display module 40 and a driving controller 30. In FIG. 1, a terminal 1 is exemplarily taken as a straight-screen mobile phone, and the present application only exemplarily takes the terminal 1 as a straight-screen mobile phone in the embodiments.

[0076] The driving controller 30 is coupled with the display module 40, and the driving controller 30 receives an image signal RGB and a control signal CTRL. The driving controller 30 outputs an image data signal DATA matched with the interface specification of the display module 40 according to the image signal RGB. The driving controller 30 also outputs a data control signal DCS. The driving controller 30 may, for example, include a system on chips (SOC).

[0077] The display module 40 may, for example, include a display panel 10 and a display driving integrated circuit 20. The display driving integrated circuit 20 may, for example, be coupled with the driving controller 30, receive the signal output by the driving controller 30, and provide a display signal for the display panel 10.

[0078] For example, the display drive integrated circuit 20 receives the data control signal DCS and the image data signal DATA from the drive controller 30. The display drive integrated circuit 20 converts the image data signal DATA into a data signal, and outputs the data signal to the plurality of data signal lines DL1-DLm. The data signal is an analog voltage corresponding to the gray scale value of the image data signal DATA. The display drive integrated circuit (DDIC) 20 is also configured to output display required scan control signals SCS (e.g., a clock signal CLK, a gate start signal STV, a reset signal RST, etc.) to the display panel 10.

[0079] In one possible embodiment, the display panel 10 is a liquid crystal display (LCD). Based on this, the electronic device 1 further includes a back light unit (BLU) located at the back of the liquid crystal display panel. The back light unit can provide a light source to the liquid crystal display panel, so that each sub pixel in the liquid crystal display panel can emit light to realize image display.

[0080] In another possible embodiment, the display panel 10 is a self-luminous display module 40 such as an organic light emitting diode (OLED) display module 40, an active-matrix organic light-emitting diode (AMOLED) display module 40, a mini organic light-emitting diode (Mini-OLED) display module 40, a micro light-emitting diode (Micro-LED) display module 40, a micro organic light-emitting diode (Micro-OLED) display module 40, a quantum dot light emitting diodes (QLED) display module 40, etc. At this time, the display panel 10 can be a rigid display panel, and the display panel 10 can also be a flexible display panel.

[0081] For any one of the display panels 10 described above, the display panel 10 includes an active area (AA) and a non-display area (BB) located at the periphery of the active area AA. The active area AA is used to display images, and includes a plurality of sub-pixels (SP), each of which is provided with a pixel circuit 11 that receives a data signal provided by a display driving integrated circuit 20. The non-display area BB includes a driving circuit 12 that receives a scan control signal SCS provided by the display driving integrated circuit 20.

[0082] The pixel circuits 11 in this application are described by way of example in a matrix form. Pixel circuits 11 arranged in a row along the horizontal direction X are referred to as pixel circuits 11 in the same row, and pixel circuits 11 arranged in a row along the vertical direction Y are referred to as pixel circuits 11 in the same column.

[0083] In some embodiments, the pixel circuit 11 generally includes a driving circuit composed of a plurality of transistors and a light-emitting unit, and a driving current is generated by the driving circuit to drive the light-emitting unit to emit light, so as to realize the light emission of the pixel circuit 11.

[0084] In some embodiments, the electronic device 1 further includes a middle frame, and the display panel 10 is arranged on the middle frame and is carried by the middle frame.

[0085] With the diversification of the form and use scenarios of the electronic device 1, the size of the display panel 10 is gradually expanding, and the larger the display panel 10 means that the display power consumption is relatively increased, which affects the overall endurance of the electronic device 1. Therefore, the demand for low-power display panels 10 has become a new design improvement point in the display field. For example, the “picture-in-picture” function is used on a mobile phone product, and a video is suspended on the upper part of the display panel 10, and the lower part is static reading. Or, for example, the “parallel view” is used on a tablet product, and during application use, the left part is mostly static, and the right part dynamically changes with browsing sliding.

[0086] In order to simultaneously support high refresh rate (such as 120Hz) and low refresh rate (such as 1Hz) on the same display panel 10, and smoothly switch between high refresh rate and low refresh rate on any row of the display panel 10, the high mobility of low temperature poly-silicon thin-film transistor (LTPS TFT) and the low leakage characteristics of indium gallium zinc oxide thin-film transistor (IGZO TFT) can be comprehensively utilized in the pixel circuit of the display panel 10, and relevant circuit design is performed. Thus, both the smoothness of high refresh rate and the power consumption saving of low refresh rate are taken into account. The combination of LTPS TFT and IGZO TFT (or referred to as low temperature poly crystalline oxide (LTPO) technology) as the driving circuit of the pixel circuit 11 can simultaneously realize high refresh rate, low refresh rate, and seamless switching between different refresh rates, meet the requirement of dynamic frame change, and has wide application prospect in OLED display panels.

[0087] FIG. 2 is a schematic diagram of a topology structure of a pixel circuit provided in an embodiment of the present application.

[0088] In some embodiments, as shown in FIG. 2, the pixel circuit 11 includes a first node initialization circuit 111, a write-in and threshold compensation circuit 112, a light-emitting control circuit 113, a light-emitting unit 114, an anode reset circuit 115, and a second node initialization circuit 116. The pixel circuit 11 shown in FIG. 2 is only an example and is not limited in any way.

[0089] In the embodiments of the present application, the first power supply voltage terminal ELVDD is taken as a high-level power supply voltage terminal, and the second power supply voltage terminal ELVSS is taken as a low-level power supply voltage terminal, but this is not limited in any way.

[0090] In some embodiments, referring to FIG. 2, the first node initialization circuit 111 includes a fourth transistor M4 and a third transistor M3, the write-in and threshold compensation circuit 112 includes a second transistor M2, a first transistor M1, the third transistor M3, and a storage capacitor Cst, the light-emitting control circuit 113 includes a fifth transistor M5 and a sixth transistor M6, the anode reset circuit 115 includes a seventh transistor M7, and the second node initialization circuit 116 includes an eighth transistor M8. The first transistor M1 is a driving transistor, the other transistors are switching transistors, the first node initialization circuit 111 and the write-in and threshold compensation circuit 112 share the third transistor M3, and the light-emitting unit 114 is, for example, an OLED.

[0091] In the following description, the control electrode of a transistor can be, for example, a gate of the transistor, and a first electrode and a second electrode of the transistor can be a source and a drain of the transistor. Note that the following description will not be repeated here.

[0092] The control electrode of the fourth transistor M4 is coupled to an initialization scan signal line SC, a first electrode of the fourth transistor M4 is coupled to a first initialization voltage line Vinit1, and a second electrode of the fourth transistor M4 is coupled to a fourth node N4.

[0093] The control electrode of the third transistor M3 is coupled to a compensation scan signal line SB, a first electrode of the third transistor M3 is coupled to the fourth node N4, and a second electrode of the third transistor M3 is coupled to a node N.

[0094] The control electrode of the second transistor M2 is coupled to a write scan signal line SX, a first electrode of the second transistor M2 is coupled to a data voltage line Vdata, and a second electrode of the second transistor M2 is coupled to a third node N3.

[0095] The control electrode of the first transistor M1 is coupled to the node N, a first electrode of the first transistor M1 is coupled to the third node N3, and a second electrode of the first transistor M1 is coupled to a second node N2. The second node N2 is also coupled to the fourth node N4.

[0096] One end of a storage capacitor Cst is coupled to the node N, and the other end of the storage capacitor Cst is coupled to a first power supply voltage line ELVDD.

[0097] The control electrode of the fifth transistor M5 is coupled to an emission control signal line EM, a first electrode of the fifth transistor M5 is coupled to the first power supply voltage line ELVDD, and a second electrode of the fifth transistor M5 is coupled to the third node N3.

[0098] The control electrode of the sixth transistor M6 is coupled to the emission control signal line EM, a first electrode of the sixth transistor M6 is coupled to the second node N2, and a second electrode of the sixth transistor M6 is coupled to an anode of the light emitting unit 114. A cathode of the light emitting unit 114 is coupled to a second power supply voltage line ELVSS.

[0099] The control electrode of the seventh transistor M7 is coupled to a reset control signal line SF, a first electrode of the seventh transistor M7 is coupled to a second initialization voltage line Vinit2, and a second electrode of the seventh transistor M7 is coupled to the anode of the light emitting unit 114.

[0100] The control electrode of the eighth transistor M8 is coupled to the reset control signal line SF, a first electrode of the eighth transistor M8 is coupled to a third initialization voltage line Vinit3, and a second electrode of the eighth transistor M8 is coupled to the second node N2.

[0101] For example, in the pixel circuit 11, the third transistor M3 and the fourth transistor M4 are IGZO TFTs, and are N-type transistors, which are turned on under the control of a high-level signal. The third transistor M3 and the fourth transistor M4 can also be other types of transistors, which are not limited in the embodiments of the present application. The first transistor M1, the second transistor M2, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 are LTPS TFTs, and are P-type transistors, which are turned on under the control of a low-level signal.

[0102] The initialization scan signal end SC of the pixel circuit 11 is coupled with the initialization scan signal line SCL, the compensation scan signal end SB of the pixel circuit 11 is coupled with the compensation scan signal line SBL, the write scan signal end SX of the pixel circuit 11 is coupled with the write scan signal line SXL, the light-emitting control signal end EM of the pixel circuit 11 is coupled with the light-emitting control scan signal line EML, and the reset scan signal end SF of the pixel circuit 11 is coupled with the reset scan signal line SFL. The data voltage end Vdata of the pixel circuit 11 is coupled with the data signal line DL. The voltages of the first initialization voltage end Vinit1, the second initialization voltage end Vinit2, the third initialization voltage end Vinit3, the first power voltage end ELVDD, and the second power voltage end ELVSS can be provided by a voltage generator in the electronic device.

[0103] For example, the compensation scan signal line SBL in the scan signal line is taken as an example, and in FIG. 1, one row of pixel circuits 11 is taken as an example and is coupled with the same compensation scan signal line SBL, and the same row of pixel circuits 11 can also be coupled with multiple compensation scan signal lines SBL. For example, the pixel circuits 11 in the left half of the row are coupled with one compensation scan signal line SBL, and the pixel circuits 11 in the right half of the row are coupled with another compensation scan signal line SBL. Similarly, in FIG. 1, the same column of pixel circuits 11 is taken as an example and is coupled with the same data signal line DL, and the same column of pixel circuits 11 can also be coupled with multiple data signal lines DL. For example, the pixel circuits 11 in the upper half of the column are coupled with one data signal line DL, and the pixel circuits 11 in the lower half of the column are coupled with another data signal line DL.

[0104] The drive circuit 12 receives a scan control signal SCS from the drive controller 30. The drive circuit 12 can output a scan signal to a scan signal line in response to the scan control signal SCS. The scan signal line includes, for example, an initialization scan signal line SCL1-SCLn, a compensation scan signal line SBL1-SBLn, a write scan signal line SXL1-SXLn, a reset scan signal line SFL1-SFLn, and an emission control scan signal line EML1-EMLn. The drive circuit 12 can output an initialization scan signal to the initialization scan signal line SCL1-SCLn, a compensation scan signal to the compensation scan signal line SBL1-SBLn, a write scan signal to the write scan signal line SXL1-SXLn, a reset scan signal to the reset scan signal line SFL1-SFLn, and an emission control signal to the emission control scan signal line EML1-EMLn in response to the scan control signal SCS.

[0105] The drive circuit 12 can be, for example, a gate driver on array (GOA) and / or an emission circuit on array (EOA). The EOA outputs an emission control signal to the emission control scan signal line EML1-EMLn, and the GOA outputs an initialization scan signal to the initialization scan signal line SCL1-SCLn, a compensation scan signal to the compensation scan signal line SBL1-SBLn, a write scan signal to the write scan signal line SXL1-SXLn, and a reset scan signal to the reset scan signal line SFL1-SFLn. For example, a gate initialization driver GOA1 outputs an initialization scan signal to the initialization scan signal line SCL1-SCLn and controls the fourth transistor M4 in the pixel circuit 11. A gate compensation driver GOA2 outputs a compensation scan signal to the compensation scan signal line SBL1-SBLn and controls the third transistor M3 in the pixel circuit 11. A gate write driver GOA3 outputs a write scan signal to the write scan signal line SXL1-SXLn and controls the second transistor M2 in the pixel circuit 11. A gate reset driver GOA4 outputs a reset scan signal to the reset scan signal line SFL1-SFLn and controls the seventh transistor M7 in the pixel circuit 11. When the gate of the eighth transistor M8 is also controlled by the reset scan signal line SFL1-SFLn, the gate reset driver GOA4 also controls the eighth transistor M8 in the pixel circuit 11.

[0106] FIG. 3A is a structural schematic diagram of a display module provided by an embodiment of the present application, FIG. 3B is a structural schematic diagram of an EOA provided by an embodiment of the present application, and FIG. 3C is an output waveform diagram of an EOA and a GOA provided by an embodiment of the present application.

[0107] In some embodiments, as shown in FIG. 3A, a display module 40 with a folding function is illustrated, and the display panel 10 included in the display module 40 has a folding function and includes a folding boundary. Taking the EOA circuit in the display panel 10 as an example, the two sides of the active display area AA can be provided with an EOA, and one row of pixel circuits 11 is driven by two EOAs. Each EOA is coupled with a DDIC, and the edge pin of the DDIC is used to provide a signal or a power supply to the EOA, and the internal pin of the DDIC is used to provide a signal to the data signal line DL.

[0108] As shown in FIG. 3B, for the display panel 10 with the folding function, the structure of the EOA included in the display panel 10 is the same as that of the EOA of the conventional non-folding display panel 10, and the different display areas are not controlled by partitioning.

[0109] The EOA includes at least two cascaded shift registers RS(1) to RS(n). The signal input end STVI of the first-level shift register RS(1) is used to receive a gate start (STV) signal. Except for the first-level shift register RS(1), the signal input end STVI of each shift register RS(m) is coupled with the output end GO of the previous shift register RS(m-1). Except for the last-level shift register, the reset signal end RST of each shift register RS(m) is coupled with the output end GO of the next shift register RS(m+1). The reset signal end RST of the last-level shift register RSn receives the STV signal. When the STV signal is an enable signal, the first-level shift register RS1 of the driving circuit 12 starts to work, and then the multi-level shift registers start to work level by level.

[0110] The design of the GOA in the display panel 10 is the same as that of the EOA described above, and the number of the GOA is different according to the structure of the pixel circuit 11.

[0111] As shown in FIG. 3C, no matter how the active display area AA displays a picture, the EOA and the GOA in the display panel 10 always keep row-by-row output.

[0112] In the inner folding use scenario, the display panel 10 is used as a whole, and there is no need to control different regions of the display separately. For the outer folding use scenario, there is a scenario where part of the display panel 10 is used separately. If the traditional architecture is adopted, the EOA and the GOA are not controlled separately for different partition positions of the folding screen, and the non-display region cannot be closed during partition display. The actual driving power consumption during partition display is close to that during full-screen display, and the driving power consumption during partition display cannot be optimized, which affects the overall endurance of the electronic device 1.

[0113] With the diversification of the form and use scenario of the electronic device 1, the size of the display panel 10 is gradually expanding, and the larger the display panel 10 means the relative increase of display power consumption, which affects the overall endurance of the electronic device 1. Therefore, the demand for low power consumption of the display panel 10 has become a new design improvement point in the display field.

[0114] At present, the person skilled in the art proposes to make the display panel have the function of partition display, and to reduce the power consumption of the display panel by partition refreshing of the display panel. Partition display can save the power consumption of the electronic device 1, for example, in an outer folding screen, a multi-folding screen, or other scenarios that realize partition display applications.

[0115] In some embodiments, in order to realize partition display, the EOA in the display panel 10 is divided into two or more parts, and different STV signals are used to drive the EOA of different parts to control the display of different regions of the display panel 10.

[0116] FIG. 4A is a structural schematic diagram of a display module provided by an embodiment of the present application, FIG. 4B is a structural schematic diagram of an EOA provided by an embodiment of the present application, and FIG. 4C is an output waveform diagram of an EOA and a GOA provided by an embodiment of the present application.

[0117] As shown in FIG. 4A, the EOA in the display panel 10 includes a first light-emitting driving sub-circuit EOA1 and a second light-emitting driving sub-circuit EOA2. The boundary of the first light-emitting driving sub-circuit EOA1 and the second light-emitting driving sub-circuit EOA2 corresponds to the folding boundary in the active display area AA, the first shift register RS1 is used to send a scanning signal to the pixel circuit 11 in the first display partition, and the second shift register RS2 is used to send a scanning signal to the pixel circuit 11 in the second display partition. However, the structure of the GOA is the same as that of the EOA shown in FIG. 3B.

[0118] As shown in FIG. 4B, the first light-emitting driving sub-circuit EOA1 includes a plurality of cascaded first shift registers RS1, and the first stage of the first shift registers RS1 receives the first gate start signal STV1. The second light-emitting driving sub-circuit EOA2 includes a plurality of cascaded second shift registers RS2, and the first stage of the second shift registers RS2 receives the second gate start signal STV2. That is, the first light-emitting driving sub-circuit EOA1 is controlled by the first gate start signal STV1, and the second light-emitting driving sub-circuit EOA2 is controlled by the second gate start signal STV2.

[0119] As shown in FIG. 4C, the first light-emitting driving sub-circuit EOA1 and the second light-emitting driving sub-circuit EOA2 independently output signals, and the EOA can separately drive the first display sub-zone and the second display sub-zone in the active display area AA. The first light-emitting driving sub-circuit EOA1 can be implemented to drive the first display sub-zone to display an image, and the second light-emitting driving sub-circuit EOA2 can be implemented to drive the second display sub-zone to not display an image. The first light-emitting driving sub-circuit EOA1 can also be implemented to drive the first display sub-zone to not display an image, and the second light-emitting driving sub-circuit EOA2 can be implemented to drive the second display sub-zone to display an image. The first light-emitting driving sub-circuit EOA1 can also be implemented to drive the first display sub-zone to not display an image, and the second light-emitting driving sub-circuit EOA2 can be implemented to drive the second display sub-zone to not display an image. The first light-emitting driving sub-circuit EOA1 can also be implemented to drive the first display sub-zone to display an image, and the second light-emitting driving sub-circuit EOA2 can be implemented to drive the second display sub-zone to display an image. The various display scenarios can be switched at will.

[0120] In the display panel 10, the EOA that provides signals to the light-emitting control signal end EM can be controlled independently in zones, but the GOA is still controlled in full screen. With the upgrade of the current pixel circuit 11 architecture, the number of GOA signals that control the operation of the pixel circuit 11 increases, and the number of GOAs is significantly more than the number of EOAs. The above scheme can only save the power consumption of the EOA, and cannot save the power consumption of the GOA, so the power consumption saving degree of the display panel 10 is very limited.

[0121] Based on this, the embodiment of the present application provides a GOA for further saving the power consumption of the display panel 10.

[0122] FIG. 5 is a structural schematic diagram of a GOA provided by an embodiment of the present application.

[0123] The embodiment of the present application provides a GOA, as shown in FIG. 5, which includes a first gate driving sub-circuit GOA I and a second gate driving sub-circuit GOA II.

[0124] The first gate driving sub-circuit GOA I includes a plurality of cascaded first shift registers RS1. An input terminal STVI of a first stage first shift register RS1 receives a first gate start signal STV1. An input terminal STVI of an Nth stage first shift register RS1 is coupled with an output terminal GO of an (N-1)th stage first shift register RS1. N is an integer greater than 1.

[0125] The second gate driving sub-circuit GOA II includes a plurality of cascaded second shift registers RS2. An input terminal STVI of a first stage second shift register RS2 receives a second gate start signal STV2. An input terminal STVI of an Mth stage second shift register RS2 is coupled with an output terminal GO of an (M-1)th stage second shift register RS2. M is an integer greater than 1.

[0126] The first gate driving sub-circuit GOA I is controlled by the first gate start signal STV1. The second gate driving sub-circuit GOA II is controlled by the second gate start signal STV2. The first gate driving sub-circuit GOA I and the second gate driving sub-circuit GOA II independently output signals. The GOA can separately drive a first display sub-area and a second display sub-area in the active display area AA.

[0127] In the display panel 10, the GOA that provides signals to the scan signal terminal can be controlled independently in different areas to save the power consumption of the GOA. One or more GOAs in the display panel 10 can be configured as the above-mentioned structure of independent control in different areas, thereby greatly reducing the power consumption of the display panel 10.

[0128] In some embodiments, the first shift register RS1 is also coupled with a gate high-voltage power supply voltage terminal (VGH) of the display module 40, and the second shift register RS2 is also coupled with the gate high-voltage power supply voltage terminal. In this way, the design of the GOA can be simplified.

[0129] Of course, the first shift register RS1 and the second shift register RS2 can also be coupled with different gate high-voltage power supply voltage terminals, respectively.

[0130] In some embodiments, the first shift register RS1 is also coupled with a gate low-voltage power supply voltage terminal (VGL) of the display module 40, and the second shift register RS2 is also coupled with the gate low-voltage power supply voltage terminal. In this way, the design of the GOA can be simplified.

[0131] Of course, the first shift register RS1 and the second shift register RS2 can also be coupled with different gate low-voltage power supply voltage terminals, respectively.

[0132] In some embodiments, the first shift register RS1 is further coupled with a first clock signal terminal CLK1 of the display driving integrated circuit 20, and the second shift register RS2 is also coupled with the first clock signal terminal CLK1. In this way, the design of the GOA can be simplified.

[0133] Of course, the first shift register RS1 and the second shift register RS2 can also be coupled with different first clock signal terminals CLK1 respectively.

[0134] In some embodiments, the first shift register RS1 is further coupled with a second clock signal terminal CLK2 of the display driving integrated circuit 20, and the second shift register RS2 is also coupled with the second clock signal terminal CLK2. In this way, the design of the GOA can be simplified.

[0135] Of course, the first shift register RS1 and the second shift register RS2 can also be coupled with different second clock signal terminals CLK2 respectively.

[0136] In some embodiments, the first shift register RS1 is further coupled with a recognition signal terminal CX of the display driving integrated circuit 20, and the second shift register RS2 is also coupled with the recognition signal terminal CX. In this way, the design of the GOA can be simplified. The recognition signal terminal CX is used to transmit a signal for recognizing the working state of the first driving circuit 121.

[0137] Of course, the first shift register RS1 and the second shift register RS2 can also be coupled with different recognition signal terminals CX respectively.

[0138] FIG. 6 and FIG. 7 are structural schematic diagrams of a display module provided by embodiments of the present application.

[0139] Embodiments of the present application also provide a display module 40, as shown in FIG. 6, which includes an effective display area AA, a first driving circuit 121 and a first display driving integrated circuit 21. The first driving circuit 121 and the first display driving integrated circuit 21 are arranged at the periphery of the effective display area AA.

[0140] The first driving circuit 121 is arranged at the first side of the display module 40, and the first driving circuit 121 comprises a first driving sub-circuit 121I and a second driving sub-circuit 121II. The first driving sub-circuit 121I comprises a plurality of cascaded first shift registers RS1, and the input end of the first stage first shift register RS1 receives the first gate start signal STV1 provided by the first display driving integrated circuit. The second driving sub-circuit 121II comprises a plurality of cascaded second shift registers RS2, and the input end of the first stage second shift register RS2 receives the second gate start signal STV2 provided by the first display driving integrated circuit. The first driving circuit 121 is used to provide a scanning signal to the active display area AA, the first driving sub-circuit 121I in the first driving circuit 121 is used to output a gate scanning signal for controlling the first display sub-area, and the second driving sub-circuit 121II in the first driving circuit 121 is used to output a gate scanning signal for controlling the second display sub-area. The first driving sub-circuit 121I and the second driving sub-circuit 121II can be independently driven.

[0141] For example, as shown in FIG. 6, the first driving circuit 121 is the GOA shown in FIG. 5, the first driving sub-circuit 121I is the first gate driving sub-circuit GOA1, and the second driving sub-circuit 121II is the second gate driving sub-circuit GOAII. Alternatively, the first driving circuit 121 is the EOA shown in FIG. 4B, the first driving sub-circuit 121I is the first light-emitting driving sub-circuit EOA1, and the second driving sub-circuit 121II is the second light-emitting driving sub-circuit EOA2.

[0142] The first display driving integrated circuit 21 comprises a first gate start signal end 211 and a second gate start signal end 212. The first gate start signal end 211 is coupled with the input end of the first stage first shift register RS1, and is used to provide the first gate start signal STV1 to the input end of the first stage first shift register RS1. The second gate start signal end 212 is coupled with the input end of the first stage second shift register RS2, and is used to provide the second gate start signal STV2 to the input end of the first stage second shift register RS2. That is, the first gate start signal end 211 is used to provide the first gate start signal STV1, and the second gate start signal end 212 is used to provide the second gate start signal STV2.

[0143] The first gate start signal terminal 211 and the second gate start signal terminal 212 are located at different sides of the first display driving integrated circuit 21. For example, the first display driving integrated circuit 21 is rectangular and has four sides. The first gate start signal terminal 211 is close to any one of the four sides of the first display driving integrated circuit 21 relative to the second gate start signal terminal 212, and the second gate start signal terminal 212 is close to any one of the remaining three sides of the first display driving integrated circuit 21 relative to the first gate start signal terminal 211. The first gate start signal terminal 211 and the second gate start signal terminal 212 can be arranged adjacently, and other signal terminals can be arranged between the first gate start signal terminal 211 and the second gate start signal terminal 212.

[0144] For example, in FIG. 6, the first gate start signal terminal 211 and the second gate start signal terminal 212 are located at different sides of the middle line of the first display driving integrated circuit 21. Alternatively, for example, in FIG. 7, the first gate start signal terminal 211 and the second gate start signal terminal 212 are located at the same side of the middle line of the first display driving integrated circuit 21. The first gate start signal terminal 211 and the second gate start signal terminal 212 can be located at any position in the first display driving integrated circuit 21, and FIGS. 6 and 7 are only schematic.

[0145] The first display driving integrated circuit 21 and the first driving circuit 121 can be arranged at the same side or different sides. For example, the first display driving integrated circuit 21 is arranged at the second side of the display module 40, and the second side intersects the first side.

[0146] The first driving sub-circuit 121I in the first driving circuit 121 is configured to output a gate scanning signal for controlling the first display sub-area, and the second driving sub-circuit 121II in the first driving circuit 121 is configured to output a gate scanning signal for controlling the second display sub-area. The first display sub-area can be arranged close to the first display driving integrated circuit 21. Alternatively, the second display sub-area can be arranged close to the first display driving integrated circuit 21.

[0147] The display module 40 provided by the embodiment of the present application includes the first driving sub-circuit 121I and the second driving sub-circuit 121II, and the first driving sub-circuit 121I and the second driving sub-circuit 121II are controlled by the first gate start signal STV1 and the second gate start signal STV2 provided by the first display driving integrated circuit 21. The first driving sub-circuit 121I and the second driving sub-circuit 121II can be independently controlled in sub-areas, and even each driving circuit in the display module 40 can be independently controlled in sub-areas. The power consumption of multiple driving circuits in the display module 40 can be saved, thereby greatly reducing the power consumption of the display module 40.

[0148] FIG. 8A and FIG. 8B are structural schematic diagrams of a display module according to an embodiment of the present application.

[0149] In some embodiments, as shown in FIG. 8A, the display module 40 further comprises a data line DL, and the first display driving integrated circuit 21 further comprises a first data signal terminal 215. The pixel circuits 11 in the same column are coupled with the same data line DL, and the first data signal terminal 215 is coupled with the data line DL for providing a data signal.

[0150] The first data signal terminal 215 is arranged between the first gate start signal terminal 211 and the second gate start signal terminal 212. For example, some of the plurality of first data signal terminals 215 are arranged between the first gate start signal terminal 211 and the second gate start signal terminal 212. Alternatively, for example, all of the plurality of first data signal terminals 215 are arranged between the first gate start signal terminal 211 and the second gate start signal terminal 212. The embodiments of the present application do not limit the specific arrangement, as long as the first data signal terminal 215 is arranged between the first gate start signal terminal 211 and the second gate start signal terminal 212.

[0151] Of course, the first display driving integrated circuit 21 is not limited to comprising only the first gate start signal terminal 211, the second gate start signal terminal 212 and the first data signal terminal 215, but can further comprise signal terminals for transmitting other signals (such as clock signals or power supply signals).

[0152] During the driving process of the display module 40, the signals of the first gate start signal terminal 211 and the second gate start signal terminal 212 are both provided by the first display driving integrated circuit 21. By arranging the first gate start signal terminal 211 and the second gate start signal terminal 212 for providing the first gate start signal STV1 and the second gate start signal STV2 on the two sides of the first data signal terminal 215, the signal terminals on both sides of the first display driving integrated circuit 21 can be utilized, and the modification to the existing layout design of the display module 40 is small, thereby reducing the difficulty of process implementation.

[0153] In some embodiments, as shown in FIG. 8A, the display module 40 further comprises a plurality of connection lines 14, the first gate start signal terminal 211 and the input terminal of the first-stage first shift register RS1 are coupled through the connection line 14, and the second gate start signal terminal 212 and the input terminal of the first-stage second shift register RS2 are coupled through the connection line 14.

[0154] For example, as shown in FIG. 8A, the first gate start signal terminal 211 is disposed close to the first driving circuit 121 relative to the second gate start signal terminal 212, and the connection line 14 connecting the second gate start signal terminal 212 and the input terminal of the first-stage second shift register RS2 is routed from the side of the first display driving integrated circuit 21 away from the effective display area AA to be coupled with the input terminal of the first-stage second shift register RS2.

[0155] Alternatively, for example, as shown in FIG. 8B, the first gate start signal terminal 211 is disposed close to the first driving circuit 121 relative to the second gate start signal terminal 212, and the connection line 14 connecting the second gate start signal terminal 212 and the input terminal of the first-stage second shift register RS2 is routed from the side of the first display driving integrated circuit 21 toward the effective display area AA (away from the edge of the display module 40) to be coupled with the input terminal of the first-stage second shift register RS2.

[0156] The wiring structure on the side of the first display driving integrated circuit 21 toward the effective display area AA is simple. Therefore, the connection line 14 is routed in the region on the side of the first display driving integrated circuit 21 toward the effective display area AA, which has low process difficulty and low manufacturing cost.

[0157] For example, the connection line 14 coupled with the second gate start signal terminal 212 includes a first segment 141, a second segment 142 and a third segment 143. One end of the first segment 141 is coupled with the second gate start signal terminal 212, and the other end of the first segment 141 is coupled with the second segment 142. One end of the third segment 143 is coupled with the input terminal of the first-stage second shift register RS2, and the other end of the third segment 143 is coupled with the second segment 142. The second segment 142 is connected between the first segment 141 and the third segment 143. The second segment 142 is disposed between the first display driving integrated circuit 21 and the pixel array (effective display area AA), the extension direction of the second segment 142 intersects the extension direction of the data line DL, and the projection of the second segment 142 intersects the data line DL.

[0158] Of course, the embodiment of the present application does not limit the connection line 14 to include only the above three segments, and the structure of the connection line 14 can be increased or reduced on the basis of the above three segments.

[0159] FIG. 9 is a sectional view along A1-A2 direction in FIG. 8B provided by the embodiment of the present application.

[0160] In some embodiments, as shown in FIG. 9, the plurality of connection lines 14 and the data line DL are disposed in different layers. The different layers can be understood as that the plurality of connection lines 14 and the data line DL are not disposed on the surface of the same layer of insulating layer. Or it can be understood that an insulating layer is disposed between the plurality of connection lines 14 and the data line DL. Or it can be understood that the plurality of connection lines 14 and the data line DL are not formed by the same patterning process.

[0161] The plurality of connection lines 14 can be arranged in the same layer, or can be arranged in different layers, and the embodiments of the present application do not make any limitation in this regard, as long as the connection lines 14 and the data lines DL are arranged in different layers.

[0162] By arranging the connection lines 14 and the data lines DL in different layers, the jumper difficulty at the intersection of the connection lines 14 and the data lines DL can be reduced, and the manufacturing process can be simplified.

[0163] In some embodiments, the display module 40 further includes a shielding layer, which is arranged between the data lines DL and the plurality of connection lines 14.

[0164] For example, the shielding layer is connected to a fixed voltage terminal, such as a reference ground voltage terminal, a first power voltage terminal ELVDD, or a second power voltage terminal ELVSS. An insulating layer can be arranged between the shielding layer and the data lines DL, and an insulating layer can also be arranged between the shielding layer and the connection lines 14.

[0165] By arranging the shielding layer between the data lines DL and the connection lines 14, the signal of the data lines DL can be shielded, and the coupling effect between the data lines DL and the connection lines 14 can be reduced, so as to reduce the noise on the connection lines 14.

[0166] In some embodiments, along the thickness direction of the display module 40, the plurality of connection lines 14 are arranged on the side of the data lines DL facing the first display driving integrated circuit 21. That is, as shown in FIG. 9, the plurality of connection lines 14 are arranged above the data lines DL.

[0167] The data lines DL are usually arranged in the same layer as the source and drain of the transistors in the pixel circuit 11. By arranging the connection lines 14 above the data lines DL, the process modification can be reduced, and the implementation difficulty can be reduced.

[0168] Of course, the connection lines 14 can also be arranged below the data lines DL, and the embodiments of the present application do not make any limitation in this regard.

[0169] FIGS. 10A-10E are structural schematic diagrams of a display module according to an embodiment of the present application.

[0170] In some embodiments, as shown in FIG. 10A, the display module 40 further includes a second driving circuit 122, and the second driving circuit 122 and the first driving circuit 121 are located on the same side of the display module 40.

[0171] The second driving circuit 122 includes a third driving sub-circuit 122I and a fourth driving sub-circuit 122II, the third driving sub-circuit 122I includes a plurality of cascaded third shift registers RS3, and the fourth driving sub-circuit 122II includes a plurality of cascaded fourth shift registers RS4. The first stage third shift register RS3 is configured to receive a third gate start signal STV3, and the third driving sub-circuit 122I is controlled by the third gate start signal STV3. The first stage fourth shift register RS4 is configured to receive a fourth gate start signal STV4, and the fourth driving sub-circuit 122II is controlled by the fourth gate start signal STV4. The third driving sub-circuit 122I in the second driving circuit 122 is configured to output a gate scanning signal for controlling a first display sub-area, and the fourth driving sub-circuit 122II in the second driving circuit 122 is configured to output a gate scanning signal for controlling a second display sub-area.

[0172] For example, the second driving circuit 122 includes an EOA, an array substrate gate initialization driving circuit GOA1, an array substrate gate compensation driving circuit GOA2, an array substrate gate writing driving circuit GOA3, or an array substrate gate reset driving circuit GOA4.

[0173] The first display driving integrated circuit 21 further includes a third gate start signal terminal 213 and a fourth gate start signal terminal 214. The third gate start signal terminal 213 is coupled to the input terminal of the first stage third shift register RS3, and the fourth gate start signal terminal 214 is coupled to the input terminal of the first stage fourth shift register RS4.

[0174] The at least one first gate start signal terminal 211, the second gate start signal terminal 212, the third gate start signal terminal 213, and the fourth gate start signal terminal 214 are located at different sides of the first display driving integrated circuit 21. For example, the first display driving integrated circuit 21 has four sides, and at least one of the first gate start signal terminal 211, the second gate start signal terminal 212, the third gate start signal terminal 213, and the fourth gate start signal terminal 214 is located close to the first side, and the other signal terminals are located close to one or more of the remaining three sides.

[0175] For example, as shown in FIG. 10A, the first gate start signal terminal 211 and the third gate start signal terminal 213 can be located on one side of the first data signal terminal 215, and the second gate start signal terminal 212 and the fourth gate start signal terminal 214 can be located on the other side of the first data signal terminal 215.

[0176] Alternatively, as shown in FIG. 10B, the first gate start signal terminal 211, the third gate start signal terminal 213, and the fourth gate start signal terminal 214 can be located on one side of the first data signal terminal 215, and the second gate start signal terminal 212 can be located on the other side of the first data signal terminal 215.

[0177] Of course, other distribution manners can also be used, as long as at least one of the first gate start signal terminal 211, the second gate start signal terminal 212, the third gate start signal terminal 213, and the fourth gate start signal terminal 214 is located at a different side of the first display driving integrated circuit 21 from the other signal terminals.

[0178] In some embodiments, as shown in FIG. 10C, the display module 40 includes an EOA, an array substrate gate initialization driving circuit GOA1, an array substrate gate compensation driving circuit GOA2, an array substrate gate write driving circuit GOA3, and an array substrate gate reset driving circuit GOA4. The EOA, the array substrate gate initialization driving circuit GOA1, the array substrate gate compensation driving circuit GOA2, the array substrate gate write driving circuit GOA3, and the array substrate gate reset driving circuit GOA4 are all arranged at the first side of the active display area AA. The structures of the EOA, the array substrate gate initialization driving circuit GOA1, the array substrate gate compensation driving circuit GOA2, the array substrate gate write driving circuit GOA3, and the array substrate gate reset driving circuit GOA4 can be the same as the structure of the first driving circuit 121 in the display module 40 described above.

[0179] For example, the EOA includes a first light-emitting driving sub-circuit EOA1 and a second light-emitting driving sub-circuit EOA2, the array substrate gate initialization driving circuit GOA1 includes a first initialization driving sub-circuit GOA1I and a second initialization driving sub-circuit GOA1II, the array substrate gate compensation driving circuit GOA2 includes a first compensation driving sub-circuit GOA2I and a second compensation driving sub-circuit GOA2II, the array substrate gate write driving circuit GOA3 includes a first write driving sub-circuit GOA3I and a second write driving sub-circuit GOA3II, and the array substrate gate reset driving circuit GOA4 includes a first reset driving sub-circuit GOA4I and a second reset driving sub-circuit GOA4II.

[0180] The gate start signal STVA5 received by the first light-emitting driving sub-circuit EOA1, the gate start signal STVA1 received by the first initialization driving sub-circuit GOA1I, the gate start signal STVA2 received by the first compensation driving sub-circuit GOA2I, the gate start signal STVA3 received by the first write driving sub-circuit GOA3I, and the gate start signal STVA4 received by the first reset driving sub-circuit GOA4I are all provided by the first display driving integrated circuit 21.

[0181] The gate start signal STVB5 received by the second light emitting driving sub-circuit EOA2, the gate start signal STVB1 received by the second initialization driving sub-circuit GOA1 II, the gate start signal STVB2 received by the second compensation driving sub-circuit GOA2 II, the gate start signal STVB3 received by the second writing driving sub-circuit GOA3 II, and the gate start signal STVB4 received by the second reset driving sub-circuit GOA4 II are all provided by the second display driving integrated circuit 22.

[0182] For example, as shown in FIG. 10C, the first display driving integrated circuit 21 includes a plurality of first gate start signal terminals 211 and a plurality of second gate start signal terminals 212, which are located on opposite sides of the first data signal terminal 215.

[0183] The gate start signal STVA5, the gate start signal STVA1, the gate start signal STVA2, the gate start signal STVA3, and the gate start signal STVA4 are provided by the first gate start signal terminal 211, and the gate start signal STVB5, the gate start signal STVB1, the gate start signal STVB2, the gate start signal STVB3, and the gate start signal STVB4 are provided by the second gate start signal terminal 212.

[0184] The first light emitting driving sub-circuit EOA1, the first initialization driving sub-circuit GOA1 I, the first compensation driving sub-circuit GOA2 I, the first writing driving sub-circuit GOA3 I, and the first reset driving sub-circuit GOA4 I are respectively coupled with different first gate start signal terminals 211. The second light emitting driving sub-circuit EOA2, the second initialization driving sub-circuit GOA1 II, the second compensation driving sub-circuit GOA2 II, the second writing driving sub-circuit GOA3 II, and the second reset driving sub-circuit GOA4 II are respectively coupled with different second gate start signal terminals 212.

[0185] Alternatively, for example, as shown in FIG. 10D and FIG. 10E, as long as part of the first light emitting driving sub-circuit EOA1, the second light emitting driving sub-circuit EOA2, the first initialization driving sub-circuit GOA1 I, the second initialization driving sub-circuit GOA1 II, the first compensation driving sub-circuit GOA2 I, the second compensation driving sub-circuit GOA2 II, the first writing driving sub-circuit GOA3 I, the second writing driving sub-circuit GOA3 II, the first reset driving sub-circuit GOA4 I, and the second reset driving sub-circuit GOA4 II are coupled with the first gate start signal terminal 211, and the other part is coupled with the second gate start signal terminal 212, the specific coupling relationship is not limited.

[0186] The embodiments of the present application do not limit the specific coupling relationship, as long as two driving sub-circuits in one driving circuit are coupled with the first gate start signal terminal 211 and the second gate start signal terminal 212 respectively. It is not limited that two driving sub-circuits in each driving circuit are coupled with the first gate start signal terminal 211 and the second gate start signal terminal 212 respectively. For example, as shown in FIG. 10D, the first light emitting driving sub-circuit EOA1 and the second light emitting driving sub-circuit EOA2 are both coupled with the first gate start signal terminal 211. Alternatively, as shown in FIG. 10E, the first reset driving sub-circuit GOA4I and the second reset driving sub-circuit GOA4II are both coupled with the second gate start signal terminal 212.

[0187] The setting position of the driving circuit in the display module 40 and the setting position of the corresponding first gate start signal terminal 211 and the second gate start signal terminal 212 are only one example, and are not limited in any way.

[0188] In the case that the display module 40 includes multiple driving circuits, the display module 40 needs to include multiple connection lines 14. In some embodiments, the distance between adjacent connection lines 14 is greater than or equal to ΔV / 0.5um, where ΔV is the potential difference of the signals on the adjacent connection lines 14. That is, the distance between the adjacent connection lines 14 depends on the potential difference of the signals transmitted on the two connection lines 14 to meet the requirement of weakening signal interference.

[0189] For example, if the potential difference between the adjacent connection lines 14 is 10V, the distance between the two connection lines 14 needs to be greater than or equal to 20um.

[0190] In some embodiments, the connection lines 14 for transmitting low-level active signals are arranged adjacent to each other, and the connection lines 14 for transmitting high-level active signals are arranged adjacent to each other.

[0191] Since the signals of some gate start signal terminals are high-level start signals and the signals of some gate start signal terminals are low-level start signals, the connection lines 14 for transmitting low-level active signals are arranged adjacent to each other, and the connection lines 14 for transmitting high-level active signals are arranged adjacent to each other, which avoids cross arrangement and can reduce the distance between the connection lines 14 to reduce the layout area.

[0192] FIGS. 11A-11C are structural schematic diagrams of a display module provided by an embodiment of the present application.

[0193] In some embodiments, as shown in FIG. 11A, the display module 40 further includes a second display driving integrated circuit 22, and the second display driving integrated circuit 22 and the first display driving integrated circuit 21 are arranged side by side. For example, the second display driving integrated circuit 22 is arranged on the side of the first display driving integrated circuit 21 away from the first side. In this way, the display module 40 can be driven by two display driving integrated circuits.

[0194] In some embodiments, the display module 40 further comprises a third driving circuit 123, the third driving circuit 123 is located at a different side of the display module 40 from the first driving circuit 121.

[0195] For example, the third driving circuit 123 comprises a fifth driving sub-circuit 123Ⅰ and a sixth driving sub-circuit 123Ⅱ, the fifth driving sub-circuit 123Ⅰ comprises a plurality of cascaded fifth shift registers RS5, and the sixth driving sub-circuit 123Ⅱ comprises a plurality of cascaded sixth shift registers RS6. The fifth driving sub-circuit 123Ⅰ in the third driving circuit 123 is used to output a gate scanning signal for controlling the first display sub-area, and the sixth driving sub-circuit 123Ⅱ in the third driving circuit 123 is used to output a gate scanning signal for controlling the second display sub-area.

[0196] In this way, the display module 40 can be provided with driving circuits on multiple sides, which is more friendly to large-screen display modules 40.

[0197] In some embodiments, the second display driving integrated circuit 22 comprises a fifth gate start signal end 221 and a sixth gate start signal end 222, the fifth gate start signal end 221 is coupled to the input end of the first fifth shift register RS5 for providing a fifth gate start signal STV5, and the sixth gate start signal end 222 is coupled to the input end of the first fourth shift register RS4 for providing a sixth gate start signal STV6.

[0198] For example, the fifth gate start signal end 221 and the sixth gate start signal end 222 are located at different sides of the second display driving integrated circuit 22. The relative relationship between the fifth gate start signal end 221 and the sixth gate start signal end 222 can refer to the above description about the relative relationship between the first gate start signal end 211 and the second gate start signal end 212.

[0199] For example, the sixth gate start signal end 222 is arranged close to the first display driving integrated circuit 21 relative to the fifth gate start signal end 221. The connection mode of the second display driving integrated circuit 22 and the second driving circuit 122 can refer to the above description about the connection mode of the first display driving integrated circuit 21 and the first driving circuit 121.

[0200] The first driving circuit 121 and the third driving circuit 123 can be used to provide the same kind of gate scanning signal for the display module 40. For example, the first driving circuit 121 and the third driving circuit 123 are both EOA. The first driving circuit 121 and the third driving circuit 123 can also be used to provide different kinds of gate scanning signals for the display module 40. For example, the first driving circuit 121 is GOA, and the third driving circuit 123 is EOA.

[0201] In some embodiments, as shown in FIG. 11A, the second display driving integrated circuit 22 further includes a second data signal terminal 225, the second data signal terminal 225 is coupled with the data line DL, and one or more second data signal terminals 225 are arranged between the fifth gate start signal terminal 221 and the sixth gate start signal terminal 222. In this way, the multiple signal ports of the second display driving integrated circuit 22 can be utilized.

[0202] In some embodiments, as shown in FIG. 11B and FIG. 11C, the display module 40 further includes a fourth driving circuit 124, the fourth driving circuit 124 is located at the same side of the display module 40 as the third driving circuit 123. The fourth driving circuit 124 includes a seventh driving sub-circuit 124I and an eighth driving sub-circuit 124II, the seventh driving sub-circuit 124I includes a plurality of cascaded seventh shift registers RS7, and the eighth driving sub-circuit 124II includes a plurality of cascaded eighth shift registers RS8. The seventh driving sub-circuit 124I in the fourth driving circuit 124 is used to output a gate scanning signal for controlling the first display sub-area, and the eighth driving sub-circuit 124II in the fourth driving circuit 124 is used to output a gate scanning signal for controlling the second display sub-area.

[0203] The fourth driving circuit 124 and the first driving circuit 121 (or the second driving circuit 122) can be used to provide the same kind of gate scanning signal or different kinds of gate scanning signals for the display module 40.

[0204] In some embodiments, the second display driving integrated circuit 22 further includes a seventh gate start signal terminal 223 and an eighth gate start signal terminal 224, the seventh gate start signal terminal 223 is coupled with the input terminal of the first stage seventh shift register RS7 for providing a seventh gate start signal STV7. The eighth gate start signal terminal 224 is coupled with the input terminal RS8 of the first stage eighth shift register for providing an eighth gate start signal STV8.

[0205] The at least one fifth gate start signal terminal 221, the sixth gate start signal terminal 222, the seventh gate start signal terminal 223, and the eighth gate start signal terminal 224 are located at different sides of the second display driving integrated circuit 22. The connection relationship between the second display driving integrated circuit 22 and the third driving circuit 123 and the fourth driving circuit 124 can refer to the above description about the connection relationship between the first display driving integrated circuit 21 and the first driving circuit 121 and the second driving circuit 122, which will not be described here.

[0206] The positional relationship of the first gate start signal terminal 211, the second gate start signal terminal 212, the third gate start signal terminal 213, and the fourth gate start signal terminal 214 in the first display driving integrated circuit 21 can be the same as or different from the positional relationship of the fifth gate start signal terminal 221, the sixth gate start signal terminal 222, the seventh gate start signal terminal 223, and the eighth gate start signal terminal 224 in the second display driving integrated circuit 22.

[0207] FIGS. 12A and 12B are structural schematic diagrams of a display module provided in an embodiment of the present application.

[0208] In some embodiments, as shown in FIG. 12A, a plurality of driving circuits are arranged on opposite sides of the display module 40. For example, the first side of the display module 40 is provided with an EOA, an array substrate gate initialization driving circuit GOA1, an array substrate gate compensation driving circuit GOA2, an array substrate gate write driving circuit GOA3, and an array substrate gate reset driving circuit GOA4. The opposite side of the display module 40 is provided with an EOA, an array substrate gate initialization driving circuit GOA1, an array substrate gate compensation driving circuit GOA2, an array substrate gate write driving circuit GOA3, and an array substrate gate reset driving circuit GOA4.

[0209] The first display driving integrated circuit 21 provides gate start signals for the EOA, the array substrate gate initialization driving circuit GOA1, the array substrate gate compensation driving circuit GOA2, the array substrate gate write driving circuit GOA3, and the array substrate gate reset driving circuit GOA4 arranged on the first side of the effective display area AA. The signal ports inside and outside the first display driving integrated circuit 21 are both used for coupling with the gate start signal terminals, and the signal ports in the middle are used for coupling with the data lines DL and other signal terminals.

[0210] The second display driving integrated circuit 22 provides gate start signals for the EOA, the array substrate gate initialization driving circuit GOA1, the array substrate gate compensation driving circuit GOA2, the array substrate gate write driving circuit GOA3, and the array substrate gate reset driving circuit GOA4 arranged on the side opposite to the first side. The signal ports inside and outside the second display driving integrated circuit 22 are both used for coupling with the gate start signal terminals, and the signal ports in the middle are used for coupling with the data lines DL and other signal terminals.

[0211] When the display module 40 provided by the embodiment of the present application is applied to the electronic device 1 provided by the embodiment of the present application, the driving controller 30 in the electronic device is coupled with the display driving integrated circuit 20, and is configured to provide a signal to the display driving integrated circuit 20. For example, an application processor (AP) in the driving controller 30 provides a signal to the display driving integrated circuit 20.

[0212] For example, the driving controller 30 is configured to control the display driving integrated circuit 20 to output an image signal. The image signal includes coordinate information of a scan start line and a scan stop line and a data signal, so that the display module 40 realizes partition display.

[0213] FIGS. 13A and 13B are structural schematic diagrams of a display module provided by an embodiment of the present application.

[0214] The embodiment of the present application provides another display module 40, as shown in FIG. 13A, the display module 40 includes an effective display area AA, a first driving circuit 121, a third driving circuit 123, a first display driving integrated circuit 21 and a second display driving integrated circuit 22 which are arranged at the periphery of the effective display area AA.

[0215] The effective display area AA includes a first display partition and a second display partition, and the first display partition and the second display partition are respectively arranged with a plurality of pixel circuits 11.

[0216] The first driving circuit 121 includes a first driving sub-circuit 121Ⅰ and a second driving sub-circuit 121Ⅱ, the first driving sub-circuit 121Ⅰ includes a plurality of cascaded first shift registers RS1, and the input end of the first first shift register RS1 receives a first gate start signal STV1 provided by the first display driving integrated circuit. The second driving sub-circuit 121Ⅱ includes a plurality of cascaded second shift registers RS2, and the input end of the first second shift register RS2 receives a second gate start signal STV2 provided by the first display driving integrated circuit. The first driving circuit 121 is configured to provide a scan signal to the effective display area AA, the first driving sub-circuit 121Ⅰ in the first driving circuit 121 is configured to output a gate scan signal for controlling the first display partition, and the second driving sub-circuit 121Ⅱ in the first driving circuit 121 is configured to output a gate scan signal for controlling the second display partition. The first driving sub-circuit 121Ⅰ and the second driving sub-circuit 121Ⅱ can be independently driven.

[0217] As an example, as shown in FIG. 13A, the first drive circuit 121 is the GOA shown in FIG. 5, the first drive sub-circuit 121I is the first gate drive sub-circuit GOA1, and the second drive sub-circuit 121II is the second gate drive sub-circuit GOA2. Alternatively, the first drive circuit 121 is the EOA shown in FIG. 4B, the first drive sub-circuit 121I is the first light-emitting drive sub-circuit EOA1, and the second drive sub-circuit 121II is the second light-emitting drive sub-circuit EOA2.

[0218] The third drive circuit 123 includes a fifth drive sub-circuit 123I and a sixth drive sub-circuit 123II. The fifth drive sub-circuit 123I includes a plurality of cascaded fifth shift registers RS5, and the input terminal of the first-stage fifth shift register RS5 is configured to receive a fifth gate start signal STV5 provided by the second display drive integrated circuit 22. The sixth drive sub-circuit 123II includes a plurality of cascaded sixth shift registers RS6, and the input terminal of the first-stage sixth shift register RS6 is configured to receive a sixth gate start signal STV6 provided by the second display drive integrated circuit 22. The third drive circuit 123 is configured to provide scan signals to the active display area AA, the fifth drive sub-circuit 123I in the third drive circuit 123 is configured to output gate scan signals for controlling the first display sub-area, and the sixth drive sub-circuit 123II in the third drive circuit 123 is configured to output gate scan signals for controlling the second display sub-area. The fifth drive sub-circuit 123I and the sixth drive sub-circuit 123II can be independently driven.

[0219] The third drive circuit 123 can be any two of the EOA and the above-described various GOAs. As an example, the first drive circuit 121 and the third drive circuit 123 are any one of the EOA, the array substrate gate initialization drive circuit GOA1 configured to output initialization scan signals to the initialization scan signal lines SCL1-SCLn, the array substrate gate compensation drive circuit GOA2 configured to output compensation scan signals to the compensation scan signal lines SBL1-SBLn, the array substrate gate write drive circuit GOA3 configured to output write scan signals to the write scan signal lines SXL1-SXLn, or the array substrate gate reset drive circuit GOA4 configured to output reset scan signals to the reset scan signal lines SFL1-SFLn.

[0220] With the change of the structure of the pixel circuit 11, the types of the first drive circuit 121 and the third drive circuit 123 can also change, as long as the first drive circuit 121 and the third drive circuit 123 are configured to provide scan signals to the pixel circuit 11.

[0221] The first driving circuit 121 and the third driving circuit 123 can be used to output the same gate scanning signal, that is, the first driving circuit 121 and the third driving circuit 123 can be the same GOA, which is used to control the same transistor in the pixel circuit 11. The first driving circuit 121 and the third driving circuit 123 can also be used to output different gate scanning signals, that is, the first driving circuit 121 and the third driving circuit 123 can be different GOAs, which are used to control different transistors in the pixel circuit 11.

[0222] The connection relationship between the fifth shift register RS5 and the sixth shift register RS6 in the third driving circuit 123 and the voltage terminal and the signal terminal can refer to the related description of the connection relationship between the first shift register RS1 and the second shift register RS2 in the GOA and the voltage terminal and the signal terminal, which will not be described here.

[0223] In some embodiments, the first driving circuit 121 and the third driving circuit 123 are located on different sides of the display module 40. For example, the first driving circuit 121 and the third driving circuit 123 are located on opposite sides of the display module 40.

[0224] The display module 40 provided by the embodiments of the present application, the first driving circuit 121 includes a first driving sub-circuit 121Ⅰ and a second driving sub-circuit 121Ⅱ, the first driving sub-circuit 121Ⅰ and the second driving sub-circuit 121Ⅱ are controlled by the first gate start signal STV1 and the second gate start signal STV2 provided by the first display driving integrated circuit 21. The third driving circuit 123 includes a fifth driving sub-circuit 123Ⅰ and a sixth driving sub-circuit 123Ⅱ, the fifth driving sub-circuit 123Ⅰ and the sixth driving sub-circuit 123Ⅱ are controlled by the fifth gate start signal STV5 and the sixth gate start signal STV6 provided by the second display driving integrated circuit 22. To achieve the independent control of the first driving sub-circuit 121Ⅰ and the second driving sub-circuit 121Ⅱ, the independent control of the fifth driving sub-circuit 123Ⅰ and the sixth driving sub-circuit 123Ⅱ, and even the independent control of each driving circuit in the display module 40. The power consumption of multiple driving circuits in the display module 40 can be saved, thereby greatly reducing the power consumption of the display module 40.

[0225] In some embodiments, as shown in FIG. 13B, the display module 40 further includes a second driving circuit 122. The second driving circuit 122 is located on the same side of the display module 40 as the first driving circuit 121.

[0226] The second driving circuit 122 comprises a third driving sub-circuit 122I and a fourth driving sub-circuit 122II. The third driving sub-circuit 122I comprises a plurality of cascaded third shift registers RS3, and the input end of the first stage third shift register RS3 is configured to receive the third gate start signal STV3 provided by the first display driving integrated circuit 21. The fourth driving sub-circuit 122II comprises a plurality of cascaded fourth shift registers RS4, and the input end of the first stage fourth shift register RS4 is configured to receive the fourth gate start signal STV4 provided by the first display driving integrated circuit 21. The second driving circuit 122 is configured to provide a scanning signal to the active display area AA, the third driving sub-circuit 122I in the second driving circuit 122 is configured to output a gate scanning signal for controlling the first display sub-area, and the fourth driving sub-circuit 122II in the second driving circuit 122 is configured to output a gate scanning signal for controlling the second display sub-area. The third driving sub-circuit 122I and the fourth driving sub-circuit 122II can be independently driven.

[0227] In some embodiments, as shown in FIG. 13B, the display module 40 further comprises a fourth driving circuit 124. The fourth driving circuit 124 is located on the same side of the display module 40 as the third driving circuit 123.

[0228] The fourth driving circuit 124 comprises a seventh driving sub-circuit 124I and an eighth driving sub-circuit 124II. The seventh driving sub-circuit 124I comprises a plurality of cascaded seventh shift registers RS7, and the input end of the first stage seventh shift register RS7 is configured to receive the third gate start signal STV3 provided by the second display driving integrated circuit 22. The eighth driving sub-circuit 124II comprises a plurality of cascaded eighth shift registers RS8, and the input end of the first stage eighth shift register RS8 is configured to receive the eighth gate start signal STV8 provided by the second display driving integrated circuit 22. The fourth driving circuit 124 is configured to provide a scanning signal to the active display area AA, the seventh driving sub-circuit 124I in the fourth driving circuit 124 is configured to output a gate scanning signal for controlling the first display sub-area, and the eighth driving sub-circuit 124II in the fourth driving circuit 124 is configured to output a gate scanning signal for controlling the second display sub-area. The seventh driving sub-circuit 124I and the eighth driving sub-circuit 124II can be independently driven.

[0229] The second driving circuit 122 and the fourth driving circuit 124 in the display module 40 can also be independently controlled in sub-areas, further reducing the power consumption of the display module 40.

[0230] In some embodiments, the display module 40 further comprises a third display sub-area, the first driving circuit 121 further comprises a ninth driving sub-circuit, and the ninth driving sub-circuit is controlled by a ninth gate start signal provided by the first display driving integrated circuit 21. The third driving circuit 123 further comprises a tenth driving sub-circuit, and the tenth driving sub-circuit is controlled by a tenth gate start signal provided by the second display driving integrated circuit 22.

[0231] In some embodiments, the display module 40 further comprises one or more of the second driving circuit or the fourth driving circuit.

[0232] FIG. 14 is a structural schematic diagram of a display module according to an embodiment of the present application.

[0233] In some embodiments, as shown in FIG. 14, the display module 40 comprises an EOA, an array substrate gate initialization driving circuit GOA1, an array substrate gate compensation driving circuit GOA2, an array substrate gate write driving circuit GOA3, and an array substrate gate reset driving circuit GOA4. The structure of the EOA can be as shown in FIG. 4B, the structures of the array substrate gate initialization driving circuit GOA1, the array substrate gate compensation driving circuit GOA2, the array substrate gate write driving circuit GOA3, and the array substrate gate reset driving circuit GOA4 can be as shown in FIG. 5, and the structure of the pixel circuit 11 in the active display area AA can be as shown in FIG. 2.

[0234] For example, the EOA comprises a first light-emitting driving sub-circuit EOA1 and a second light-emitting driving sub-circuit EOA2, the array substrate gate initialization driving circuit GOA1 comprises a first initialization driving sub-circuit GOA1I and a second initialization driving sub-circuit GOA1II, the array substrate gate compensation driving circuit GOA2 comprises a first compensation driving sub-circuit GOA2I and a second compensation driving sub-circuit GOA2II, the array substrate gate write driving circuit GOA3 comprises a first write driving sub-circuit GOA3I and a second write driving sub-circuit GOA3II, and the array substrate gate reset driving circuit GOA4 comprises a first reset driving sub-circuit GOA4I and a second reset driving sub-circuit GOA4II.

[0235] The first light-emitting driving sub-circuit EOA1, the first initialization driving sub-circuit GOA1I, the first compensation driving sub-circuit GOA2I, the first write driving sub-circuit GOA3I, and the first reset driving sub-circuit GOA4I are configured to output a gate scanning signal for controlling the first display sub-area, and the second light-emitting driving sub-circuit EOA2, the second initialization driving sub-circuit GOA1II, the second compensation driving sub-circuit GOA2II, the second write driving sub-circuit GOA3II, and the second reset driving sub-circuit GOA4II are configured to output a gate scanning signal for controlling the second display sub-area.

[0236] The gate start signal STVA5 received by the first light-emitting driving sub-circuit EOA1, the gate start signal STVA1 received by the first initialization driving sub-circuit GOA1I, the gate start signal STVA2 received by the first compensation driving sub-circuit GOA2I, the gate start signal STVA3 received by the first writing driving sub-circuit GOA3I, and the gate start signal STVA4 received by the first reset driving sub-circuit GOA4I are all provided by the first display driving integrated circuit 21.

[0237] The gate start signal STVB5 received by the second light-emitting driving sub-circuit EOA2, the gate start signal STVB1 received by the second initialization driving sub-circuit GOA1II, the gate start signal STVB2 received by the second compensation driving sub-circuit GOA2II, the gate start signal STVB3 received by the second writing driving sub-circuit GOA3II, and the gate start signal STVB4 received by the second reset driving sub-circuit GOA4II are all provided by the second display driving integrated circuit 22.

[0238] In the embodiments of the present application, the first driving circuit 121 and the second driving circuit 122 can be any two of the left EOA, the array substrate gate initialization driving circuit GOA1, the array substrate gate compensation driving circuit GOA2, the array substrate gate writing driving circuit GOA3, and the array substrate gate reset driving circuit GOA4. The third driving circuit 123 and the fourth driving circuit 124 can be any two of the right EOA, the array substrate gate initialization driving circuit GOA1, the array substrate gate compensation driving circuit GOA2, the array substrate gate writing driving circuit GOA3, and the array substrate gate reset driving circuit GOA4.

[0239] The embodiments of the present application do not limit the connection mode of the first display driving integrated circuit 21 and the first driving circuit 121 (or the second driving circuit 122), and do not limit the connection mode of the second display driving integrated circuit 22 and the third driving circuit 123 (or the fourth driving circuit 124). For reference, the connection mode of the signal terminal in the first display driving integrated circuit 21 and the first driving circuit 121 (or the second driving circuit 122) and the connection mode of the signal terminal in the second display driving integrated circuit 22 and the third driving circuit 123 (or the fourth driving circuit 124) are described above, and will not be described here.

[0240] FIGS. 15A-15D are schematic diagrams of a display scenario provided by the embodiments of the present application.

[0241] Based on the above two display modules 40 provided by the embodiments of the present application, the first driving circuit 121 and the third driving circuit 123 can be controlled in zones, and the display module 40 can realize multiple display scenarios.

[0242] For example, as shown in FIG. 15A, the display module 40 can realize that the first display partition displays a picture and the second display partition does not display a picture. The driving sub-circuit of the first display partition receives the start signal transmitted by the gate start signal terminal, and the driving sub-circuit of the second display partition receives the non-start signal transmitted by the gate start signal terminal.

[0243] Alternatively, for example, as shown in FIG. 15B, the display module 40 can realize that the first display partition does not display a picture and the second display partition displays a picture. The driving sub-circuit of the first display partition receives the non-start signal transmitted by the gate start signal terminal, and the driving sub-circuit of the second display partition receives the start signal transmitted by the gate start signal terminal.

[0244] Alternatively, for example, as shown in FIG. 15C, the display module 40 can realize that the first display partition displays a picture and the second display partition displays a picture. The driving sub-circuit of the first display partition receives the start signal transmitted by the gate start signal terminal, and the driving sub-circuit of the second display partition receives the start signal transmitted by the gate start signal terminal.

[0245] Alternatively, for example, as shown in FIG. 15D, the display module 40 can realize that the first display partition does not display a picture and the second display partition does not display a picture. The driving sub-circuit of the first display partition receives the non-start signal transmitted by the gate start signal terminal, and the driving sub-circuit of the second display partition receives the non-start signal transmitted by the gate start signal terminal.

[0246] FIGS. 16A-16E are schematic diagrams of a display module according to an embodiment of the present application.

[0247] The present application does not limit the shape of the display module 40 when realizing the above-mentioned partition display effect. For example, the display module 40 is a display module with an outer folding function.

[0248] In the first state, the display module 40 can realize the display effects shown in FIGS. 15A, 15B and 15D. For example, as shown in FIG. 16A, the display module 40 is an outer folding display module, and the display module 40 is in a folded state (or a hovering state). The folded state of the display module can be defined by the light-emitting side of the display module 40. Alternatively, as shown in FIG. 16B, the display module 40 is in an inner folding hovering state. Alternatively, as shown in FIG. 16C, the display module 40 is a three-fold display module in an "S" shape or a "G" shape, and the display module 40 is in a half-folded state. Alternatively, as shown in FIG. 16D, the display module 40 is a three-fold display module in a "G" shape, and the display module 40 is in a folded state. In these cases, the display module 40 can realize the display effects shown in FIGS. 15A, 15B and 15D.

[0249] In the second state, the display module 40 of any structure is in a flat state, and the display module 40 can realize the display effects shown in FIGS. 15C and 15D.

[0250] In the third state, as shown in FIG. 16E, the display module 40 is an S-shaped three-fold display module, and the display module 40 is in a folded state, and the display module 40 can realize the display effects shown in FIGS. 15A and 15D.

[0251] After the display module 40 has the partition display function, the display effects shown in FIGS. 15A-15D can be realized. The display pictures of each partition can be dynamically adjusted to match the actual display area.

[0252] FIGS. 17A-17D are driving timing diagrams of a display module provided in an embodiment of the present application.

[0253] An embodiment of the present application further provides a driving method of a display module, which is used to realize picture display in the above-mentioned various display scenarios. The display module 40 includes a first driving circuit 121, and the driving method of the display module includes, for example, taking the first display partition as normally displayed and the second display partition as not displayed.

[0254] As shown in FIG. 17A, in a first time period t1 of an image frame, the first stage first shift register RS1 receives an opening signal of the first gate start signal end 211, the Nth stage first shift register RS1 receives a signal output by the (N-1)th stage first shift register RS1, and each stage first shift register RS1 outputs a scanning opening signal. N is an integer greater than 1, and an embodiment of the present application does not limit the value of N.

[0255] In some embodiments, at the same time, each stage first shift register RS1 receives a first clock signal of the first clock signal end CLK1, and the frequency of the first clock signal is a first frequency. The first frequency is, for example, the normal refresh frequency of the first clock signal.

[0256] In other embodiments, at the same time, each stage first shift register RS1 receives a third clock signal of the third clock signal end CLK3, and the frequency of the third clock signal is a third frequency. The third frequency is, for example, the normal refresh frequency of the third clock signal.

[0257] In a second time period t2 of the image frame, the first stage second shift register RS2 receives an off signal of the second gate start signal end 212, the Mth stage second shift register RS2 receives a signal output by the (M-1)th stage second shift register RS2, and each stage second shift register RS2 outputs a scanning cutoff signal. M is an integer greater than 1, and an embodiment of the present application does not limit the value of M.

[0258] The first gate start signal STV1 of the first gate start signal terminal 211 is an on signal only when it is a low signal, and the second gate start signal STV2 of the second gate start signal terminal 212 is an off signal when it is a high signal, as shown in FIG. 17A. Alternatively, the opposite can also be true, which is not limited in the embodiments of the present application.

[0259] As shown in FIG. 17A, in some embodiments, at the same time, the first clock signal terminal CLK1 coupled with the second shift register RS2 provides a fixed voltage signal. That is, the signal of the first clock signal terminal CLK1 stops flipping.

[0260] In other embodiments, at the same time, the third clock signal terminal CLK3 coupled with the first shift register RS1 provides a fixed voltage signal. That is, the signal of the third clock signal terminal CLK3 stops flipping.

[0261] In FIG. 17A, only the high signal is provided when the first clock signal terminal CLK1 and the third clock signal terminal CLK3 stop flipping is shown for illustration. The low signal can also be continuously provided when the first clock signal terminal CLK1 and the third clock signal terminal CLK3 stop flipping, which is not limited in the embodiments of the present application.

[0262] Alternatively, as shown in FIG. 17B, in some embodiments, at the same time, the first clock signal terminal CLK1 coupled with the second shift register RS2 provides a second clock signal, and the frequency of the second clock signal is a second frequency, which is less than the first frequency. That is, the frequency of the clock signal provided by the first clock signal terminal CLK1 is reduced. For example, the second frequency is 1 / 2, 1 / 4, 1 / 8, 1 / 16, 1 / 32, etc. of the first frequency.

[0263] In other embodiments, at the same time, the third clock signal terminal CLK3 coupled with the first shift register RS1 provides a fourth clock signal, and the frequency of the fourth clock signal is a fourth frequency, which is less than the third frequency. That is, the frequency of the clock signal provided by the third clock signal terminal CLK3 is reduced. For example, the fourth frequency is 1 / 2, 1 / 4, 1 / 8, 1 / 16, 1 / 32, etc. of the third frequency.

[0264] The first driving circuit 121 can be any one of an EOA, an array substrate gate initialization driving circuit GOA1, an array substrate gate compensation driving circuit GOA2, an array substrate gate writing driving circuit GOA3, and an array substrate gate reset driving circuit GOA4.

[0265] In some embodiments, the display module 40 further includes a second driving circuit 122. The driving method of the display module includes:

[0266] As shown in FIG. 17C, in the first time period t1, the first stage of the third shift register RS3 receives the opening signal of the third gate start signal end 213, the 0th stage of the third shift register RS3 receives the signal output by the (O-1)th stage of the third shift register RS3; each stage of the third shift register RS3 outputs a scanning opening signal. O is an integer greater than 1.

[0267] In an example, at the same time, the second clock signal end CLK2 coupled with the third shift register RS3 provides a third clock signal, and the third clock signal normally flips.

[0268] In an example, at the same time, the fourth clock signal end CLK4 coupled with the third shift register RS3 provides a fourth clock signal, and the fourth clock signal normally flips.

[0269] In the second time period t2, the first stage of the fourth shift register RS4 receives the opening signal of the fourth gate start signal end 214, and the Pth stage of the fourth shift register RS4 receives the signal output by the (P-1)th stage of the fourth shift register RS4; each stage of the fourth shift register RS4 outputs a scanning opening signal. P is an integer greater than 1.

[0270] In an example, at the same time, the second clock signal end CLK2 coupled with the fourth shift register RS4 provides a third clock signal, and the third clock signal normally flips.

[0271] In an example, at the same time, the fourth clock signal end CLK4 coupled with the fourth shift register RS4 provides a fourth clock signal, and the fourth clock signal normally flips.

[0272] That is, in the scenario of local display of the display module 40, the display module 40 can still include a normally driven second drive circuit 122, but the normal driving of the second drive circuit 122 does not affect the local display of the display module 40.

[0273] In an example, the second drive circuit 122 is an array substrate gate reset drive circuit GOA4, which is configured to provide a scanning signal for an anode reset circuit 115 for controlling anode reset of the light emitting unit 114. In the case of local non-display, the light emitting unit 114 in the non-display area is still normally reset to improve the display effect.

[0274] When the display module 40 simultaneously includes the EOA, the array substrate gate initialization driving circuit GOA1, the array substrate gate compensation driving circuit GOA2, the array substrate gate writing driving circuit GOA3, and the array substrate gate reset driving circuit GOA4, the EOA, the array substrate gate initialization driving circuit GOA1, the array substrate gate compensation driving circuit GOA2, the array substrate gate writing driving circuit GOA3, and the array substrate gate reset driving circuit GOA4 can be driven according to the driving method of the first driving circuit 121.

[0275] Alternatively, part of the EOA, the array substrate gate initialization driving circuit GOA1, the array substrate gate compensation driving circuit GOA2, the array substrate gate writing driving circuit GOA3, and the array substrate gate reset driving circuit GOA4 is driven according to the driving method of the first driving circuit 121. For example, as shown in FIG. 17D, the EOA, the array substrate gate initialization driving circuit GOA1, the array substrate gate compensation driving circuit GOA2, and the array substrate gate writing driving circuit GOA3 are driven according to the driving method of the first driving circuit 121, and the array substrate gate reset driving circuit GOA4 is driven according to the driving method of the second driving circuit 122. In FIG. 17D, STVA in each driving circuit is a gate start signal terminal for controlling the shift register of the first display partition, STVB is a gate start signal terminal for controlling the shift register of the second display partition, CK and CB are a pair of inverse clock signal terminals coupled to the shift register.

[0276] If the first display partition shown in FIG. 15B is not displayed and the second display partition is normally displayed, the driving timing in the first time period t1 and the driving timing in the second time period t2 can be exchanged.

[0277] If the first display partition and the second display partition shown in FIG. 15C are both normally displayed, the driving timing in the second time period t2 does not need to be processed by turning off the gate start signal and not inverting or reducing the frequency of the clock signal. The second time period t2 is the same as the first time period t1, and can be normally started.

[0278] If the first display partition and the second display partition shown in FIG. 15D are both not displayed, the driving timing in the first time period t1 also needs to be processed by turning off the gate start signal and not inverting or reducing the frequency of the clock signal. The first time period t1 is the same as the second time period t2, and can be normally turned off.

[0279] The driving method of the display module provided in the embodiments of the present application can reduce the driving power consumption of the non-display area by turning off the signal of the clock signal terminal or reducing the frequency of the signal of the clock signal terminal when the display module 40 is in a local display scenario, so that the effect of display power consumption optimization can be achieved.

[0280] The above is only to control the display of the first display partition by the first shift register RS1, and to control the display of the second display partition by the second shift register RS2 for the purpose of illustration. Alternatively, the first shift register RS1 can control the display of the second display partition, and the second shift register RS2 can control the display of the first display partition, and the display states of the first display partition and the second display partition are exchanged.

[0281] In the embodiments of the present application, the signals of the STVA, the STVB, the CK and the CB are all provided by the display driving integrated circuit 20 in the display module 40.

[0282] FIG. 18 is a signal transmission diagram in the partition display provided by the embodiments of the present application.

[0283] In the display process, when the partition display is performed, as shown in FIG. 18, the driving controller 30 sends the partial image to the display driving integrated circuit 20, and the graphics random access memory (GRAM) of the display driving integrated circuit 20 can support the partial image signal to be written. The image signal transmitted by the driving controller 30 to the display driving integrated circuit 20 includes the coordinates of the partial writing of the display driving integrated circuit 20 and the data signal of the partial writing. For example, the image signal includes the coordinates of the start line and the stop line of scanning, the coordinates of the start line and the stop line of data writing, etc.

[0284] FIG. 19 is a driving logic diagram in the partition display provided by the embodiments of the present application.

[0285] For example, as shown in FIG. 19, the display module 40 first displays the picture in the first display partition, and does not display the picture in the second display partition. Then, the driving controller 30 sends the new image signal to the display driving integrated circuit 20. The display driving integrated circuit 20 receives the image signal, outputs the gate start signal STV matched with the image to be displayed according to the image signal, and transmits the gate start signal STV to each driving circuit to control whether the first display partition displays the picture or the second display partition displays the picture. The display driving integrated circuit 20 also outputs the clock signal to control the driving circuit to output the scanning signal step by step. The display driving integrated circuit 20 outputs the data signal to control the display gray scale of each row, and realizes the picture display.

[0286] The above is only the specific implementation of the present application, but the protection scope of the present application is not limited to this. Any change or replacement within the technical scope disclosed by the present application should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A display module, characterized by The display module comprises: The first drive circuit comprises a plurality of cascaded first shift registers and a plurality of cascaded second shift registers, the plurality of cascaded first shift registers are used to output a gate scanning signal for controlling the first display subarea, and the plurality of cascaded second shift registers are used to output a gate scanning signal for controlling the second display subarea; The first display drive integrated circuit comprises a first gate start signal end and a second gate start signal end; the first gate start signal end is coupled with the input end of the first stage of the first shift register, and the second gate start signal end is coupled with the input end of the first stage of the second shift register; The first gate start signal end and the second gate start signal end are located on different sides of the first display drive integrated circuit.

2. The display module of claim 1, wherein, The first display drive integrated circuit further comprises a first data signal end, the first data signal end is coupled with a data line, and the first gate start signal end and the second gate start signal end are provided with the first data signal end therebetween.

3. The display module of claim 2, wherein, The display module further comprises a plurality of connection lines, the plurality of connection lines and the data line are provided in different layers; The first gate start signal end and the input end of the first stage of the first shift register are coupled through the connection line, and the second gate start signal end and the input end of the first stage of the second shift register are coupled through the connection line.

4. The display module of claim 3, wherein, The display module further comprises a shielding layer, and the shielding layer is located between the data line and the plurality of connection lines.

5. The display module of claim 3 or 4, wherein, In the thickness direction of the display module, the plurality of connection lines are provided on the side of the data line facing the first display drive integrated circuit.

6. The display module of any of claims 3-5, wherein, The first drive circuit is located on the first side of the display module, the first display drive integrated circuit is located on the second side of the display module, and the second side intersects with the first side; The first gate start signal end is closer to the first side relative to the second gate start signal end; The connection line coupled with the second gate start signal end comprises a first segment, a second segment and a third segment; The first segment is coupled with the second gate start signal end, the third segment is coupled with the input end of the first stage of the second shift register, and the second segment is connected between the first segment and the third segment; the second segment is provided on the side of the first display drive integrated circuit away from the edge of the display module, and the second segment intersects with the data line.

7. The display module of any of claims 3-6, wherein, The connection lines for transmitting low-level effective signals are provided adjacently, and the connection lines for transmitting high-level effective signals are provided adjacently.

8. The display module of any of claims 3-7, wherein, The spacing between adjacent connection lines is greater than or equal to ΔV / 0.5um, and ΔV is the potential difference of signals on adjacent connection lines.

9. The display module of any of claims 1-8, wherein, The display module further comprises a second drive circuit, the second drive circuit is located on the same side of the display module as the first drive circuit; the second drive circuit comprises a plurality of cascaded third shift registers and a plurality of cascaded fourth shift registers; the plurality of cascaded third shift registers are used to output a gate scanning signal for controlling the first display subarea, and the plurality of cascaded fourth shift registers are used to output a gate scanning signal for controlling the second display subarea; The first display driving integrated circuit further comprises a third gate start signal end and a fourth gate start signal end; the third gate start signal end is coupled with an input end of the third shift register of the first stage, and the fourth gate start signal end is coupled with an input end of the fourth shift register of the first stage.

10. The display module of claim 9, wherein, At least one of the first gate start signal end, the second gate start signal end, the third gate start signal end and the fourth gate start signal end is located at different sides of the first display driving integrated circuit.

11. The display module of any of claims 1-10, wherein, The display module further comprises a second display driving integrated circuit, which is arranged side by side with the first display driving integrated circuit.

12. The display module of claim 11, wherein, The display module further comprises a third driving circuit; the third driving circuit is located at a different side of the display module from the first driving circuit; the third driving circuit comprises a plurality of cascaded fifth shift registers and a plurality of cascaded sixth shift registers; the plurality of cascaded fifth shift registers are used for outputting gate scanning signals for controlling the first display sub-area, and the plurality of cascaded sixth shift registers are used for outputting gate scanning signals for controlling the second display sub-area.

13. The display module of claim 12, wherein, The second display driving integrated circuit comprises a fifth gate start signal end and a sixth gate start signal end; the fifth gate start signal end is coupled with an input end of the fifth shift register of the first stage, and the sixth gate start signal end is coupled with an input end of the sixth shift register of the first stage.

14. The display module of claim 13, wherein, The second display driving integrated circuit further comprises a second data signal end, which is coupled with the data line; the second data signal end is arranged between the fifth gate start signal end and the sixth gate start signal end.

15. The display module of any of claims 12-14, wherein, The display module further comprises a fourth driving circuit, which is located at the same side of the display module as the third driving circuit; the fourth driving circuit comprises a plurality of cascaded seventh shift registers and a plurality of cascaded eighth shift registers; the plurality of cascaded seventh shift registers are used for outputting gate scanning signals for controlling the first display sub-area, and the plurality of cascaded eighth shift registers are used for outputting gate scanning signals for controlling the second display sub-area. The second display driving integrated circuit further comprises a seventh gate start signal end and an eighth gate start signal end; the seventh gate start signal end is coupled with an input end of the seventh shift register of the first stage, and the eighth gate start signal end is coupled with an input end of the eighth shift register of the first stage.

16. The display module of claim 15, wherein, At least one of the fifth gate start signal end, the sixth gate start signal end, the seventh gate start signal end and the eighth gate start signal end is located at different sides of the second display driving integrated circuit.

17. The display module of any of claims 12-16, wherein, The first driving circuit and the third driving circuit are used for transmitting the same gate scanning signals or different gate scanning signals.

18. The display module according to any one of claims 1-17, characterized in that, The display module further comprises a power voltage end, and the first shift register and the second shift register are coupled with the power voltage end. Or, The first display driving integrated circuit further comprises a clock signal end, and the first shift register and the second shift register are coupled with the clock signal end.

19. A display module, characterized by The display module comprises: The first driving circuit comprises a plurality of cascaded first shift registers and a plurality of cascaded second shift registers, the plurality of cascaded first shift registers are used for outputting a gate scanning signal for controlling a first display partition, and the plurality of cascaded second shift registers are used for outputting a gate scanning signal for controlling a second display partition; The second driving circuit is located at a different side of the display module from the first driving circuit, the second driving circuit comprises a plurality of cascaded third shift registers and a plurality of cascaded fourth shift registers, the plurality of cascaded third shift registers are used for outputting a gate scanning signal for controlling the first display partition, and the plurality of cascaded fourth shift registers are used for outputting a gate scanning signal for controlling the second display partition; The first display driving integrated circuit is used for providing a first gate start signal for a first stage of the first shift register and a second gate start signal for a first stage of the second shift register. The second display driving integrated circuit is used for providing a third gate start signal for a first stage of the third shift register and a fourth gate start signal for a first stage of the fourth shift register.

20. The display module of claim 19, wherein, The first display driving integrated circuit comprises a first gate start signal end and a second gate start signal end; the first gate start signal end is coupled with an input end of a first stage of the first shift register, and the second gate start signal end is coupled with an input end of a first stage of the second shift register; the first gate start signal end and the second gate start signal end are located at different sides of the first display driving integrated circuit.

21. The display module of claim 19 or 20, wherein, The second display driving integrated circuit comprises a third gate start signal end and a fourth gate start signal end, the third gate start signal end is coupled with an input end of a first stage of the third shift register, and the fourth gate start signal end is coupled with an input end of a first stage of the fourth shift register; the third gate start signal end and the fourth gate start signal end are located at different sides of the second display driving integrated circuit.

22. The display module of any of claims 19-21, wherein, The display module further comprises a third driving circuit; the third driving circuit is located at the same side of the display module as the first driving circuit; the third driving circuit comprises a plurality of cascaded fifth shift registers and a plurality of cascaded sixth shift registers; the plurality of cascaded fifth shift registers are used for outputting a gate scanning signal for controlling the first display partition, and the plurality of cascaded sixth shift registers are used for outputting a gate scanning signal for controlling the second display partition; The first display driving integrated circuit is used for providing a fifth gate start signal for a first stage of the fifth shift register and a sixth gate start signal for a first stage of the sixth shift register.

23. The display module of claim 22, wherein, The first display driving integrated circuit further comprises a fifth gate start signal end and a sixth gate start signal end, the fifth gate start signal end is coupled with an input end of the fifth shift register of the first stage, and the sixth gate start signal end is coupled with an input end of the sixth shift register of the first stage. At least one of the first gate start signal end, the second gate start signal end, the fifth gate start signal end and the sixth gate start signal end is located at different sides of the first display driving integrated circuit.

24. The display module of any of claims 19-23, wherein, The display module further comprises a fourth driving circuit, the fourth driving circuit is located at the same side of the display module as the second driving circuit; the fourth driving circuit comprises a plurality of cascaded seventh shift registers and a plurality of cascaded eighth shift registers; the plurality of cascaded seventh shift registers are used for outputting gate scanning signals for controlling the first display sub-area, and the plurality of cascaded eighth shift registers are used for outputting gate scanning signals for controlling the second display sub-area; The second display driving integrated circuit is used for providing a seventh gate start signal for the first stage of the seventh shift register and an eighth gate start signal for the first stage of the eighth shift register.

25. The display module of claim 24, wherein, The second display driving integrated circuit further comprises a seventh gate start signal end and an eighth gate start signal end; the seventh gate start signal end is coupled with an input end of the first stage of the seventh shift register, and the eighth gate start signal end is coupled with an input end of the first stage of the eighth shift register. At least one of the third gate start signal end, the fourth gate start signal end, the seventh gate start signal end and the eighth gate start signal end is located at different sides of the second display driving integrated circuit.

26. The display module of any of claims 19-25, wherein, The first driving circuit and the second driving circuit are used for transmitting the same gate scanning signals or different gate scanning signals.

27. An electronic device, comprising: The electronic device comprises a driving controller and a display module, the driving controller is coupled with the display module; the display module comprises the display module in any one of claims 1-26.

28. The electronic device of claim 27, wherein, The driving controller is used for outputting an image signal to the display driving integrated circuit; the image signal comprises coordinate information of a scanning start line and a scanning stop line and a data signal.

29. A driving method of a display module, comprising: The display module comprises a first driving circuit and a first display driving integrated circuit, the first driving circuit comprises a plurality of cascaded first shift registers and a plurality of cascaded second shift registers, A driving method of the display module comprises: In a first time period of an image frame, the first stage of the first shift register receives an opening signal of the first gate start signal end, the Nth stage of the first shift register receives a signal of an output end of the N-1th stage of the first shift register; each stage of the first shift register receives a first clock signal of the first clock signal end; each stage of the first shift register outputs a scanning opening signal; N is an integer greater than 1; the frequency of the first clock signal is a first frequency; In the second time period of the image frame, the first stage of the second shift register receives an off signal of a second gate start signal end, the Mth stage of the second shift register receives a signal of an output end of the M-1th stage of the second shift register; each stage of the second shift register receives a second clock signal of the first clock signal end or a fixed voltage signal; each stage of the second shift register outputs a scanning off signal; M is an integer greater than 1; the second clock signal has a second frequency, and the second frequency is less than the first frequency.

30. The driving method according to claim 29, wherein The display module further comprises a second driving circuit, and the second driving circuit comprises a plurality of cascaded third shift registers and a plurality of cascaded fourth shift registers. In the first time period, the first stage of the third shift register receives an on signal of a third gate start signal end, the Oth stage of the third shift register receives a signal of an output end of the O-1th stage of the third shift register; each stage of the third shift register receives a third clock signal of a second clock signal end; each stage of the third shift register outputs a scanning on signal; O is an integer greater than 1. In the second time period, the first stage of the fourth shift register receives an on signal of a fourth gate start signal end, the Pth stage of the fourth shift register receives a signal of an output end of the P-1th stage of the fourth shift register; each stage of the fourth shift register receives the third clock signal of the second clock signal end; each stage of the fourth shift register outputs a scanning on signal; P is an integer greater than 1.

Images