Shift register and gate driver circuit

Abstract

The present disclosure relates to the technical field of displays, and provides a shift register and a gate driver circuit. The shift register comprises a first input circuit, a first output circuit, a first control circuit, and a second control circuit; the first input circuit is electrically connected to an input signal terminal, a seventh node, a ninth node, and a first clock signal terminal; the first output circuit is electrically connected to an output terminal and the seventh node, and is configured for loading a second power supply voltage to the output terminal in response to a gating level on the seventh node; the first control circuit is electrically connected to the seventh node and the ninth node, and is configured for loading a level on the ninth node to the seventh node in response to a gating level on the ninth node; the second control circuit is electrically connected to the ninth node and the first clock signal terminal, and is configured for changing a voltage of the ninth node by means of a coupling effect in response to a voltage change of the first clock signal. The present disclosure can improve the display quality of a display panel. (FIG. 8)

Description

Shift register and gate drive circuit

[0001] Cross-reference to related applications

[0002] The present disclosure claims priority to Chinese Patent Application No. 202410734402.8, filed on June 6, 2024, entitled “Shift register and gate drive circuit”, the entire contents of which are incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present disclosure relates to the technical field of display, in particular, to a shift register and a gate drive circuit. BACKGROUND

[0004] In the field of display, for example, in OLED (Organic Light Emitting Diode) display, the application of LTPO (Low Temperature Polycrystalline Oxide) is more and more widely. For the consideration of narrow frame, the gate drive circuit generally needs P-type LTPS (Low Temperature Polycrystalline Silicon); however, there is a step in the output waveform of the gate drive circuit, thereby affecting the display quality of the display panel.

[0005] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present disclosure, and therefore can include information that does not constitute prior art known to those of ordinary skill in the art. SUMMARY

[0006] The purpose of the present disclosure is to overcome the shortcomings of the prior art, and to provide a shift register and a gate drive circuit, which can improve the display quality of the display panel.

[0007] According to one aspect of the present disclosure, a shift register is provided, comprising a first input circuit, a first output circuit, a first control circuit, a second control circuit;

[0008] The first input circuit is electrically connected to an input signal terminal, a seventh node, a ninth node, and a first clock signal terminal, and is configured to load an input signal to the seventh node and the ninth node in response to a gating level of the first clock signal;

[0009] The first output circuit is electrically connected to an output terminal and the seventh node, and is configured to load a second power voltage to the output terminal in response to a gating level on the seventh node;

[0010] The first control circuit is electrically connected to the seventh node and the ninth node, and is configured to load a level on the ninth node to the seventh node in response to a gating level on the ninth node;

[0011] The second control circuit is electrically connected with the ninth node and the first clock signal terminal, and is configured to change the voltage of the ninth node by coupling effect in response to the voltage change of the first clock signal.

[0012] In an embodiment of the present disclosure, the second control circuit comprises a coupling sub-circuit and a control sub-circuit.

[0013] The coupling sub-circuit is electrically connected with the fifth node and the ninth node, and is configured to couple the voltage level on the fifth node to the ninth node.

[0014] The control sub-circuit is configured to control the voltage level of the fifth node according to the first clock signal.

[0015] The response speed of the control sub-circuit is less than the response speed of the first input circuit.

[0016] In an embodiment of the present disclosure, the control sub-circuit is electrically connected with the fifth node, the ninth node and the first clock signal terminal, and is configured to load the voltage level of the ninth node to the fifth node in response to the gating voltage level of the first clock signal.

[0017] In an embodiment of the present disclosure, the coupling sub-circuit comprises a third capacitor, which is electrically connected with the fifth node and the ninth node, and is configured to couple the voltage level on the fifth node to the ninth node.

[0018] The control sub-circuit comprises a seventeenth transistor, which is electrically connected with the fifth node, the ninth node and the first clock signal terminal, and is configured to load the voltage level of the ninth node to the fifth node in response to the gating voltage level of the first clock signal.

[0019] In an embodiment of the present disclosure, the control sub-circuit is electrically connected with the fifth node and the first clock signal terminal, and is configured to load the first clock signal to the fifth node in response to the gating voltage level of the first clock signal.

[0020] Alternatively, the control sub-circuit is electrically connected with the fifth node, the first clock signal terminal and the second power voltage terminal, and is configured to load the first clock signal to the fifth node in response to the second power voltage.

[0021] In an embodiment of the present disclosure, the coupling sub-circuit comprises a third capacitor, which is electrically connected with the fifth node and the ninth node, and is configured to couple the voltage level on the fifth node to the ninth node.

[0022] The control sub-circuit comprises a seventeenth transistor electrically connected to the fifth node, a first clock signal terminal, and configured to load the first clock signal to the fifth node in response to a gating level of the first clock signal.

[0023] Alternatively, the control sub-circuit comprises a seventeenth transistor electrically connected to the fifth node, a first clock signal terminal, and a second power voltage terminal, and configured to load the first clock signal to the fifth node in response to the second power voltage.

[0024] In an embodiment of the present disclosure, the second control circuit comprises a coupling sub-circuit electrically connected to the fifth node and a ninth node, and configured to couple a level on the fifth node to the ninth node; and the fifth node is electrically connected to the first clock signal terminal.

[0025] In an embodiment of the present disclosure, the coupling sub-circuit comprises a third capacitor electrically connected to the fifth node and the ninth node, and configured to couple a level on the fifth node to the ninth node; and the fifth node is electrically connected to the first clock signal terminal.

[0026] In an embodiment of the present disclosure, the second control circuit further comprises a fifth transistor electrically connected to a first power voltage terminal, a fourth node, and the fifth node, and configured to load the first power voltage to the fifth node in response to a gating level on the fourth node.

[0027] In an embodiment of the present disclosure, the second control circuit further comprises a fourth transistor electrically connected to the fifth node and the ninth node, and configured to load a level of the ninth node to the fifth node in response to a gating level on the ninth node.

[0028] When the second control circuit does not comprise a control sub-circuit, the fourth transistor is electrically connected to the fifth node, the ninth node, and the first clock signal terminal, and configured to load the first clock signal to the fifth node in response to a gating level on the ninth node.

[0029] When the second control circuit comprises a control sub-circuit, the fourth transistor is electrically connected to the fifth node, the ninth node, and the tenth node, and configured to load a level of the tenth node to the fifth node in response to a gating level on the ninth node.

[0030] In an embodiment of the present disclosure, the shift register further comprises a second input circuit, a node control circuit, a reset circuit, an isolation circuit, and a second output circuit.

[0031] The second input circuit is electrically connected with the second power voltage terminal, the second node and the first clock signal terminal, and is configured to load the second power voltage to the second node in response to the gating level of the first clock signal.

[0032] The node control circuit is electrically connected with the first node, the second node, the fourth node, the first power voltage terminal and the first clock signal terminal, and is configured to load the first clock signal to the second node in response to the gating level of the first node, and load the first power voltage to the fourth node in response to the gating level of the first node.

[0033] The reset circuit is electrically connected with the first power voltage terminal, the reset signal terminal and the first node, and is configured to load the first power voltage to the first node in response to the gating level of the reset signal.

[0034] The isolation circuit is electrically connected with the first node, the second node, the third node, the fourth node, the sixth node, the seventh node, the eighth node, the ninth node, the second clock signal terminal and the second power voltage terminal, and is configured to load the level of the second node to the sixth node in response to the second power voltage, load the level of the first node to the seventh node in response to the second power voltage, load the level of the eighth node to the ninth node in response to the second power voltage, and load the level of the third node to the fourth node in response to the second clock signal.

[0035] The second output circuit is electrically connected with the third node, the fourth node, the sixth node, the second clock signal terminal, the first power voltage terminal and the output terminal, and is configured to load the second clock signal to the third node in response to the gating level of the sixth node, and load the first power voltage to the output terminal in response to the gating level of the fourth node.

[0036] The clock period of the first clock signal is the same as that of the second clock signal, the gating level of the first clock signal lasts for no more than 1 / 4 clock period, and the gating level of the first clock signal is 1 / 2 clock period earlier than that of the second clock signal.

[0037] In an embodiment of the present disclosure, the first input circuit comprises a first transistor and a fourteenth transistor.

[0038] The first transistor is electrically connected with the input signal terminal, the first node and the first clock signal terminal, and is configured to load the input signal to the first node in response to the gating level of the first clock signal.

[0039] The fourteenth transistor is electrically connected with the input signal end, the eighth node and the first clock signal end, and is used for loading the input signal to the eighth node in response to the gating level of the first clock signal;

[0040] The first control circuit includes a sixteenth transistor, and the sixteenth transistor is electrically connected with the seventh node and the ninth node, and is used for loading the level of the ninth node to the seventh node in response to the gating level of the ninth node;

[0041] The first output circuit includes a tenth transistor, and the tenth transistor is electrically connected with the seventh node, the second power supply voltage end and the output end, and is used for loading the second power supply voltage to the output end in response to the gating level of the seventh node;

[0042] The second input circuit includes a third transistor, and the third transistor is electrically connected with the second power supply voltage end, the second node and the first clock signal end, and is used for loading the second power supply voltage to the second node in response to the gating level of the first clock signal;

[0043] The node control circuit includes a second transistor and an eighth transistor, and the second transistor is electrically connected with the first node, the second node and the first clock signal end, and is used for loading the first clock signal to the second node in response to the gating level of the first node;

[0044] The eighth transistor is electrically connected with the first node, the fourth node and the first power supply voltage end, and is used for loading the first power supply voltage to the fourth node in response to the gating level of the first node;

[0045] The reset circuit includes a thirteenth transistor, and the thirteenth transistor is electrically connected with the first power supply voltage end, the reset signal end and the first node, and is used for loading the first power supply voltage to the first node in response to the gating level of the reset signal;

[0046] The isolation circuit includes a seventh transistor, an eleventh transistor, a twelfth transistor and a fifteenth transistor, and the seventh transistor is electrically connected with the third node, the fourth node and the second clock signal end, and is used for loading the level of the third node to the fourth node in response to the second clock signal;

[0047] The eleventh transistor is electrically connected with the second node, the sixth node and the second power supply voltage end, and is used for loading the level of the second node to the sixth node in response to the second power supply voltage;

[0048] The twelfth transistor is electrically connected with the first node, the seventh node and the second power supply voltage end, and is used for loading the level of the first node to the seventh node in response to the second power supply voltage;

[0049] The fifteenth transistor is electrically connected with the eighth node, the ninth node and the second power voltage terminal, and is used for loading the level of the eighth node to the ninth node in response to the second power voltage;

[0050] The second output circuit comprises a sixth transistor, a ninth transistor, a first capacitor and a second capacitor; wherein the sixth transistor is electrically connected with the third node, the sixth node and the second clock signal terminal, and is used for loading the second clock signal to the third node in response to the gating level of the sixth node;

[0051] The ninth transistor is electrically connected with the fourth node, the first power voltage terminal and the output terminal, and is used for loading the first power voltage to the output terminal in response to the gating level of the fourth node;

[0052] The first capacitor is electrically connected with the third node and the sixth node, and is used for coupling the level of the sixth node to the third node;

[0053] The second capacitor is electrically connected with the first power voltage terminal and the fourth node, and is used for coupling the first power voltage to the fourth node.

[0054] According to another aspect of the present disclosure, there is also provided a gate driving circuit comprising the above-mentioned shift register; in two adjacent shift registers, the stage output terminal of the upper shift register is electrically connected with the input signal terminal of the lower shift register.

[0055] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0056] The accompanying drawings, which are incorporated into and form part of the specification, illustrate embodiments consistent with the present disclosure and, together with the specification, serve to explain the principles of the present disclosure. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0057] FIG. 1 is a schematic diagram of a display panel in an embodiment of the present disclosure.

[0058] FIG. 2 is a schematic diagram of a display panel in an embodiment of the present disclosure.

[0059] FIG. 3 is a schematic diagram of a display panel in an embodiment of the present disclosure.

[0060] FIG. 4 is a schematic diagram of a shift register in the related art.

[0061] FIG. 5 is a driving timing diagram of a shift register in the related art.

[0062] FIG. 6 is a simulation diagram of a scan signal output by a gate driving circuit in the related art.

[0063] FIG. 7 is a schematic diagram of a display panel in an embodiment of the present disclosure.

[0064] FIG. 8 is a schematic diagram of a shift register in an embodiment of the present disclosure.

[0065] FIG. 9 is a schematic diagram of a shift register in an embodiment of the present disclosure.

[0066] FIG. 10 is a driving timing diagram of a shift register in an embodiment of the present disclosure.

[0067] FIG. 11 is a schematic diagram of a shift register in an embodiment of the present disclosure.

[0068] FIG. 12 is a schematic diagram of a shift register in an embodiment of the present disclosure.

[0069] FIG. 13 is a schematic diagram of a shift register in an embodiment of the present disclosure.

[0070] FIG. 14 is a schematic diagram of a shift register in an embodiment of the present disclosure.

[0071] FIG. 15 is a simulation diagram of a scan signal output by a gate driving circuit in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0072] Example embodiments now will be described more fully hereinafter with reference to the accompanying drawings. Example embodiments, however, can be implemented in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of example embodiments to those skilled in the art. Like reference numerals refer to like elements throughout the drawings, and thus description of the same will be omitted. In addition, the drawings are to be considered in the illustrative mode, and not a restrictive one.

[0073] Although relative terms such as "upper", "lower", etc. are used herein to describe one component's relationship to another component in the drawings, these terms are used herein for convenience only and are not to be construed as limiting the scope of example embodiments. It is understood that if a device were turned over, the components described as being on "top" would then be on the "bottom". When a structure is on another structure, it can mean that the structure is formed integrally with the other structure, or that the structure is "directly" on the other structure, or that the structure is "indirectly" on the other structure via another structure.

[0074] The words "one", "a", "an", "the", and "said" are used as modifiers for conveying structural relationships made by the elements / components / etc. to which they refer; the words "include" and "has" are used as open-ended terms to mean that additional elements / components / etc. can be present in addition to those listed; the words "first", "second", and "third" etc. are used as labels for the purpose of distinguishing between elements / components / etc. that are otherwise identical.

[0075] In the embodiments of the present disclosure, a transistor refers to an element including at least three terminals of a gate, a source, and a drain. The transistor has a channel region between the drain (drain electrode terminal, drain region, or drain electrode) and the source (source electrode terminal, source region, or source electrode), and a current can flow through the source, the channel region, and the drain. The channel region refers to a region through which a current mainly flows. In the embodiments of the present disclosure, in the case of using a transistor with opposite polarity or in the case of changing the current direction in the operation of a circuit, the functions of the "source" and the "drain" are sometimes exchanged with each other, that is, the "source" and the "drain" can be exchanged with each other. In the embodiments of the present disclosure, for any one transistor, one of the "source" and the "drain" is referred to as a first electrode of the transistor, and the other is referred to as a second electrode of the transistor, and the gate is referred to as a control terminal of the transistor. In the embodiments of the present disclosure, at least part of a signal has a high level and a low level; one of the high level and the low level can be a gate-on level of the signal, which can cause a controlled transistor to be on; the other of the high level and the low level can be a gate-off level of the signal, which can cause the controlled transistor to be off. For example, for a signal for controlling a P-type transistor (which can be applied to the control terminal of the P-type transistor), the gate-on level thereof is the low level, and the gate-off level thereof is the high level. For another example, for a signal for controlling an N-type transistor (which can be applied to the control terminal of the N-type transistor), the gate-on level thereof is the high level, and the gate-off level thereof is the low level.

[0076] The structure layer A is located on the side of the structure layer B away from the substrate, which can be understood as that the structure layer A is formed on the side of the structure layer B away from the substrate. When the structure layer B is a patterned structure, part of the structure of the structure layer A can also be located at the same physical height as the structure layer B or below the physical height of the structure layer B, wherein the substrate is the height reference.

[0077] The display panel PNL includes a display area AA and a peripheral area BB located at least one side of the display area AA. In the display area AA, the display panel PNL is provided with display units UU arranged in an array, the display units UU including sub-pixels PIX and pixel driving circuits PDC driving the sub-pixels PIX. The display panel PNL is not provided with display units in the peripheral area BB, or the display units provided are not used for displaying pictures. Referring to FIG. 1, the display panel PNL is provided with a plurality of scan lines GL extending along a row direction DH in the display area AA, each scan line GL being arranged in one-to-one correspondence with each display unit row. The pixel driving circuit PDC of each display unit in the display unit row is electrically connected to the corresponding scan line GL. The display panel PNL is further provided with a plurality of data lines DL extending along a column direction DV in the display area AA, each data line DL being arranged in one-to-one correspondence with each display unit column. The pixel driving circuit PDC of each display unit in the display unit column is electrically connected to the corresponding data line DL. In this way, the pixel driving circuit PDC of each display unit is connected to the scan line GL and the data line DL. A scan signal is loaded on the scan line GL to control the state of the pixel driving circuit PDC. It can be understood that in the example of FIG. 1, only one kind of scan line GL corresponding to the display unit row is illustrated; according to needs, the display panel PNL can be provided with a plurality of different scan lines GL corresponding to the display unit row. The data line DL can be loaded with a data voltage Vdata for driving the pixel driving circuit PDC, and the pixel driving circuit PDC can drive the sub-pixel PIX according to the written data voltage Vdata, thereby controlling the brightness of the sub-pixel PIX. It can be understood that the pixel driving circuit PDC can also control the brightness of the sub-pixel PIX according to other signals.

[0078] Optionally, the pixel driving circuit PDC at least includes a data writing transistor, a driving transistor and a storage capacitor, the gate of the driving transistor can be electrically connected with one of the electrode plates of the storage capacitor. The source of the data writing transistor can be electrically connected with the data line DL, and the gate of the data writing transistor can be electrically connected with a writing control wire for loading a data writing signal (a kind of scanning signal). When the gating level of the data writing signal is loaded on the writing control wire, the data writing transistor is turned on, so that the driving voltage on the data line DL is written to the gate of the driving transistor and the storage capacitor. When the data writing transistor is turned off, the driving voltage can be maintained by the storage capacitor. The driving transistor can output a driving current to drive the sub-pixel PIX to emit light under the control of the voltage on its gate. It can be understood that the pixel driving circuit PDC of the embodiment of the present disclosure can also include other transistors or capacitors to make the pixel driving circuit PDC have better driving performance. For example, the pixel driving circuit PDC can be a 7T1C (7 thin film transistors and one storage capacitor), 8T1C (8 thin film transistors and one storage capacitor) or other architecture of pixel driving circuit.

[0079] Optionally, the sub-pixel PIX can be a current-driven self-luminous element, for example, can be any one of OLED, PLED, QLED, Micro LED, MiNi LED and the like. In this embodiment, the sub-pixel PIX can include sub-pixels PIX of multiple different colors, for example, including red sub-pixels for emitting red light, blue sub-pixels for emitting green light and green sub-pixels for emitting green light. It can be understood that in other embodiments of the present disclosure, the sub-pixels PIX in the display area AA can also have sub-pixels PIX of other colors (for example, yellow sub-pixels for emitting yellow light, cyan sub-pixels for emitting cyan light, white sub-pixels for emitting white light, etc.).

[0080] In an embodiment of the present disclosure, referring to FIG. 2, the display panel PNL can include a substrate SBT, a driving layer DRL and a pixel layer PIXL which are sequentially stacked. The pixel layer PIXL is provided with sub-pixels PIX, and the driving layer DRL is provided with pixel driving circuits PDC for driving the sub-pixels PIX; each sub-pixel PIX can emit light under the driving of the pixel driving circuit PDC to display a picture. Further, the display panel PNL further includes a thin film encapsulation layer TFE located away from the driving backplane DBP side of the pixel layer PIXL, and the thin film encapsulation layer TFE can encapsulate and protect the pixel layer PIXL.

[0081] Optionally, the substrate SBT can be a substrate of inorganic material, or a substrate of organic material, or a composite substrate of inorganic material and organic material. For example, in some embodiments of the present disclosure, the substrate SBT can be made of glass material such as soda lime glass, quartz glass, sapphire glass, etc. In some other embodiments of the present disclosure, the substrate SBT can be made of poly(methyl methacrylate), polyvinyl alcohol, polyvinyl phenol, polyether sulfone, polyimide, polyamide, polyacetal, polycarbonate, polyethylene terephthalate, polyethylene naphthalate, or a combination thereof. In some other embodiments of the present disclosure, the substrate SBT can be a flexible substrate, for example, the substrate SBT can include polyimide.

[0082] Optionally, in the driving layer DRL, any one of the pixel driving circuits PDC can include a thin film transistor TFT and a storage capacitor. Further, the thin film transistor TFT can be selected from a top-gate thin film transistor, a bottom-gate thin film transistor, or a dual-gate thin film transistor; the material of the active layer of the thin film transistor can be amorphous silicon semiconductor material, low-temperature polysilicon semiconductor material, metal oxide semiconductor material, organic semiconductor material, carbon nanotube semiconductor material, or other types of semiconductor material; the thin film transistor can be an N-type thin film transistor or a P-type thin film transistor.

[0083] It can be understood that in the pixel driving circuit, the types of any two transistors among the transistors can be the same or different. For example, in some embodiments, in a pixel driving circuit, part of the transistors can be N-type transistors and part of the transistors can be P-type transistors. For another example, in some other embodiments, in a pixel driving circuit, part of the transistors can be made of low-temperature polysilicon semiconductor material and part of the transistors can be made of metal oxide semiconductor material. In some embodiments of the present disclosure, the thin film transistor is a low-temperature polysilicon transistor. In some other embodiments of the present disclosure, part of the thin film transistors are low-temperature polysilicon transistors and part of the thin film transistors are metal oxide transistors.

[0084] Optionally, the driving layer DRL can include a semiconductor layer SCL, a gate insulating layer GI, a gate layer GT, an interlayer dielectric layer ILD, a source-drain metal layer SD, a planarization layer PLN, etc. which are stacked between the substrate base plate SBT and the pixel layer PI XL. Each thin film transistor and storage capacitor can be formed by the semiconductor layer SCL, the gate insulating layer GI, the gate layer GT, the interlayer dielectric layer ILD, the source-drain metal layer SD, etc. The positional relationship of each film layer can be determined according to the film layer structure of the thin film transistor. Further, the semiconductor layer SCL can be used to form the channel region of the transistor, and can also be used to form part of the wiring or conductive structure by being made conductive if necessary. The gate layer can be used to form one or more scanning lines, such as one or more of a write control line, a reset control line, a light-emitting control line, etc., and can also be used to form the gate of the transistor, and can also be used to form part or all of the electrode plate of the storage capacitor. The source-drain metal layer can be used to form the data line DL, the driving power supply voltage line, etc., and can also be used to form part of the electrode plate of the storage capacitor. Of course, in other embodiments of the present disclosure, the driving layer DRL can also include other film layers as needed, such as a light-blocking layer between the semiconductor layer SCL and the substrate base plate SBT, etc. Any of the above-mentioned semiconductor layer SCL, gate layer GT, source-drain metal layer SD, etc. can also be multi-layered as needed, such as two different semiconductor layers SCL in the driving layer DRL, or two or three source-drain metal layers SD, or two or three gate layers GT; accordingly, the insulating film layers in the driving layer DRL (such as the gate insulating layer GI, the interlayer dielectric layer ILD, the planarization layer PLN, etc.) can be adaptively increased or decreased, or new insulating film layers can be added as needed.

[0085] Optionally, the driving layer DRL can also include a passivation layer, which can be arranged on the surface of the source-drain metal layer SD away from the substrate base plate SBT, so as to protect the source-drain metal layer SD.

[0086] As an example, referring to FIG. 2, the driving layer DRL can include an inorganic buffer layer BUF, a semiconductor layer SCL, a gate insulating layer GI, a gate layer GT, an interlayer dielectric layer ILD, a source-drain metal layer SD, and a planarization layer PLN which are arranged in sequence, and the thin film transistor thus formed is a top-gate type thin film transistor.

[0087] In one embodiment of the present disclosure, referring to FIG. 2, the sub-pixel PIX in the pixel layer PIXL is a thin film light emitting element, which can include two electrodes and a light emitting functional layer arranged in a stack. For example, referring to FIG. 2, the pixel layer PIXL can include a pixel electrode layer PEL, a light emitting functional layer EFL and a common electrode layer COML arranged in a stack. The pixel electrode layer PEL has a plurality of pixel electrodes PE in the display area of the display panel; the light emitting functional layer EFL has a part connected with the pixel electrode PE as a light emitting functional unit of the sub-pixel PIX; and the common electrode layer COML is electrically connected with the light emitting functional unit of each sub-pixel PIX as a common electrode.

[0088] Further, the pixel layer PIXL can further include a pixel definition layer PDL between the pixel electrode layer PEL and the light emitting functional layer EFL. The pixel definition layer PDL has a plurality of through pixel openings corresponding to the plurality of pixel electrodes PE, and any one pixel opening exposes at least a part of the corresponding pixel electrode. For example, the pixel definition layer PDL covers the edges of the pixel electrode PE and exposes at least a part of the internal area of the pixel electrode PE, so that the pixel definition layer PDL can effectively define the actual effective area (the area directly connected with the light emitting functional layer EFL) of the pixel electrode PE, and further define the light emitting area and the light emitting area of the sub-pixel PIX. The light emitting functional layer EFL covers at least the pixel electrode PE exposed by the pixel definition layer PDL. The common electrode layer COML can cover the light emitting functional layer EFL in the display area. The pixel electrode PE and the common electrode layer COML provide carriers such as electrons and holes to the light emitting functional layer EFL, so that the light emitting functional layer EFL emits light. The part of the light emitting functional layer EFL between the pixel electrode PE and the common electrode layer COML can be a light emitting functional unit. The pixel electrode PE, the common electrode layer COML and the light emitting functional unit form a light emitting element LD as a sub-pixel. One of the pixel electrode PE and the common electrode layer COML is an anode of the sub-pixel PIX, and the other is a cathode of the sub-pixel PIX.

[0089] In one example, the pixel electrode PE is an anode of the sub-pixel PIX, and the common electrode layer COML is a cathode of the sub-pixel PIX.

[0090] It can be understood that the type of light emitting element is different, and the material and film layer of the light emitting functional layer EFL are different.

[0091] For example, when the light emitting element is an OLED, the light emitting functional layer EFL can include an organic light emitting layer EML, and can include one or more of a hole injection layer HIL, a hole transport layer HTL, an electron blocking layer EBL, a hole blocking layer HBL, an electron transport layer ETL, and an electron injection layer EIL. Further, the organic light emitting layer EML can include a light emitting layer host material and a light emitting layer guest material, which can be a fluorescent dopant or a phosphorescent dopant, and in particular, can be a thermally activated delayed fluorescence material. It can be understood that when the OLED adopts a stacked structure, a charge generation layer CGL can also be provided in the light emitting functional layer EFL.

[0092] For another example, when the light emitting element is a QLED, the light emitting functional layer EFL can include a quantum dot layer QDL, and can include one or more of a hole injection layer HIL, an electron transport layer ETL, an electron blocking layer EBL, a hole blocking layer HBL, an electron transport layer ETL, and an electron injection layer EIL. Further, the quantum dot layer QDL can have quantum dot particles, which can be connected to each other by surface modification groups. It can be understood that when the QLED adopts a stacked structure, a charge generation layer CGL can also be provided in the light emitting functional layer EFL.

[0093] Referring to FIG. 3, in the display panel PNL, a gate drive circuit GOA is provided in the peripheral region BB to provide a scan signal to the pixel drive circuit PDC. According to the needs of the pixel drive circuit PDC, a plurality of gate drive circuits GOA can be provided in the peripheral region BB to provide different scan signals, respectively. Of course, some scan signals can also share one gate drive circuit GOA.

[0094] Optionally, according to the needs of the pixel drive circuit PDC, the scan signal can include, but is not limited to, one or more of the following signals: a write control signal for controlling the writing of a data voltage to the pixel drive circuit PDC, a light emitting control signal for controlling the output of a drive current by the pixel drive circuit PDC, a reset control signal for controlling the reset of the pixel drive circuit PDC, and the like.

[0095] With the shift register SR of the related art shown in FIG. 4 as an example, referring to FIG. 4, the shift register SR includes first transistor T1-sixteenth transistor T16, and first capacitor C1-third capacitor C3. Wherein, each transistor is a P-type transistor, and the first electrode of the first transistor T1 is electrically connected with an input signal end, the second electrode of the first transistor T1 is electrically connected with a first node N1, and the control electrode of the first transistor T1 is electrically connected with a first clock signal end. The first electrode of the second transistor T2 is electrically connected with the first clock signal end, the second electrode of the second transistor T2 is electrically connected with a second node N2, and the control electrode of the second transistor T2 is electrically connected with the first node N1. The first electrode of the third transistor T3 is electrically connected with a low-level power voltage VGL, the second electrode of the third transistor T3 is electrically connected with the second node N2, and the control electrode of the third transistor T3 is electrically connected with the first clock signal end. The first electrode of the fourth transistor T4 is electrically connected with a second clock signal end, the second electrode of the fourth transistor T4 is electrically connected with a fifth node N5, and the control electrode of the fourth transistor T4 is electrically connected with a ninth node N9. The first electrode of the fifth transistor T5 is electrically connected with a high-level power voltage end, the second electrode of the fifth transistor T5 is electrically connected with the fifth node N5, and the control electrode of the fifth transistor T5 is electrically connected with the second node N2. The first electrode of the sixth transistor T6 is electrically connected with the second clock signal end, the second electrode of the sixth transistor T6 is electrically connected with a third node N3, and the control electrode of the sixth transistor T6 is electrically connected with a sixth node N6. The first electrode of the seventh transistor T7 is electrically connected with the third node N3, the second electrode of the seventh transistor T7 is electrically connected with a fourth node N4, and the control electrode of the seventh transistor T7 is electrically connected with the second clock signal end. The first electrode of the eighth transistor T8 is electrically connected with the high-level power voltage end, the second electrode of the eighth transistor T8 is electrically connected with the fourth node N4, and the control electrode of the eighth transistor T8 is electrically connected with the first node N1. The first electrode of the ninth transistor T9 is electrically connected with the high-level power voltage end, the second electrode of the ninth transistor T9 is electrically connected with an output end OUT, and the control electrode of the ninth transistor T9 is electrically connected with the fourth node N4. The first electrode of the tenth transistor T10 is electrically connected with a low-level power voltage end, the second electrode of the tenth transistor T10 is electrically connected with the output end OUT, and the control electrode of the tenth transistor T10 is electrically connected with a seventh node N7. The first electrode of the eleventh transistor T11 is electrically connected with the second node N2, the second electrode of the eleventh transistor T11 is electrically connected with the sixth node N6, and the control electrode of the eleventh transistor T11 is electrically connected with the low-level power voltage end. The first electrode of the twelfth transistor T12 is electrically connected with the first node N1, the second electrode of the twelfth transistor T12 is electrically connected with the seventh node N7, and the control electrode of the twelfth transistor T12 is electrically connected with the low-level power voltage end. The first electrode of the thirteenth transistor T13 is electrically connected with the high-level power voltage end, the second electrode of the thirteenth transistor T13 is electrically connected with the first node N1, and the control electrode of the thirteenth transistor T13 is electrically connected with a reset signal end.The first electrode of the fourteenth transistor T14 is electrically connected with an input signal terminal, the second electrode of the fourteenth transistor T14 is electrically connected with the eighth node N8, and the control electrode of the fourteenth transistor T14 is electrically connected with a first clock signal terminal. The first electrode of the fifteenth transistor T15 is electrically connected with the eighth node N8, the second electrode of the fifteenth transistor T15 is electrically connected with the ninth node N9, and the control electrode of the fifteenth transistor T15 is electrically connected with a low-level power supply voltage terminal. The first electrode of the sixteenth transistor T16 is electrically connected with the ninth node N9, the second electrode of the sixteenth transistor T16 is electrically connected with the seventh node N7, and the control electrode of the sixteenth transistor T16 is electrically connected with the ninth node N9. One end of the first capacitor C1 is electrically connected with the sixth node N6, and the other end of the first capacitor C1 is electrically connected with the third node N3. One end of the second capacitor C2 is electrically connected with a high-level power supply voltage terminal, and the other end of the second capacitor C2 is electrically connected with the fourth node N4. One end of the third capacitor C3 is electrically connected with the fifth node N5, and the other end of the third capacitor C3 is electrically connected with the ninth node N9.

[0096] Fig. 5 is a driving timing diagram of the shift register SR shown in Fig. 4. Referring to Fig. 5, in the P1 stage and the P2 stage, the high-level power supply voltage VGH and the high level of the second clock signal CKB are loaded to the fifth node N5 in turn, through the coupling effect of the third capacitor C3, the sixteenth transistor T16 is not completely turned on, and the low level of the first node N1 and the ninth node N9 is loaded to the seventh node N7, so that the tenth transistor T10 is turned on (but due to the threshold voltage of the tenth transistor T10, the tenth transistor T10 is not completely turned on), thereby the output terminal OUT outputs a low level. In the P3 stage, the second clock signal CKB is loaded to the fifth node N5 as a low level, through the coupling effect of the third capacitor C3, the ninth node N9 is further pulled down, so that the sixteenth transistor T16 is completely turned on, and then the seventh node N7 is further pulled down, thereby the tenth transistor T10 is completely turned on, and the output terminal OUT outputs a lower level.

[0097] In the related art, referring to Figs. 5 and 6, the waveform output by the output terminal OUT has steps, and loading this waveform into the pixel driving circuit PDC (not shown in the figure) will cause the driving current to be of different sizes, thereby affecting the display quality of the display panel PNL. For example, horizontal stripes and other defects appear on the display panel PNL.

[0098] To solve the above problems, in the embodiments of the present disclosure, referring to FIG. 7, a gate drive circuit GOA and first and second control wires CL1 and CL2 for the gate drive circuit GOA are arranged in the peripheral area BB of the display panel PNL to provide a scanning signal to the display area AA of the display panel PNL. The gate drive circuit GOA includes a plurality of shift registers SR cascaded in sequence. The first control wire CL1 is electrically connected to the first clock signal end of the odd-numbered shift registers SR and the second clock signal end of the even-numbered shift registers SR. The second control wire CL2 is electrically connected to the second clock signal end of the odd-numbered shift registers SR and the first clock signal end of the even-numbered shift registers SR. In the two adjacent shift registers SR, the stage output end OUT of the upper shift register SR is electrically connected to the input signal end of the lower shift register SR. It can be understood that in the first shift register SR, the input signal IN is a start signal STV. Referring to FIG. 8, the shift register SR includes a first input circuit INM1, a first output circuit OUTM1, a first control circuit CTR1, and a second control circuit CTR2.

[0099] The first input circuit INM1 is electrically connected to the input signal end, the seventh node N7, the ninth node N9, and the first clock signal end, and is configured to load the input signal IN to the seventh node N7 and the ninth node N9 in response to the gating level of the first clock signal CKA. The first output circuit OUTM1 is electrically connected to the output end OUT, the seventh node N7, and the second power supply voltage end, and is configured to load the second power supply voltage V2 to the output end OUT in response to the gating level on the seventh node N7. The first control circuit CTR1 is electrically connected to the seventh node N7 and the ninth node N9, and is configured to load the level on the ninth node N9 to the seventh node N7 in response to the gating level on the ninth node N9. The second control circuit CTR2 is electrically connected to the ninth node N9 and the first clock signal end, and is configured to change the voltage of the ninth node N9 through a coupling effect in response to the voltage change of the first clock signal CKA.

[0100] In this way, the level of the ninth node N9 is controlled by the voltage change of the first clock signal CKA, and when the shift register SR starts to work, the first output circuit OUTM1 can be completely turned on, so that the output end OUT outputs a scanning signal without steps, which is beneficial to improve the uniformity of the driving current in the pixel driving circuit PDC, reduces the possibility of horizontal lines appearing on the display panel PNL, and facilitates to improve the display quality of the display panel PNL.

[0101] It can be understood that in the present disclosure, each signal has a corresponding signal terminal. In one example, the first clock signal CKA has a first clock signal terminal. In another example, the second clock signal CKB has a second clock signal terminal.

[0102] In an embodiment of the present disclosure, one gate drive circuit GOA includes a plurality of shift registers SR connected in series. Between any two adjacent shift registers SR of the same gate drive circuit GOA, no shift register SR of another gate drive circuit GOA can be arranged, or a shift register SR of another gate drive circuit GOA can be arranged as needed.

[0103] In one example, the shift registers SR of at least one gate drive circuit GOA are arranged linearly along the column direction DV and connected in series. Between any two adjacent shift registers SR of the same gate drive circuit GOA, no shift register SR of another gate drive circuit GOA is arranged.

[0104] In another example, the shift registers SR of at least one gate drive circuit GOA are arranged linearly along the column direction DV, and between any two adjacent shift registers SR of the same gate drive circuit GOA, a shift register SR of another gate drive circuit GOA is arranged. In other words, the shift registers SR arranged linearly along the column direction DV can belong to a plurality of different gate drive circuits GOA, and the shift registers SR of the plurality of gate drive circuits GOA can be arranged alternately in series.

[0105] For example, the shift registers SR of the four gate driving circuits GOA are arranged in a straight line along the column direction DV and are arranged alternately; GOA(m)-SR(k) represents the kth shift register SR of the mth gate driving circuit GOA. The arrangement order of the shift registers SR of the four gate driving circuits GOA is GOA(1)-SR(1), GOA(2)-SR(1), GOA(3)-SR(1), GOA(4)-SR(1), GOA(1)-SR(2), GOA(2)-SR(2), GOA(3)-SR(2), GOA(4)-SR(2)…GOA(1)-SR(i), GOA(2)-SR(i), GOA(3)-SR(i), GOA(4)-SR(i), GOA(1)-SR(i+1), GOA(2)-SR(i+1), GOA(3)-SR(i+1), GOA(4)-SR(i+1). Wherein, m, k, i are all integers greater than 0. For example, m, k, i can be 1, 2, 3, 4, 5, 6, etc. GOA(1)-SR(1), GOA(1)-SR(2)…GOA(1)-SR(i), GOA(1)-SR(i+1) and the like are cascaded in turn until the last shift register SR of the first gate driving circuit GOA, forming the first gate driving circuit GOA; similarly, GOA(2)-SR(1), GOA(2)-SR(2)…GOA(2)-SR(i), GOA(2)-SR(i+1) and the like are cascaded in turn until the last shift register SR of the second gate driving circuit GOA, forming the second gate driving circuit GOA; GOA(3)-SR(1), GOA(3)-SR(2)…GOA(3)-SR(i), GOA(3)-SR(i+1) and the like are cascaded in turn until the last shift register SR of the third gate driving circuit GOA, forming the third gate driving circuit GOA; GOA(4)-SR(1), GOA(4)-SR(2)…GOA(4)-SR(i), GOA(4)-SR(i+1) and the like are cascaded in turn until the last shift register SR of the fourth gate driving circuit GOA, forming the fourth gate driving circuit GOA.

[0106] In this example, the formation of four gate driving circuits GOA by the same shift register column is exemplarily described. It can be understood that the same shift register column can form other numbers of gate driving circuits GOA, for example, 2 gate driving circuits GOA, 3 gate driving circuits GOA, 5 gate driving circuits GOA or 6 gate driving circuits GOA, etc.

[0107] In one embodiment of the present disclosure, referring to FIG. 8, the second control circuit CTR2 includes a coupling sub-circuit COC and a control sub-circuit COS. The coupling sub-circuit COC is electrically connected to the fifth node N5 and the ninth node N9, and is configured to couple the level on the fifth node N5 to the ninth node N9. The control sub-circuit COS is configured to control the level of the fifth node N5 according to the first clock signal CKA. For example, the control sub-circuit COS controls the fifth node N5 to be at a low level according to the low level of the first clock signal CKA. The response speed of the control sub-circuit COS is less than the response speed of the first input circuit INM1. In this way, by controlling the level of the fifth node N5 according to the first clock signal CKA by the control sub-circuit COS, coupling the level of the fifth node N5 to the ninth node N9 by the coupling sub-circuit COC, and the response speed of the control sub-circuit COS being less than the response speed of the first input circuit INM1, when the shift register SR starts to work, the speed of loading the input signal IN to the seventh node N7 is faster than the speed of coupling the level of the fifth node N5 to the ninth node N9, so as to facilitate the first input circuit INM1 to be fully turned on.

[0108] In one embodiment of the present disclosure, the control sub-circuit COS is electrically connected to the fifth node N5, the ninth node N9, and the first clock signal terminal, and is configured to load the level of the ninth node N9 to the fifth node N5 in response to the gating level of the first clock signal CKA. In other words, the first end of the control sub-circuit COS is electrically connected to the ninth node N9, the second end is electrically connected to the fifth node N5, and the control end is electrically connected to the first clock signal terminal.

[0109] In one embodiment of the present disclosure, the control sub-circuit COS is electrically connected to the fifth node N5, the first clock signal terminal, and is configured to load the first clock signal CKA to the fifth node N5 in response to the gating level of the first clock signal CKA. In other words, the first end, the control end, and the first clock signal CKA of the control sub-circuit COS are electrically connected to each other, and the second end is electrically connected to the fifth node N5.

[0110] In one embodiment of the present disclosure, the control sub-circuit COS is electrically connected to the fifth node N5, the first clock signal terminal, and the second power supply voltage terminal, and is configured to load the first clock signal CKA to the fifth node N5 in response to the second power supply voltage V2. In other words, the first end of the control sub-circuit COS is electrically connected to the first clock signal terminal, the second end is electrically connected to the fifth node N5, and the control end is electrically connected to the second power supply voltage V2.

[0111] In one embodiment of the present disclosure, the second control circuit CTR2 comprises a coupling sub-circuit COC. The coupling sub-circuit COC is electrically connected to the fifth node N5 and the ninth node N9, and is configured to couple the level on the fifth node N5 to the ninth node N9. The fifth node N5 is configured to be electrically connected to the first clock signal terminal. In one example, one end of the coupling sub-circuit COC, the fifth node N5, and the first clock signal terminal are electrically connected to each other, and the other end is electrically connected to the ninth node N9. In another example, one end of the coupling sub-circuit COC is electrically connected to the fifth node N5, and the other end is electrically connected to the ninth node N9. The fifth node N5 is electrically connected to the first clock signal terminal through at least one transistor.

[0112] In one embodiment of the present disclosure, referring to FIG. 8, the second control circuit CTR2 further comprises a fifth transistor T5. The fifth transistor T5 is electrically connected to the first power supply voltage terminal, the fourth node N4, and the fifth node N5, and is configured to load the first power supply voltage V1 to the fifth node N5 in response to the gating level on the fourth node N4. In other words, the first electrode of the fifth transistor T5 is electrically connected to the first power supply voltage V1, the second electrode is electrically connected to the fifth node N5, and the control electrode is electrically connected to the fourth node N4. In this way, the level of the fifth node N5 can be controlled by turning on the fifth transistor T5. In other embodiments of the present disclosure, the second control circuit CTR2 can further comprise a plurality of fifth transistors T5 connected in series or in parallel.

[0113] In one embodiment of the present disclosure, referring to FIG. 8, the second control circuit CTR2 further comprises a fourth transistor T4. When the second control circuit CTR2 does not comprise the control sub-circuit COS, the fourth transistor T4 is electrically connected to the fifth node N5, the ninth node N9, and the first clock signal terminal, and is configured to load the first clock signal CKA to the fifth node N5 in response to the gating level on the ninth node N9. In other words, the first electrode of the fourth transistor T4 is electrically connected to the first clock signal terminal, the second electrode is electrically connected to the fifth node N5, and the control electrode is electrically connected to the ninth node N9.

[0114] When the second control circuit CTR2 includes the control sub-circuit COS, the fourth transistor T4 is electrically connected with the fifth node N5, the ninth node N9 and the tenth node N10, and is configured to load the level of the tenth node N10 to the fifth node N5 in response to the gate-on level on the ninth node N9. In other words, the first electrode of the fifth transistor T5 is electrically connected with the second end of the control sub-circuit COS, the second electrode is electrically connected with the fifth node N5, and the control electrode is electrically connected with the ninth node N9. In this way, the fourth transistor T4 can isolate the tenth node N10 from the fifth node N5, so as to prevent the level change of the tenth node N10 from affecting the level of the fifth node N5.

[0115] In an embodiment of the present disclosure, the second control circuit CTR2 further includes a fourth transistor T4 and a fifth transistor T5. The fifth transistor T5 is electrically connected with the first power voltage terminal, the fourth node N4 and the fifth node N5, and is configured to load the first power voltage V1 to the fifth node N5 in response to the gate-on level on the fourth node N4. In other words, the first electrode of the fifth transistor T5 is electrically connected with the first power voltage V1, the second electrode is electrically connected with the fifth node N5, and the control electrode is electrically connected with the fourth node N4.

[0116] When the second control circuit CTR2 does not include the control sub-circuit COS, the fourth transistor T4 is electrically connected with the fifth node N5, the ninth node N9 and the first clock signal terminal, and is configured to load the first clock signal CKA to the fifth node N5 in response to the gate-on level on the ninth node N9. In other words, the first electrode of the fourth transistor T4 is electrically connected with the first clock signal terminal, the second electrode is electrically connected with the fifth node N5, and the control electrode is electrically connected with the ninth node N9.

[0117] When the second control circuit CTR2 includes the control sub-circuit COS, the fourth transistor T4 is electrically connected with the fifth node N5, the ninth node N9 and the tenth node N10, and is configured to load the level of the tenth node N10 to the fifth node N5 in response to the gate-on level on the ninth node N9. The first electrode of the fifth transistor T5 is electrically connected with the second end of the control sub-circuit COS, the second electrode is electrically connected with the fifth node N5, and the control electrode is electrically connected with the ninth node N9.

[0118] In one embodiment of the present disclosure, referring to FIG. 8, the shift register SR further comprises a second input circuit INM2, a node control circuit PRM, a reset circuit REC, an isolation circuit ISC, a second output circuit OUTM2. The second input circuit INM2 is electrically connected with a second power voltage terminal, a second node N2, a first clock signal terminal, and is configured to load the second power voltage V2 to the second node N2 in response to a gating level of the first clock signal CKA. In this way, the level of the second node N2 is controlled.

[0119] The node control circuit PRM is electrically connected with the first node N1, the second node N2, the fourth node N4, the first power voltage terminal, the first clock signal terminal, and is configured to load the first clock signal CKA to the second node N2 in response to a gating level of the first node N1, and is configured to load the first power voltage V1 to the fourth node N4 in response to a gating level of the first node N1. In this way, the levels of the second node N2 and the fourth node N4 are controlled.

[0120] The reset circuit REC is electrically connected with the first power voltage terminal, a reset signal terminal, the first node N1, and is configured to load the first power voltage V1 to the first node N1 in response to a gating level of the reset signal Reset. In this way, the level of the first node N1 is controlled.

[0121] The isolation circuit ISC is electrically connected with the first node N1, the second node N2, the third node N3, the fourth node N4, the sixth node N6, the seventh node N7, the eighth node N8, the ninth node N9, a second clock signal terminal, a second power voltage terminal, and is configured to load the level of the second node N2 to the sixth node N6 in response to the second power voltage V2, and is configured to load the level of the first node N1 to the seventh node N7 in response to the second power voltage V2, and is configured to load the level of the eighth node N8 to the ninth node N9 in response to the second power voltage V2, and is configured to load the level of the third node N3 to the fourth node N4 in response to the second clock signal CKB. In this way, the levels of the first node N1, the second node N2, the third node N3, the fourth node N4, the sixth node N6, the seventh node N7, the eighth node N8, the ninth node N9 are controlled without affecting each other.

[0122] The second output circuit OUTM2 is electrically connected with the third node N3, the fourth node N4, the sixth node N6, a second clock signal terminal, a first power voltage terminal and the output terminal OUT, and is configured to load the second clock signal CKB to the third node N3 in response to the gating level of the sixth node N6, and load the first power voltage V1 to the output terminal OUT in response to the gating level of the fourth node N4, so as to control the level of the output terminal OUT.

[0123] In one embodiment of the present disclosure, referring to FIG. 10, the first clock signal CKA and the second clock signal CKB have the same clock period; the gating level of the first clock signal CKA and the gating level of the second clock signal CKB each lasts no more than 1 / 4 of a clock period; for example, the gating level of the first clock signal CKA and the gating level of the second clock signal CKB can each last 1 / 4, 1 / 5, 1 / 6, 1 / 7, etc. of a clock period. The gating level of the first clock signal CKA is 1 / 2 of a clock period earlier than the gating level of the second clock signal CKB.

[0124] It can be understood that in the embodiments of the present disclosure, one clock period refers to the period of a clock signal. Referring to FIG. 10, taking the first clock signal CKA as an example, one clock period refers to the time length used in the process from the first time when the first clock signal CKA becomes low to the second time when the first clock signal CKA becomes low. In other words, one clock period refers to the time length from P1 to P4.

[0125] In one embodiment of the present disclosure, referring to FIG. 8, the first input circuit INM1 includes a first transistor T1 and a fourteenth transistor T14. The first transistor T1 is electrically connected with an input signal terminal, a first node N1 and a first clock signal terminal, and is configured to load an input signal IN to the first node N1 in response to the gating level of the first clock signal CKA. In other words, the first electrode of the first transistor T1 is electrically connected with the input signal terminal, the second electrode is electrically connected with the first node N1, and the control electrode is electrically connected with the first clock signal terminal.

[0126] The fourteenth transistor T14 is electrically connected with the input signal terminal, an eighth node N8 and the first clock signal terminal, and is configured to load the input signal IN to the eighth node N8 in response to the gating level of the first clock signal CKA. In other words, the first electrode of the fourteenth transistor T14 is electrically connected with the input signal terminal, the second electrode is electrically connected with the eighth node N8, and the control electrode is electrically connected with the first clock signal terminal.

[0127] In one implementation of the present disclosure, referring to FIG. 8, the first control circuit CTR1 includes a sixteenth transistor T16; the sixteenth transistor T16 is electrically connected with the seventh node N7 and the ninth node N9, and is configured to load the level of the ninth node N9 to the seventh node N7 in response to the gating level of the ninth node N9. In other words, the first pole, the control pole and the ninth node N9 of the sixteenth transistor T16 are electrically connected with each other, and the second pole is electrically connected with the seventh node N7.

[0128] In one implementation of the present disclosure, referring to FIG. 8, the first output circuit OUTM1 includes a tenth transistor T10; the tenth transistor T10 is electrically connected with the seventh node N7, the second power supply voltage terminal and the output terminal OUT, and is configured to load the second power supply voltage V2 to the output terminal OUT in response to the gating level of the seventh node N7. In other words, the first pole of the tenth transistor T10 is electrically connected with the second power supply voltage V2, the second pole is electrically connected with the output terminal OUT, and the control pole is electrically connected with the seventh node N7.

[0129] In one implementation of the present disclosure, referring to FIG. 8, the second input circuit INM2 includes a third transistor T3. The third transistor T3 is electrically connected with the second power supply voltage terminal, the second node N2 and the first clock signal terminal, and is configured to load the second power supply voltage V2 to the second node N2 in response to the gating level of the first clock signal CKA; in other words, the first pole of the third transistor T3 is electrically connected with the second power supply voltage V2, the second pole of the third transistor T3 is electrically connected with the second node N2, and the control pole of the third transistor T3 is electrically connected with the first clock signal terminal.

[0130] In one implementation of the present disclosure, referring to FIG. 8, the node control circuit PRM includes a second transistor T2 and an eighth transistor T8. The second transistor T2 is electrically connected with the first node N1, the second node N2 and the first clock signal terminal, and is configured to load the first clock signal CKA to the second node N2 in response to the gating level on the first node N1; in other words, the first pole of the second transistor T2 is electrically connected with the first clock signal terminal, the second pole of the second transistor T2 is electrically connected with the second node N2, and the control pole of the second transistor T2 is electrically connected with the first node N1.

[0131] In one implementation of the present disclosure, referring to FIG. 8, the eighth transistor T8 is electrically connected with the first node N1, the fourth node N4 and the first power supply voltage terminal, and is configured to load the first power supply voltage V1 to the fourth node N4 in response to the gating level on the first node N1; in other words, the first pole of the eighth transistor T8 is electrically connected with the first power supply voltage V1, the second pole of the eighth transistor T8 is electrically connected with the fourth node N4, and the control pole of the eighth transistor T8 is electrically connected with the first node N1.

[0132] In one embodiment of the present disclosure, referring to FIG. 8, the reset circuit REC comprises a thirteenth transistor T13; the thirteenth transistor T13 is electrically connected with the first power voltage terminal, the reset signal terminal, and the first node N1, and is configured to load the first power voltage V1 to the first node N1 in response to the gating level of the reset signal Reset; in other words, the first electrode of the thirteenth transistor T13 is electrically connected with the first power voltage V1, the second electrode of the thirteenth transistor T13 is electrically connected with the first node N1, and the control electrode of the thirteenth transistor T13 is electrically connected with the reset signal terminal.

[0133] In one embodiment of the present disclosure, referring to FIG. 8, the isolation circuit ISC comprises a seventh transistor T7, an eleventh transistor T11, a twelfth transistor T12, and a fifteenth transistor T15; wherein the seventh transistor T7 is electrically connected with the third node N3, the fourth node N4, and the second clock signal terminal, and is configured to load the level of the third node N3 to the fourth node N4 in response to the second clock signal CKB; in other words, the first electrode of the seventh transistor T7 is electrically connected with the third node N3, the second electrode of the seventh transistor T7 is electrically connected with the fourth node N4, and the control electrode of the seventh transistor T7 is electrically connected with the second clock signal terminal. So as to isolate the third node N3 and the fourth node N4.

[0134] The eleventh transistor T11 is electrically connected with the second node N2, the sixth node N6, and the second power voltage terminal, and is configured to load the level of the second node N2 to the sixth node N6 in response to the second power voltage V2; in other words, the first electrode of the eleventh transistor T11 is electrically connected with the second node N2, the second electrode of the eleventh transistor T11 is electrically connected with the sixth node N6, and the control electrode of the eleventh transistor T11 is electrically connected with the second power voltage V2. So as to isolate the second node N2 and the sixth node N6.

[0135] The twelfth transistor T12 is electrically connected with the first node N1, the seventh node N7, and the second power voltage terminal, and is configured to load the level of the first node N1 to the seventh node N7 in response to the second power voltage V2; in other words, the first electrode of the twelfth transistor T12 is electrically connected with the first node N1, the second electrode of the twelfth transistor T12 is electrically connected with the seventh node N7, and the control electrode of the twelfth transistor T12 is electrically connected with the second power voltage V2. So as to isolate the first node N1 and the seventh node N7.

[0136] The fifteenth transistor T15 is electrically connected with the eighth node N8, the ninth node N9, and the second power voltage terminal, and is used for loading the level of the eighth node N8 to the ninth node N9 in response to the second power voltage V2; in other words, the first pole of the fifteenth transistor T15 is electrically connected with the eighth node N8, the second pole of the fifteenth transistor T15 is electrically connected with the ninth node N9, and the control pole of the fifteenth transistor T15 is electrically connected with the second power voltage V2. So as to isolate the eighth node N8 and the ninth node N9.

[0137] In one embodiment of the present disclosure, referring to FIG. 8, the second output circuit OUTM2 includes a sixth transistor T6, a ninth transistor T9, a first capacitor C1, and a second capacitor C2; wherein the sixth transistor T6 is electrically connected with the third node N3, the sixth node N6, and the second clock signal terminal, and is used for loading the second clock signal CKB to the third node N3 in response to the gating level of the sixth node N6; in other words, the first pole of the sixth transistor T6 is electrically connected with the second clock signal terminal, the second pole of the sixth transistor T6 is electrically connected with the third node N3, and the control pole of the sixth transistor T6 is electrically connected with the sixth node N6.

[0138] In one embodiment of the present disclosure, referring to FIG. 8, the ninth transistor T9 is electrically connected with the fourth node N4, the first power voltage terminal, and the output terminal OUT, and is used for loading the first power voltage V1 to the output terminal OUT in response to the gating level of the fourth node N4; in other words, the first pole of the ninth transistor T9 is electrically connected with the first power voltage V1, the second pole of the ninth transistor T9 is electrically connected with the output terminal OUT, and the control pole of the ninth transistor T9 is electrically connected with the fourth node N4.

[0139] In one embodiment of the present disclosure, referring to FIG. 8, the first capacitor C1 is electrically connected with the third node N3 and the sixth node N6, and is used for coupling the level of the sixth node N6 to the third node N3. In other words, one end of the first capacitor C1 is electrically connected with the sixth node N6, and the other end of the first capacitor C1 is electrically connected with the third node N3.

[0140] In one embodiment of the present disclosure, referring to FIG. 8, the second capacitor C2 is electrically connected with the first power voltage terminal and the fourth node N4, and is used for coupling the first power voltage V1 to the fourth node N4. In other words, one end of the second capacitor C2 is electrically connected with the first power voltage V1, and the other end of the second capacitor C2 is electrically connected with the fourth node N4.

[0141] In one embodiment of the present disclosure, the coupling sub-circuit COC includes a third capacitor C3. The third capacitor C3 is electrically connected to the fifth node N5 and the ninth node N9, and is configured to couple a level on the fifth node N5 to the ninth node N9. In other words, one end of the third capacitor C3 is electrically connected to the fifth node N5, and the other end of the third capacitor C3 is electrically connected to the ninth node N9.

[0142] The control sub-circuit COS includes a seventeenth transistor T17. The seventeenth transistor T17 is electrically connected to the fifth node N5, the ninth node N9, and the first clock signal terminal, and is configured to load a level of the ninth node N9 to the fifth node N5 in response to a gating level of the first clock signal CKA. In other words, the first electrode of the seventeenth transistor T17 is electrically connected to the ninth node N9, the second electrode of the seventeenth transistor T17 is electrically connected to the fifth node N5, and the control electrode of the seventeenth transistor T17 is electrically connected to the first clock signal terminal.

[0143] In one embodiment of the present disclosure, the coupling sub-circuit COC includes a third capacitor C3. The third capacitor C3 is electrically connected to the fifth node N5 and the ninth node N9, and is configured to couple a level on the fifth node N5 to the ninth node N9. In other words, one end of the third capacitor C3 is electrically connected to the fifth node N5, and the other end of the third capacitor C3 is electrically connected to the ninth node N9.

[0144] The control sub-circuit COS includes a seventeenth transistor T17. The seventeenth transistor T17 is electrically connected to the fifth node N5, the ninth node N9, and the first clock signal terminal, and is configured to load a level of the ninth node N9 to the fifth node N5 in response to a gating level of the first clock signal CKA. In other words, the first electrode of the seventeenth transistor T17 is electrically connected to the ninth node N9, the second electrode of the seventeenth transistor T17 is electrically connected to the fifth node N5, and the control electrode of the seventeenth transistor T17 is electrically connected to the first clock signal terminal.

[0145] In one embodiment of the present disclosure, the coupling sub-circuit COC includes a third capacitor C3. The third capacitor C3 is electrically connected to the fifth node N5 and the ninth node N9, and is configured to couple a level on the fifth node N5 to the ninth node N9. In other words, one end of the third capacitor C3 is electrically connected to the fifth node N5, and the other end of the third capacitor C3 is electrically connected to the ninth node N9.

[0146] The control sub-circuit COS includes a seventeenth transistor T17, which is electrically connected with the fifth node N5, a first clock signal terminal, and a second power voltage terminal, and is used for loading the first clock signal CKA to the fifth node N5 in response to the second power voltage V2. In other words, the first electrode of the seventeenth transistor T17 is electrically connected with the first clock signal terminal, the second electrode is electrically connected with the fifth node N5, and the control electrode is electrically connected with the second power voltage V2.

[0147] In one embodiment of the present disclosure, the coupling sub-circuit COC includes a third capacitor C3, which is electrically connected with the fifth node N5 and a ninth node N9, and is used for coupling the level on the fifth node N5 to the ninth node N9; the fifth node N5 is used for being electrically connected with the first clock signal terminal. In other words, one end of the third capacitor C3 is electrically connected with the fifth node N5, and the other end of the third capacitor C3 is electrically connected with the ninth node N9.

[0148] The working principle of the shift register SR of the present disclosure will be described below in combination with five examples.

[0149] In a first example, referring to FIG. 9, the shift register SR includes first transistor T1-seventeenth transistor T17, and first capacitor C1-third capacitor C3. Wherein, the first electrode of the first transistor T1 is electrically connected with the input signal end, the second electrode is electrically connected with the first node N1, and the control electrode is electrically connected with the first clock signal end. The first electrode of the second transistor T2 is electrically connected with the first clock signal end, the second electrode of the second transistor T2 is electrically connected with the second node N2, and the control electrode of the second transistor T2 is electrically connected with the first node N1. The first electrode of the third transistor T3 is electrically connected with the second power supply voltage V2, the second electrode of the third transistor T3 is electrically connected with the second node N2, and the control electrode of the third transistor T3 is electrically connected with the first clock signal end. The first electrode of the fourth transistor T4 is electrically connected with the tenth node N10, the second electrode is electrically connected with the fifth node N5, and the control electrode is electrically connected with the ninth node N9. The first electrode of the fifth transistor T5 is electrically connected with the first power supply voltage V1, the second electrode is electrically connected with the fifth node N5, and the control electrode is electrically connected with the fourth node N4. The first electrode of the sixth transistor T6 is electrically connected with the second clock signal end, the second electrode of the sixth transistor T6 is electrically connected with the third node N3, and the control electrode of the sixth transistor T6 is electrically connected with the sixth node N6. The first electrode of the seventh transistor T7 is electrically connected with the third node N3, the second electrode of the seventh transistor T7 is electrically connected with the fourth node N4, and the control electrode of the seventh transistor T7 is electrically connected with the second clock signal end. The first electrode of the eighth transistor T8 is electrically connected with the first power supply voltage V1, the second electrode of the eighth transistor T8 is electrically connected with the fourth node N4, and the control electrode of the eighth transistor T8 is electrically connected with the first node N1. The first electrode of the ninth transistor T9 is electrically connected with the first power supply voltage V1, the second electrode of the ninth transistor T9 is electrically connected with the output end OUT, and the control electrode of the ninth transistor T9 is electrically connected with the fourth node N4. The first electrode of the tenth transistor T10 is electrically connected with the second power supply voltage V2, the second electrode is electrically connected with the output end OUT, and the control electrode is electrically connected with the seventh node N7. The first electrode of the eleventh transistor T11 is electrically connected with the second node N2, the second electrode of the eleventh transistor T11 is electrically connected with the sixth node N6, and the control electrode of the eleventh transistor T11 is electrically connected with the second power supply voltage V2. The first electrode of the twelfth transistor T12 is electrically connected with the first node N1, the second electrode of the twelfth transistor T12 is electrically connected with the seventh node N7, and the control electrode of the twelfth transistor T12 is electrically connected with the second power supply voltage V2. The first electrode of the thirteenth transistor T13 is electrically connected with the first power supply voltage V1, the second electrode of the thirteenth transistor T13 is electrically connected with the first node N1, and the control electrode of the thirteenth transistor T13 is electrically connected with the reset signal end. The first electrode of the fourteenth transistor T14 is electrically connected with the input signal end, the second electrode is electrically connected with the eighth node N8, and the control electrode is electrically connected with the first clock signal end.The first electrode of the fifteenth transistor T15 is electrically connected with the eighth node N8, the second electrode of the fifteenth transistor T15 is electrically connected with the ninth node N9, and the control electrode of the fifteenth transistor T15 is electrically connected with the second power supply voltage V2. The first electrode, the control electrode of the sixteenth transistor T16, and the ninth node N9 are electrically connected with each other, and the second electrode is electrically connected with the seventh node N7. The first electrode of the seventeenth transistor T17 is electrically connected with the eighth node N8, the second electrode is electrically connected with the tenth node N10, and the control electrode is electrically connected with the first clock signal terminal. The width-length ratio of the channel region of the seventeenth transistor T17 is smaller than the width-length ratio of the channel region of the fourteenth transistor T14 and the fifteenth transistor T15. One end of the first capacitor C1 is electrically connected with the sixth node N6, and the other end of the first capacitor C1 is electrically connected with the third node N3. One end of the second capacitor C2 is electrically connected with the first power supply voltage V1, and the other end of the second capacitor C2 is electrically connected with the fourth node N4. One end of the third capacitor C3 is electrically connected with the fifth node N5, and the other end of the third capacitor C3 is electrically connected with the ninth node N9.

[0150] It should be noted that in this example, each transistor is a P-type transistor. The gating level of each signal is low, and the cutoff level is high. The first power supply voltage V1 is a high-level power supply voltage VGH, and the second power supply voltage V2 is a low-level power supply voltage.

[0151] FIG. 10 is a driving timing diagram of the shift register SR shown in FIG. 9. In FIG. 10, the clock period of the first clock signal CKA and the clock period of the second clock signal CKB are the same. The time length of the gating level of the first clock signal CKA is 1 / 4 of a clock period. The time length of the gating level of the second clock signal CKB is 1 / 4 of a clock period. The gating level of the first clock signal CKA is 1 / 2 of a clock period earlier than the gating level of the second clock signal CKB.

[0152] The working principle of the shift register SR in the example of FIG. 9 will be described below with reference to FIG. 10.

[0153] Referring to FIGS. 9 and 10, in the P1 stage, the input signal IN, the first clock signal CKA is low, and the second clock signal CKB is high, then the first transistor T1, the third transistor T3, the fourteenth transistor T14, the seventeenth transistor T17 are turned on, and the seventh transistor T7 is turned off; the input signal IN is loaded to the first node N1, the seventh node N7, the eighth node N8, the ninth node N9, the tenth node N10, so that the second transistor T2, the fourth transistor T4, the eighth transistor T8, the tenth transistor T10, the sixteenth transistor T16 are turned on, so that the fifth node N5 is pulled to low level, through the coupling effect of the third capacitor C3, the ninth node N9 is further pulled down to low level, the sixteenth transistor T16 is fully turned on, so that the low level of the ninth node N9 is loaded to the seventh node N7 after the input signal IN, so that the level of the seventh node N7 is pulled down to lower, the tenth transistor T10 is fully turned on, and the output end OUT directly outputs the low level of the second power supply voltage V2. At the same time, the first clock signal CKA is loaded to the second node N2 and the sixth node N6, so that the sixth transistor T6 is turned on, and the high level of the second clock signal CKB is loaded to the third node N3; because the first power supply voltage V1 is loaded to the fourth node N4, the ninth transistor T9 is turned off, so that the output end OUT outputs the low level of the second power supply voltage V2 once.

[0154] Referring to FIGS. 9 and 10, in the P2 stage, the input signal IN is low, the first clock signal CKA and the second clock signal CKB are high, then the first transistor T1, the third transistor T3, the seventh transistor T7, the fourteenth transistor T14, the seventeenth transistor T17 are turned off, the first clock signal CKA pulls up the second node N2 and the sixth node N6 to high level, so that the sixth transistor T6 is turned off; the levels of the remaining nodes remain the same as the previous stage, the tenth transistor T10 is fully turned on, and the output end OUT keeps outputting the low level of the second power supply voltage V2.

[0155] Referring to FIGS. 9 and 10, in the P3 stage, the input signal IN and the second clock signal CKB are low, and the first clock signal CKA is high, then the seventh transistor T7 is turned on, the first transistor T1, the third transistor T3, the fourteenth transistor T14, the seventeenth transistor T17 are still turned off, and the levels of the nodes remain unchanged, the tenth transistor T10 is fully turned on, and the output end OUT keeps outputting the low level of the second power supply voltage V2.

[0156] Referring to FIGS. 9 and 10, in the P4 stage, the input signal IN is at a low level, and the first clock signal CKA and the second clock signal CKB are at a high level. The first transistor T1, the third transistor T3, the seventh transistor T7, the fourteenth transistor T14, and the seventeenth transistor T17 are turned off, and the levels of the nodes remain unchanged. The tenth transistor T10 is fully turned on, and the output terminal OUT keeps outputting the low level of the second power supply voltage V2.

[0157] Referring to FIGS. 9 and 10, in the P5 stage, the input signal IN and the first clock signal CKA are at a low level, and the second clock signal CKB is at a high level. The first transistor T1, the third transistor T3, the fourteenth transistor T14, and the seventeenth transistor T17 are turned on, and the seventh transistor T7 is turned off. The first clock signal CKA pulls down the second node N2 and the sixth node N6 to a low level, so that the sixth transistor T6 is turned on. The levels of the remaining nodes remain unchanged. The tenth transistor T10 is fully turned on, and the output terminal OUT keeps outputting the low level of the second power supply voltage V2.

[0158] Referring to FIGS. 9 and 10, the P6 stage is the same as the P2 stage, the P7 stage is the same as the P3 stage, and the P8 stage is the same as the P4 stage. The tenth transistor T10 is fully turned on, and the output terminal OUT keeps outputting the low level of the second power supply voltage V2.

[0159] Referring to FIGS. 9 and 10, in the P9 stage, the first clock signal CKA is at a low level, and the input signal IN and the second clock signal CKB are at a high level. The first node N1, the fifth node N5, the seventh node N7, the eighth node N8, the ninth node N9, and the tenth node N10 are pulled up to a high level. The second transistor T2, the fourth transistor T4, the eighth transistor T8, the tenth transistor T10, and the sixteenth transistor T16 are turned off. The first transistor T1, the third transistor T3, the fourteenth transistor T14, and the seventeenth transistor T17 are turned on. At the same time, the second power supply voltage V2 pulls down the second node N2 and the sixth node N6 to a low level, so that the sixth transistor T6 is turned on. Since the second clock signal CKB is still at a high level, the third node N3 remains at a high level, and the fourth node N4 also remains at a high level, so that the ninth transistor T9 is turned off. The output terminal OUT keeps outputting the low level of the previous stage.

[0160] Referring to FIGS. 9 and 10, in the P10 stage, the input signal IN, the first clock signal CKA, and the second clock signal CKB are at a high level. The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the eighth transistor T8, the tenth transistor T10, the fourteenth transistor T14, the sixteenth transistor T16, and the seventeenth transistor T17 are turned off. The levels of the nodes remain unchanged. The sixth transistor T6 is turned on, and the output terminal OUT keeps outputting the low level of the previous stage.

[0161] Referring to FIGS. 9 and 10, in the P11 stage, the second clock signal CKB is at a low level, the input signal IN and the first clock signal CKA are at a high level, the sixth transistor T6 and the seventh transistor T7 are turned on, and the second clock signal CKB pulls down the third node N3 and the fourth node N4 to a low level, so that the ninth transistor T9 is turned on; since the levels of the remaining nodes remain unchanged, the tenth transistor T10 remains cut off, and the output terminal OUT outputs a high level of the first power supply voltage V1.

[0162] In this way, by adding the seventeenth transistor T17, the tenth transistor T10 can be completely turned on by being pulled down to a low level in the P1 stage, so that the output terminal OUT outputs a scan signal without a step, which is beneficial to improve the uniformity of the driving current in the pixel driving circuit PDC and reduce the possibility of horizontal lines appearing on the display panel PNL, thereby facilitating the improvement of the display quality of the display panel PNL.

[0163] In a second example, referring to FIG. 11, the difference between this example and the first example is that the shift register SR does not provide the seventeenth transistor T17, and the first electrode of the fourth transistor T4 is electrically connected to the first clock signal end; the working principle of this example is similar to that of the first example.

[0164] In a third example, referring to FIG. 12, the difference between this example and the first example is that the first electrode of the seventeenth transistor T17 is electrically connected to the first clock signal end; the working principle of this example is the same as that of the first example.

[0165] In a fourth example, referring to FIG. 13, the difference between this example and the first example is that the shift register SR does not provide the fourth transistor T4, the fifth transistor T5, and the seventeenth transistor T17, and the fifth node N5 is electrically connected to the first clock signal end; the working principle of this example is similar to that of the first example.

[0166] In a fifth example, referring to FIG. 14, the difference between this example and the first example is that the shift register SR does not provide the fourth transistor T4 and the fifth transistor T5, the first electrode of the seventeenth transistor T17 is electrically connected to the first clock signal end, the second electrode of the seventeenth transistor T17 is electrically connected to the fifth node N5, and the control electrode of the seventeenth transistor T17 is electrically connected to the second power supply voltage end; the working principle of this example is similar to that of the first example.

[0167] FIG. 15 is a simulation diagram of scan signals of two rows of sub-pixels after the implementation of the present disclosure. Referring to FIG. 15, after the implementation of the shift register of the present disclosure, the gate driving circuit outputs the scan signals without steps, which is beneficial to improve the uniformity of the driving current in the pixel driving circuit, reduces the possibility of horizontal lines of the display panel, and facilitates to improve the display quality of the display panel.

[0168] Other embodiments of the present disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. It is intended that the specification and examples be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the following claims.

Claims

1. A shift register, wherein, The shift register comprises a first input circuit, a first output circuit, a first control circuit, a second control circuit; The first input circuit is electrically connected with an input signal terminal, a seventh node, a ninth node and a first clock signal terminal, and is configured to load an input signal to the seventh node and the ninth node in response to a gating level of the first clock signal; The first output circuit is electrically connected with an output terminal and the seventh node, and is configured to load a second power voltage to the output terminal in response to a gating level on the seventh node; The first control circuit is electrically connected with the seventh node and the ninth node, and is configured to load a level on the ninth node to the seventh node in response to a gating level on the ninth node; The second control circuit is electrically connected with the ninth node and the first clock signal terminal, and is configured to change a voltage of the ninth node through a coupling effect in response to a voltage change of the first clock signal.

2. The shift register of claim 1, wherein, The second control circuit comprises a coupling sub-circuit and a control sub-circuit; The coupling sub-circuit is electrically connected with a fifth node and the ninth node, and is configured to couple a level on the fifth node to the ninth node; The control sub-circuit is configured to control a level of the fifth node according to the first clock signal; A response speed of the control sub-circuit is less than a response speed of the first input circuit.

3. The shift register of claim 2, wherein, The control sub-circuit is electrically connected with the fifth node, the ninth node and the first clock signal terminal, and is configured to load a level of the ninth node to the fifth node in response to a gating level of the first clock signal.

4. The shift register of claim 3, wherein, The coupling sub-circuit comprises a third capacitor, which is electrically connected with the fifth node and the ninth node, and is configured to couple a level on the fifth node to the ninth node; The control sub-circuit comprises a seventeenth transistor, which is electrically connected with the fifth node, the ninth node and the first clock signal terminal, and is configured to load the first clock signal to the fifth node in response to a gating level of the first clock signal.

5. The shift register of claim 2, wherein, The control sub-circuit is electrically connected with the fifth node and the first clock signal terminal, and is configured to load the first clock signal to the fifth node in response to a gating level of the first clock signal; Alternatively, the control sub-circuit is electrically connected with the fifth node, the first clock signal terminal and a second power voltage terminal, and is configured to load the first clock signal to the fifth node in response to the second power voltage.

6. The shift register of claim 5, wherein, The coupling sub-circuit comprises a third capacitor, which is electrically connected with the fifth node and the ninth node, and is configured to couple a level on the fifth node to the ninth node; The control sub-circuit comprises a seventeenth transistor, which is electrically connected with the fifth node and the first clock signal terminal, and is configured to load the first clock signal to the fifth node in response to a gating level of the first clock signal; Alternatively, the control sub-circuit comprises a seventeenth transistor, which is electrically connected with the fifth node, the first clock signal terminal and the second power voltage terminal, and is configured to load the first clock signal to the fifth node in response to the second power voltage.

7. The shift register of claim 1, wherein, The second control circuit comprises a coupling sub-circuit; the coupling sub-circuit is electrically connected with the fifth node and the ninth node, and is configured to couple the level on the fifth node to the ninth node; and the fifth node is configured to be electrically connected with the first clock signal terminal.

8. The shift register of claim 7, wherein, The coupling sub-circuit comprises a third capacitor; the third capacitor is electrically connected with the fifth node and the ninth node, and is configured to couple the level on the fifth node to the ninth node; and the fifth node is configured to be electrically connected with the first clock signal terminal.

9. The shift register of any of claims 2-8, wherein, The second control circuit further comprises a fifth transistor; the fifth transistor is electrically connected with the first power supply voltage terminal, the fourth node and the fifth node, and is configured to load the first power supply voltage to the fifth node in response to the gating level on the fourth node.

10. The shift register of any of claims 2-8, wherein, The second control circuit further comprises a fourth transistor; When the second control circuit does not comprise the control sub-circuit, the fourth transistor is electrically connected with the fifth node, the ninth node and the first clock signal terminal, and is configured to load the first clock signal to the fifth node in response to the gating level on the ninth node; When the second control circuit comprises the control sub-circuit, the fourth transistor is electrically connected with the fifth node, the ninth node and the tenth node, and is configured to load the level of the tenth node to the fifth node in response to the gating level on the ninth node.

11. The shift register of claim 1, wherein, The shift register further comprises a second input circuit, a node control circuit, a reset circuit, an isolation circuit and a second output circuit; The second input circuit is electrically connected with the second power supply voltage terminal, the second node and the first clock signal terminal, and is configured to load the second power supply voltage to the second node in response to the gating level of the first clock signal; The node control circuit is electrically connected with the first node, the second node, the fourth node, the first power supply voltage terminal and the first clock signal terminal, and is configured to load the first clock signal to the second node in response to the gating level on the first node, and to load the first power supply voltage to the fourth node in response to the gating level on the first node; The reset circuit is electrically connected with the first power supply voltage terminal, the reset signal terminal and the first node, and is configured to load the first power supply voltage to the first node in response to the gating level of the reset signal; The isolation circuit is electrically connected with the first node, the second node, the third node, the fourth node, the sixth node, the seventh node, the eighth node, the ninth node, the second clock signal terminal and the second power supply voltage terminal, and is configured to load the level of the second node to the sixth node in response to the second power supply voltage, to load the level of the first node to the seventh node in response to the second power supply voltage, to load the level of the eighth node to the ninth node in response to the second power supply voltage, and to load the level of the third node to the fourth node in response to the second clock signal. The second output circuit is electrically connected with the third node, the fourth node, the sixth node, the second clock signal terminal, the first power voltage terminal and the output terminal, and is configured to load the second clock signal to the third node in response to a gate-on level of the sixth node, and load the first power voltage to the output terminal in response to a gate-on level of the fourth node; The clock period of the first clock signal is the same as that of the second clock signal; the gate-on level of the first clock signal is not longer than 1 / 4 of a clock period, and the gate-on level of the second clock signal is not longer than 1 / 4 of a clock period; the gate-on level of the first clock signal is 1 / 2 of a clock period earlier than the gate-on level of the second clock signal.

12. The shift register of claim 11, wherein, The first input circuit comprises a first transistor and a fourteenth transistor; The first transistor is electrically connected with the input signal terminal, the first node and the first clock signal terminal, and is configured to load the input signal to the first node in response to a gate-on level of the first clock signal; The fourteenth transistor is electrically connected with the input signal terminal, the eighth node and the first clock signal terminal, and is configured to load the input signal to the eighth node in response to a gate-on level of the first clock signal; The first control circuit comprises a sixteenth transistor; The sixteenth transistor is electrically connected with the seventh node and the ninth node, and is configured to load the level of the ninth node to the seventh node in response to a gate-on level of the ninth node; The first output circuit comprises a tenth transistor; The tenth transistor is electrically connected with the seventh node, the second power voltage terminal and the output terminal, and is configured to load the second power voltage to the output terminal in response to a gate-on level of the seventh node; The second input circuit comprises a third transistor; the third transistor is electrically connected with the second power voltage terminal, the second node and the first clock signal terminal, and is configured to load the second power voltage to the second node in response to a gate-on level of the first clock signal; The node control circuit comprises a second transistor and an eighth transistor; the second transistor is electrically connected with the first node, the second node and the first clock signal terminal, and is configured to load the first clock signal to the second node in response to a gate-on level of the first node; The eighth transistor is electrically connected with the first node, the fourth node and the first power voltage terminal, and is configured to load the first power voltage to the fourth node in response to a gate-on level of the first node; The reset circuit comprises a thirteenth transistor; the thirteenth transistor is electrically connected with the first power voltage terminal, the reset signal terminal and the first node, and is configured to load the first power voltage to the first node in response to a gate-on level of the reset signal; The isolation circuit comprises a seventh transistor, an eleventh transistor, a twelfth transistor and a fifteenth transistor; the seventh transistor is electrically connected with the third node, the fourth node and the second clock signal terminal, and is configured to load the level of the third node to the fourth node in response to the second clock signal; The eleventh transistor is electrically connected with the second node, the sixth node and the second power voltage terminal, and is configured to load the level of the second node to the sixth node in response to the second power voltage. The twelfth transistor is electrically connected with the first node, the seventh node and the second power supply voltage terminal, and is used for loading the level of the first node to the seventh node in response to the second power supply voltage; The fifteenth transistor is electrically connected with the eighth node, the ninth node and the second power supply voltage terminal, and is used for loading the level of the eighth node to the ninth node in response to the second power supply voltage; The second output circuit comprises a sixth transistor, a ninth transistor, a first capacitor and a second capacitor; wherein the sixth transistor is electrically connected with the third node, the sixth node and the second clock signal terminal, and is used for loading the second clock signal to the third node in response to the gating level of the sixth node; The ninth transistor is electrically connected with the fourth node, the first power supply voltage terminal and the output terminal, and is used for loading the first power supply voltage to the output terminal in response to the gating level of the fourth node; The first capacitor is electrically connected with the third node and the sixth node, and is used for coupling the level of the sixth node to the third node; The second capacitor is electrically connected with the first power supply voltage terminal and the fourth node, and is used for coupling the first power supply voltage to the fourth node.

13. A gate driving circuit comprising the shift register according to any one of claims 1-12, wherein the stage output terminal of an upper stage shift register is electrically connected with the input signal terminal of a lower stage shift register.

Images