Full-color microled and manufacturing method therefor

Abstract

The present disclosure relates to the technical field of display chips. Disclosed are a full-color MicroLED and a manufacturing method therefor. The full-color MicroLED comprises a driving substrate, a first light-emitting layer, a first connecting layer, a second light-emitting layer, and a second connecting layer; the driving substrate comprises a first P-type semiconductor electrode transition layer; the first light-emitting layer comprises first light-emitting units and a second P-type semiconductor electrode transition layer; the first connecting layer comprises a first N-type semiconductor electrode transition layer, first N-electrode grids, and a third P-type semiconductor electrode transition layer; the second light-emitting layer comprises second light-emitting units and a fourth P-type semiconductor electrode transition layer; the second connecting layer comprises a second N-type semiconductor electrode transition layer and second N-electrode grids; a color conversion layer is provided at the position of the second connecting layer corresponding to some of the second light-emitting units. In the present disclosure, the driving substrate drives the light-emitting units on the first light-emitting layer and the second light-emitting layer to respectively emit green light and blue light, and then part of the blue light of the second light-emitting units is converted into red light by means of the color conversion layer, thereby achieving full-color light emission.

Description

Full-color Micro LED and preparation method thereof

[0001] Cross-reference to Related Applications

[0002] The present disclosure claims priority to the Chinese patent application No. 202410706455.9, entitled "Full-color Micro LED and preparation method thereof", filed on June 03, 2024 with the China Patent Office; the entire content of which is incorporated herein by reference. TECHNICAL FIELD

[0003] The present disclosure belongs to the technical field of display chips, and particularly relates to a full-color Micro LED and a preparation method thereof. BACKGROUND

[0004] The full name of Micro LED in English is Micro Light Emitting Diode, which is also called micro light emitting diode in Chinese, and can also be written as μLED. It generally refers to a technology that uses LED light emitting units with a size of 1-60 um to form a display array. The size is equivalent to 1 / 10 of a human hair. It has the characteristics of no need for backlight, high photoelectric conversion efficiency, and response time in the order of ns. It is a technology that makes LED thin, micro and arrayed, so that the volume reaches only 1% of the size of mainstream LED, and the pixel distance reaches from millimeter to micrometer. Micro LED, as a new display technology, has the advantages of high resolution, low power consumption, high brightness and fast response time, and therefore has important application value in high-resolution display, wearable devices, augmented reality and high-speed visible light communication fields. Especially full-color display Micro LED can realize red, green and blue light emission, so it has greater advantages in the field of full-color display which requires higher pixel size and pixel pitch.

[0005] At present, Micro LED needs to realize full-colorization, but there is no reliable full-colorization technology. Mass transfer technology and quantum dot color conversion technology can be called the current fast-developing full-colorization technology. However, mass transfer technology and quantum dot color conversion technology both have their own defects: 1. Mass transfer technology is to separate the light emitting units. The single light emitting unit of Micro LED is only 2-20 um. There are hundreds of thousands to millions of light emitting units on a chip, and there are billions to tens of billions of light emitting units on a wafer. If all the light emitting units are cut off, it will take a long time, and the minimum cutting path can only be 25-35 um. The light emitting units are easily damaged during cutting, which reduces the yield; 2. Quantum dot color conversion technology adds quantum dots to the light emitting pixels, but the light emitting efficiency of the color conversion technology is low.

[0006] DISCLOSURE

[0007] To solve the problems mentioned in the background art, the purpose of the present disclosure is to provide a full-color MicroLED and a preparation method thereof. The light emitting units on the first light emitting layer and the second light emitting layer are connected to the upper electrode of the driving substrate through the N-type semiconductor electrode transition layer, and the light emitting units on the first light emitting layer and the second light emitting layer emit green light and blue light respectively through the driving substrate. The color conversion layer is arranged at the corresponding part of the second light emitting unit in the second connecting layer, and part of the blue light is converted into red light through the color conversion layer, so as to realize full-color light emission.

[0008] The purpose of the present disclosure can be achieved by the following technical solutions:

[0009] A full-color MicroLED includes a driving substrate, a first insulating isolation layer is deposited on the driving substrate, and a first P-type semiconductor electrode transition layer is arranged at the corresponding electrode of the driving substrate.

[0010] A first light emitting layer includes a second insulating isolation layer, a plurality of first light emitting units are arranged in an array on the second insulating isolation layer, a second P-type semiconductor electrode transition layer is arranged at the corresponding first P-type semiconductor electrode transition layer of the second insulating isolation layer, the second P-type semiconductor electrode transition layer includes a short P-type semiconductor electrode transition layer and a long P-type semiconductor electrode transition layer, the first light emitting units are connected to the first P-type semiconductor electrode transition layer through the short P-type semiconductor electrode transition layer at the bottom, and the long P-type semiconductor electrode transition layer penetrates the second insulating isolation layer.

[0011] A first connecting layer includes a first N-type semiconductor electrode transition layer, the first N-type semiconductor electrode transition layer is connected to the first light emitting layer at the bottom, a first N-electrode grid is arranged on the surface of the first N-type semiconductor electrode transition layer, a third insulating isolation layer is deposited above the first N-type semiconductor electrode transition layer, and a third P-type semiconductor electrode transition layer is arranged at the corresponding long P-type semiconductor electrode transition layer of the third insulating isolation layer.

[0012] A second light emitting layer includes a fourth insulating isolation layer, a plurality of second light emitting units are arranged in an array on the fourth insulating isolation layer, a fourth P-type semiconductor electrode transition layer is arranged at the corresponding third P-type semiconductor electrode transition layer of the fourth insulating isolation layer, and the second light emitting units are connected to the third P-type semiconductor electrode transition layer through the fourth P-type semiconductor electrode transition layer at the bottom.

[0013] A second connecting layer includes a second N-type semiconductor electrode transition layer, the second N-type semiconductor electrode transition layer is connected to the second light emitting layer at the bottom, a second N-electrode grid is arranged on the surface of the second N-type semiconductor electrode transition layer, a fifth insulating isolation layer is deposited above the second N-type semiconductor electrode transition layer, the fifth insulating isolation layer is windowed at the corresponding part of the second light emitting unit, and a color conversion layer is formed by filling a color conversion material in the window of the fifth insulating isolation layer.

[0014] Optionally, the driving substrate is a silicon-based CMOS backplane.

[0015] Optionally, the first, second, third, fourth and fifth insulating isolation layers are SiO2, Al2O3 or Si3N4 materials.

[0016] Optionally, the first light emitting unit comprises a first epitaxial layer, the bottom of the first epitaxial layer is provided with a first P electrode layer, the sidewall of the first epitaxial layer is sequentially provided with a first passivation layer and a first light reflection layer, and the second light emitting unit has the same structure as the first light emitting unit.

[0017] Optionally, the epitaxial layer of the first light emitting unit is a semiconductor material for exciting green light, and the epitaxial layer of the second light emitting unit is a semiconductor material for exciting blue light.

[0018] Optionally, the projection of the first light emitting unit, the second light emitting unit and the color conversion layer on the top surface can be a triangle, a circle or a polygon.

[0019] Optionally, the first P electrode layer is an ITO thin film.

[0020] Optionally, the first passivation layer is SiO2, Al2O3 or Si3N4 material.

[0021] Optionally, the first light reflection layer is a Ti / Ni / Gr / TiN structure; the second light reflection layer is an Ag / Al / Au structure; and the third light reflection layer is a Ti / Ni / Gr / TiN / ITO / SiO2 structure.

[0022] Optionally, the first, second, third and fourth P-type semiconductor electrode transition layers are metal materials, and the metal materials are Cu, Al, Sn, Au, Pt, Ti or Cr.

[0023] Optionally, the first and second N-type semiconductor electrode transition layers are ITO thin films.

[0024] Optionally, the first and second N electrode grids are Cr / Pt / Au or Cr / Al / Au / Cu / Ti materials.

[0025] Optionally, the color conversion material is a quantum dot material, the quantum dot material is a red quantum dot material, and the sidewall of the color conversion layer is provided with a third light reflection layer.

[0026] Optionally, the surface of the second connecting layer is further provided with an encapsulation layer, the surface of the encapsulation layer is provided with a lens structure, the lens structure corresponds to a single pixel or a single RGB unit, and the single RGB unit comprises at least one R, G and B pixel.

[0027] Optionally, a distributed Bragg reflector or a filter is arranged between the surface of the encapsulation layer and the lens structure.

[0028] A preparation method of a full-color MicroLED includes the following steps:

[0029] S1, a SiO2 layer is deposited on the surface of a driving substrate to form a first insulating isolation layer, then a window is opened on the first insulating isolation layer corresponding to an electrode by means of photolithography-etching, and after the first insulating isolation layer is electroplated with metal, chemical mechanical polishing is performed for planarization to form a first P-type semiconductor electrode transition layer;

[0030] S2, a first epitaxial wafer is processed, a first light-emitting unit is formed at a corresponding position according to a chip design, then a SiO2 layer is deposited above the light-emitting unit to form a second insulating isolation layer, a window is opened on the second insulating isolation layer corresponding to the first P-type semiconductor electrode transition layer by means of photolithography-etching, and after the second insulating isolation layer is electroplated with metal, chemical mechanical polishing is performed for planarization to form a second P-type semiconductor electrode transition layer;

[0031] S3, the first epitaxial wafer of step S2 and the chip of step S1 are surface-activated and pre-aligned, then the first epitaxial wafer and the chip are bonded by means of hybrid bonding, and finally the substrate of the first epitaxial wafer is removed;

[0032] S4, an ITO film is sputtered on the surface of the first epitaxial wafer to form a first N-type semiconductor electrode transition layer, a first N-electrode grid is plated on the surface of the first N-type semiconductor electrode transition layer by means of photolithography-lift off process, then a SiO2 layer is deposited above the first N-type semiconductor electrode transition layer to form a third insulating isolation layer, a window is opened on the third insulating layer corresponding to a long P-type semiconductor electrode transition layer by means of photolithography-etching, and finally the third insulating isolation layer is electroplated with metal after chemical mechanical polishing for planarization to form a third P-type semiconductor electrode transition layer, thereby completing the preparation of a first connecting layer;

[0033] S5, a second epitaxial wafer is processed by the method in step S2 to complete the preparation of a second light-emitting unit of a second light-emitting layer, a fourth insulating isolation layer and a fourth P-type semiconductor electrode transition layer;

[0034] S6, the second epitaxial wafer of step S5 and the chip of step S4 are surface-activated and pre-aligned, then the second epitaxial wafer and the chip are bonded by means of hybrid bonding, and finally the substrate of the second epitaxial wafer is removed;

[0035] S7, sputtering ITO film on the surface of the second epitaxial wafer to form a second N-type semiconductor electrode transition layer, then plating a second N electrode grid on the surface of the second N-type semiconductor electrode transition layer by means of photolithography-lift off process, and finally depositing a layer of SiO2 above the second N-type semiconductor electrode transition layer to form a fifth insulating isolation layer, thereby completing the preparation of the second connecting layer;

[0036] S8, according to the chip design, opening a window in the fifth insulating isolation layer corresponding to the second light emitting unit by means of photolithography-etching, plating a composite metal layer on the surface of the fifth insulating isolation layer, then removing the composite metal layer at the excess position by means of photolithography-etching, only retaining the position of the inner wall of the window of the fifth insulating isolation layer, forming a third light reflecting layer, and finally filling quantum dot material by means of photolithography to form a color conversion layer.

[0037] Optionally, the step S2 of tooling the first epitaxial wafer comprises the following steps:

[0038] S201, sputtering ITO film on the surface of the first epitaxial layer of the first epitaxial wafer, and then etching the ITO film by means of photolithography-etching to form a first P electrode layer;

[0039] S202, continuing to etch the first epitaxial layer by means of photolithography-etching to form a first light emitting unit;

[0040] S203, depositing a layer of SiO2 on the surface of the first epitaxial wafer to form a first passivation layer, and then plating a composite metal layer on the surface of the first passivation layer to form a first light reflecting layer, and removing the first passivation layer and the first light reflecting layer at the top of the first light reflecting unit by means of photolithography-etching to expose the first P electrode layer at the top of the first light emitting unit;

[0041] S204, depositing a layer of SiO2 above the light emitting unit to form a second insulating isolation layer, and then opening a window in the second insulating isolation layer corresponding to the first P-type semiconductor electrode transition layer by means of photolithography-etching;

[0042] S205, after electroplating metal on the surface of the second insulating isolation layer, chemical mechanical polishing is performed to planarize, thereby forming a second P-type semiconductor electrode transition layer, and completing the processing of the first epitaxial wafer.

[0043] Optionally, the overall processing step of the second epitaxial wafer in step S5 is the same as that of the first epitaxial wafer, except that the fourth insulating isolation layer is opened at the position corresponding to the third P-type semiconductor electrode transition layer in step S204.

[0044] Optionally, the line width of the first P-type semiconductor electrode transition layer, the second P-type semiconductor electrode transition layer and the third P-type semiconductor electrode transition layer is 1-2 um.

[0045] Optionally, the bonding accuracy of the first epitaxial wafer and the second epitaxial wafer in steps S3 and S5 is less than or equal to 0.5 um.

[0046] Advantages of the present disclosure:

[0047] The light emitting units on the first light emitting layer and the second light emitting layer of the present disclosure are respectively connected to the electrode on the driving substrate through the N-type semiconductor electrode transition layer, and the light emitting units on the first light emitting layer and the second light emitting layer are respectively driven by the driving substrate to emit green light and blue light. The second connection layer is provided with a color conversion layer at the corresponding part of the second light emitting unit, and part of the blue light is converted into red light through the color conversion layer to realize full-color light emission. The present disclosure breaks the conventional MicroLED pixel arrangement mode, adopts hybrid bonding technology, SiO2 plays a supporting role, the P-type semiconductor electrode transition layer is conductive, one driving substrate bonds two epitaxial wafers, realizes simultaneous driving of G / B epitaxial structure, and simultaneously superimposes quantum dot color conversion, so that color MicroLED is more easily realized, and the pixel arrangement makes the RGB color ratio have more operability and selectivity. BRIEF DESCRIPTION OF DRAWINGS

[0048] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, for those skilled in the art, other drawings can also be obtained without creative labor on the basis of these drawings.

[0049] FIG. 1 is a structural schematic diagram of a full-color MicroLED of the present disclosure;

[0050] FIG. 2 is a pixel arrangement schematic diagram of a full-color MicroLED of the present disclosure;

[0051] FIG. 3 is a structural schematic diagram of another embodiment of a full-color MicroLED of the present disclosure;

[0052] FIG. 4 is a process flow schematic diagram of step S1 of the present disclosure;

[0053] FIG. 5 is a process flow schematic diagram of step S2 of the present disclosure;

[0054] FIG. 6 is a process flow schematic diagram of step S3 of the present disclosure;

[0055] FIG. 7 is a process flow schematic diagram of step S4 of the present disclosure;

[0056] FIG. 8 is a process flow schematic diagram of step S5 of the present disclosure;

[0057] FIG. 9 is a process flow schematic diagram of step S6 of the present disclosure;

[0058] FIG. 10 is a process flow schematic diagram of step S7 of the present disclosure;

[0059] Fig. 11 is a process flow diagram of step S8 of the present disclosure.

[0060] In the figure: 100 - driving substrate, 101 - first insulating isolation layer, 102 - first P-type semiconductor electrode transition layer, 200 - first light-emitting layer, 201 - first substrate, 202 - first epitaxial layer, 203 - first P electrode layer, 204 - first passivation layer, 205 - first light-reflecting layer, 206 - second insulating isolation layer, 207 - second P-type semiconductor electrode transition layer, 2071 - short P-type semiconductor electrode transition layer, 2072 - long P-type semiconductor electrode transition layer, 300 - first connecting layer, 301 - first N-type semiconductor electrode transition layer, 302 - first N electrode grid, 303 - third insulating isolation layer, 304 - third P-type semiconductor electrode transition layer, 400 - second light-emitting layer, 401 - second substrate, 402 - second epitaxial layer, 403 - second P electrode layer, 404 - second passivation layer, 405 - second light-reflecting layer, 406 - fourth insulating isolation layer, 407 - fourth P-type semiconductor electrode transition layer, 500 - second connecting layer, 501 - second N-type semiconductor electrode transition layer, 502 - second N electrode grid, 503 - fifth insulating isolation layer, 600 - color conversion layer, 601 - third light-reflecting layer, 700 - packaging layer, 701 - lens structure. DETAILED DESCRIPTION

[0061] The technical solutions in the embodiments of the present disclosure will be described clearly and completely below in combination with the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative labor are within the scope of protection of the present disclosure.

[0062] As shown in Fig. 1, the present disclosure provides a full-color MicroLED, which comprises a driving substrate 100, a first insulating isolation layer 101 is deposited on the driving substrate 100, and a first P-type semiconductor electrode transition layer 102 is arranged at the first insulating isolation layer 101 corresponding to the driving substrate electrode.

[0063] The first light-emitting layer 200 comprises a second insulating isolation layer 206, and a plurality of first light-emitting units are arranged on the second insulating isolation layer 206 in an array, wherein the first light-emitting unit comprises a first epitaxial layer 202, the bottom of the first epitaxial layer 202 is provided with a first P electrode layer 203, the sidewall of the first epitaxial layer 202 is sequentially provided with a first passivation layer 204 and a first light reflection layer 205, the second insulating isolation layer 206 is provided with a second P-type semiconductor electrode transition layer 207 at a position corresponding to the first P-type semiconductor electrode transition layer 102, the second P-type semiconductor electrode transition layer 207 comprises a short P-type semiconductor electrode transition layer 2071 and a long P-type semiconductor electrode transition layer 2072, the bottom of the first light-emitting unit is connected with the first P-type semiconductor electrode transition layer 102 through the short P-type semiconductor electrode transition layer 2071, and the long P-type semiconductor electrode transition layer 2072 penetrates through the second insulating isolation layer 206.

[0064] The first connecting layer 300 comprises a first N-type semiconductor electrode transition layer 301, the bottom of the first N-type semiconductor electrode transition layer 301 is bonded with the first light-emitting layer 200, the surface of the first N-type semiconductor electrode transition layer 301 is provided with a first N electrode grid 302, a third insulating isolation layer 303 is deposited above the first N-type semiconductor electrode transition layer 301, and a third P-type semiconductor electrode transition layer 304 is provided through the third insulating isolation layer 303 at a position corresponding to the long P-type semiconductor electrode transition layer 2072.

[0065] The second light-emitting layer 400 comprises a fourth insulating isolation layer 406, and a plurality of second light-emitting units are arranged on the fourth insulating isolation layer 406 in an array, wherein the second light-emitting unit comprises a second epitaxial layer 402, the bottom of the second epitaxial layer 402 is provided with a second P electrode layer 403, the sidewall of the second epitaxial layer 402 is sequentially provided with a second passivation layer 404 and a second light reflection layer 405, the fourth insulating isolation layer 406 is provided with a fourth P-type semiconductor electrode transition layer 407 at a position corresponding to the third P-type semiconductor electrode transition layer 303, and the bottom of the second light-emitting unit is connected with the third P-type semiconductor electrode transition layer 304 through the fourth P-type semiconductor electrode transition layer 407.

[0066] The second connecting layer 500 comprises a second N-type semiconductor electrode transition layer 501, the bottom of the second N-type semiconductor electrode transition layer 501 is bonded with the second light-emitting layer 400, the surface of the second N-type semiconductor electrode transition layer 501 is provided with a second N electrode grid 502, a fifth insulating isolation layer 503 is deposited above the second N-type semiconductor electrode transition layer 501, the fifth insulating isolation layer 503 is windowed at a position corresponding to part of the second light-emitting unit, a color conversion layer 600 is formed by filling a color conversion material in the window of the fifth insulating isolation layer 503, and the color conversion layer 600 is provided with a third light reflection layer 601 on the sidewall.

[0067] The driving substrate 100 is a silicon-based CMOS backplane, the first epitaxial layer 202 is a semiconductor material for exciting green light, the second light-emitting unit 402 epitaxial layer is a semiconductor material for exciting blue light, and the color conversion material is a quantum dot material, preferably a red quantum dot material, which can convert the blue light emitted by the second light-emitting unit into red light.

[0068] The three color pixel arrangement modes and the shapes of the light-emitting areas can be selected according to different distribution modes and shapes as required. The projection area ratio of the first light-emitting unit, the second light-emitting unit, and the color conversion layer on the top surface is 3:5-6:2-1. The projection of the first light-emitting unit, the second light-emitting unit, and the color conversion layer on the top surface can be a triangle, a circle, or a polygon. FIG. 2 shows five possible pixel arrangement modes and shapes. The sizes of the light-emitting units are not necessarily the same and can be adjusted according to the brightness requirements. Those skilled in the art should understand that the present disclosure is not limited to the pixel arrangement modes shown in FIG. 2.

[0069] The first insulating isolation layer 101, the second insulating isolation layer 206, the third insulating isolation layer 303, the fourth insulating isolation layer 406, the fifth insulating isolation layer 503, the first passivation layer 204, and the second passivation layer 404 are transparent, non-conductive, and have a certain strength, such as SiO2, Al2O3, or Si3N4 materials. The first P electrode layer 203 and the second P electrode layer 404 are ITO thin films. The first reflective layer 205, the second reflective layer 405, and the third reflective layer 601 are Ti / Ni / Gr / TiN structures, Ag / Al / Au structures, Ti / Ni / Gr / TiN / ITO / SiO2, and preferably Ti / Al / TiN, wherein the thickness of the Ti layer is 5-10 nm, the thickness of the Al layer is 140-160 nm, and the thickness of the TiN layer is 10-15 nm.

[0070] The first P-type semiconductor electrode transition layer 102, the second P-type semiconductor electrode transition layer 207, the third P-type semiconductor electrode transition layer 304, and the fourth P-type semiconductor electrode transition layer 407 are metal materials, such as Cu, Al, Sn, Au, Pt, Ti, or Cr. The first N-type semiconductor electrode transition layer 301 and the second N-type semiconductor electrode transition layer 501 are ITO thin films. The first N electrode grid 302 and the second N electrode grid 502 are materials with good stress, conductivity, and adhesion, and can use Cr / Pt / Au or Cr / Al / Au / Cu / Ti materials.

[0071] As shown in FIG. 3, as another embodiment of the present disclosure, the surface of the second connection layer 500 is further provided with an encapsulation layer 700, and the surface of the encapsulation layer 700 is provided with a lens structure 701 corresponding to a single pixel or a single RGB unit including at least one R, G and B pixel. The encapsulation layer 700 is transparent and non-conductive material, which can be SiO2, Al2O3 or Si3N4 material, and the lens structure 701 is etched from the encapsulation layer 700 and can be hemispherical in shape. A distributed Bragg reflector or a filter is further arranged between the surface of each encapsulation layer and the lens structure, which is configured to prevent red and blue light leakage.

[0072] As shown in FIGS. 4-11, the preparation method of the full-color MicroLED includes the following steps:

[0073] S1, a layer of SiO2 is deposited on the surface of the driving substrate 100 to form a first insulating isolation layer 101, and then the first insulating isolation layer 101 is windowed at the position corresponding to the electrode by means of photoetching. After the surface of the first insulating isolation layer 101 is electroplated with metal and then planarized by chemical mechanical polishing, a first P-type semiconductor electrode transition layer 102 is formed.

[0074] S2, the first epitaxial wafer is processed, which includes a first substrate 201 and a first epitaxial layer 202, and the first epitaxial wafer plus tool body includes:

[0075] S201, ITO film is sputtered on the surface of the first epitaxial layer 202 of the first epitaxial wafer, and then the ITO film is etched by means of photoetching to form a first P electrode layer 203.

[0076] S202, the first epitaxial layer 202 is etched by means of photoetching to be patterned to form a first light emitting unit.

[0077] S203, a layer of SiO2 is deposited on the surface of the first epitaxial wafer to form a first passivation layer 204, and then a composite metal layer is plated on the surface of the first passivation layer 204 to form a first light reflecting layer 205. The first passivation layer 204 and the first light reflecting layer 205 on the top of the first light reflecting unit are removed by means of photoetching to expose the first P electrode layer 203 on the top of the first light emitting unit.

[0078] S204, a layer of SiO2 is deposited on the light emitting unit to form a second insulating isolation layer 206, and then the second insulating isolation layer 206 is windowed at the position corresponding to the first P-type semiconductor electrode transition layer by means of photoetching.

[0079] S205, after the surface of the second insulating isolation layer 206 is electroplated with metal and then planarized by chemical mechanical polishing, a second P-type semiconductor electrode transition layer 207 is formed, and the processing of the first epitaxial wafer is completed.

[0080] S3, surface activation and pre-alignment of the first epitaxial wafer of step S2 and the chip of step S1 are performed, then the first epitaxial wafer and the chip are bonded by hybrid bonding, the bonding accuracy is less than or equal to 0.5 um, and finally the first substrate of the first epitaxial wafer is removed.

[0081] S4, ITO film is sputtered on the surface of the first epitaxial wafer to form a first N-type semiconductor electrode transition layer 301, then a first N electrode grid 302 is plated on the surface of the first N-type semiconductor electrode transition layer 301 by a photolithography-lift off process, then a layer of SiO2 is deposited above the first N-type semiconductor electrode transition layer 301 to form a third insulating isolation layer 303, then the third insulating layer is windowed at a position corresponding to the long P-type semiconductor electrode transition layer 2072 by a photolithography-etching method, and finally after electroplating metal on the surface of the third insulating isolation layer 303, chemical mechanical polishing is performed to planarize, forming a third P-type semiconductor electrode transition layer 304, and the preparation of the first connecting layer is completed.

[0082] S5, the second epitaxial wafer is processed by the method in step S2, the second epitaxial wafer includes a second substrate 401 and a second epitaxial layer 402, and the preparation of the second light emitting layer, the fourth insulating isolation layer 406 and the fourth P-type semiconductor electrode transition layer 407 is completed.

[0083] S6, surface activation and pre-alignment of the second epitaxial wafer of step S5 and the chip of step S4 are performed, then the second epitaxial wafer and the chip are bonded by hybrid bonding, the bonding accuracy is less than or equal to 0.5 um, and finally the second substrate 401 of the second epitaxial wafer is removed.

[0084] S7, ITO film is sputtered on the surface of the second epitaxial wafer to form a second N-type semiconductor electrode transition layer 501, then a second N electrode grid 502 is plated on the surface of the second N-type semiconductor electrode transition layer by a photolithography-lift off process, and finally a layer of SiO2 is deposited above the second N-type semiconductor electrode transition layer 501 to form a fifth insulating isolation layer 503, and the preparation of the second connecting layer is completed.

[0085] S8, according to the chip design, the fifth insulating isolation layer 503 is windowed at a position corresponding to the second light emitting unit by a photolithography-etching method, a composite metal layer is plated on the surface of the fifth insulating isolation layer 503, then the composite metal layer at the excess position is removed by a photolithography-etching method, only the inner wall position of the window of the fifth insulating isolation layer 503 is reserved, a third reflective layer 601 is formed, and finally a color conversion layer 600 is formed by filling quantum dot material through photolithography.

[0086] Among them, the line width of the first P-type semiconductor electrode transition layer, the second P-type semiconductor electrode transition layer and the third P-type semiconductor electrode transition layer is 1-2 um.

[0087] In the description of the specification, the description referring to the terms "one embodiment", "an example", "a specific example" and the like means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present disclosure. In the specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0088] The basic principles, main features and advantages of the present disclosure are shown and described above. It should be understood by those skilled in the art that the present disclosure is not limited by the above embodiments, and the above embodiments and descriptions in the specification are only illustrative of the principles of the present disclosure. Without departing from the spirit and scope of the present disclosure, various changes and improvements of the present disclosure can be made, and these changes and improvements all fall within the scope of the claimed present disclosure. Industrial applicability

[0089] In summary, the present disclosure provides a full-color MicroLED and a preparation method thereof. The light emitting units on the first light emitting layer and the second light emitting layer are respectively connected to the electrode on the driving substrate through the N-type semiconductor electrode transition layer. The light emitting units on the first light emitting layer and the second light emitting layer are respectively driven by the driving substrate to emit green light and blue light. The color conversion layer is arranged at the corresponding part of the second light emitting units in the second connecting layer. Part of the blue light is converted into red light by the color conversion layer, and full-color light emission is realized.

Claims

1. A full-color MicroLED, characterized in that, The driving substrate is provided with a first insulating isolation layer, and the first insulating isolation layer is provided with a first P-type semiconductor electrode transition layer at a position corresponding to an electrode of the driving substrate; The first light-emitting layer is provided with a second insulating isolation layer, and the second insulating isolation layer is provided with a plurality of first light-emitting units arranged in an array; the second insulating isolation layer is provided with a second P-type semiconductor electrode transition layer at a position corresponding to the first P-type semiconductor electrode transition layer; the second P-type semiconductor electrode transition layer comprises a short P-type semiconductor electrode transition layer and a long P-type semiconductor electrode transition layer; the first light-emitting unit is connected to the first P-type semiconductor electrode transition layer through the short P-type semiconductor electrode transition layer at the bottom of the first light-emitting unit; and the long P-type semiconductor electrode transition layer penetrates the second insulating isolation layer; The first connecting layer comprises a first N-type semiconductor electrode transition layer, and the first N-type semiconductor electrode transition layer is connected to the first light-emitting layer at the bottom of the first N-type semiconductor electrode transition layer; the first N-type semiconductor electrode transition layer is provided with a first N-electrode grid on the surface of the first N-type semiconductor electrode transition layer; a third insulating isolation layer is deposited above the first N-type semiconductor electrode transition layer; and the third insulating isolation layer is provided with a third P-type semiconductor electrode transition layer at a position corresponding to the long P-type semiconductor electrode transition layer. The second light-emitting layer comprises a fourth insulating isolation layer, and the fourth insulating isolation layer is provided with a plurality of second light-emitting units arranged in an array; the fourth insulating isolation layer is provided with a fourth P-type semiconductor electrode transition layer at a position corresponding to the third P-type semiconductor electrode transition layer; and the second light-emitting unit is connected to the third P-type semiconductor electrode transition layer through the fourth P-type semiconductor electrode transition layer at the bottom of the second light-emitting unit. The second connecting layer comprises a second N-type semiconductor electrode transition layer, and the second N-type semiconductor electrode transition layer is connected to the second light-emitting layer at the bottom of the second N-type semiconductor electrode transition layer; the second N-type semiconductor electrode transition layer is provided with a second N-electrode grid on the surface of the second N-type semiconductor electrode transition layer; a fifth insulating isolation layer is deposited above the second N-type semiconductor electrode transition layer; the fifth insulating isolation layer is windowed at a position corresponding to part of the second light-emitting unit; and the fifth insulating isolation layer is filled with a color conversion material to form a color conversion layer in the window.

2. The full-color MicroLED according to claim 1, wherein, The driving substrate is a silicon-based CMOS backplane.

3. The full-color MicroLED according to claim 1 or 2, characterized in that, The first insulating isolation layer, the second insulating isolation layer, the third insulating isolation layer, the fourth insulating isolation layer and the fifth insulating isolation layer are SiO2, Al2O3 or Si3N4 materials.

4. The full-color MicroLED according to any one of claims 1-3, wherein, The first light-emitting unit comprises a first epitaxial layer, and the first epitaxial layer is provided with a first P-electrode layer at the bottom of the first epitaxial layer; the sidewall of the first epitaxial layer is sequentially provided with a first passivation layer and a first light-reflecting layer; and the second light-emitting unit has the same structure as the first light-emitting unit.

5. The full-color MicroLED according to claim 4, wherein, The epitaxial layer of the first light-emitting unit is a semiconductor material for exciting green light, and the epitaxial layer of the second light-emitting unit is a semiconductor material for exciting blue light.

6. The full-color MicroLED according to claim 4 or 5, wherein, The projection of the first light-emitting unit, the second light-emitting unit and the color conversion layer on the top surface can be a triangle, a circle or a polygon.

7. The full-color MicroLED according to any one of claims 4-6, wherein, The first P-electrode layer is an ITO thin film.

8. The full-color MicroLED according to any one of claims 4-7, wherein, The first passivation layer is SiO2, Al2O3 or Si3N4 material.

9. The full-color MicroLED according to any one of claims 4-8, wherein, The first light-reflecting layer has a Ti / Ni / Gr / TiN structure; the second light-reflecting layer has an Ag / Al / Au structure; and the third light-reflecting layer has a Ti / Ni / Gr / TiN / ITO / SiO2 structure.

10. The full-color MicroLED according to any one of claims 1-9, wherein, The first P-type semiconductor electrode transition layer, the second P-type semiconductor electrode transition layer, the third P-type semiconductor electrode transition layer and the fourth P-type semiconductor electrode transition layer are metal materials, and the metal material is Cu, Al, Sn, Au, Pt, Ti or Cr.

11. The full-color MicroLED according to any one of claims 1-10, wherein, The first N-type semiconductor electrode transition layer and the second N-type semiconductor electrode transition layer are ITO films.

12. The full-color MicroLED according to any one of claims 1-11, wherein, The first N electrode grid and the second N electrode grid are Cr / Pt / Au or Cr / Al / Au / Cu / Ti materials.

13. The full-color MicroLED according to any one of claims 1-12, wherein, The color conversion material is a quantum dot material, the quantum dot material is a red quantum dot material, and the sidewall of the color conversion layer is provided with a third light reflection layer.

14. The method of any one of claims 1-13, wherein, The surface of the second connecting layer is further provided with an encapsulation layer, the surface of the encapsulation layer is provided with a lens structure, the lens structure corresponds to a single pixel or a single RGB unit, and the single RGB unit comprises at least one R, G and B pixel.

15. The method of any one of claims 1-14, wherein the method further comprises: A distributed Bragg reflector or a filter is further arranged between the surface of the encapsulation layer and the lens structure.

16. The method of any one of claims 1-15, wherein, The method comprises the following steps: S1, a layer of SiO2 is deposited on the surface of a driving substrate to form a first insulating isolation layer, then a window is opened on the first insulating isolation layer at a position corresponding to an electrode by means of photolithography-etching, the surface of the first insulating isolation layer is electroplated with a metal and then is subjected to chemical mechanical polishing planarization to form a first P-type semiconductor electrode transition layer; S2, a first epitaxial wafer is processed, a first light emitting unit is formed at a corresponding position according to a chip design, then a layer of SiO2 is deposited on the first light emitting unit to form a second insulating isolation layer, a window is opened on the second insulating isolation layer at a position corresponding to the first P-type semiconductor electrode transition layer by means of photolithography-etching, the surface of the second insulating isolation layer is electroplated with a metal and then is subjected to chemical mechanical polishing planarization to form a second P-type semiconductor electrode transition layer; S3, the first epitaxial wafer of step S2 and the chip of step S1 are subjected to surface activation and pre-alignment, then the first epitaxial wafer and the chip are bonded by means of hybrid bonding, and finally the substrate of the first epitaxial wafer is removed; S4, an ITO film is sputtered on the surface of the first epitaxial wafer to form a first N-type semiconductor electrode transition layer, a first N electrode grid is plated on the surface of the first N-type semiconductor electrode transition layer by means of photolithography-lift off process, then a layer of SiO2 is deposited on the first N-type semiconductor electrode transition layer to form a third insulating isolation layer, a window is opened on the third insulating layer at a position corresponding to the long P-type semiconductor electrode transition layer by means of photolithography-etching, and finally the surface of the third insulating isolation layer is electroplated with a metal and then is subjected to chemical mechanical polishing planarization to form a third P-type semiconductor electrode transition layer, thereby completing the preparation of the first connecting layer; S5, a second epitaxial wafer is processed by the method in step S2, thereby completing the preparation of a second light emitting unit of a second light emitting layer, a fourth insulating isolation layer and a fourth P-type semiconductor electrode transition layer; S6, the second epitaxial wafer of step S5 and the chip of step S4 are subjected to surface activation and pre-alignment, then the second epitaxial wafer and the chip are bonded by means of hybrid bonding, and finally the substrate of the second epitaxial wafer is removed; S7, sputtering ITO film on the surface of the second epitaxial wafer to form a second N-type semiconductor electrode transition layer, then plating a second N electrode grid on the surface of the second N-type semiconductor electrode transition layer by means of photolithography-lift off process, and finally depositing a layer of SiO2 above the second N-type semiconductor electrode transition layer to form a fifth insulating isolation layer, thereby completing the preparation of the second connecting layer; S8, according to the chip design, the fifth insulating isolation layer is opened at the corresponding part of the second light emitting unit by means of photolithography-etching, a composite metal layer is plated on the surface of the fifth insulating isolation layer, then the composite metal layer at the excess position is removed by means of photolithography-etching, only the position of the inner wall of the window of the fifth insulating isolation layer is reserved, a third light reflecting layer is formed, and finally the quantum dot material is filled by means of photolithography to form a color conversion layer.

17. The method of claim 16, wherein the method further comprises: The step S2 of tooling the first epitaxial wafer includes the following steps: S201, sputtering ITO film on the surface of the first epitaxial layer of the first epitaxial wafer, and then etching the ITO film by means of photolithography-etching to form a first P electrode layer; S202, continuing to etch the first epitaxial layer by means of photolithography-etching to form a first light emitting unit; S203, depositing a layer of SiO2 on the surface of the first epitaxial wafer to form a first passivation layer, and then plating a composite metal layer on the surface of the first passivation layer to form a first light reflecting layer, and removing the first passivation layer and the first light reflecting layer on the top of the first light reflecting unit by means of photolithography-etching to expose the first P electrode layer on the top of the first light emitting unit; S204, depositing a layer of SiO2 above the light emitting unit to form a second insulating isolation layer, and then opening a window in the second insulating isolation layer corresponding to the first P-type semiconductor electrode transition layer by means of photolithography-etching; S205, after electroplating metal on the surface of the second insulating isolation layer, chemical mechanical polishing is performed to planarize, thereby forming a second P-type semiconductor electrode transition layer, and completing the processing of the first epitaxial wafer.

18. The method of claim 17, wherein the method further comprises: The overall processing step of the second epitaxial wafer in the step S5 is the same as that of the first epitaxial wafer, except that the fourth insulating isolation layer is opened at the position corresponding to the third P-type semiconductor electrode transition layer in the step S204.

19. The method of any one of claims 16-18, wherein the method further comprises: The line width of the first P-type semiconductor electrode transition layer, the second P-type semiconductor electrode transition layer and the third P-type semiconductor electrode transition layer is 1-2 um.

20. The method of any one of claims 16-19, wherein the method further comprises: The bonding accuracy of the first epitaxial wafer and the second epitaxial wafer in the step S3 and the step S5 is less than or equal to 0.5 um.

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