Communication method and communication apparatus

Abstract

A communication method. The method comprises: a receiving end device generating a bit sequence on the basis of A information bits and the number of PC bits nPC, wherein the bit sequence comprises N bits, the information bits and the PC bits are located at A+nPC positions having the highest sequence reliability in the bit sequence, the PC positions where the PC bits are placed satisfy a first condition and a second condition, the first condition is that the minimum row weight of the A positions where the A information bits are located is not less than the minimum row weight of the A positions having the highest sequence reliability in the bit sequence, the second condition is that the number of a k-th highest position among the nPC positions in the bit sequence is not less than the number of a k-th highest position in a set S3, and the set S3 comprises nPC positions having the lowest reliability among the A+nPC positions having the highest sequence reliability; and performing polar encoding on the bit sequence to obtain a codeword sequence. The method provides a PC bit placement mode by considering the requirements for determining a correct decoding path on the basis of PC bits.

Description

Communication method and communication apparatus

[0001] This application claims priority to the Chinese Patent Application No. 202410710693.7, filed on June 3, 2024, entitled “Communication method and communication apparatus”, the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the field of coding, and more particularly, to a communication method and a communication apparatus. BACKGROUND

[0003] Currently, a parity check (PC) polar code (PC-Polar code) is proposed, and the PC bits in the PC-Polar code can correct the path metric (PM) of the Successive Cancellation List (SCL) decoding, so as to improve the probability that the correct decoding path is ranked first. The main principle of the PC-Polar code is that if n PC PC bits are needed, n PC positions are selected from the frozen bit positions of N positions where the to-be-encoded bits are located as PC positions, the values of the PC positions are different from the other frozen bits and are not fixed as 0, and the values of the PC positions are determined based on the PC check relationship and the values of the to-be-encoded bits before the PC positions. For example, the PC check relationship indicates that the value of the current PC position is the exclusive-OR result of the bit at the i-th position before the current PC position and the bit at the j-th position.

[0004] In the SCL decoding process, if the current decoding bit is a PC bit, the value of the current PC position needs to be calculated according to the previous decoding result and the PC check relationship. If the value is different from the hard decision result of the log-likelihood ratio (LLR) corresponding to the current PC position, a penalty needs to be added to the current decoding path, and the PM value of the current decoding path will increase, and the sorting will be later. Therefore, the addition of the PC bit can make the correct decoding path earlier, and the probability that the first decoding path output is the correct codeword is improved. However, the existing placement method of the PC bit does not consider the requirement of determining the correct decoding path based on the PC bit, and therefore the decoding performance based on the PC bit needs to be improved. SUMMARY

[0005] Embodiments of the present application provide a communication method and a communication apparatus, and a PC bit placement method based on the requirement of determining the correct decoding path based on the PC bit.

[0006] In a first aspect, a communication method is provided, which can be executed by a transmitting device. Unless otherwise specified, the term "transmitting device" in this application can refer to the transmitting device itself (e.g., a network device, a terminal device), a component in the transmitting device (e.g., a processor, a chip, or a chip system), or a logic module or software that can implement all or part of the functions of the transmitting device.

[0007] The method includes: obtaining A information bits and the number n of parity check (PC) bits. PC A information bits include K payload bits and L cyclic redundancy check (CRC) bits, where K, L, and n are... PC All are positive integers; generate the first bit sequence, which consists of N bits, including A information bits and n. PC One PC bits, A information bits, and n PC The PC bits are located in the first bit sequence with the highest sequence reliability (A+n). PC In ) positions, where N is 2 to the power of n and n is a positive integer, n are placed. PC n PC bits PC The PC positions satisfy the first and second conditions. The first condition is that the minimum row weight corresponding to the A positions containing the A information bits is not less than the minimum row weight corresponding to the A positions with the highest sequence reliability in the first bit sequence. Each position corresponds to one row weight. The second condition is n... PC n corresponding to each PC position PC Among the position numbers, the k-th highest position number is greater than or equal to the n corresponding to the third position set S3. PC The k-th highest position number among the position numbers, the third position set S3 includes the sequence with the highest reliability (A+n). PC The nth position with the lowest sequence reliability among ) positions PC There are n positions, 1≤k≤n PC Perform polar coding on the first bit sequence to obtain the codeword sequence; output the codeword sequence.

[0008] It is understandable that in this application, there are A information bits and n... PC How should the PC bits be placed, given A information bits and n? PC The PC bits are always located in the first bit sequence with the highest sequence reliability (A+n). PC At positions N-(A+n), the remaining positions are N-(A+n). PC There are 10 positions for placing the freeze bits.

[0009] It can also be understood that the row weight is an engineering index of the quality of the reaction code spectrum, but it is not equivalent to the code spectrum (the better the code spectrum, the stronger the error correction capability of the code). Since the process of calculating the code spectrum is very complex, it cannot be directly used as an index for engineering construction. Therefore, the first condition can also be understood as the code spectrum corresponding to the positions of the A information bits in the first bit sequence is not worse than the original code spectrum. The original code spectrum refers to the code spectrum corresponding to the case where the A information bits are placed in the A positions with the highest sequence reliability in the first bit sequence when there is no PC bit. In this application, no matter how the n PC PC bits are placed, as long as the minimum row weight corresponding to the positions of the A information bits does not change or becomes larger than the minimum row weight corresponding to the A positions with the highest sequence reliability in the first bit sequence, it is considered that the n PC PC positions of the first bit sequence satisfy the first condition.

[0010] It can also be understood that the larger the number of the positions of the PC bits, the wider the checking range of the PC bits. In this application, no matter how the n PC PC bits are placed, as long as the checking range corresponding to the n PC PC bits in the first PC placement mode is not worse than the checking range corresponding to the n PC PC bits, the first PC placement mode refers to placing the n PC PC bits in the n PC positions with the lowest sequence reliability in the (A+n PC ) positions with the highest sequence reliability in the first bit sequence, it is considered that the n PC PC positions of the first bit sequence satisfy the second condition.

[0011] In a second aspect, a communication method is provided, which can be executed by a receiving end device. In the absence of special description, the "receiving end device" in this application can refer to the receiving end device itself (for example, a network device, a terminal device), a component (for example, a processor, a chip, or a chip system) in the receiving end device, or a logic module or software capable of realizing all or part of the functions of the receiving end device.

[0012] The method comprises: obtaining a symbol sequence; determining a log-likelihood ratio (LLR) corresponding to positions of A information bits and n PC parity check bits (PC bits) in a first bit sequence based on the symbol sequence, the A information bits comprising K payload bits and L cyclic redundancy check (CRC) bits, the A information bits and the n PC PC bits being located in (A+n PC ) positions with the highest sequence reliability in the first bit sequence, wherein N is 2 raised to the power of n, K, L, and nPC are positive integers, wherein the n PC PC bits are placed in n PC PC positions satisfying a first condition and a second condition, the first condition being that a minimum row weight corresponding to A positions where the A information bits are located is not less than a minimum row weight corresponding to A positions with a highest sequence reliability in the first bit sequence, wherein each position corresponds to a row weight, and the second condition being that a kth highest position number in n PC position numbers corresponding to the n PC PC positions is greater than or equal to a kth highest position number in n PC position numbers corresponding to a third position set S3, the third position set S3 indicating n PC positions with a lowest sequence reliability in the (A+n PC ) positions with the highest sequence reliability, 1≤k≤n PC ; obtaining S decoding paths with a minimum path metric value PM corresponding to positions before an ith PC position, wherein the ith PC position is any position in the n PC PC positions, the PM of the S decoding paths being determined based on LLRs corresponding to the positions before the ith PC position; if a first value of the ith PC position corresponding to a first decoding path is different from a second value of the ith PC position, increasing the PM of the first decoding path, wherein the first decoding path is any path in the S paths, the first value being determined based on a decoding result corresponding to the first decoding path and a PC check relation corresponding to the ith PC position, and the second value being a hard decision result of the LLR corresponding to the ith PC position; if the first value of the ith PC position corresponding to the first decoding path is the same as the second value of the ith PC position, keeping the PM value of the first decoding path unchanged; continuing decoding based on the symbol sequence and the S decoding paths until a final S decoding paths with a minimum PM are obtained by completing decoding of the symbol sequence; obtaining the first bit sequence, the first bit sequence being determined based on a decoding result of a decoding path with a minimum PM in the final S decoding paths with a minimum PM.

[0013] The beneficial effects of the second aspect are described in the first aspect, which will not be repeated here.

[0014] In some implementations of the first aspect or the second aspect, n PCThe first PC position of the three PC positions is determined based on the minimum row weight corresponding to the second position set S2 and the row weight corresponding to the first candidate position, the first PC position being the first determined PC position of the three PC positions, wherein the first candidate position is a position with the highest sequence reliability in the third position set S3, the second position set S2 including A positions with the highest sequence reliability in the first bit sequence, and if the row weight corresponding to the first candidate position is smaller than the minimum row weight corresponding to the second position set S2, the first candidate position is taken as the first PC position, and if the row weight corresponding to the first candidate position is greater than or equal to the minimum row weight corresponding to the second position set S2, a position with the largest position number or the highest sequence reliability in the fourth position set S4 is taken as the first PC position, the fourth position set S4 including positions in the first position set S1 with the minimum row weight equal to the minimum row weight of the second position set S2, and the first position set S1 including the second position set S2 and the first candidate position.

[0015] It can be understood that blindly expanding the checking range of the PC bit may cause the native code spectrum to deteriorate. Therefore, in order to improve the native code spectrum as much as possible when there is no PC bit, and to make the checking range of the PC bit as wide as possible, a compromise between the checking range and the row weight is needed to determine the PC position. The above technical solution takes n PC As an example, a compromise implementation of determining the first PC position is given when n = 3, the first PC position being the first determined PC position of the three PC positions.

[0016] In some implementations of the first aspect or the second aspect, the second PC position of the three PC positions is determined based on the minimum row weight corresponding to the second position set S2 after the first update and the row weight corresponding to the second candidate position, the second PC position being the second determined PC position of the three PC positions, wherein the second candidate position is a position with the second highest sequence reliability in the third position set S3, the second position set S2 after the first update being a position set corresponding to the first position set S1 after the first PC position is deleted, if the row weight corresponding to the second candidate position is smaller than the minimum row weight corresponding to the second position set S2 after the first update, the second candidate position is taken as the second PC position, and if the row weight corresponding to the second candidate position is greater than or equal to the minimum row weight corresponding to the second position set S2 after the first update, a position with the largest position number or the highest sequence reliability in the fifth position set S5 is taken as the second PC position, the fifth position set S5 including positions in the first position set S1 after the first update with the minimum row weight equal to the minimum row weight of the second position set S2 after the first update, and the first position set S1 after the first update including the second position set S2 after the first update and the second candidate position.

[0017] The above technical solution takes n PCFor example, when n

[0018] In some implementations of the first aspect or the second aspect, the third PC position is determined based on the minimum row weight corresponding to the second position set S2 after the second update and a row weight corresponding to a third candidate position, the third PC position being the third determined PC position among the n

[0019] The above technical solutions are based on n PC For example, when n

[0020] In some implementations of the first aspect or the second aspect, the i-th PC position among the n PC PC positions is determined based on the minimum row weight corresponding to the second position set S2 after the i-th round and a row weight corresponding to an i-th candidate position among the third position set, the i-th candidate position being the i-th position with the i-th highest sequence reliability among the third position set S3, the n PC PC positions being determined in turn as a PC position based on the sequence reliability from high to low, the n PC The first PC position among the n PC-1; If the row weight corresponding to the i-th candidate position is less than the minimum row weight corresponding to the second position set S2 in the i-th round, the i-th candidate position is taken as the i-th PC position. If the row weight corresponding to the i-th candidate position is greater than or equal to the minimum row weight corresponding to the second position set S2 in the i-th round, the position with the largest position number or the highest sequence reliability in the fourth position set S4 is taken as the i-th PC position. The fourth position set S4 includes the position in the first position set S1 in the i-th round whose row weight is equal to the minimum row weight of the second position set S2 in the i-th round. The first position set S1 in the i-th round includes the second position set S2 in the i-th round and the i-th candidate position; n PC The (i+1)th PC position is determined based on the row weight of the second position set S2 in the (i+1)th round and the row weight of the (i+1)th candidate position. The second position set S2 in the (i+1)th round includes all positions remaining in the first position set in the i-th round except for the ith PC position. The (i+1)th candidate position is the position with the (i+1)th highest sequence reliability in the third position set S3. If the row weight corresponding to the (i+1)th candidate position is less than the minimum row weight corresponding to the second position set S2 in the (i+1)th round, the (i+1)th candidate position is selected as the... For the (i+1)th PC position, if the row weight corresponding to the (i+1)th candidate position is greater than or equal to the minimum row weight corresponding to the second position set S2 of the (i+1)th round, the position with the largest position number or the highest sequence reliability in the fifth position set S5 is taken as the (i+1)th PC position. The fifth position set S5 includes the position in the first position set S1 of the (i+1)th round with the minimum row weight equal to the minimum row weight of the second position set S2 of the (i+1)th round. The first position set S1 of the (i+1)th round includes the second position set S2 of the (i+1)th round and the (i+1)th candidate position.

[0021] The above technical solution provides a method for determining the PC position by compromising between the check range and line weight. It can maximize the original code spectrum when PC bits are absent while simultaneously expanding the PC bit check range. In this solution, n needs to be determined sequentially. PC There are n PC positions, and the previous PC position affects the determination of the next PC position. This implementation can be viewed as determining n positions serially. PC The method of PC location.

[0022] In some implementations of the first or second aspect, n PC The PC positions are based on the minimum row weight corresponding to the second position set S2 and n in the third position set S3. PC The row weight corresponding to each position is determined. The second position set S2 includes the A positions with the highest sequence reliability in the first bit sequence. If the row weight corresponding to m1 positions in the third position set S3 is less than the minimum row weight corresponding to the second position set S2, then m1 positions are used as PC positions, where 1 ≤ m1 ≤ n.PC If the row weight corresponding to the m2 positions in the third position set S3 is greater than or equal to the minimum row weight corresponding to the second position set S2, the m2 positions with the largest position number or the m2 positions with the highest sequence reliability in the fourth position set S4 are PC positions, the fourth position set S4 includes positions in the first position set S1 with the minimum row weight equal to the second position set S2, the first position set S1 includes the second position set S2 and the third position set S3, and m1+m2=n PC .

[0023] The technical solution provides another implementation mode of determining PC positions between the check range and the row weight, which can improve the native code spectrum as much as possible when there is no PC bit, and make the PC bit check range as wide as possible. In the technical solution, n PC PC positions are determined at the same time, and the implementation mode can be regarded as a mode of determining n PC PC positions in parallel.

[0024] In some implementations of the first aspect or the second aspect, the n PC PC positions are determined based on the minimum row weight corresponding to the second position set S2 and the row weight corresponding to the n PC positions in the third position set S3, wherein the second position set S2 includes A positions with the highest sequence reliability in the first bit sequence, if the row weight corresponding to the i-th position in the third position set S3 is less than the minimum row weight corresponding to the second position set S2, the i-th position is a PC position, 1≤i≤n PC If the row weight corresponding to the i-th position in the third position set S3 is greater than or equal to the minimum row weight corresponding to the second position set S2, the position with the largest position number or the position with the highest sequence reliability in the fifth position set S5 is a PC position, wherein the fifth position set S5 is the remaining positions in the fourth position set S4 except the determined PC positions, and the fourth position set includes positions in the first position set S1 with the minimum row weight equal to the second position set S2, and the first position set S1 includes the second position set S2 and the third position set S3.

[0025] The technical solution provides another implementation mode of determining PC positions between the check range and the row weight, which can improve the native code spectrum as much as possible when there is no PC bit, and make the PC bit check range as wide as possible. In the implementation mode, n PC PC positions can be determined in parallel.

[0026] In some implementations of the first aspect or the second aspect, the n PC PC positions are the n PCpositions, or, n PC positions with the highest sequence reliability or the largest position number in the first bit sequence. PC

[0027] In some implementations of the first aspect or the second aspect, the A information bits are located in the remaining A positions in the first bit sequence except for the n PC positions. PC

[0028] In some implementations of the first aspect or the second aspect, the method further includes determining values of the n PC PC bits based on PC check relations corresponding to the n PC PC positions.

[0029] In a third aspect, a communication method is provided, which can be performed by a sending end device. In the absence of special description, the "sending end device" in the present application can refer to the sending end device itself (for example, a network device, a terminal device), a component (for example, a processor, a chip, or a chip system, etc.) in the sending end device, or a logic module or software capable of realizing all or part of the functions of the sending end device.

[0030] The method includes: obtaining A information bits and a number n PC of parity check (PC) bits, the A information bits including K payload bits and L cyclic redundancy check (CRC) bits, K, L, and n PC are positive integers; generating a first bit sequence, the first bit sequence including N bits, the N bits including the A information bits and the n PC PC bits, the A information bits and the n PC PC bits being located in (A+n PC ) positions with the highest sequence reliability in the first bit sequence, wherein N is a power of 2, n is a positive integer,

[0031] The i-th PC position in the n PC PC positions is determined based on a minimum row weight corresponding to a second position set S2 of the i-th round and a row weight of an i-th candidate position in a third position set S3, wherein the i-th candidate position is a position with the i-th highest sequence reliability in the third position set S3, and the n PC positions in the third position set S3 are sequentially determined as a PC position as a candidate position in descending order of sequence reliability, and n PC ​​The first PC position in the PC positions is determined based on a row weight of a second position set S2 of the first round and a row weight of a first candidate position, the second position set S2 of the first round including A positions with the highest sequence reliability in the first bit sequence, and the first candidate position being a position with the highest sequence reliability in the third position set S3, 1≤i≤n PC -1,

[0032] If the row weight corresponding to the ith candidate position is less than the minimum row weight corresponding to the second position set S2 of the ith round, the ith candidate position is taken as the ith PC position,

[0033] If the row weight corresponding to the ith candidate position is greater than or equal to the minimum row weight corresponding to the second position set S2 of the ith round, a position with the largest position number or the highest sequence reliability in the fourth position set S4 is taken as the ith PC position, the fourth position set S4 including positions with the row weight equal to the minimum row weight of the second position set S2 of the ith round in the first position set S1 of the ith round, and the first position set S1 of the ith round including the second position set S2 of the ith round and the ith candidate position;

[0034] n PC The ith+1 PC position in the PC positions is determined based on a row weight of a second position set S2 of the ith+1 round and a row weight of an ith+1 candidate position, the second position set S2 of the ith+1 round including positions other than the ith PC position in the first position set S1 of the ith round, and the ith+1 candidate position being a position with the ith+1 highest sequence reliability in the third position set S3,

[0035] If the row weight corresponding to the ith+1 candidate position is less than the minimum row weight corresponding to the second position set S2 of the ith+1 round, the ith+1 candidate position is taken as the ith+1 PC position,

[0036] If the row weight corresponding to the ith+1 candidate position is greater than or equal to the minimum row weight corresponding to the second position set S2 of the ith+1 round, a position with the largest position number or the highest sequence reliability in the fifth position set S5 is taken as the ith+1 PC position, the fifth position set S5 including positions with the row weight equal to the minimum row weight of the second position set S2 of the ith+1 round in the first position set S1 of the ith+1 round, and the first position set S1 of the ith+1 round including the second position set S2 of the ith+1 round and the ith+1 candidate position;

[0037] The first bit sequence is polarized to obtain a code word sequence; and the code word sequence is output.

[0038] In a fourth aspect, a communication method is provided, which can be performed by a transmitting device. In the present application, the "transmitting device" can refer to the transmitting device itself (e.g., a network device, a terminal device), a component (e.g., a processor, a chip, or a chip system) in the transmitting device, or a logic module or software capable of realizing all or part of the functions of the transmitting device.

[0039] The method comprises: obtaining A information bits and a number n of parity check PC bits PC , the A information bits comprising K payload bits and L cyclic redundancy check CRC bits, K, L, and n PC are positive integers; generating a first bit sequence, the first bit sequence comprising N bits, the N bits comprising the A information bits and the n PC PC bits, the A information bits and the n PC PC bits being located at (A+n PC ) positions with the highest sequence reliability in the first bit sequence, wherein N is a power of 2, n is a positive integer,

[0040] n PC PC positions are determined based on a minimum row weight corresponding to a second position set S2 and row weights corresponding to n PC positions in a third position set S3, wherein the second position set S2 comprises A positions with the highest sequence reliability in the first bit sequence,

[0041] If m1 positions in the third position set S3 correspond to row weights smaller than the minimum row weight corresponding to the second position set S2, the m1 positions are taken as the PC positions, 1≤m1≤n PC ,

[0042] If m2 positions in the third position set S3 correspond to row weights greater than or equal to the minimum row weight corresponding to the second position set S2, m2 positions with the largest position number or the highest sequence reliability in a fourth position set S4 are taken as the PC positions, the fourth position set S4 comprising positions in the first position set S1 with row weights equal to the minimum row weight of the second position set S2, the first position set S1 comprising the second position set S2 and the third position set S3, wherein m1+m2=n PC ;

[0043] Polar encoding the first bit sequence to obtain a codeword sequence; and outputting the codeword sequence.

[0044] In a fifth aspect, a communication method is provided, which can be performed by a transmitting device. In the present application, the "transmitting device" can refer to the transmitting device itself (e.g., a network device, a terminal device), a component (e.g., a processor, a chip, or a chip system) in the transmitting device, or a logic module or software capable of realizing all or part of the functions of the transmitting device.

[0045] The method comprises: obtaining A information bits and a number n of parity check PC bits PC , the A information bits comprising K payload bits and L cyclic redundancy check CRC bits, K, L and n PC being positive integers; generating a first bit sequence, the first bit sequence comprising N bits, the N bits comprising the A information bits and the n PC PC bits, the A information bits and the n PC PC bits being located at (A+n PC ) positions with the highest sequence reliability in the first bit sequence, wherein N is a power of 2, n is a positive integer,

[0046] n PC PC positions are determined based on a minimum row weight corresponding to a second position set S2 and row weights corresponding to n PC positions in a third position set S3, wherein the second position set S2 comprises A positions with the highest sequence reliability in the first bit sequence,

[0047] if an i-th position in the third position set S3 corresponds to a row weight smaller than the minimum row weight corresponding to the second position set S2, the i-th position is taken as a PC position, 1≤i≤n PC ,

[0048] if an i-th position in the third position set S3 corresponds to a row weight greater than or equal to the minimum row weight corresponding to the second position set S2, a position with the largest position number or the highest sequence reliability in a fifth position set S5 is taken as a PC position, wherein the fifth position set S5 is a set of positions remaining in a fourth position set S4 except the PC positions already determined, the fourth position set S4 comprises positions in a first position set S1 with a row weight equal to the minimum row weight of the second position set S2, and the first position set S1 comprises the second position set S2 and the third position set S3.

[0049] polar encoding the first bit sequence to obtain a codeword sequence; and outputting the codeword sequence.

[0050] In a sixth aspect, a communication apparatus is provided. The apparatus is configured to perform the method in any one of the preceding aspects or implementation manners. Specifically, the apparatus can include units and / or modules for performing the method in any one of the preceding aspects or implementation manners, such as a processing unit and / or a transceiving unit.

[0051] In an implementation manner, the apparatus is a sending device or a receiving device. When the apparatus is the sending device or the receiving device, the transceiving unit can be a transceiver, or an input / output interface, or a communication interface; and the processing unit can be at least one processor. Optionally, the transceiver is a transceiving circuit. Optionally, the input / output interface is an input / output circuit.

[0052] In another implementation manner, the apparatus is a chip, a chip system or a circuit for the sending device or the receiving device. When the apparatus is the chip, the chip system or the circuit for the sending device or the receiving device, the transceiving unit can be an input / output interface, an interface circuit, an output circuit, an input circuit, a pin or related circuit, etc. on the chip, the chip system or the circuit; and the processing unit can be at least one processor, a processing circuit or a logic circuit, etc.

[0053] In a seventh aspect, a communication apparatus is provided. The apparatus includes a memory configured to store a computer program or instructions; and at least one processor configured to execute the computer program or instructions stored in the memory to perform the method in any one of the preceding aspects or implementation manners.

[0054] In an implementation manner, the apparatus is a sending device or a receiving device.

[0055] In another implementation manner, the apparatus is a chip, a chip system or a circuit for the sending device or the receiving device.

[0056] In an eighth aspect, a communication apparatus is provided. The apparatus includes at least one processor and a communication interface. The at least one processor is configured to acquire, through the communication interface, a computer program or instructions stored in a memory, to perform the method in any one of the preceding aspects or implementation manners. The communication interface can be implemented by hardware or software.

[0057] In an implementation manner, the apparatus further includes the memory.

[0058] In a ninth aspect, a processor is provided. The processor is configured to perform the method in any one of the preceding aspects.

[0059] For the sending and obtaining / receiving operations involved by the processor, if no special description is made, or if it does not conflict with the actual role or internal logic in the related description, it can be understood as the processor output and receiving, input operations, and also can be understood as the sending and receiving operations performed by the radio frequency circuit and the antenna, and the present application does not limit this.

[0060] In a tenth aspect, a computer readable storage medium is provided, which stores program codes for execution by a device, and the program codes comprise codes for executing the method provided in any one of the above aspects or implementation manners thereof.

[0061] In an eleventh aspect, a computer program product containing instructions which, when the computer program product is run on a computer, cause the computer to execute the method provided in any one of the above aspects or implementation manners thereof.

[0062] In a twelfth aspect, a chip is provided, which comprises a processor and a communication interface, and the processor reads instructions stored on a memory through the communication interface and executes the method provided in any one of the above aspects or implementation manners thereof. The communication interface can be realized by hardware or software.

[0063] Optionally, as an implementation manner, the chip further comprises a memory, and the memory stores a computer program or instructions, and the processor is configured to execute the computer program or instructions stored on the memory, and when the computer program or instructions are executed, the processor is configured to execute the method provided in any one of the above aspects or implementation manners thereof.

[0064] When the method provided in the present application is executed by a chip, the present application does not limit the number of chips for specifically implementing the method of the present application, for example, the method can be executed by one chip, or two or more chips. Moreover, when the number of chips for implementing the method of the present application is two or more, the chip manufacturers are not limited, and can be the same manufacturer or different manufacturers.

[0065] In a thirteenth aspect, a communication system is provided, which comprises at least one of the above-mentioned sending device or receiving device. BRIEF DESCRIPTION OF DRAWINGS

[0066] FIG. 1 is a schematic diagram of a network architecture to which the embodiments of the present application are applicable.

[0067] FIG. 2 is a schematic diagram of an information transmission process.

[0068] FIG. 3 is a schematic diagram of 8x8 Polar code encoding.

[0069] FIG. 4 is a schematic diagram of SC decoding.

[0070] FIG. 5 is a schematic diagram of a binary tree of Polar code SC decoding.

[0071] FIG. 6 is a schematic diagram of a binary tree for SCL-2 decoding of a Polar code.

[0072] FIG. 7 is a schematic flow chart of a communication method 700 according to an embodiment of the present application.

[0073] FIGS. 8-10 are schematic diagrams of code spectrums corresponding to Tables 3-5, respectively.

[0074] FIG. 11 is a schematic block diagram of a communication apparatus 1000 according to an embodiment of the present application.

[0075] FIG. 12 is a schematic block diagram of a communication apparatus 1100 according to an embodiment of the present application. DETAILED DESCRIPTION

[0076] In order to facilitate understanding of the embodiments of the present application, the following points are explained before the embodiments of the present application are introduced.

[0077] "Indicative of" or "indicate" can include both direct and indirect indication, or "indicative of" or "indicate" can explicitly and / or implicitly indicate. The first, second, etc. various numerical designations are only for the convenience of description and do not limit the scope of the embodiments of the present application, for example, to distinguish different messages, different information, etc. "Predefined" can be achieved by pre-storing corresponding codes, tables or other means for indicating relevant information in the device, and the specific implementation manner is not limited in the present application. The "protocol" referred to can refer to a standard protocol in the communication field, which can include a long term evolution (LTE) protocol, a new radio (NR) protocol and a related protocol applied in a future communication system, and the present application is not limited thereto. The words "example", "for example", "exemplary", "as an example", etc. are used to indicate an example, illustration or description. Any embodiment or design scheme described as "example" in the present application should not be interpreted as more preferred or more advantageous than other embodiments or design schemes. The terms "include", "contain", "have" and their variants mean "including but not limited to", unless otherwise specifically emphasized. "At least one" refers to one or more, and "multiple" refers to two or more. "At most one" refers to one or 0. "And / or", which describes the association relationship of the associated objects, means that there can be three kinds of relationships, for example, A and / or B can represent the following three cases: A exists alone, A and B exist together, and B exists alone, where A and B can be singular or plural. The character " / " generally represents an "or" relationship between the associated objects before and after it. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or multiple items. For example, at least one of a, b and c can represent: a, or b, or c, or a and b, or a and c, or b and c, or a, b and c. Where a, b and c can be single or multiple. The description related to the network element A sending a message, information or data to the network element B, and the network element B receiving the message, information or data from the network element A, is intended to indicate which network element the message, information or data is intended to send to, and does not limit whether they are directly sent or indirectly sent via other network elements. "When", "in the case of", "if" and "if" and other descriptions all refer to the objective situation in which the device will make corresponding processing, and are not limited by time, and do not require the device to have a judgment action when implemented, nor does it mean that there are other limitations.

[0078] In addition, the network architecture and service scenarios described in the embodiments of the present application are for more clearly illustrating the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided by the embodiments of the present application. Those skilled in the art can know that, with the evolution of network architecture and the emergence of new service scenarios, the technical solutions provided by the embodiments of the present application are also applicable to similar technical problems.

[0079] The communication system to which the embodiments of the present application can be applied will be described below.

[0080] The embodiments of the present application can be applied to various communication systems, including but not limited to: a 5th generation (5G) system, an LTE system, a long term evolution-advanced (LTE-A) system, an LTE frequency division duplex (FDD) system, an LTE time division duplex (TDD) system, etc. It can also be applied to future communication systems, such as a 6th generation mobile communication system. In addition, it can also be applied to device to device (D2D) communication, vehicle-to-everything (V2X) communication, machine to machine (M2M) communication, machine type communication (MTC), an internet of things (IoT) communication system, a narrow band-internet of things (NB-IoT) system, or other communication systems. In addition, it can also be extended to similar wireless communication systems, such as wireless-fidelity (WiFi), worldwide interoperability for microwave access (WIMAX), and 3rd generation partnership project (3GPP) related communication systems, etc., without limitation.

[0081] The communication system to which the embodiments of the present application can be applied can include one or more transmitting end devices and one or more receiving end devices. Alternatively, one of the transmitting end device and the receiving end device can be a terminal device, and the other can be a network device. Alternatively, the transmitting end device and the receiving end device can both be terminal devices. Alternatively, the transmitting end device and the receiving end device can both be network devices.

[0082] FIG. 1 is a schematic diagram of a network architecture to which embodiments of the present application are applicable. As shown in FIG. 1, embodiments of the present application are applicable to both uplink data transmission and downlink data transmission. In FIG. 1, only uplink data transmission or downlink data transmission between one network device and two terminal devices (e.g., terminal device 1 and terminal device 2) is taken as an example. In uplink data transmission, the transmitting terminal device is the terminal device and the receiving terminal device is the network device; conversely, in downlink data transmission, the transmitting terminal device is the network device and the receiving terminal device is the terminal device. In addition, embodiments of the present application are not limited to be applicable to other communication scenarios, for example, they can also be applied to sidelink communication.

[0083] The terminal device in the embodiments of the present application can also be referred to as a user equipment (UE), an access terminal, a user unit, a user station, a mobile station, a mobile station, a mobile terminal (MT), a remote station, a remote terminal, a mobile device, a user terminal, a terminal, a drone, a wireless communication device, a user agent or a user apparatus, etc. The terminal device in the embodiments of the present application can refer to a device that provides voice and / or data connectivity to a user, and can be used to connect people, things and machines, such as handheld devices with wireless connection functions, vehicle-mounted devices, etc. The terminal device in the embodiments of the present application can be a mobile phone, a tablet computer, a notebook computer, a palm computer, a mobile internet device (MID), a wearable device, a virtual reality (VR) device, an augmented reality (AR) device, a wireless terminal in industrial control, a wireless terminal in self driving, a wireless terminal in remote medical surgery, a wireless terminal in smart grid, a wireless terminal in transportation safety, a wireless terminal in smart city, a wireless terminal in smart home, etc.

[0084] The network device of the present application can be a device with wireless transceiving function, which can be a device providing wireless communication function service, usually located at the network side, including but not limited to next generation base station (gNodeB, gNB) in 5G system, base station in sixth generation mobile communication system, base station in future mobile communication system, or access node in wireless fidelity (WiFi) system, evolved node B (eNB) in long term evolution (LTE) system, radio network controller (RNC), node B (NB), base station controller (BSC), home base station (such as home evolved NodeB or home Node B, HNB), base band unit (BBU), transmission reception point (TRP), transmitting point (TP), base transceiver station (BTS), satellite, unmanned aerial vehicle, etc. In one network structure, the network device can include a centralized unit (CU) node, or include a distributed unit (DU) node, or be a RAN device including CU node and DU node, or be a RAN device including control plane CU node and user plane CU node, and DU node, or the network device can also be a wireless controller in cloud radio access network (CRAN) scenario, relay station, vehicle-mounted device, wearable device, etc. In addition, the base station can be a macro base station, micro base station, relay node, donor node or combination thereof. The base station can also refer to a communication module, modem or chip for setting in the foregoing device or apparatus. The base station can also be a mobile switching center, and a device assuming base station function in D2D, V2X, M2M communication, a device assuming base station function in future communication system, etc. The base station can support networks of the same or different access technologies, without limitation.

[0085] Unless otherwise defined, the apparatuses used for realizing the functions of the terminal device or the network device in the present application can refer to the terminal device or the network device itself, or can refer to an apparatus capable of supporting the terminal device or the network device to realize the functions, such as a chip system or a chip, specifically, a system on a chip (SoC) or a Modem. The apparatus can be installed in the terminal device or the network device. In the embodiments of the present application, the chip system can be composed of a chip, or can include a chip and other discrete devices.

[0086] It should also be noted that some embodiments in the present application take the 5G system as an example to introduce specific scheme details. It can be understood that when the scheme is used in other communication systems, for example, an LTE system or a future communication system, the messages, channels or information in the scheme can be replaced by messages, channels or information capable of realizing corresponding functions in other communication systems, and the present application does not limit this.

[0087] In addition, the embodiments of the present application can be applied to various application scenarios, such as a high throughput scenario, a high reliability scenario, a low latency scenario, a high reliability low latency scenario or a low power consumption scenario. The high throughput scenario can be, for example, an enhanced mobile broadband (eMBB) scenario, and the high reliability low latency scenario can be, for example, an ultra reliable low latency communication (URLLC) scenario.

[0088] FIG. 2 is a schematic diagram of an information transmission process. As shown in FIG. 2, information is sent by a source, processed by source encoding, channel encoding, modulation, air interface transmission, demodulation, channel decoding, source recovery and the like, and reaches a destination, thereby completing the transmission of information from the source to the destination. The processing shown in the upper layer of FIG. 2 (including source encoding, channel encoding and modulation, etc.) is performed at the sending end device, and the processing shown in the lower layer (including demodulation, channel decoding, source recovery, etc.) is performed at the receiving end device. The embodiments of the present application mainly involve source encoding, channel encoding, channel decoding and source recovery shown in FIG. 2.

[0089] At present, Polar code is the first channel coding scheme that can be strictly proved to "reach" the Shannon channel capacity, and has the characteristics of good error correction performance and low decoding complexity. Polar code has been determined by 3GPP as the encoding scheme of the control channel in the 5G eMBB scenario (uplink / downlink). The encoding, construction and decoding process of Polar code are briefly introduced below.

[0090] [Corrected according to Rule 91 on 04.08.2025] FIG. 3 is a schematic diagram of Polar code encoding with length 8. The encoding process includes several polar kernel operations (polar kernel is shown by a smaller dashed box), and the polar kernel multiplies two input bits to get two output bits. As can be seen, the Polar code is recursively constructed, where the Polar code with length 8 can be seen as coupling 2 Polar codes with length 4 (corresponding to the two larger dashed boxes in the figure), and the Polar code with length 4 can be seen as coupling 2 Polar codes with length 2. As can be seen, the Polar code is recursively constructed, where the Polar code with length 8 can be seen as coupling 2 Polar codes with length 4 (corresponding to the two larger dashed boxes in the figure), and the Polar code with length 4 can be seen as coupling 2 Polar codes with length 2.

[0091] It can be understood that the N positions corresponding to the N to-be-encoded bits before Polar code encoding have different reliabilities. Among the N positions, the A positions with the highest reliability are used to place A data bits in the to-be-encoded bits, and the remaining N-A positions are used to place frozen bits. The bits on the frozen bit positions are usually 0, and the frozen bits are known at both ends of the actual transmission. In this application, the positions carrying the A information bits can be referred to as information bit positions, and the positions carrying the frozen bits can be referred to as frozen bit positions. For example, as shown in FIG. 3, N = 8, 8 positions are used to carry 8 to-be-encoded bits, and the 8 to-be-encoded bits are u0-u7 on the leftmost side. Among the to-be-encoded bits, there are 4 information bits (i.e., u7, u6, u5, u3), and the information bit positions where the 4 information bits are placed are the four bit positions with the highest reliability. The remaining 4 positions place frozen bits (u4, u2, u1, u0), and the frozen bit positions where the 4 frozen bits are placed are the four bit positions with the lowest reliability. As shown in FIG. 3, after encoding, the 8 codeword bits on the rightmost side are 01010101, which are denoted as c0-c7. The sending end device sends c0-c7 to the channel W.

[0092] For Polar code decoding, the Successive Cancellation (SC) decoding algorithm can be used. In SC, the decoding result is directly determined by hard decision, specifically, the log-likelihood ratio (LLR) of information bits is calculated step by step, for information bits, if LLR>0, the bit is determined as 0, if LLR<0, the bit is determined as 1; for frozen bits, no matter what the LLR is, the bit is set as 0. FIG. 4 is a schematic diagram of the simplest SC decoding. There are 8 calculation nodes in the figure, including 4 f nodes and 4 g nodes. The calculation of the f node needs 2 LLR inputs on the right side, and the calculation of the g node needs 2 LLR inputs on the right side and 1 "partial sum" input on the top. It can be understood that only after the calculation of the input is completed, the calculation of the output can be performed. According to the above rule, the 8 nodes in FIG. 4 are calculated in order from the right side of the received signal, and the order of the obtained decoding bits is ①→②→③→④, and the above process is the SC decoding process. From another point of view, since each information bit only has two values of 0 and 1, the SC decoding of the Polar code can be abstracted as a binary tree search problem, and FIG. 5 is a schematic diagram of the binary tree of the SC decoding of the Polar code. Each layer of the binary tree represents the judgment result of an information bit, and the binary tree can represent 0 to the left and 1 to the right. The 4 decoding bits correspond to 2 4 decoding paths, and the darker path in the figure is the decoding path obtained by hard decision.

[0093] Based on the SC algorithm, it is proved that the Polar code can reach the infinite-length capacity. However, the performance of SC is not satisfactory in the finite length. In view of this problem, the industry proposes the Successive Cancellation List (SCL) decoding algorithm and the cyclic redundancy check (CRC)-Aided Successive Cancellation List (CA-SCL) decoding algorithm to improve the performance of the Polar code. The two algorithms are introduced below.

[0094] The SCL algorithm is an extension of the SC algorithm. FIG. 6 is a binary tree diagram of Polar code SCL-2 decoding. As shown in FIG. 6, the SCL algorithm does not directly determine the decoding result by hard decision in the middle process, but saves the decoding results corresponding to 0 and 1 into two branch decoding paths. Through the above method, if the SCL algorithm saves List decoding paths in total, and finally selects the correct path through path metric (PM), the List paths can be sorted in ascending order of PM, and the decoding path at the front of the sorting is more likely to be the correct codeword. This way of selecting the path without CRC is the way of outputting the final codeword in the traditional SCL decoding, that is, outputting the path with the optimal PM (i.e., the first path with the smallest PM) as the final codeword. The CA-SCL will use CRC check to select the correct path from the first path, thereby obtaining better error correction performance than the bit SCL. The two paths with darker colors in FIG. 6 are the two paths output by SCL2, and the SCL decoder will output the path with smaller PM (more like the correct codeword) as the final decoding result. The CA-SCL will first test the path with the smallest PM using CRC, and if it does not pass the CRC, it will continue to test the second path with the second smallest PM, until it finds a path that passes the CRC as the final decoding result. If all paths do not pass the CRC check, the decoding fails. However, this CA-SCL decoding algorithm using CRC to select the path will lose the error detection capability of CRC, because the CRC polynomial with a length of L crc can detect errors with a probability of about 1 / 2 Lcrc , where L crc is the length of the CRC, but the CA-SCL decoding uses List CRC detection, so the error detection probability of the CRC is increased by List times, becoming List / 2 Lcrc . Therefore, using CRC to select the path in CA-SCL decoding will lose the error detection performance.

[0095] At present, as shown in the background art, a PC-Polar code is proposed, and based on the PC bits in the PC-Polar code, the PM of the SCL decoding can be corrected to improve the probability that the correct decoding path is ranked first. The PC bits in this application can also be called dynamic frozen bits (the position comes from the frozen bit, but the value is not fixed as 0). The position of the PC bit in this application can be called dynamic frozen bit position, or PC position, which is not limited in this application. The addition of PC bits can make the correct decoding path more forward, and the probability that the first output path is the correct codeword is improved, so that the decoding path does not need to be checked by CRC, thereby saving the number of CRC usage and not losing the error detection capability of CRC. However, the existing placement method of PC bits does not consider the need to determine the correct decoding path based on PC bits, so the decoding performance based on PC bits needs to be improved.

[0096] Therefore, the application provides a communication method, which can effectively solve the above technical problems. The method embodiments provided by the application are described below.

[0097] FIG. 7 is a schematic flowchart of a communication method 700 provided by the application. The method includes the following steps.

[0098] It can be understood that the method 700 can be executed by a sending device and a receiving device. Unless otherwise specified, the "sending device" or the "receiving device" can refer to the sending device or the receiving device itself, or can refer to an apparatus capable of supporting the sending device or the receiving device to implement the function. For the convenience of description, the sending device and the receiving device are used to describe the following embodiments. The sending device can be a terminal device or a network device, and the receiving device can be a terminal device or a network device.

[0099] S710, the sending device obtains A information bits and the number n of PC bits PC of which the A information bits include K payload bits and L CRC bits, K, L and n PC are positive integers.

[0100] It can be understood that the value of the n PC PC bits is determined based on the PC position where each PC bit is located and the corresponding PC check relationship. Therefore, the placement position of the n PC PC bits (i.e., the n PC PC position) needs to be determined first, and then the value of the PC bit at each PC position is determined.

[0101] S720, the sending device generates a first bit sequence, the first bit sequence includes N bits, the N bits include A information bits and n PC PC bits, the A information bits and the n PC PC bits are located at the (A+n PC ) positions with the highest sequence reliability in the first bit sequence, N is the mother code length of a Polar code word, N is 2 raised to the power of n, and n is a positive integer.

[0102] It can be understood that no matter how the A information bits and the n PC PC bits are placed, the A information bits and the n PC PC bits are always located at the (A+n PC ) positions with the highest sequence reliability in the first bit sequence, and the remaining N-(A+n PC ) positions are used to place frozen bits, and the values at the frozen positions are known to the sending device and the receiving device, and the value of the frozen bit can be fixed as 0.

[0103] Optionally, in the present application, the sequence reliability can also be replaced by a Gaussian approximate (GA) reliability, which is a reliability calculated based on a Gaussian approximation.

[0104] wherein n PC PC positions satisfy the first condition and the second condition. The first condition and the second condition are as follows:

[0105] (1) The first condition is that the minimum row weight corresponding to the A positions where the A information bits are located is not less than the minimum row weight corresponding to the A positions with the highest sequence reliability in the first bit sequence, wherein each position corresponds to a row weight.

[0106] The row weight corresponding to a position can be calculated in the following manner: the current position number is i, and the binary representation corresponding thereto is (b0, b1, b2,..,b m-1 ), then the row weight corresponding to the current position i is For example, the current position is 3, and the binary representation corresponding thereto is (0, 1, 1), then the row weight of position 0 is 2 2 = 4; the current position is 7, and the binary representation corresponding thereto is (1, 1, 1), then the row weight of position 7 is 2 3 = 8.

[0107] It can be understood that the row weight is an engineering index reflecting the quality of the code spectrum, and is not equivalent to the code spectrum (the better the code spectrum, the stronger the error correction capability of the code). Since the process of calculating the code spectrum is very complex, it cannot be directly used as an index for engineering construction. Therefore, the first condition can also be understood as the code spectrum corresponding to the positions where the A information bits are located in the first bit sequence is not worse than the original code spectrum, wherein the original code spectrum refers to the code spectrum corresponding to the case where the A information bits are placed in the A positions with the highest sequence reliability in the first bit sequence when there are no PC bits.

[0108] In the present application, due to the presence of PC bits, the A information bits and n PC PC bits are placed in the (A+n PC ) positions with the highest sequence reliability in the first bit sequence. If the n PC PC bits are placed in the n PC positions with the lowest sequence reliability among the (A+n PC ) positions with the highest sequence reliability (hereinafter referred to as the first PC placement manner), the sequence reliability of the positions where the A information bits are located does not change, and the minimum row weight corresponding to the positions where the A information bits are located does not change compared to the minimum row weight corresponding to the A positions with the highest sequence reliability in the first bit sequence, if the n PCThe A information bits are placed in the other positions of the (A+n PC ) positions with the highest sequence reliability (different from the first PC placement manner), the sequence reliability of the positions where the A information bits are located will be lost, and the minimum row weight corresponding to the positions where the A information bits are located may be larger, smaller, or unchanged compared to the minimum row weight corresponding to the A positions with the highest sequence reliability in the first bit sequence. Regardless of how the n PC PC bits are placed, as long as the minimum row weight corresponding to the positions where the A information bits are located is unchanged or larger compared to the minimum row weight corresponding to the A positions with the highest sequence reliability in the first bit sequence, the n PC PC positions of the first bit sequence are considered to satisfy the first condition.

[0109] (2) The second condition is that the kth highest position number in the n PC position numbers corresponding to the n PC PC positions is greater than or equal to the kth highest position number in the n PC position numbers corresponding to the third position set, and the third position set indicates the n PC positions with the lowest sequence reliability in the (A+n PC ) positions with the highest sequence reliability.

[0110] It can be understood that the larger the position number of the PC bit is, the wider the checking range of the PC bit is. Therefore, the second condition can be understood as that the checking range corresponding to the n PC PC bits in the first bit sequence is not worse than the checking range corresponding to the n PC PC bits in the first PC placement manner.

[0111] For example, n PC = 3, and the position numbers of the 3 PC bits from small to large are {190, 216, 220} in the first PC placement manner. Then, as long as the 1st position number (the smallest position number) is not less than 190, the 2nd position number is not less than 216, and the 3rd position number (the largest position number) is not less than 220, the n PC PC positions of the first bit sequence are considered to satisfy the second condition.

[0112] It can be understood that for the first bit sequence with different K values and N values, there can be multiple PC placement manners that satisfy the above first condition and second condition. The following gives the PC placement manners that satisfy the first condition and the second condition based on the first PC placement manner and in combination with different examples.

[0113] Example 1: The number of payload bits K = 17, the number of CRC bits L = 6 (then A = 23), and the number of PC bits nPC = 3, the length of the first bit sequence N = 256. Then the first PC bit placement mode corresponding to this example is shown in Table 1. Table 1 includes 26 (i.e. A + n PC ) position numbers and the corresponding row weights of each position, the 26 position numbers indicate the 26 positions with the highest sequence reliability in the first bit sequence, and the sequence reliability decreases from right to left, i.e. the position numbered 256 has the highest sequence reliability, and the position numbered 190 has the lowest sequence reliability. The PC bits are placed in the three positions with the lowest sequence reliability in Table 1, and the CRC bits are placed in the positions with the largest position numbers in the remaining positions.

[0114] Table 1

[0115] In order to further improve the probability that the first decoding path in SCL decoding is the correct codeword, the three PC bits can be used to check as many payload bits as possible. In this embodiment, the PC bits are placed in the three positions with the largest position numbers in the first bit sequence, which can check all the payload bits and the CRC bits. Then the PC bit placement mode corresponding to this example is shown in Table 2.

[0116] Table 2

[0117] It can be seen that when the PC bits are placed in the positions with the largest position numbers, the payload bits and the CRC bits will be moved forward in turn, and the sequence reliability of the positions where the A information bits are located is lost. However, the minimum row weight corresponding to the position set composed of the positions where the payload bits and the CRC bits are located does not change compared with the minimum row weight corresponding to the position set composed of the positions where the payload bits and the CRC bits are located in Table 1, and the minimum row weight is still 32 (the row weight corresponding to the position numbered 249). Moreover, the position numbers corresponding to the three PC bits in Table 2 are greater than the position numbers corresponding to the three PC bits in Table 1. In summary, the three PC positions in Table 2 satisfy the first condition and the second condition, i.e. the PC placement mode shown in Table 2 is acceptable. It can be understood that although placing the PC bits in the positions with the lowest sequence reliability in Table 1 does not lose the sequence reliability of the payload bits and the CRC bits, when errors occur in the payload bits and the CRC bits, it is difficult to detect these errors through the PC bits, and these errors cannot be reflected in the PM, so the error decoding path cannot be moved backward, and the probability that the first decoding path is an error path is relatively larger. However, when errors occur in the 17 payload bits and the 6 CRC bits in Table 2, the three PC bits at the end of the first bit sequence can detect these errors, so that a penalty value is added to the PM value of the error decoding path, and the ranking of the error decoding path in the List paths is moved backward, thereby improving the probability that the first path is the correct codeword.

[0118] Based on example one, in a possible implementation, if the n PC PC bits are placed in the position with the largest position number in the position set #1 formed by the A+n PC positions with the highest sequence reliability in the first bit sequence, the minimum row weight corresponding to the position set #2 formed by the positions where the payload bits and the CRC bits (i.e., A information bits) are located is not reduced compared with the minimum row weight corresponding to the position set #3 formed by the positions where the A information bits are located in the first PC placement manner, the n PC PC bits can be placed in the position with the largest position number in the position set #1, so that the PC bits check the widest range (i.e., all the payload and CRC bits before the PC bits are checked).

[0119] Example two, the number of payload bits K=19, the number of CRC bits L=6 (then A=25), the number of PC bits n PC =3, and the length of the first bit sequence N=256. The first PC bit placement manner corresponding to this example is shown in Table 3. Table 3 includes 28 (i.e., A+n PC ) position numbers and the row weight corresponding to each position. The 28 position numbers indicate the 28 positions with the highest sequence reliability in the first bit sequence, and the sequence reliability decreases from right to left, i.e., the position numbered 256 has the highest sequence reliability, and the position numbered 243 has the lowest sequence reliability. The PC bits are placed in the three positions with the lowest sequence reliability in Table 3, and the CRC bits are placed in the position with the largest position number in the remaining positions.

[0120] Table 3

[0121] To further improve the probability that the first decoding path in SCL decoding is the correct codeword, the three PC bits need to check as many payload bits as possible. In this embodiment, the PC bits are placed in the three positions with the largest position numbers in the first bit sequence, which can check all the payload bits and the CRC bits. The PC bit placement manner corresponding to this example is shown in Table 4.

[0122] Table 4

[0123] It can be seen that the PC bits are placed in the position with the largest position number, the payload bits and the CRC bits are moved forward correspondingly, the sequence reliability of the positions where the payload bits and the CRC bits are located is lost, but the minimum row weight corresponding to the position set constituted by the positions where the payload bits and the CRC bits are located does not change compared with the minimum row weight corresponding to the position set constituted by the positions where the payload bits and the CRC bits are located in Table 3, and the position numbers corresponding to the three PC bits in Table 4 are greater than the position numbers corresponding to the three PC bits in Table 3, in summary, the three PC positions in Table 4 meet the first condition and the second condition, that is, the PC placement mode shown in Table 4 is acceptable.

[0124] Another possible PC placement mode is given based on the example, the sequence reliability of the positions where the payload bits and the CRC bits are located in the PC placement mode shown in Table 3 is the highest (that is, the sequence reliability is not lost at all), and at this time the minimum row weight corresponding to the positions where the payload bits and the CRC bits are located is 32, and there is only one position with a row weight of 32, if the PC bits are placed in the position with the minimum row weight, and the payload bits and the CRC bits are moved forward in turn, the minimum row weight corresponding to the payload bits and the CRC bits will be improved from 32 to 64, then the PC bit placement mode corresponding to the example is shown in Table 5.

[0125] Table 5

[0126] It can be seen that the sequence reliability of the positions where the payload bits and the CRC bits are located in Table 5 is lost, but the minimum row weight corresponding to the position set constituted by the positions where the payload bits and the CRC bits are located is increased, and the position numbers corresponding to the three PC bits in Table 4 are greater than the position numbers corresponding to the three PC bits in Table 3, in summary, the three PC positions in Table 5 meet the first condition and the second condition, that is, the PC placement mode shown in Table 4 is also acceptable.

[0127] As can be seen from the above, the PC placement modes shown in Table 4 and Table 5 are acceptable, but compared with the PC placement modes in Table 3 and Table 4, the PC placement mode shown in Table 5 improves the minimum row weight of the position set constituted by the positions where the payload bits and the CRC bits are located, becomes better compared with the original code spectrum, and improves the error correction capability of the code.

[0128] FIG. 8, FIG. 9 and FIG. 10 are schematic diagrams of code spectrum corresponding to Table 3, Table 4 and Table 5 respectively. In FIG. 8, FIG. 9 and FIG. 10, the horizontal axis is code weight, and the vertical axis is the number of codewords with corresponding code weight. In this example, the PC placement mode shown in Table 4 is improved relative to the PC placement mode shown in Table 3, although the minimum row weight of the positions where the A information bits are located is 32, the code spectrum shown in FIG. 9 is improved relative to the code spectrum shown in FIG. 8. In addition, the PC placement mode shown in Table 5 eliminates the positions where the row weight is equal to 32 in the position set where the A information bits are located, compared with Table 3, which is reflected in the code spectrum, and the code spectrum shown in FIG. 10 is better than the code spectrum shown in FIG. 8 and FIG. 9.

[0129] Example three, the number of payload bits K = 13, the number of CRC bits L = 6 (then A = 19), the number of PC bits n PC = 3, the length of the first bit sequence N = 128. Then the first PC bit placement mode corresponding to this example is shown in Table 6. Table 6 includes 22 (i.e. A + n PC ) position numbers and the row weight corresponding to each position. The 22 position numbers indicate the 22 positions with the highest sequence reliability in the first bit sequence, where the sequence reliability decreases from right to left, i.e. the position numbered 128 has the highest sequence reliability, and the position numbered 121 has the lowest sequence reliability. The PC bits are placed in the 3 positions with the lowest sequence reliability in Table 6, and the CRC bits are placed in the position with the largest position number in the remaining positions.

[0130] Table 6

[0131] Similarly, in order to further improve the probability that the first decoding path in SCL decoding is the correct codeword, it is necessary to let the 3 PC bits check as many payload bits as possible. In this embodiment, placing the PC bits in the 3 positions with the largest position number in the first bit sequence can check all the payload bits and CRC bits, and the PC bit placement mode corresponding to this example is shown in Table 7.

[0132] Table 7

[0133] As can be seen, the minimum row weight corresponding to the position set composed of the positions where the payload bits and CRC bits (i.e. A information bits) are located in Table 6 is 32, and the minimum row weight corresponding to the position set composed of the positions where the payload bits and CRC bits are located in Table 7 is 16. The minimum row weight is reduced, and the first condition is not met, so the PC placement mode shown in Table 7 is unacceptable.

[0134] Based on example three, in a possible implementation, if n PC PC bits are placed in the A + n PCWhen the position with the largest position number in the position set #1 composed of the positions where the A information bits are located is the position with the largest position number in the position set #3 composed of the positions where the A information bits are located in the first PC placement manner, the minimum row weight corresponding to the position set #2 composed of the positions where the A information bits are located is smaller than the minimum row weight corresponding to the position set #3 composed of the positions where the A information bits are located in the first PC placement manner, the n PC PC bits (i.e., the placement manner shown in Table 6) is placed based on the first PC placement manner.

[0135] Based on Example Two, there can be multiple PC placement manners that satisfy the first condition and the second condition. Based on Example Three, blindly expanding the check range of the PC bits can cause the native code spectrum to deteriorate. Therefore, in order to improve the native code spectrum as much as possible when there is no PC bit, and to make the check range of the PC bits as wide as possible, a compromise between the check range and the row weight needs to be made to determine the PC position. The following gives several specific implementation manners of determining the PC position.

[0136] The implementation manner one can include the following steps.

[0137] a) determining a first position set, the first position set including an i-th candidate position in the second position set and the third position set of the i-th round, 1≤i≤n PC -1.

[0138] Wherein, the n PC positions in the third position set are sequentially determined as a candidate position to determine a PC position according to the sequence reliability from high to low.

[0139] It can be understood that the i-th candidate position is a position with the i-th highest sequence reliability in the n PC positions. Specifically, the first candidate position is the position with the highest sequence reliability in the third position set, the second candidate position is the position with the second highest sequence reliability in the third position set, and so on. Here, no further description is given.

[0140] It can also be understood that a total of n PC PC positions need to be determined. When determining the first PC position, the second position set of the first round indicates the A positions with the highest sequence reliability in the first bit sequence and the first candidate position in the third position set.

[0141] b) determining the i-th PC position based on the row weight corresponding to the i-th candidate position and the minimum row weight corresponding to the second position set of the i-th round.

[0142] If the row weight corresponding to the i-th candidate position is smaller than the minimum row weight corresponding to the second position set, the i-th candidate position is taken as the i-th PC position.

[0143] If the row weight corresponding to the i-th candidate position is greater than or equal to the minimum row weight corresponding to the second position set, the position with the largest position number or the highest sequence reliability in the fourth position set is taken as the i-th PC position, and the fourth position set S4 includes all positions in the first position set of the i-th round with the row weight equal to the minimum row weight of the second position set S2 of the i-th round.

[0144] It can be understood that based on step b), one PC position (i.e., the i-th PC position) can be determined in the first position set. Then, the first position set and the second position set of the i-th round need to be updated to obtain the first position set and the second position set required for the i+1-th round, so as to determine the next PC position (i.e., the i+1-th PC position). The following continues to be described.

[0145] c) updating the second position set of the i-th round to obtain the second position set of the i+1-th round. The second position set of the i+1-th round is the position set corresponding to the i-th PC position after the i-th PC position is deleted from the first position set of the i-th round.

[0146] It can be understood that the number of positions corresponding to the second position set used in each round of iteration is A.

[0147] d) updating the first position set of the i-th round to obtain the first position set of the i+1-th round. The first position set of the i+1-th round includes the i+1-th candidate position in the second position set of the i+1-th round and the third position set.

[0148] It can be understood that the number of positions corresponding to the first position set used in each round of iteration is A+1.

[0149] e) determining the i+1-th PC position based on the row weight corresponding to the i+1-th candidate position and the minimum row weight corresponding to the second position set of the i+1-th round.

[0150] If the row weight corresponding to the i+1-th candidate position is less than the minimum row weight corresponding to the second position set of the i+1-th round, the i+1-th candidate position is taken as the i+1-th PC position.

[0151] If the row weight corresponding to the i+1-th candidate position is greater than or equal to the minimum row weight corresponding to the second position set of the i+1-th round, the position with the largest position number or the highest sequence reliability in the fifth position set is taken as the i+1-th PC position, and the fifth position set includes all positions in the first position set of the i+1-th round with the row weight equal to the minimum row weight of the second position set S2 of the i+1-th round.

[0152] f) repeating the operations in c) to e) to update the first position set and the second position set required for the next round until n PC PC positions are determined.

[0153] For the convenience of understanding, the following takes n PC = 3 as an example to describe the first implementation.

[0154] (1) The first PC position in the three PC positions is determined based on the minimum row weight corresponding to the second position set of the first round and the row weight corresponding to the first candidate position, and the first PC position is the first determined PC position in the three PC positions.

[0155] The first candidate position is the position with the highest sequence reliability in the third position set, and the second position set of the first round includes A positions with the highest sequence reliability in the first bit sequence.

[0156] If the row weight corresponding to the first candidate position is less than the minimum row weight corresponding to the second position set of the first round, the first candidate position is taken as the first PC position; if the row weight corresponding to the first candidate position is greater than or equal to the minimum row weight corresponding to the second position set of the first round, the position with the largest position number or the highest sequence reliability in the fourth position set is taken as the first PC position, the fourth position set includes all positions in the first position set of the first round with the row weight equal to the minimum row weight of the second position set of the first round, and the first position set of the first round includes the second position set of the first round and the first candidate position.

[0157] (2) The second PC position in the three PC positions is determined based on the minimum row weight corresponding to the second position set of the second round and the row weight corresponding to the second candidate position, and the second PC position is the second determined PC position in the three PC positions.

[0158] The second candidate position is the position with the second highest sequence reliability in the third position set, and the second position set of the second round is the position set corresponding to the first PC position after deleting the first position set of the first round.

[0159] If the row weight corresponding to the second candidate position is less than the minimum row weight corresponding to the second position set of the second round, the second candidate position is taken as the second PC position; if the row weight corresponding to the second candidate position is greater than or equal to the minimum row weight corresponding to the second position set of the second round, the position with the largest position number or the highest sequence reliability in the fifth position set is taken as the second PC position, the fifth position set includes all positions in the first position set of the second round with the row weight equal to the minimum row weight of the second position set of the second round, and the first position set of the second round includes the second position set of the second round and the second candidate position.

[0160] (3) The third PC position in the three PC positions is determined based on the minimum row weight corresponding to the second position set of the third round and the row weight corresponding to the third candidate position, and the third PC position is the third determined PC position in the three PC positions.

[0161] The third candidate position is a position with the lowest sequence reliability in the third position set, and the second position set in the third round is a position set corresponding to the first position set in the second round after the second PC position is deleted.

[0162] If the row weight corresponding to the third candidate position is less than the minimum row weight corresponding to the second position set in the third round, the third candidate position is taken as the third PC position. If the row weight corresponding to the third candidate position is greater than or equal to the minimum row weight corresponding to the second position set in the third round, a position with the largest position number or the highest sequence reliability in the sixth position set is taken as the third PC position. The sixth position set includes all positions in the first position set in the third round with the row weight equal to the minimum row weight of the second position set in the third round, and the first position set in the third round includes the second position set in the third round and the third candidate position.

[0163] The pseudo code corresponding to the first implementation when n PC = 3 is given below.

[0164] / / used to indicate an added position (i.e., to indicate a candidate PC position in the third position set), initialize the value, which is equivalent to i in the first implementation

[0165] n PC = 3; / / initialize the total number of target PC bits

[0166] S = []; / / initialize the PC position set S

[0167] According to the NR sequence reliability sequence and the rate matching puncturing mode, the sequence reliability of each position is determined. The sequence B is a sequence with a length of N, and the N elements in the sequence B are N position numbers, each position number indicating a position. The positions indicated by the N elements are sorted in ascending order of sequence reliability, i.e., the sequence reliability of the position corresponding to the first element is the lowest, and the sequence reliability of the position corresponding to the last element is the highest.

[0168] weights is a sequence with a length of N, recording the corresponding row weight of each position in the N positions.

[0169] while length(S) < n PC / / if the number of elements in the PC position set is less than 3

[0170] / / get the set S1 (i.e. the first position set) which is composed of the current set S2 (i.e. the second position set) and the new position (i.e. a candidate PC position in the third position set), end indicates the number of the last position in the sequence B, the last position in the sequence B is the position with the highest reliability, end equals to N, A is the number of information bits

[0171] S1_weights = weights (S1) ; / / get the row weight of all positions in S1

[0172] w_min_new = S1_weights (1) ; / / get the row weight of the new position

[0173] S2_weights = weights (S2) ; / / get the row weight of set S2

[0174] w_min = min (S2_weights) ; / / get the minimum row weight of set S2

[0175] Implementation mode two

[0176] Implementation mode two can be regarded as replacing the maximum position number criterion in implementation mode one with the highest sequence reliability criterion. Specifically, the difference between implementation mode two and implementation mode one is in steps b) and e). In step b) of implementation mode two, if the row weight of the i-th candidate position is greater than or equal to the minimum row weight of the second position set, the first position in the second position set is taken as the i-th PC position, and the first position is the position with the highest sequence reliability in the position with the minimum row weight in the second position set. Similarly, in step e), if the row weight of the i+1-th candidate position is greater than or equal to the minimum row weight of the updated second position set, the first position in the updated second position set is taken as the i+1-th PC position, and the first position is the position with the highest sequence reliability in the position with the minimum row weight in the updated second position set.

[0177] The pseudo code corresponding to implementation mode two is given below.

[0178] / / used to indicate a new position (i.e. to indicate a candidate PC position in the third position set), initialize the value, which is equivalent to i in implementation mode one

[0179] n PC = 3; / / initialize the total number of target PC bits

[0180] S = [] ; / / initialize the PC position set S

[0181] while length (S) < nPC / / if the number of elements in the PC position set is less than 3

[0182] / / get the set S1 (i.e. the first position set) composed of the current set S2 (i.e. the second position set) and the new position (i.e. a candidate PC position in the third position set), end indicates the number of the last position in the sequence B, the last position in the sequence B is the position with the highest reliability, end equals N, A is the number of information bits

[0183] S1_weights = weights (S1) ; / / get the row weight of all positions in S1

[0184] w_min_new = S1_weights (1) ; / / get the row weight corresponding to the new position

[0185] S2_weights = weights (S2) ; / / get the row weight of set S2

[0186] w_min = min (S2_weights) ; / / get the minimum row weight corresponding to set S2

[0187] Implementation Mode Three

[0188] The difference between implementation mode three and implementation mode one is in steps b) and e). As can be seen, in implementation mode one, when the row weight corresponding to the candidate position in steps b) and e) is greater than or equal to the minimum row weight corresponding to the second position set, the corresponding operation is the same, and the position with the largest position number in the second position set is required as the PC position. Therefore, in implementation mode three, it can be further subdivided. If it is equal, the first position is the position with the largest position number in the second position set, and if it is greater, the first position is the position with the highest sequence reliability in the second position set.

[0189] The pseudo code corresponding to implementation mode three is given below.

[0190] / / used to indicate a new position (i.e. to indicate a candidate PC position in the third position set), initialize the value, which is equivalent to i in implementation mode one

[0191] n PC = 3; / / initialize the total number of target PC bits

[0192] S = [] ; / / initialize the PC position set S

[0193] while length (S) < n PC / / If the number of elements in the PC position set is less than 3

[0194] / / Get the set S1 (i.e., the first position set) composed of the current set S2 (i.e., the second position set) and the newly added position (i.e., a candidate PC position in the third position set), end indicates the number of the last position in sequence B, the last position in sequence B is the position with the highest reliability, end is equal to N, and A is the number of information bits

[0195] S1_weights = weights(S1); / / Get the row weight of all positions in S1

[0196] w_min_new = S1_weights(1); / / Get the row weight corresponding to the newly added position

[0197] S2_weights = weights(S2); / / Get the row weight of set S2

[0198] w_min = min(S2_weights); / / Get the minimum row weight corresponding to set S2

[0199] Implementation Method Four

[0200] The difference between implementation method four and implementation method one is in steps b) and e). As can be seen, in implementation method one, when the row weight corresponding to the candidate position in steps b) and e) is greater than or equal to the minimum row weight corresponding to the second position set, the corresponding operation is the same, and the position with the largest position number in the second position set is required as the PC position. Therefore, in implementation method four, it can be further subdivided. If it is greater than, the first position is the position with the largest position number in the second position set. If it is equal to, the first position is the position with the highest sequence reliability in the second position set.

[0201] The pseudo code corresponding to implementation method four is given below.

[0202] / / Used to indicate a newly added position (i.e., to indicate a candidate PC position in the third position set), initialize the value, which is equivalent to i in implementation method one

[0203] n PC = 3; / / Initialize the total number of target PC bits

[0204] S = []; / / Initialize the PC position set S

[0205] while length(S) < n PC / / If the number of elements in the PC position set is less than 3

[0206] / / get the set S1 (i.e. the first position set) which is composed of the current set S2 (i.e. the second position set) and the new position (i.e. a candidate PC position in the third position set), end indicates the number of the last position of the sequence B, the last position of the sequence B is the position with the highest reliability, end equals to N, A is the number of information bits

[0207] S1_weights = weights (S1) ; / / get the row weight of all positions in S1

[0208] w_min_new = S1_weights (1) ; / / get the row weight of the new position

[0209] S2_weights = weights (S2) ; / / get the row weight of the set S2

[0210] w_min = min (S2_weights) ; / / get the minimum row weight of the set S2

[0211] The above implementation mode one to implementation mode four can be regarded as the implementation mode of serial determination of PC position, and the following two parallel determination modes of PC position are given.

[0212] Implementation mode five, the implementation mode includes the following steps.

[0213] a) determine the first position set, the first position set includes the second position set and the third position set.

[0214] Wherein, the second position set indicates A positions with the highest sequence reliability in the first bit sequence, and the third position set indicates n positions with the lowest sequence reliability in the (A+n) positions with the highest sequence reliability. PC ) positions with the highest sequence reliability in the first bit sequence. PC ) positions with the highest sequence reliability in the first bit sequence. PC

[0215] b) determine n PC positions based on the row weight corresponding to each position in the third position set and the minimum row weight corresponding to the second position set. PC

[0216] If the row weight corresponding to m1 positions in the third position set is less than the minimum row weight corresponding to the second position set, the m1 positions are taken as PC positions, 1≤m1≤n PC .

[0217] ​​If the row weight corresponding to the m2 positions in the third position set is greater than or equal to the minimum row weight corresponding to the second position set, the m2 positions with the largest position number or the m2 positions with the highest sequence reliability in the fourth position set are PC positions, the fourth position set including all positions in the first position set with the row weight equal to the minimum row weight of the second position set, wherein m1+m2=n PC .

[0218] Implementation six includes the following steps.

[0219] a) determining a first position set, the first position set including a second position set and a third position set.

[0220] The second position set and the third position set are described in the fifth implementation, which will not be repeated here.

[0221] b) determining n PC positions based on the row weight corresponding to each position in the third position set and the minimum row weight corresponding to the second position set. PC

[0222] If the row weight corresponding to the i-th position in the third position set is less than the minimum row weight corresponding to the second position set, the i-th position is a PC position, 1≤i≤n PC .

[0223] If the row weight corresponding to the i-th position in the third position set is greater than or equal to the minimum row weight corresponding to the second position set, the position with the largest position number or the position with the highest sequence reliability in the fifth position set is a PC position, wherein the fifth position set is the remaining positions in the fourth position set excluding the PC positions that have been determined, and the fourth position set includes all positions in the first position set with the row weight equal to the minimum row weight of the second position set.

[0224] The above describes in detail the placement of PC bits. After determining n PC positions, A information bits are placed in the remaining A positions in the first bit sequence excluding the n PC positions with the highest sequence reliability (A+n PC PC positions. PC In addition, the values of the PC bits in the n PC positions are determined based on the PC check relationship corresponding to the n PC positions, so as to obtain the first bit sequence to be encoded. PC PC PC

[0225] S730, the sending end device performs Polar encoding on the first bit sequence to output a codeword sequence.

[0226] The Polar encoding process is described in FIG. 3, which will not be repeated here. ​​​​

[0227] S740, the sending device determines a symbol sequence based on the codeword sequence.

[0228] It can be understood that the symbol sequence can be a sequence after rate matching and modulation. For example, the sending device performs rate matching on the codeword sequence, then modulates the sequence after rate matching to obtain a symbol sequence, and maps the modulated symbol sequence to a physical resource for transmission.

[0229] For example, the modulation mode can be QPSK (quaternary phase shift keying), and the obtained QPSK symbol (i.e., codeword sequence #2) after modulation is mapped to a physical resource for transmission. For example, the sending device modulates the codeword sequence after rate matching, modulates bit 0 in the codeword sequence after rate matching to 1, and modulates bit 1 to -1 to obtain a symbol sequence to be sent. For example, the sequence before modulation is {1, 0, 0, 1, 1, 0}, and the sequence after modulation is symbol sequence #1 {-1, 1, 1, -1, -1, 1}.

[0230] S750, the sending device sends the symbol sequence to the receiving device. Correspondingly, the receiving device receives the symbol sequence from the sending device.

[0231] It can be understood that the symbol sequence #1 output or sent by the sending device and the symbol sequence #2 received by the receiving device can be different due to the introduction of channel noise signals in the transmission process of the symbol sequence.

[0232] S760, the receiving device performs PC-SCL decoding on the symbol sequence to obtain a first bit sequence.

[0233] It can be understood that the PC position obtained by the receiving device is the same as the PC position obtained by the sending device, and the application does not specifically limit how the receiving device and the sending device obtain the PC position. For example, the receiving device and the sending device can determine the PC position by themselves based on the same criteria. The receiving device knows A information bit positions, n PC PC positions and the position range corresponding to the frozen bit position. The A information bit positions and the n PC PC positions are the (A+n PC ) positions with the highest sequence reliability in the first bit sequence. In addition, the frozen bit position is the remaining N-A-n PC position in the first bit sequence.

[0234] It can also be understood that the PC-SCL decoding algorithm does not use CRC test decoding paths, and the path criterion PM of the SCL decoding is corrected by the PC bit, so as to improve the probability that the correct decoding path is ranked first.

[0235] It can also be understood that in the PC-SCL decoding algorithm, only the 8 decoding paths with the minimum PM are saved as candidate decoding paths each time decoding is performed (i.e., decoding is performed on one bit), and then the bit at the i-th PC position needs to be decoded, and the corresponding decoding process includes the following steps.

[0236] a) Obtain the LLRs corresponding to the N positions of the first bit sequence based on the symbol sequence #2.

[0237] For example, the symbol sequence #1 sent by the sending end is {-1, 1, 1, -1, -1, 1}, and the receiving end demodulates the symbol sequence #2 to obtain the LLRs corresponding to the positions where A information bits and n PC bits are placed in the first bit sequence, such as {-0.8, 1.1, 0.9, -0.9, -1.2, 0.6}. PC

[0238] b) Obtain the S decoding paths with the minimum PM before the i-th PC position (S = 8 is taken as an example below), and the i-th PC position is any position in the n PC positions of the first bit sequence. PC

[0239] It can be understood that the positions before the i-th PC position in the first bit sequence place payload bits and CRC bits, and two decoding results correspond to the positions. For example, if the number of positions before the i-th PC position in the first bit sequence that place payload bits and CRC bits is 4, there will be 2 4 = 16 decoding paths, and the 8 decoding paths here are the 8 paths with the minimum PM among the 16 decoding paths.

[0240] It can also be understood that the PM of each decoding path is determined based on the LLRs corresponding to all (i-1) positions before the i-th PC position.

[0241] c) Determine whether to increase the penalty of the current path based on the first value of the i-th PC position corresponding to the decoding path #1 and the second value of the i-th PC position. The decoding path #1 is any one of the current 8 decoding paths, the first value is determined based on the decoding result corresponding to the decoding path #1 and the PC check relationship corresponding to the i-th PC position, and the second value is the hard decision result of the LLR corresponding to the i-th PC position.

[0242] If the first value of the i-th PC position corresponding to the decoding path #1 is different from the second value of the i-th PC position, the PM value of the decoding path #1 is increased, i.e., a value is added to the current PM to obtain a new PM.

[0243] ​​If the first value of the i-th PC position corresponding to the decoding path #1 is the same as the second value of the i-th PC position, the PM value of the decoding path #1 is kept unchanged, the PM value of the decoding path #1 is kept unchanged.

[0244] It can be understood that, in the present application, when the PM value of the decoding path is calculated, the decoding path with smaller PM is more likely to be the correct codeword, thus, the penalty added to the decoding path can be realized by increasing the PM value of the decoding path.

[0245] In another implementation, if, when the PM value of the decoding path is calculated, the decoding path with larger PM is more likely to be the correct codeword, the S decoding paths with the largest PM are selected in each round of decoding, the penalty added to the decoding path can also be realized by reducing the PM value of the decoding path, i.e., a numerical value can be subtracted from the PM of the current decoding path.

[0246] d) Based on the LLR corresponding to the positions after the i-th PC position in the first bit sequence and the above-mentioned 8 decoding paths, the decoding is continued until the final 8 decoding paths with the smallest PM are obtained.

[0247] e) The first bit sequence is determined, the first bit sequence is the decoding result corresponding to the decoding path with the smallest PM in the above-mentioned final 8 decoding paths with the smallest PM.

[0248] It can be understood that, in the above-mentioned drawings, each step is only an exemplary description, and is not strictly limited. In addition, the size of the serial number of each process does not mean the order of execution, the execution order of each process should be determined according to its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0249] It can also be understood that some optional features in each embodiment of the present application can not depend on other features in some scenarios, or can be combined with other features in some scenarios, without limitation.

[0250] It can also be understood that, in each of the above-mentioned method embodiments, the method and operation realized by the device (the sending end device or the receiving end device) can also be realized by the component parts (such as chips or circuits) of the device, without limitation.

[0251] The method embodiments provided by the present application are described in detail above in combination with FIG. 1 to FIG. 10. The apparatus embodiments of the present application will be described below in combination with FIG. 11 and FIG. 12. It can be understood that, in order to implement the functions in the above embodiments, the apparatus in FIG. 11 and FIG. 12 comprises corresponding hardware structure and / or software module for performing each function. Those skilled in the art should easily realize that, in combination with the units and method steps of each example described in the embodiments disclosed in the present application, the present application can be implemented in the form of hardware or a combination of hardware and computer software. It can be understood that the technical features described in the above method embodiments are also applicable to the following apparatus embodiments.

[0252] FIG. 11 and FIG. 12 are structural schematic diagrams of possible apparatuses provided by the embodiments of the present application. The apparatuses can be used to implement the functions of the sending end device or the receiving end device in the above method embodiments, and thus can also achieve the beneficial effects possessed by the above method embodiments.

[0253] FIG. 11 is a schematic block diagram of a communication apparatus 1000 provided by the embodiments of the present application. As shown in FIG. 11, the apparatus 1000 can comprise a communication unit 1010 and a processing unit 1020. The communication unit 1010 can communicate with the outside, and the processing unit 1020 is configured to perform data processing. The communication unit 1010 can also be referred to as a communication interface or a transceiver unit.

[0254] In a possible design, the apparatus 1000 can implement the steps or procedures corresponding to those performed by the sending end device in the above method embodiments, wherein the processing unit 1020 is configured to perform processing-related operations of the sending end device in the above method embodiments, and the communication unit 1010 is configured to perform sending-related operations of the sending end device in the above method embodiments.

[0255] In another possible design, the apparatus 1000 can implement the steps or procedures corresponding to those performed by the receiving end device in the above method embodiments, wherein the communication unit 1010 is configured to perform receiving-related operations of the receiving end device in the above method embodiments, and the processing unit 1020 is configured to perform processing-related operations of the receiving end device in the above method embodiments.

[0256] It should be appreciated that the apparatus 1000 herein is embodied in the form of functional units. The term "unit" herein can refer to an application specific integrated circuit (ASIC), an electronic circuit, a processor (for example, a shared processor, a dedicated processor, or a group processor, etc.) and a memory for executing one or more software or firmware programs, a combination of logic circuitry and / or other suitable components that support the described functions. In an optional example, those skilled in the art can understand that the apparatus 1000 can be embodied in the form of the sending device in the above-described embodiments, and can be used to execute the respective processes and / or steps corresponding to the sending device in the above-described method embodiments, or the apparatus 1000 can be embodied in the form of the receiving device in the above-described embodiments, and can be used to execute the respective processes and / or steps corresponding to the receiving device in the above-described method embodiments. To avoid repetition, details are not described herein.

[0257] The apparatus 1000 in each of the above-described schemes has a function of implementing the respective steps performed by the sending device in the above-described methods, or the apparatus 1000 in each of the above-described schemes has a function of implementing the respective steps performed by the receiving device in the above-described methods. The function can be implemented by hardware or by executing corresponding software by hardware. The hardware or software includes one or more modules corresponding to the above-described functions; for example, the communication unit can be replaced by a transceiver (for example, the sending unit in the communication unit can be replaced by a transmitter, and the receiving unit in the communication unit can be replaced by a receiver), and other units, such as the processing unit, can be replaced by a processor, which respectively performs the transceiving operations and related processing operations in each of the method embodiments.

[0258] In addition, the communication unit can also be a transceiving circuit (for example, can include a receiving circuit and a sending circuit), and the processing unit can be a processing circuit. In the embodiments of the present application, the apparatus in FIG. 11 can be the receiving device or the sending device in the above-described embodiments, or can be a chip or a chip system, for example, a system on chip (SoC). The communication unit can be an input / output circuit, a communication interface; and the processing unit can be a processor or a microprocessor integrated on the chip or an integrated circuit. Details are not limited herein.

[0259] FIG. 12 is a schematic block diagram of a communication apparatus 1100 provided by the embodiments of the present application. The apparatus 1100 includes a processor 1110 and a transceiver 1120. The processor 1110 and the transceiver 1120 communicate with each other through an internal connection path. The processor 1110 is configured to execute instructions to control the transceiver 1120 to send and / or receive signals.

[0260] Optionally, the apparatus 1100 further includes a memory 1130, which is in communication with the processor 1110 and the transceiver 1120 via the internal connection path. The memory 1130 is used to store instructions, which the processor 1110 can execute. In one possible implementation, the apparatus 1100 is configured to implement the procedures and steps corresponding to the transmitting end device in the above-described method embodiments. In another possible implementation, the apparatus 1100 is configured to implement the procedures and steps corresponding to the receiving end device in the above-described method embodiments.

[0261] Optionally, the memory 1130 can be integrated in the processor 1110.

[0262] In one possible scenario, the apparatus 1100 includes at least one processor integrated with a memory, and other memory in addition to the memory integrated in the processor.

[0263] It can be understood that the apparatus 1100 can be specifically the transmitting end device or the receiving end device in the above-described embodiments, or a chip or chip system. Correspondingly, the transceiver 1120 can be a transceiver circuit of the chip, which is not limited here. Specifically, the apparatus 1100 can be configured to execute the procedures and steps corresponding to the transmitting end device or the receiving end device in the above-described method embodiments.

[0264] Optionally, the memory 1130 can include a read-only memory and a random access memory, and provide instructions and data for the processor. The memory can include a non-volatile random access memory. For example, the memory can also store device type information. The processor 1110 can be configured to execute the instructions stored in the memory, and when the processor 1110 executes the instructions stored in the memory, the processor 1110 is configured to execute the procedures and steps of the above-described method embodiments corresponding to the transmitting end device or the receiving end device.

[0265] In the implementation process, the procedures of the above-described method can be completed by the integrated logic circuit of the hardware in the processor or the instructions in the form of software. The procedures of the method disclosed in the embodiments of the present application can be directly embodied as being completed by a hardware processor, or completed by a combination of hardware and software modules in the processor. The software modules can be located in the random access memory, the flash memory, the read-only memory, the programmable read-only memory, the electrically erasable programmable memory, the register, or other mature storage media in the field. The storage medium is located in the memory, and the processor reads the information in the memory and combines the hardware to complete the procedures of the above-described method. To avoid repetition, it will not be described in detail here.

[0266] It should be noted that the processor in the embodiments of the present application can be an integrated circuit chip with a signal processing capability. In the implementation process, the steps of the above method embodiments can be completed by the integrated logic circuit or the instruction in the form of software in the processor. The processor mentioned above can be a general processor, a digital signal processing (DSP), an ASIC, a field-programmable gate array (FPGA) or other programmable logic devices, a discrete gate or transistor logic device, a discrete hardware component. The processor in the embodiments of the present application can realize or execute the methods, steps and logic block diagrams disclosed in the embodiments of the present application. The general processor can be a microprocessor or the processor can also be any conventional processor and the like. The steps of the method disclosed in conjunction with the embodiments of the present application can be directly embodied as a hardware code processor for execution, or be executed by a combination of hardware and software modules in the code processor. The software module can be located in a random memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register or other mature storage medium in the art. The storage medium is located in the memory, and the processor reads the information in the memory, and combines the hardware to complete the steps of the above method.

[0267] It is to be appreciated that the memory in the embodiments of the application can be a volatile memory or a nonvolatile memory, or can include both volatile and nonvolatile memory. Where the nonvolatile memory is, for example, read-only memory (ROM), programmable ROM (PROM), erasable PROM (EPROM), electrically EPROM (EEPROM), or flash memory. The volatile memory, which can be used as external cache, can be, for example, random access memory (RAM), static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), or direct rambus RAM (DR RAM). It is to be appreciated that the memory described herein is intended to include, among other things, these and any other memory suitable for storing or providing program code or instructions to a processor or other system.

[0268] Optionally, the memory (e.g., 1130) in the embodiments of the application can be integrated in the processor (e.g., 1110).

[0269] In addition, the application also provides a computer readable storage medium, the computer readable storage medium stores computer instructions, when the computer instructions run on the computer, the operations and / or processes performed by the sending end device or the receiving end device in the method embodiments of the application are executed.

[0270] The application also provides a computer program product, the computer program product includes computer program code or instructions, when the computer program code or instructions run on the computer, the operations and / or processes performed by the sending end device or the receiving end device in the method embodiments of the application are executed.

[0271] Further, the application provides a chip including a processor. A memory for storing a computer program is arranged independently of the chip, and the processor is configured to execute the computer program stored in the memory, so that the operations and / or processes performed by the sending device or the receiving device in any one of the method embodiments are performed.

[0272] Further, the chip can further include a communication interface. The communication interface can be an input / output interface, an interface circuit, or the like. Further, the chip can further include a memory.

[0273] Further, the application provides a communication system including the sending device and the receiving device in the embodiments of the application.

[0274] It should be further noted that the memory described herein is intended to include, but not limited to, these and any other suitable types of memory.

[0275] Those skilled in the art can appreciate that the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether the functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the application. Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described system, device and unit can refer to the corresponding processes in the foregoing method embodiments, which will not be described here. In several embodiments provided in the application, it should be understood that the disclosed system, device and method can be implemented in other ways. For example, the above-described device embodiments are only schematic, for example, the division of the units is only a logical function division, and actual implementation can have another division manner, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be indirect coupling or communication connection through some interface, device or unit, which can be electrical, mechanical or other form. The units described as separate components can be or can not be physically separate, and the components shown as units can be or can not be physical units, i.e. they can be located in one place, or can be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the embodiment. In addition, the functional units in each embodiment of the application can be integrated in one processing unit, or each unit can be physically present, or two or more units can be integrated in one unit.

[0276] If the functions are implemented in the form of software function units and sold or used as independent products, they can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application or the parts of the present application that essentially contribute to the prior art or the parts of the technical solutions of the present application can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the embodiments of the present application. The aforementioned storage medium includes various media that can store program codes, such as a U disk, a mobile hard disk, a ROM, a RAM, a magnetic disk, or an optical disk.

[0277] It can be understood that the "embodiments" mentioned throughout the specification mean that the specific features, structures or characteristics related to the embodiments are included in at least one embodiment of the present application. Therefore, the various embodiments throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner.

[0278] It can also be understood that in the present application, "when", "if" and "when" all refer to the case that the network element will make corresponding processing under certain objective circumstances, not the time limit, and it is not required that the network element must have a judgment action when it is implemented, nor does it mean that there are other limitations.

[0279] It can also be understood that in the embodiments of the present application, "A corresponding B" means that B is associated with A, and B can be determined according to A. However, it can also be understood that determining B according to A does not mean that B is determined only according to A, but B can also be determined according to A and / or other information.

Claims

1. A communication method characterized by comprising: The first condition is that minimum row weights corresponding to A positions where the A information bits are located are not less than minimum row weights corresponding to A positions with highest sequence reliability in the first bit sequence, where each position corresponds to a row weight. obtaining A information bits and a number n of parity check PC bits PC , the A information bits including K payload bits and L cyclic redundancy check CRC bits, the K, the L and the n PC are positive integers; generating a first bit sequence, the first bit sequence comprising N bits, the N bits comprising A information bits and n PC PC bits, the A information bits and the n PC PC bits being located at (A+n PC ) positions of the first bit sequence with highest sequence reliability, wherein the N is 2 raised to the power of n, the n is a positive integer, n PC PC positions where the n PC PC bits are located satisfy a first condition and a second condition, perform polar encoding on the first bit sequence to obtain a code word sequence; The second condition is that the n PC th highest position number in the n PC position numbers corresponding to the PC positions is greater than or equal to the kth highest position number in n PC position numbers corresponding to a third position set S3, the third position set S3 including n PC positions with the lowest sequence reliability among the (A+n PC ) positions with the highest sequence reliability, and 1≤k≤n PC ; output the code word sequence. The first condition is that minimum row weights corresponding to A positions where the A information bits are located are not less than minimum row weights corresponding to A positions with highest sequence reliability in the first bit sequence, where each position corresponds to a row weight.

2. A communication method characterized by comprising: If the first value of the ith PC position corresponding to the first decoding path is different from the second value of the ith PC position, the PM of the first decoding path is increased, where the first value is determined based on a decoding result corresponding to the first decoding path and a PC check relationship corresponding to the ith PC position, and the second value is a hard decision result of the LLR corresponding to the ith PC position. If the first value of the ith PC position corresponding to the first decoding path is the same as the second value of the ith PC position, the PM value of the first decoding path is kept unchanged. Based on the symbol sequence, determine the log-likelihood ratio (LLR) corresponding to N positions of the first bit sequence, where the first bit sequence includes A information bits and n... PC The A information bits include K payload bits and L cyclic redundancy check (CRC) bits. The A information bits and the n... PC The PC bits are located in the first bit sequence with the highest sequence reliability (A+n). PC At positions ), where N is 2 to the power of n, and K, L, and n PC All are positive integers, where n is placed. PC n PC bits PC The PC locations satisfy both the first and second conditions. The S decoding paths continue to be decoded based on the LLR of the positions after the ith PC position until the S decoding paths with the minimum PM are obtained. The second condition is that the n PC th highest position number in the n PC position numbers corresponding to the PC positions is greater than or equal to the kth highest position number in n PC position numbers corresponding to a third position set S3, the third position set S3 indicating n PC positions with the lowest sequence reliability in the (A+n PC ) positions with the highest sequence reliability, 1≤k≤n PC ; S decoding paths with the minimum path metric value PM corresponding to the position before the ith PC position, wherein the ith PC position is any one of n PC positions, and the PM of the S decoding paths is determined based on the LLR corresponding to the position before the ith PC position. PC S decoding paths with the minimum path metric value PM corresponding to the position before the ith PC position, wherein the ith PC position is any one of n PC positions, and the PM of the S decoding paths is determined based on the LLR corresponding to the position before the ith PC position. The first bit sequence is obtained, and the first bit sequence is a decoding result corresponding to the decoding path with the minimum PM in the S decoding paths with the minimum PM. The first candidate position is a position with the highest sequence reliability in the third position set S3, and the second position set S2 includes A positions with the highest sequence reliability in the first bit sequence, If the row weight corresponding to the first candidate position is less than the minimum row weight corresponding to the second position set S2, the first candidate position is taken as the first PC position. If the row weight corresponding to the first candidate position is greater than or equal to the minimum row weight corresponding to the second position set S2, a position with the maximum position number or the highest sequence reliability in the fourth position set S4 is taken as the first PC position, the fourth position set S4 includes positions with the minimum row weight equal to the minimum row weight of the second position set S2 in the first position set S1, and the first position set S1 includes the second position set S2 and the first candidate position.

3. The method according to claim 1 or 2, characterized in that, n PC = 3, The n PC The first PC position among the n PC PC positions is determined based on the minimum row weight corresponding to the second position set S2 and the row weight corresponding to the first candidate position, and the first PC position is the first determined PC position among the n 4. The method of claim 3, wherein the second candidate position is a position with the second highest sequence reliability in the third position set S3, and the second position set S2 after the first update is a position set corresponding to the first position set S1 after the first PC position is deleted, If the row weight corresponding to the second candidate position is less than the minimum row weight corresponding to the second position set S2 after the first update, the second candidate position is taken as the second PC position, ​ ​ The n PC The second PC position among the n PC PC positions is determined based on the minimum row weight corresponding to the second position set S2 after the first update and the row weight corresponding to the second candidate position, and the second PC position is the second determined PC position among the n ​ ​ If the row weight corresponding to the second candidate position is greater than or equal to the minimum row weight corresponding to the first updated second position set S2, the position with the largest position number or the highest sequence reliability in a fifth position set S5 is taken as the second PC position, the fifth position set S5 including positions in the first updated first position set S1 with row weights equal to the minimum row weight of the first updated second position set S2, the first updated first position set S1 including the first updated second position set S2 and the second candidate position.

5. The method of claim 4, wherein the third candidate position is a position with the lowest sequence reliability in the third position set S3, and the second updated second position set S2 is a position set corresponding to the second PC position being removed from the first updated first position set S1. The n PC The third PC position among the n PC PC positions is determined based on the minimum row weight corresponding to the second position set S2 after the second update and the row weight corresponding to the third candidate position, and the third PC position is the third determined PC position among the n If the row weight corresponding to the third candidate position is less than the minimum row weight corresponding to the second updated second position set S2, the third candidate position is taken as the third PC position. If the row weight corresponding to the third candidate position is greater than or equal to the minimum row weight corresponding to the second updated second position set S2, the position with the largest position number or the highest sequence reliability in a sixth position set S6 is taken as the third PC position, the sixth position set S6 including positions in the second updated first position set S1 with row weights equal to the minimum row weight of the second updated second position set S2, the second updated position set including the second updated second position set S2 and the third candidate position.

6. The method of claim 1 or 2, wherein the i-th candidate position is taken as the i-th PC position if the row weight corresponding to the i-th candidate position is less than the minimum row weight corresponding to the i-th round of second position set S2. If the row weight corresponding to the i-th candidate position is greater than or equal to the minimum row weight corresponding to the i-th round of second position set S2, the position with the largest position number or the highest sequence reliability in a fourth position set S4 is taken as the i-th PC position, the fourth position set S4 including positions in the i-th round of first position set S1 with row weights equal to the minimum row weight of the i-th round of second position set S2, the i-th round of first position set S1 including the i-th round of second position set S2 and the i-th candidate position. The n PC The ith PC position is determined based on the minimum row weight corresponding to the ith round of the second position set S2 and the row weight of the ith candidate position in the third position set, wherein, The ith candidate position is a position with the ith highest sequence reliability in the third position set S3, and the n PC positions in the third position set S3 are sequentially determined as candidate positions according to the sequence reliability from high to low to determine a PC position, and the first PC position in the n PC PC positions is determined based on the row weight of the second position set S2 in the first round and the row weight of the first candidate position, the second position set S2 in the first round includes A positions with the highest sequence reliability in the first bit sequence, the first candidate position is a position with the highest sequence reliability in the third position set S3, and 1≤i≤n PC -1; If the row weight corresponding to the i+1-th candidate position is less than the minimum row weight corresponding to the i+1-th round of second position set S2, the i+1-th candidate position is taken as the i+1-th PC position. ​ The n PC The i+1th PC position is determined based on the row weight of the i+1th round of second position set S2 and the row weight of the i+1th candidate position, wherein the i+1th round of second position set S2 includes the positions in the first position set in the i round except the i th PC position, and the i+1th candidate position is the i+1th highest sequence reliability position in the third position set S3. ​ If the row weight corresponding to the i+1th candidate position is greater than or equal to the minimum row weight corresponding to the second position set S2 of the i+1th round, a position with the largest position number or the highest sequence reliability in a fifth position set S5 is taken as the i+1th PC position, the fifth position set S5 including positions in the first position set S1 of the i+1th round with the row weight equal to the minimum row weight of the second position set S2 of the i+1th round, the first position set S1 of the i+1th round including the second position set S2 of the i+1th round and the i+1th candidate position.

7. The method of claim 1 or 2, wherein, The n PC PC positions are determined based on the minimum row weight corresponding to the second position set S2 and the row weight corresponding to the n PC PC positions in the third position set S3, wherein the second position set S2 includes A positions with the highest sequence reliability in the first bit sequence, If the row weight corresponding to m1 positions in the third position set S3 is less than the minimum row weight corresponding to the second position set S2, the m1 positions are PC positions, 1≤m1≤n PC , If the row weight corresponding to the m2 positions in the third position set S3 is greater than or equal to the minimum row weight corresponding to the second position set S2, the m2 positions with the largest position number in the fourth position set S4 or the m2 positions with the highest sequence reliability are PC positions, the fourth position set S4 includes positions in the first position set S1 with a row weight equal to the minimum row weight of the second position set S2, the first position set S1 includes the second position set S2 and the third position set S3, wherein m1+m2=n PC .

8. The method of claim 1 or 2, wherein, The n PC PC positions are determined based on the minimum row weight corresponding to the second position set S2 and the row weight corresponding to the n PC PC positions in the third position set S3, wherein the second position set S2 includes A positions with the highest sequence reliability in the first bit sequence, If the row weight corresponding to the i-th position in the third position set S3 is less than the minimum row weight corresponding to the second position set S2, the i-th position is taken as a PC position, 1≤i≤n PC , If the row weight corresponding to the i+1th candidate position is greater than or equal to the minimum row weight corresponding to the second position set S2 of the i+1th round, a position with the largest position number or the highest sequence reliability in a fifth position set S5 is taken as the i+1th PC position, the fifth position set S5 including positions in the first position set S1 of the i+1th round with the row weight equal to the minimum row weight of the second position set S2 of the i+1th round, the first position set S1 of the i+1th round including the second position set S2 of the i+1th round and the i+1th candidate position.

9. The method of any one of claims 1 to 8, wherein, The n PC PC positions are n PC positions in the first bit sequence with the lowest sequence reliability. or, The n PC PC positions are n PC positions with the highest sequence reliability or the largest position number in the first bit sequence.

10. The method according to any one of claims 1 to 9, characterized in that, The A information bits are located in the A + n PC ) positions of the first bit sequence other than the n PC PC positions with the highest sequence reliability.

11. The method according to any one of claims 1 to 10, characterized in that, The method further comprises: Based on the n PC The PC verification relationship corresponding to each PC position determines the n PC The value of each PC bit.

12. A communications device, characterized by comprising at least one processor and interface circuitry for receiving signals from other communication devices outside the communication device and transmitting signals to the processor or sending signals from the processor to other communication devices outside the communication device, the processor causing the method of any one of claims 1 to 11 to be implemented by logic circuitry or executing code instructions.

13. The communication apparatus according to claim 12, wherein The communication device is a chip or a chip system.

14. A computer-readable storage medium, characterized in that, The storage medium has stored therein a computer program or instructions, which, when executed, cause the method of any one of claims 1 to 11 to be implemented.

15. A computer program product, characterised in that, comprising a computer program, which, when executed, cause the method of any one of claims 1 to 11 to be implemented.

16. A communication system, characterized by comprising: a transmitting end device for executing the method of any one of claims 1, 3 to 11; a receiving end device for executing the method of any one of claims 2 to 11.

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