Decoding method and decoding apparatus

Abstract

Provided in the present application is a decoding method, comprising: acquiring a system bit vector with a length of k bits, and on the basis of a flipping order O, performing O rounds of flipping on the system bit vector, wherein a flipped vector corresponding to an ith instance of flipping in the O rounds of flipping is encoded to obtain an encoded vector corresponding to the ith instance of flipping, in order to obtain a difference value corresponding to the ith instance of flipping; on the basis of the difference value corresponding to the ith instance of flipping and a difference value corresponding to an (i+1)th instance of flipping, determining a decoding result corresponding to the ith instance of flipping; and repeating the above steps until a decoding result corresponding to the last instance of flipping in the last round of flipping is output as a final decoding result. The technical solution can make the number of instances of flipping required to output a final decoding result be less than the current number of instances of flipping, thereby reducing the decoding complexity of guess-based decoding.

Description

Decoding method and decoding device

[0001] The present application claims priority to the Chinese patent application No. 202410725105.7, filed on June 5, 2024, and entitled “A decoding method and decoding device”, the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the field of channel coding, and more particularly, to a decoding method and decoding device. BACKGROUND

[0003] Random noise guess decoding is a general-purpose decoder, which aims to provide performance close to maximum likelihood (ML) decoding under limited complexity. Given the channel information, random noise guess decoding (or called guess decoding) assumes a series of error patterns, evaluates and queries in descending order of the occurrence of each error pattern. In each query, random noise guess decoding subtracts the assumed noise effect from the demodulation received sequence, and checks whether the remaining part belongs to the codebook. The first result belonging to the codebook will be output as the decoding result.

[0004] The advantage of random noise guess decoding is that it only needs a check matrix to decode, and can be used for any code, and can always find and accept the code word with the closest Hamming distance to the symbol as the decoding result. For example, tail-biting convolutional code (TBCC) in the fourth generation (4G), Polar code in the fifth generation (5G), and low density parity check code (LDPC). For very high code rate or very short code length, random noise guess decoding can quickly get the decoding result. However, when the code rate decreases or the code length increases, the decoding complexity (average complexity or maximum complexity) of random noise guess decoding will increase by a combinatorial number. Therefore, the application range of random noise guess decoding is limited, and it is not suitable for current mainstream communication systems. SUMMARY

[0005] The present application provides a decoding method, which can reduce the decoding complexity of random noise guess decoding (or called guess decoding).

[0006] In a first aspect, a decoding method is provided, which is performed by a decoding end, and includes: obtaining a system bit vector, the system bit vector being composed of the first bit to the kth bit in a received vector, k being an integer greater than or equal to 1; performing O rounds of flipping on the bits in the system bit vector based on a flipping order O, the number of flipped bits corresponding to the O rounds of flipping increasing by 1 bit per round, each round of flipping in the O rounds of flipping corresponding to one or more times of flipping, each time of flipping corresponding to a flipped vector, and each flipped vector corresponding to one encoded vector obtained through encoding, wherein O is an integer greater than or equal to 1; and outputting a decoding result corresponding to the last time of flipping in the Oth round of flipping as a final decoding result.

[0007] In the case where a difference value between the encoded vector corresponding to the ith time of flipping and the received vector is less than a difference value corresponding to the (i-1)th time of flipping, the decoding result corresponding to the ith time of flipping is the encoded vector corresponding to the ith time of flipping; and

[0008] In the case where a difference value between the encoded vector corresponding to the ith time of flipping and the received vector is greater than or equal to the difference value corresponding to the (i-1)th time of flipping, the decoding result corresponding to the ith time of flipping is the decoding result corresponding to the (i-1)th time of flipping, the decoding result corresponding to the (i-1)th time of flipping being associated with the difference value corresponding to the (i-1)th time of flipping.

[0009] In the case where a difference value between the encoded vector corresponding to the ith time of flipping and the received vector is greater than or equal to the difference value corresponding to the (i-1)th time of flipping, the decoding result corresponding to the ith time of flipping is the decoding result corresponding to the (i-1)th time of flipping, the decoding result corresponding to the (i-1)th time of flipping being associated with the difference value corresponding to the (i-1)th time of flipping.

[0010] The difference value corresponding to the (i-1)th time of flipping includes any one of a difference value between a first encoded vector and the received vector, and a difference value between a first vector and the received vector, the first encoded vector being an encoded vector corresponding to any one of the first (i-1) times of flipping, and the first vector being obtained through encoding of the system bit vector, i being an integer greater than or equal to 1.

[0011] The decoding result corresponding to the first time of flipping is obtained based on a difference value between an encoded vector corresponding to the first time of flipping and the received vector, and a difference value between the first vector and the received vector.

[0012] For ease of description, the following description uses guess decoding instead of random noise guess decoding.

[0013] In the technical solution of the present application, under the same limitation of the maximum flipping order O, the method of flipping the bits in the system bit vector per round can make the number of times of flipping for outputting the final decoding result less than that of the prior art, thereby reducing the decoding complexity of guess decoding.

[0014] With reference to the first aspect, in some implementations of the first aspect, the decoding result corresponding to the i-1th flip is associated with a difference value corresponding to the i-1th flip, including: in a case where the difference value corresponding to the i-1th flip is a difference value between the first vector and the received vector, the decoding result corresponding to the i-1th flip is the first vector; and in a case where the difference value corresponding to the i-1th flip is a difference value between the first encoded vector and the received vector, the decoding result corresponding to the i-1th flip is the first encoded vector. Based on the above technical solution, the number of flips to output the final decoding result can be less than that of the prior art, thereby reducing the decoding complexity of the guess decoding.

[0015] With reference to the first aspect, in some implementations of the first aspect, in a case where the difference value between the first encoded vector corresponding to the 1st flip and the received vector is less than the difference value between the first vector and the received vector, the decoding result corresponding to the 1st flip is the first encoded vector corresponding to the 1st flip; and in a case where the difference value between the first encoded vector corresponding to the 1st flip and the received vector is greater than or equal to the difference value between the first vector and the received vector, the decoding result corresponding to the 1st flip is the first vector. Based on the above technical solution, the number of flips to output the final decoding result can be less than that of the prior art, thereby reducing the decoding complexity of the guess decoding.

[0016] With reference to the first aspect, in some implementations of the first aspect, the flip order O is less than or equal to a first value, where the first value is one half of a minimum distance of a code word space corresponding to or formed by the encoding matrix G. Based on the above technical solution, by limiting the flip order O to be less than d / 2, in a case where the minimum distance d of the encoding matrix G or the corresponding code word space is determined, meaningless flips can be saved, and the maximum number of flips to find the minimum distance code word is further reduced.

[0017] In a second aspect, a decoding method is provided, which is performed by a decoding end, and includes: obtaining a systematic bit vector, the systematic bit vector being composed of a first bit to a kth bit in a received vector, k being an integer greater than or equal to 1; in a case where a difference value between a first vector and the received vector is greater than or equal to a first value, performing i times of flipping on bits in the systematic bit vector, each time of flipping corresponding to a flipped vector, each flipped vector corresponding to the time of flipping being obtained by encoding, the first vector being obtained by encoding a code matrix corresponding to the systematic bit vector, the first value being a half of a minimum distance of a code word space formed by or corresponding to the code matrix, wherein i is an integer greater than or equal to 1; based on a difference value between a i-th flipped vector and the received vector and a first difference value, outputting a decoding result corresponding to the i-th flipped vector, and determining the difference value corresponding to the i-th flipped vector; in a case where the difference value corresponding to the i-th flipped vector is less than the first value, outputting the decoding result corresponding to the i-th flipped vector as a final decoding result; and in a case where the difference value corresponding to the i-th flipped vector is greater than or equal to the first value, performing an (i+1)-th flipping on the bits in the systematic bit vector.

[0018] wherein,

[0019] in a case where i is equal to 1, the first difference value is the difference value between the first vector and the received vector; and

[0020] in a case where i is greater than or equal to 2, the first difference value includes any one of a difference value between a first encoded vector and the received vector, and a difference value between the first vector and the received vector, the first encoded vector being an encoded vector corresponding to any one of the previous (i-1) times of flipping.

[0021] In the technical solution of the present application, under the same maximum flipping order O limitation, by the method of flipping the bits in the systematic bit vector round by round, the number of times of flipping for outputting the final decoding result can be less than that of the prior art, thereby reducing the decoding complexity of the guess decoding. Moreover, the early stopping threshold (the difference value corresponding to the flipping being less than d / 2) can greatly reduce the average number of times of flipping.

[0022] In combination with the second aspect, in some implementations of the second aspect, in a case where i is an integer greater than or equal to 2, the i times of flipping include the i-th flipping and (i-1) times of flipping before the i-th flipping; a j-th flipping in the (i-1) times of flipping satisfies: in a case where the difference value corresponding to the j-th flipping is less than the first value, performing a (j+1)-th flipping on the bits in the systematic bit vector, j≤(i-1), and j is an integer greater than or equal to 1. Based on the above technical solution, the number of times of flipping for outputting the final decoding result can be less than that of the prior art, thereby reducing the decoding complexity of the guess decoding.

[0023] With reference to the second aspect, in some implementations of the second aspect, the outputting the decoding result corresponding to the ith flip and determining the difference value corresponding to the ith flip comprises: in a case where the difference value between the encoding vector corresponding to the ith flip and the received vector is less than the first difference value, the outputted decoding result corresponding to the ith flip is the encoding vector corresponding to the ith flip, and the determined difference value corresponding to the ith flip is the difference value between the encoding vector corresponding to the ith flip and the received vector; and in a case where the difference value between the encoding vector corresponding to the ith flip and the received vector is greater than or equal to the first difference value, the outputted decoding result corresponding to the ith flip is the first decoding result, and the determined difference value corresponding to the ith flip is the first difference value, wherein the first decoding result is associated with the first difference value. Based on the above technical solution, the number of flips for outputting the final decoding result can be less than that of the prior art, thereby reducing the decoding complexity of the guess decoding.

[0024] With reference to the second aspect, in some implementations of the second aspect, the first decoding result is associated with the first difference value, comprising: in a case where the first difference value is the difference value between the first vector and the received vector, the first decoding result is the first vector; and in a case where the first difference value is the difference value between the first encoding vector and the received vector, the first decoding result is the first encoding vector. Based on the above technical solution, the number of flips for outputting the final decoding result can be less than that of the prior art, thereby reducing the decoding complexity of the guess decoding.

[0025] With reference to the second aspect, in some implementations of the second aspect, the method further comprises: in a case where the difference value between the first vector and the received vector is less than the first value, outputting the first vector as the final decoding result. Based on the above technical solution, in the flipping process, the introduction of the early stopping threshold (the difference value corresponding to the flip is less than d / 2) can greatly reduce the average number of flips.

[0026] With reference to the second aspect, in some implementations of the second aspect, the flipping the bits in the systematic bit vector for i times comprises: flipping the bits in the systematic bit vector for O rounds based on a flipping order O, the O rounds of flipping comprising i times of flipping, the flipping order O corresponding to n times of flipping, O being an integer greater than or equal to 1, n being an integer greater than 1, and i being less than or equal to n; the number of flipped bits corresponding to the O rounds of flipping increasing by 1 bit per round, and each round of flipping in the O rounds of flipping corresponding to one or more times of flipping. Based on the above technical solution, the number of flips for outputting the final decoding result can be less than that of the prior art, thereby reducing the decoding complexity of the guess decoding.

[0027] With reference to the second aspect, in some implementations of the second aspect, the flipping order O is less than or equal to the first value. Based on the above technical solution, by limiting the flipping order O to be less than d / 2, the meaningless flipping can be saved in the case of determining that the code distance d of the code matrix G or the corresponding code word space is formed, and the maximum flipping number of finding the minimum code distance code word is further reduced.

[0028] In a third aspect, a decoding device is provided, comprising:

[0029] a processing unit configured to: obtain a system bit vector composed of the first bit to the kth bit in a received vector, k being an integer greater than or equal to 1; perform O rounds of flipping on the bits in the system bit vector based on a flipping order O, the number of flipped bits corresponding to each round of the O rounds of flipping increasing by 1 bit, each round of flipping in the O rounds of flipping corresponding to one or more flips, each flip corresponding to an encoded vector obtained by encoding a flipped vector corresponding to the flip, wherein O is an integer greater than or equal to 1;

[0030] a communication unit configured to output a decoding result corresponding to the last flip in the Oth round of the O rounds of flipping as a final decoding result;

[0031] wherein the decoding result corresponding to the ith flip in the O rounds of flipping satisfies the following conditions:

[0032] in a case where a difference value between the encoded vector corresponding to the ith flip and the received vector is less than a difference value corresponding to the (i-1)th flip, the decoding result corresponding to the ith flip is the encoded vector corresponding to the ith flip; and

[0033] in a case where the difference value between the encoded vector corresponding to the ith flip and the received vector is greater than or equal to the difference value corresponding to the (i-1)th flip, the decoding result corresponding to the ith flip is the decoding result corresponding to the (i-1)th flip, the decoding result corresponding to the (i-1)th flip being associated with the difference value corresponding to the (i-1)th flip;

[0034] wherein the difference value corresponding to the (i-1)th flip includes any one of a difference value between a first encoded vector and the received vector, and a difference value between a first vector and the received vector, the first encoded vector being an encoded vector corresponding to any one of the first (i-1) flips, the first vector being obtained by encoding the system bit vector, i being an integer greater than or equal to 1;

[0035] The decoding result corresponding to the first flipping is obtained based on a difference value between the encoding vector corresponding to the first flipping and the received vector, and a difference value between the first vector and the received vector.

[0036] With reference to the third aspect, in some implementations of the third aspect, the processing unit is specifically configured to: in a case where the difference value corresponding to the (i-1)th flipping is the difference value between the first vector and the received vector, the decoding result corresponding to the (i-1)th flipping is the first vector; and in a case where the difference value corresponding to the (i-1)th flipping is the difference value between the first encoding vector and the received vector, the decoding result corresponding to the (i-1)th flipping is the first encoding vector.

[0037] With reference to the third aspect, in some implementations of the third aspect, in a case where the difference value between the encoding vector corresponding to the first flipping and the received vector is less than the difference value between the first vector and the received vector, the decoding result corresponding to the first flipping is the encoding vector corresponding to the first flipping; and in a case where the difference value between the encoding vector corresponding to the first flipping and the received vector is greater than or equal to the difference value between the first vector and the received vector, the decoding result corresponding to the first flipping is the first vector.

[0038] With reference to the third aspect, in some implementations of the third aspect, the flipping order O is less than or equal to a first value, where the first value is one half of a minimum distance of a code word space formed by or corresponding to an encoding matrix used for encoding the encoded vector.

[0039] A fourth aspect provides a decoding apparatus, comprising:

[0040] a processing unit configured to: obtain a system bit vector composed of a first bit to a kth bit in a received vector, k being an integer greater than or equal to 1; in a case where a difference value between a first vector and the received vector is greater than or equal to a first value, flip bits in the system bit vector for i times, each flipping corresponding to a flipped vector, each flipped vector being encoded to obtain an encoding vector, the first vector being obtained by encoding the system bit vector by using an encoding matrix, the first value being one half of a minimum distance of a code word space formed by or corresponding to the encoding matrix, i being an integer greater than or equal to 1; and output a decoding result corresponding to the i-th flipping based on a difference value between an encoding vector corresponding to the i-th flipping and the received vector, and the first difference value, and determine a difference value corresponding to the i-th flipping.

[0041] the communication unit is configured to: output a decoding result corresponding to the i-th flip as a final decoding result, in a case where a difference value corresponding to the i-th flip is less than the first value; and perform an (i+1)-th flip on the bits in the systematic bit vector, in a case where the difference value corresponding to the i-th flip is greater than or equal to the first value;

[0042] wherein,

[0043] in a case where i is equal to 1, the first difference value is a difference value between the first vector and the received vector; and

[0044] in a case where i is greater than or equal to 2, the first difference value comprises any one of a difference value between a first encoding vector and the received vector, and a difference value between the first vector and the received vector, the first encoding vector being an encoding vector corresponding to any one of the (i-1) flips.

[0045] With reference to the fourth aspect, in some implementations of the fourth aspect, in a case where i is an integer greater than or equal to 2, the i-th flip comprises the i-th flip and (i-1) flips before the i-th flip; a j-th flip in the (i-1) flips satisfies: performing a (j+1)-th flip on the bits in the systematic bit vector, in a case where a difference value corresponding to the j-th flip is less than the first value, j is less than or equal to (i-1), and j is an integer greater than or equal to 1.

[0046] With reference to the fourth aspect, in some implementations of the fourth aspect, the processing unit is specifically configured to: in a case where a difference value between an encoding vector corresponding to the i-th flip and the received vector is less than the first difference value, output the decoding result corresponding to the i-th flip as the encoding vector corresponding to the i-th flip, and determine the difference value corresponding to the i-th flip as the difference value between the encoding vector corresponding to the i-th flip and the received vector; and in a case where the difference value between the encoding vector corresponding to the i-th flip and the received vector is greater than or equal to the first difference value, output the decoding result corresponding to the i-th flip as a first decoding result, and determine the difference value corresponding to the i-th flip as the first difference value, wherein the first decoding result is associated with the first difference value.

[0047] With reference to the fourth aspect, in some implementations of the fourth aspect, the processing unit is specifically configured to: in a case where the first difference value is a difference value between the first vector and the received vector, the first decoding result is the first vector; and in a case where the first difference value is a difference value between a first encoding vector and the received vector, the first decoding result is the first encoding vector.

[0048] In some implementations of the fourth aspect, in combination with the fourth aspect, the communication unit is further configured to: output the first vector as a final decoding result in a case where a difference value between the first vector and the received vector is less than the first value.

[0049] In some implementations of the fourth aspect, in combination with the fourth aspect, the processing unit is specifically configured to: perform O rounds of flipping on bits in the systematic bit vector based on a flipping order O, the O rounds of flipping including i times of flipping, the flipping order O corresponding to n times of flipping, O being an integer greater than or equal to 1, n being an integer greater than 1, and i being less than or equal to n; a number of flipped bits corresponding to the O rounds of flipping increasing by 1 bit round by round, and each round of flipping in the O rounds of flipping corresponding to one or more times of flipping.

[0050] In some implementations of the fourth aspect, in combination with the fourth aspect, the flipping order O is less than or equal to the first value.

[0051] In the fifth aspect, the present application provides a decoding device having the functions of the method in the first aspect or any possible implementation manner thereof and the functions of the method in the second aspect or any possible implementation manner thereof. The functions can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more units corresponding to the above functions.

[0052] In the sixth aspect, the present application provides a decoder including one or more processors coupled with one or more memories. The one or more memories are configured to store computer programs, and the one or more processors are configured to invoke and run the computer programs stored in the one or more memories to execute the method in the first aspect or any possible implementation manner thereof and the method in the second aspect or any possible implementation manner thereof.

[0053] Optionally, the chip can be a channel decoder.

[0054] In the seventh aspect, the present application provides a chip including one or more processors. The one or more processors are configured to read and execute computer programs stored in one or more memories to execute the method in the first aspect or any possible implementation manner thereof and the method in the second aspect or any possible implementation manner thereof. The one or more memories are independently arranged outside the chip.

[0055] Optionally, the chip further includes one or more memories connected with the one or more processors through circuits or wires.

[0056] Further optionally, the chip further includes a communication interface.

[0057] In an eighth aspect, the present application provides a decoding apparatus, comprising a processor and an interface circuit, the interface circuit being configured to receive computer codes or instructions and transmit the computer codes or instructions to the processor, and the processor being configured to execute the computer codes or instructions to perform the method in the first aspect or any possible implementation manner thereof and the method in the second aspect or any possible implementation manner thereof.

[0058] In a ninth aspect, the present application provides a computer readable storage medium, wherein computer instructions are stored in the computer readable storage medium, and when the computer instructions are executed on a computer, the computer is caused to perform the method in the first aspect or any possible implementation manner thereof and the method in the second aspect or any possible implementation manner thereof.

[0059] In a tenth aspect, the present application provides a computer program product, comprising computer program codes, and when the computer program codes are executed on a computer, the computer is caused to perform the method in the first aspect or any possible implementation manner thereof and the method in the second aspect or any possible implementation manner thereof.

[0060] In an eleventh aspect, the present application provides a communication device, comprising the decoder in the sixth aspect.

[0061] In a twelfth aspect, the present application provides a wireless communication system, comprising the communication device in the eleventh aspect.

[0062] The beneficial effects of the third aspect to the twelfth aspect can refer to the beneficial effects of the first aspect and the second aspect, which will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0063] FIG. 1 is a schematic diagram of a system architecture of a communication system suitable for the technical solutions of the present application.

[0064] FIG. 2 is a schematic diagram of a basic flow of wireless communication.

[0065] FIG. 3 is a schematic diagram of a decoding method 300 provided by an embodiment of the present application.

[0066] FIG. 4 shows a flowchart of a decoding method provided by the present application.

[0067] FIG. 5 is a schematic diagram of a decoding method 500 provided by another embodiment of the present application.

[0068] FIG. 6 shows a flowchart of a decoding method provided by the present application.

[0069] FIG. 7 is a simulation comparison diagram of BLER of an existing guessing decoding method and a guessing decoding method of the present application.

[0070] FIG. 8 is a simulation comparison diagram of complexity (average number of flips) of a prior art guessing decoding method and a guessing decoding method provided by the present application.

[0071] FIG. 9 is a schematic diagram of a decoding apparatus 900 provided by the present application.

[0072] FIG. 10 is a schematic structural diagram of the decoding apparatus 900 provided by the present application.

[0073] FIG. 11 is a schematic structural diagram of a decoder 1000 according to an embodiment of the present application. DETAILED DESCRIPTION

[0074] The technical solutions in the present application will be described below with reference to the accompanying drawings.

[0075] The technical solutions of the embodiments of the present application can be applied to various communication systems, including but not limited to: satellite communication systems, the 5th generation (5G) or new radio (NR) systems, long term evolution (LTE) systems, LTE frequency division duplex (FDD) systems, LTE time division duplex (TDD) systems, etc. The technical solutions provided by the present application can also be applied to future communication systems, such as the 6th generation mobile communication system. In addition, it can also be applied to sidelink (SL) communication, vehicle-to-everything (V2X) communication, machine to machine (M2M) communication, machine type communication (MTC), and internet of things (IoT) communication systems or other communication systems, etc., which are not limited herein.

[0076] The communication system suitable for the present application can include one or more sending ends and one or more receiving ends. Optionally, one of the sending end and the receiving end can be a terminal device, and the other can be a network device. Alternatively, both the sending end and the receiving end are terminal devices. The sending end can also be considered as an encoding end or an encoding device, and the receiving end can also be considered as a decoding end or a decoding device.

[0077] Exemplarily, the terminal device can also be referred to as a user equipment (UE), an access terminal, a subscriber unit, a subscriber station, a mobile station, a mobile, a mobile terminal (MT), a remote station, a remote terminal, a mobile device, a user terminal, a terminal, a wireless communication device, a user agent, or a user device. The terminal device in the embodiments of the present application can refer to a device that provides voice and / or data connectivity to a user, and can be used to connect people, things, and machines, for example, handheld devices with wireless connection functions, vehicle-mounted devices, etc. The terminal device in the embodiments of the present application can be a mobile phone, a tablet computer, a notebook computer, a palm computer, a mobile internet device (MID), a wearable device, a virtual reality (VR) device, an augmented reality (AR) device, a wireless terminal in industrial control, a wireless terminal in self driving, a wireless terminal in remote medical surgery, a wireless terminal in smart grid, a wireless terminal in transportation safety, a wireless terminal in smart city, a wireless terminal in smart home, etc. Optionally, the UE can be used to act as a base station. For example, the UE can act as a scheduling entity, which provides a sidelink signal between UEs in V2X or SL, etc.

[0078] In the embodiments of the present application, the device for implementing the function of the terminal can be a terminal, or a device capable of supporting the terminal to implement the function, for example, a chip system or a chip, which can be installed in the terminal. In the embodiments of the present application, the chip system can be composed of a chip, or can include a chip and other discrete devices.

[0079] Exemplarily, the network device can be a device with wireless transceiving function, which can be a device providing wireless communication function service, usually located at the network side, including but not limited to a next generation base station (gNodeB, gNB) in a 5th generation (5G) communication system, a base station in a 6th generation (6G) mobile communication system, a base station in a future mobile communication system, or an access node in a wireless fidelity (Wi-Fi) system, an evolved node B (eNB) in a long term evolution (LTE) system, a radio network controller (RNC), a node B (NB), a base station controller (BSC), a home base station (for example, a home evolved NodeB, or a home Node B, HNB), a base band unit (BBU), a transmission reception point (TRP), a transmitting point (TP), a base transceiver station (BTS), and the like. In a network structure, the network device can include a centralized unit (CU) node, or include a distributed unit (DU) node, or include a RAN device including a CU node and a DU node, or include a RAN device including a control plane CU node and a user plane CU node, and a DU node, or the network device can also be a wireless controller in a cloud radio access network (CRAN) scenario, a relay station, a vehicle-mounted device, a wearable device, and the like. In addition, the base station can be a macro base station, a micro base station, a relay node, a donor node, or a combination thereof. The base station can also refer to a communication module, a modem, or a chip for being arranged in the foregoing device or apparatus. The base station can also be a mobile switching center, a device assuming a base station function in D2D, V2X, M2M communication, a network side device in a 6G (or future communication system) network, a device assuming a base station function in a future communication system, and the like. The base station can support networks of the same or different access technologies, without limitation.

[0080] In the embodiments of the present application, the device for implementing the function of the network device can be the network device, or can be a device capable of supporting the network device to implement the function, such as a chip system or a chip, which can be installed in the network device. In the embodiments of the present application, the chip system can be composed of a chip, or can include a chip and other discrete devices.

[0081] It should be understood that the coding scheme provided in the present application, that is, the channel coding scheme, can be used in a dedicated network device or a general device, and can be applied to various network devices (for example, a base station device) as described above, or can be applied to various terminal devices as described above. Specifically, the channel coding scheme is mainly implemented through a channel coding unit in the devices.

[0082] In the embodiments of the present application, the functions of the sending end or the receiving end can be implemented through an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or the like, or can be implemented through software (for example, program code in a memory), without limitation.

[0083] In addition, the technical scheme of the present application can be applied to various communication scenarios. FIG. 1 is a schematic diagram of a system architecture of a communication system suitable for the technical scheme of the present application.

[0084] As an example in FIG. 1, the coding method provided in the present application can be applied to communication between a network device and a terminal device, that is, uplink or downlink communication. In this communication scenario, the sending end in the present application can be a terminal device in uplink communication or a network device in downlink communication, and the receiving end can be a network device in uplink communication or a terminal device in downlink communication. In addition, the technical scheme of the present application can also be applied to sidelink communication. In this communication scenario, the sending end is a sending terminal device in sidelink communication, and the receiving end is a receiving terminal device in sidelink communication. In addition, the technical scheme of the present application can also be applied to other communication scenarios, which will not be described herein.

[0085] Referring to FIG. 2, FIG. 2 is a schematic diagram of a basic flow of wireless communication. As shown in FIG. 2, at the sending end of a signal, a signal source is sequentially subjected to source encoding, channel encoding, and digital modulation, and then is sent out. At the receiving end of the signal, the received signal is sequentially subjected to digital demodulation, channel decoding, and source decoding, and then is output to a signal sink. Channel encoding and decoding is one of the core technologies in the field of wireless communication.

[0086] The random noise guess decoding is a general decoder, hereinafter referred to as guess decoding. The guess decoding has the advantage that it only needs a check matrix to decode, can be used for any code, and can always find and accept the code word with the closest Hamming distance to the symbol as the decoding result. However, when the code rate decreases or the code length increases, the decoding complexity (average complexity or maximum complexity) of the guess decoding will increase by a combination number level. Therefore, the application range of the guess decoding is limited, and it is not suitable for the current mainstream communication system.

[0087] Based on this, the present application aims to provide a decoding method capable of reducing the decoding complexity of the guess decoding.

[0088] FIG. 3 is a schematic flowchart of a decoding method 300 provided by an embodiment of the present application. As shown in FIG. 3, the method at least includes the following steps. The steps shown in FIG. 3 can be executed by a decoding end.

[0089] S310: The decoding end acquires a systematic bit vector.

[0090] Optionally, before step S310, the method further includes: receiving, by the decoding end, a received vector.

[0091] Specifically, the received vector is composed of N bits, for example, the received vector is The received vector includes (1, 2, …, n) bits. After receiving the received vector , the decoding end selects the first k bits in the received vector , thereby acquiring the systematic bit vector. For example, the systematic bit vector can be The systematic bit vector includes (1, 2, …, k) elements, where 1≤k It can be understood that the k-length bit information to be sent is not changed in amplitude to the first-k position of the encoding vector.

[0092] It should be noted that the systematic bit vector may also be understood as a systematic bit vector composed of the first k bits after a simple sequential transformation of the n bits in the received vector , which will not be described hereinafter.

[0093] It should be further noted that in the present application, the received vector and the received vector can be used interchangeably, and the systematic bit vector and the systematic bit vector may also be used interchangeably, which will not be described hereinafter.

[0094] Optionally, after step S310, the method can further comprise: the decoding end performing O rounds of flipping on the bits in the systematic bit vector based on the flipping order O, wherein O is an integer greater than or equal to 1. The first vector is obtained by encoding the encoding matrix G. For example, the first vector can be obtained by formula (1).

[0095] S320, the decoding end performs O rounds of flipping on the bits in the systematic bit vector based on the flipping order O, wherein O is an integer greater than or equal to 1.

[0096] In this application, the number of flipped bits corresponding to O rounds of flipping increases by 1 bit per round. Each round of flipping in O rounds of flipping corresponds to one or more flips, and each flip corresponds to a flipped vector. Each flipped vector corresponds to an encoded vector obtained by encoding.

[0097] The number of flipped bits corresponding to O rounds of flipping increases by 1 bit per round, which can be understood as follows: in O rounds of flipping, the number of flipped bits in the oth round of flipping increases by 1 bit compared to the (o-1)th round of flipping, the number of flipped bits in the (o-1)th round of flipping increases by 1 bit compared to the (o-2)th round of flipping, and so on. For example, assuming that the number of flipped bits corresponding to 1 round of flipping (o=1) is 1 bit, then the number of flipped bits corresponding to 2 rounds of flipping (o=2) is 2 bits, the number of flipped bits corresponding to 3 rounds of flipping (o=3) is 3 bits, and so on, where 1≤o≤O.

[0098] The oth round of flipping is described in detail below with o=1 and o=2 as examples.

[0099] For example, when o=1, the decoding end performs the 1st round of flipping on the bits in the systematic bit vector, and the number of flipped bits in each flip is 1 bit, that is, in the case of the systematic bit vector including (1, 2, …, k) bits, the 1st round of flipping can correspond to k flips, and each flip corresponds to a flipped vector. Further, the decoding end encodes each flipped vector corresponding to the flip to obtain an encoded vector. It should be noted that the 1st round of flipping corresponds to k flips, which can be understood as follows: in each flip of the 1st round of flipping, different bits in the k bits of the systematic bit vector are flipped, that is, in any flip of the 1st round of flipping, any bit in the k bits is not flipped repeatedly.

[0100] For example, in the 1st flip of the 1st round of flipping, the first bit in the systematic bit vector is flipped to obtain the flipped vector

[0101] For example, in the 1st flip of the 1st round of flipping, the first bit in the systematic bit vector is flipped to obtain the flipped vector ​​​​wherein the first bit is any one bit in the systematic bit vector Further, the flipped vector after the first flipping in the first round of flipping is encoded by the encoding matrix G to obtain an encoded vector a1, as shown in equation (2-1).

[0102] wherein G is an encoding matrix of k*n order.

[0103] For example, in the second flipping in the first round of flipping, the second bit in the systematic bit vector is flipped to obtain a flipped vector wherein the second bit is any one bit in the systematic bit vector except the first bit in the above. Further, the flipped vector after the second flipping in the first round of flipping is encoded to obtain an encoded vector a2, as shown in equation (2-2).

[0104] By analogy, in the last flipping (for example, the kth flipping) in the first round of flipping, the kth bit in the systematic bit vector is flipped to obtain a flipped vector wherein the kth bit is any one bit in the systematic bit vector except the bits in the previous (k-1) flipping. Further, the flipped vector after the kth flipping in the first round of flipping is encoded to obtain an encoded vector a k , as shown in equation (2-3). For example, when o=2, the decoding end flips the bits in the systematic bit vector

[0105] in the second round of flipping, and the number of bits flipped in each flipping is 2 bits. In the case that the systematic bit vector includes (1, 2, …, k) elements, the second round of flipping can correspond to m times of flipping, each flipping corresponding to a flipped vector, and further, each flipped vector corresponding to the flipping is encoded to obtain an encoded vector. It should be noted that the second round of flipping corresponds to m times of flipping, which can be understood as follows: in each flipping in the second round of flipping, two different bits in the k bits in the systematic bit vector

[0106] are flipped, that is, in any flipping in the second round of flipping, any two bits in the k bits are not repeatedly flipped. The two different bits can be understood as follows:

[0107] ​​​Case 1: None of the two bits are different.

[0108] Case 2: Only one of the two bits is different.

[0109] It should be noted that in the case of m times of flipping corresponding to the second round of flipping, at this time, the value of m can be C 2 k That is, the value of m is k*(k-1) / 2.

[0110] For example, in the first flipping of the second round of flipping, the first bit group in the system bit vector is flipped to obtain the flipped vector , wherein the first bit group is any two bits in the system bit vector . Further, the flipped vector after the first flipping in the second round of flipping is encoded to obtain the encoding vector a1 2 , as shown in equation (3-1).

[0111] wherein G is a k*n order encoding matrix.

[0112] For example, in the second flipping of the second round of flipping, the second bit group in the system bit vector is flipped to obtain the flipped vector , wherein the second bit group is any one bit group in the system bit vector except the first bit group mentioned above, and the second bit group also includes any two bits, and the two bits in the first bit group and the two bits in the second bit group are different two bits. Further, the flipped vector after the second flipping in the second round of flipping is encoded to obtain the encoding vector a2 2 , as shown in equation (3-2).

[0113] By analogy, in the last flipping (for example, the mth flipping) of the second round of flipping, the mth bit group in the system bit vector is flipped to obtain the flipped vector , wherein the mth bit group is one bit group in the system bit vector except the bit group of the previous (m-1) times of flipping mentioned above. Further, the flipped vector after the mth flipping in the second round of flipping is encoded to obtain the encoding vector a m 2 , as shown in equation (3-3).

[0114] It should be noted that the foregoing is described in detail taking the first round of flipping (o = 1) and the second round of flipping (o = 2) as examples, and the corresponding o-th round of flipping when o takes other values can be referred to the foregoing description, which will not be repeated here.

[0115] For ease of understanding, in the following description, the i-th flipping is uniformly used instead of the i-th flipping in the O-th flipping for description.

[0116] In this application, in the process of O-th flipping of the bits in the system bit vector at the decoding end, the decoding end outputs the decoding result corresponding to the i-th flipping based on the difference value between the encoding vector corresponding to the i-th flipping and the received vector, and the difference value corresponding to the (i-1)-th flipping, where i is an integer greater than or equal to 1.

[0117] Further, the method can further include: S330, the decoding end outputs the decoding result corresponding to the last flipping in the O-th flipping in the O-th flipping as the final decoding result.

[0118] Specifically, the decoding end performs O-th flipping on the system bit vector, and encodes the flipped vector corresponding to the i-th flipping to obtain an encoding vector, i.e., the encoding vector corresponding to the i-th flipping, and then obtains the decoding result corresponding to the i-th flipping based on the encoding vector corresponding to the i-th flipping, and repeatedly performs the above flipping operation. Until the decoding end performs the last flipping in the last round (i.e., the O-th round) on the system bit vector, and finally outputs the decoding result corresponding to the last flipping in the last round as the final decoding result.

[0119] Specifically, the decoding result corresponding to the i-th flipping in the O-th flipping satisfies the following condition:

[0120] For example, in a possible implementation, in the case where the difference value between the encoding vector corresponding to the i-th flipping and the received vector is less than the difference value corresponding to the (i-1)-th flipping, the decoding result corresponding to the i-th flipping is the encoding vector corresponding to the i-th flipping.

[0121] Specifically, the encoding vector corresponding to the i-th flipping can be denoted as a i o It should be noted that how the encoding vector a i o corresponding to the i-th flipping is obtained can be referred to the foregoing description in steps S310 and S320, which will not be repeated here.

[0122] The difference value corresponding to the (i-1)-th flipping can include any one of the following: the difference value between the first encoding vector and the received vector, and the difference value between the first vector and the received vector. The first encoding vector is an encoding vector corresponding to any one of the first (i-1) flipping.

[0123] It should be noted that the encoding vector corresponding to any one of the previous (i-1) times of flipping can be understood as the encoding vector corresponding to the i-1th time of flipping, the encoding vector corresponding to the (i-2)th time of flipping, the encoding vector corresponding to the (i-3)th time of flipping, and so on, and the encoding vector corresponding to the first time of flipping. For the sake of simplicity, the following will not be described again.

[0124] Specifically, taking o=1 and i=2 as an example, the encoding vector corresponding to the second time of flipping is a2 1 At this time, the encoding vector a2 1 The difference value between the encoding vector a2

[0125] For example, taking the difference value X1 corresponding to the first time of flipping as the difference value between the encoding vector corresponding to the first time of flipping and the received vector as an example, in the case that the difference value X2 between the encoding vector corresponding to the second time of flipping and the received vector is less than the difference value X1 corresponding to the first time of flipping (at this time, X1 is the difference value between the encoding vector corresponding to the first time of flipping and the received vector), the decoding result corresponding to the second time of flipping is the encoding vector corresponding to the second time of flipping.

[0126] For example, taking the difference value X1 corresponding to the first time of flipping as the difference value between the first vector and the received vector as an example, in the case that the difference value X2 between the encoding vector corresponding to the second time of flipping and the received vector is less than the difference value X1 corresponding to the first time of flipping (at this time, X1 is the difference value between the first vector and the received vector), the decoding result corresponding to the second time of flipping is the encoding vector corresponding to the second time of flipping.

[0127] For example, in another possible implementation, in the case that the difference value between the encoding vector corresponding to the i time of flipping and the received vector is greater than or equal to the difference value corresponding to the (i-1)th time of flipping, the decoding result corresponding to the i time of flipping is the decoding result corresponding to the (i-1)th time of flipping, wherein the decoding result corresponding to the (i-1)th time of flipping is associated with the difference value corresponding to the (i-1)th time of flipping.

[0128] It should be noted that the decoding result corresponding to the (i-1)th time of flipping is associated with the difference value corresponding to the (i-1)th time of flipping, including the following examples.

[0129] Example 1, in the case that the difference value corresponding to the (i-1)th time of flipping is the difference value between the first vector and the received vector, the decoding result corresponding to the (i-1)th time of flipping is the first vector.

[0130] In the example 2, in a case that the difference value corresponding to the third flipping is the difference value between the first encoding vector and the received vector, the decoding result corresponding to the third flipping is the first encoding vector. In the example 2, the first encoding vector can be any one of the encoding vectors corresponding to the first three times of flipping. For example, the first encoding vector includes any one of the following: the encoding vector corresponding to the first flipping, the encoding vector corresponding to the second flipping, and the encoding vector corresponding to the third flipping.

[0131] The example 1 and the example 2 are described in detail below by taking i=4 as an example.

[0132] In a case that the difference value between the fourth encoding vector and the received vector is greater than or equal to the difference value corresponding to the third flipping, the decoding result corresponding to the fourth flipping is the decoding result corresponding to the third flipping, wherein the decoding result corresponding to the third flipping is associated with the difference value corresponding to the third flipping.

[0133] For the example 1, in a case that the difference value corresponding to the third flipping is the difference value between the first vector and the received vector, the decoding result corresponding to the third flipping is the first vector.

[0134] For the example 2, in a case that the difference value corresponding to the third flipping is the difference value between the first encoding vector and the received vector, the decoding result corresponding to the third flipping is the first encoding vector. In the example 2, the first encoding vector can be any one of the encoding vectors corresponding to the first three times of flipping. For example, the first encoding vector includes any one of the following: the encoding vector corresponding to the first flipping, the encoding vector corresponding to the second flipping, and the encoding vector corresponding to the third flipping.

[0135] For the example 2, in a case that the difference value corresponding to the third flipping is the difference value between the first encoding vector and the received vector, the decoding result corresponding to the third flipping is the first encoding vector. In the example 2, the first encoding vector can be any one of the encoding vectors corresponding to the first three times of flipping. For example, the first encoding vector includes any one of the following: the encoding vector corresponding to the first flipping, the encoding vector corresponding to the second flipping, and the encoding vector corresponding to the third flipping.

[0136] For the example 2, in a case that the difference value corresponding to the third flipping is the difference value between the first encoding vector and the received vector, the decoding result corresponding to the third flipping is the first encoding vector. In the example 2, the first encoding vector can be any one of the encoding vectors corresponding to the first three times of flipping. For example, the first encoding vector includes any one of the following: the encoding vector corresponding to the first flipping, the encoding vector corresponding to the second flipping, and the encoding vector corresponding to the third flipping.

[0137] For example, in a possible implementation, the first encoded vector is taken as the third corresponding encoded vector, i.e. the third corresponding difference value is taken as the difference value between the third corresponding encoded vector and the received vector. Specifically, in the case where the fourth corresponding difference value is greater than or equal to the third corresponding difference value, the fourth corresponding decoding result is the third corresponding decoding result, i.e. in this implementation, the fourth corresponding decoding result is the first encoded vector (i.e. the third corresponding encoded vector).

[0138] For example, in a possible implementation, the first encoded vector is taken as the third corresponding encoded vector, i.e. the third corresponding difference value is taken as the difference value between the third corresponding encoded vector and the received vector. Specifically, in the case where the fourth corresponding difference value is greater than or equal to the third corresponding difference value, the fourth corresponding decoding result is the third corresponding decoding result, i.e. in this implementation, the fourth corresponding decoding result is the first encoded vector (i.e. the third corresponding encoded vector).

[0139] It should be noted that the above is merely an example, and for other values of i, reference can be made to the above examples, which will not be repeated here for brevity.

[0140] It should be noted that when i = 1, the (i-1)th flip described above is the 0th flip, and it should be understood that the difference value corresponding to the 0th flip refers to the difference value corresponding to no flip, i.e. the difference value between the first vector and the received vector. Correspondingly, the decoding result corresponding to the 0th flip refers to the decoding result corresponding to no flip, wherein the decoding result corresponding to no flip can be understood as the decoding result obtained by the decoding end without flipping the system bit vector, i.e. the decoding end does not flip the system bit vector and directly obtains the encoded vector (i.e. the first vector described above).

[0141] It should be understood that the difference value corresponding to the 0th flip described above can be referred to as an initial difference value, and the decoding result corresponding to the 0th flip can also be referred to as an initial decoding result, which is not limited in the present application.

[0142] Further, in the present application, the decoding result corresponding to the first flip is obtained based on the difference value between the encoded vector corresponding to the first flip and the received vector, and the difference value corresponding to the 0th flip, wherein the difference value corresponding to the 0th flip is the difference value between the first vector and the received vector (e.g. the initial difference value). The decoding result corresponding to the first flip in different cases is described in detail below with reference to specific examples.

[0143] For example, in a possible implementation, when the difference between the first flipped corresponding encoding vector and the received vector is less than the difference between the first vector and the received vector, the decoding result corresponding to the first flipping is the first flipped corresponding encoding vector.

[0144] For example, in another possible implementation, when the difference between the first flipped corresponding encoding vector and the received vector is greater than or equal to the difference between the first vector and the received vector, the decoding result corresponding to the first flipping is the first vector. It should be noted that how the first vector is obtained can be referred to the description of formula (1) above.

[0145] Optionally, in a possible implementation, the number of the above-mentioned flipping O is less than or equal to a first value, where the first value is one half of the minimum distance of the code word space corresponding to or formed by the encoding matrix used for encoding the encoded vector.

[0146] That is, the number of the flipping O is less than or equal to d / 2, where d is the minimum distance of the code word space corresponding to or formed by the encoding matrix G used for encoding the encoded vector.

[0147] According to the above technical solution, under the same maximum flipping number O, by the method of flipping the bits in the systematic bit vector round by round, the number of the flipping for outputting the final decoding result can be less than that of the prior art, thereby reducing the decoding complexity of the guess decoding. Moreover, by limiting the number of the flipping O to be less than d / 2, the meaningless flipping can be saved when the minimum distance d of the encoding matrix G or the code word space corresponding thereto is determined, and the maximum number of the flipping for finding the minimum distance code word is further reduced.

[0148] An example of the detailed flow of the decoding method provided by the present application is given below in combination with FIG. 4.

[0149] As shown in FIG. 4, FIG. 4 is a flowchart of a decoding method provided by the present application. The flow shown in FIG. 4 can be performed by a decoding end.

[0150] S410, receiving a received vector. The received vector is composed of N bits, for example, the received vector is The received vector includes (1, 2, …, n) bits.

[0151] S420, obtaining a systematic bit vector.

[0152] After receiving the received vector , the decoding end selects the first k bits in the received vector , thereby obtaining the systematic bit vector. For example, the systematic bit vector is System bit vector including (1, 2, …, k) bits, 1≤k It can be understood that the k-length bit information to be sent is not changed in value to the 1-kth position of the encoding vector.

[0153] S430, set o=1, i=1, the maximum number of flips is O, and the maximum number of flips corresponding to each round of flipping is Imax, wherein o≤O.

[0154] Wherein, the maximum number of flips O refers to the maximum number of rounds of flipping of the system bit vector, it should be noted that the maximum number of flips Imax corresponding to the flipping in different rounds is different. For example, the maximum number of flips Imax corresponding to 1 round of flipping is k times, and the maximum number of flips corresponding to 2 rounds of flipping is m times, wherein the value of m is k*(k-1) / 2, that is to say, m is not equal to k.

[0155] It should be noted that the current execution order of step S430 is only an example, and it should be understood that the execution order of step S430 can be before or after any one of the steps before step S480, and it should be understood that the present application does not limit this.

[0156] S440, encoding the system bit vector to obtain a first vector.

[0157] Specifically, the decoding end encodes the system bit vector Through the encoding matrix G to obtain a first vector a0, how the first vector a0 is obtained can be referred to the related description of formula (1) in the foregoing, which will not be repeated here.

[0158] S450, determining the difference value between the first vector and the received vector.

[0159] The decoding end determines the difference value between the first vector a0 and the received vector , which can be denoted as the initial difference value X0, that is, the initial difference value X0 is the difference value between the first vector and the received vector , further, the decoding end determines the first vector a0 as the initial decoding result. It should be understood that the initial difference value X0 can also be referred to as the difference value corresponding to the 0th flip, and the initial decoding result can also be referred to as the decoding result corresponding to the 0th flip, and the present application does not limit this. Wherein, the 0th flip can be understood as not flipping.

[0160] S460, flipping the system bit vector for the oth round, wherein o is an integer greater than or equal to 1.

[0161] In the present application, the number of bits corresponding to the first o-th round of flipping is increased by 1 bit compared to the number of bits corresponding to the (o-1)-th round of flipping, and each round of flipping in the O rounds corresponds to one or more flips, each flip corresponds to a flipped vector, and each flipped vector corresponding to a flip is encoded to obtain an encoded vector.

[0162] It should be noted that step S460 is similar to step S320 described above, and for the sake of simplicity, it will not be described here.

[0163] S470, flip the bits in the system bit vector for the i-th time, and encode the flipped vector corresponding to the i-th flip to obtain the encoded vector corresponding to the i-th flip.

[0164] Specifically, the decoding end flips the system bit vector for the i-th time to obtain the flipped vector corresponding to the i-th flip (or also referred to as the system bit vector after the i-th flip), and encodes the flipped vector corresponding to the i-th flip to obtain the encoded vector corresponding to the i-th flip.

[0165] For example, the encoded vector corresponding to the i-th flip in the O rounds of flipping can be denoted as a i o It should be noted that how the encoded vector a i o corresponding to the i-th flip in the O rounds of flipping is obtained, which can be referred to the related description in step S320 described above.

[0166] S480, determine the difference value between the encoded vector corresponding to the i-th flip and the received vector.

[0167] S490, determine whether the difference value between the encoded vector corresponding to the i-th flip and the received vector is less than the difference value corresponding to the (i-1)-th flip.

[0168] If the difference value between the encoded vector corresponding to the i-th flip and the received vector is less than the difference value corresponding to the (i-1)-th flip, step S4100 is performed.

[0169] If the difference value between the encoded vector corresponding to the i-th flip and the received vector is not less than the difference value corresponding to the (i-1)-th flip, that is, if the difference value between the encoded vector corresponding to the i-th flip and the received vector is greater than or equal to the difference value corresponding to the (i-1)-th flip, step S4110 is performed.

[0170] S4100, determine that the decoding result corresponding to the i-th flip is the encoded vector corresponding to the i-th flip, and the difference value corresponding to the i-th flip is the difference value between the encoded vector corresponding to the i-th flip and the received vector.

[0171] S4110, determine the decoding result corresponding to the i-th flip as the decoding result corresponding to the (i-1)-th flip, and determine the difference value corresponding to the i-th flip as the difference value corresponding to the (i-1)-th flip.

[0172] The difference value corresponding to the (i-1)-th flip can include any one of the following: a difference value between the first encoding vector and the received vector, and a difference value between the first vector and the received vector. The first encoding vector is an encoding vector corresponding to any one of the previous (i-1) flips. It should be noted that the related description of the first encoding vector can be referred to the foregoing description, which will not be repeated here.

[0173] It should be noted that the related examples and corresponding descriptions of the decoding result corresponding to the (i-1)-th flip and the difference value corresponding to the (i-1)-th flip can be referred to the related description in the foregoing step S330, which will not be repeated here.

[0174] S4120, determine whether i is less than or equal to Imax.

[0175] If i is less than Imax, execute step S4130. Otherwise, execute step S4140. For example, if i is equal to Imax, execute step S4140.

[0176] S4130, i=i+1.

[0177] That is, perform the (i+1)-th flip on the system bit vector. It should be noted that how to obtain the decoding result corresponding to the (i+1)-th flip and the difference value corresponding to the (i+1)-th flip can be referred to the obtaining process of the decoding result corresponding to the i-th flip and the difference value corresponding to the i-th flip. By analogy, until the maximum number of flips corresponding to the current round Imax is completed.

[0178] S4140, determine whether o is less than or equal to O.

[0179] If o is less than O, execute step S4150. Otherwise, execute step S4160. For example, if o is equal to O, execute step S4160.

[0180] S4150, o=o+1.

[0181] That is, perform the (o+1)-th flip on the system bit vector. It should be noted that the specific process of the (o+1)-th flip can be referred to the specific process of the o-th flip.

[0182] S4160, stop decoding and output the decoding result corresponding to the last flip as the final decoding result.

[0183] If the o-th round of flipping is the last round of flipping on the systematic bit vector (i.e., o=0), the last round of flipping is performed on the systematic bit vector, and after the last flip in the last round of flipping, decoding is stopped and the decoding result corresponding to the last flip is output as the final decoding result.

[0184] The decoding method provided by the embodiment of the present application is described in detail above.

[0185] An example is given below to help understand the present application.

[0186] For example, the maximum flipping order is set to 3, i.e., the systematic bit vector needs to be flipped for 3 rounds. N=127, i.e., the received vector includes 127 bits, k=106, and the systematic bit vector includes 106 bits.

[0187] In the prior art, the number of times of flipping is 1+127+127*126 / 2+127*126*125 / (2*3)=341504.

[0188] In the technical solution of the present application, however:

[0189] In the first round of flipping, the systematic bit vector needs to be flipped for 106 times.

[0190] In the second round of flipping, the systematic bit vector needs to be flipped for 106*105 / 2 times.

[0191] In the third round of flipping, the systematic bit vector needs to be flipped for 106*105*104 / (2*3) times.

[0192] As can be seen from the above, in the present application, the number of times of flipping can be reduced to 1+106+106*105 / 2+106*105*104 / (2*3)=198592.

[0193] Therefore, the decoding method provided by the present application can reduce the decoding complexity of the guess decoding (the decoding complexity can be understood as the maximum number of times of flipping and / or the average number of times of flipping to find the minimum distance code word).

[0194] FIG. 5 is a schematic flowchart of a decoding method 500 provided by another embodiment of the present application, as shown in FIG. 5, the method at least includes the following steps.

[0195] S510, the decoding end acquires the systematic bit vector.

[0196] Optionally, before step S510, the method further includes: the decoding end receives the received vector.

[0197] It should be noted that step S510 is similar to step S310, and for the sake of simplicity, it is not described here.

[0198] S520, encoding the systematic bit vector to obtain a first vector.

[0199] It should be noted that step S520 is similar to step S440, and for the sake of brevity, will not be described here.

[0200] Optionally, in a possible implementation, the method can further include: S530a, in a case where the difference between the first vector and the received vector is less than a first value, stopping decoding and outputting the first vector as a final decoding result, wherein the first value is one half of a minimum distance d of the code word space formed by the encoding matrix G or corresponding, that is, the first value is d / 2.

[0201] Optionally, in a possible implementation, the method can further include: S530b, in a case where the difference between the first vector and the received vector is not less than the first value, flipping bits in the systematic bit vector i times.

[0202] It should be noted that the difference between the first vector and the received vector is not less than the first value can be understood as the following two cases: the first case, the difference between the first vector and the received vector is greater than the first value; the second case, the difference between the first vector and the received vector is equal to the first value.

[0203] Specifically, in a case where the difference between the first vector and the received vector is not less than the first value, the bits in the systematic bit vector are flipped i times, wherein i is an integer greater than or equal to 1.

[0204] It should be noted that flipping the bits in the systematic bit vector i times can be understood as flipping the bits in the systematic bit vector O rounds based on a flipping order O, O rounds of flipping include i times of flipping, the flipping order O corresponds to n times of flipping, O is an integer greater than or equal to 1, n is an integer greater than 1, and i is less than or equal to n.

[0205] And the number of bits flipped in O rounds of flipping increases by 1 bit per round, and each round of flipping in O rounds of flipping corresponds to one or more flips. Each flip corresponds to a flipped vector, and each flipped vector obtained by encoding corresponds to an encoded vector. For related descriptions of O rounds of flipping, please refer to the foregoing description.

[0206] It should be noted that in a case where i is an integer greater than or equal to 2, the i times of flipping include the i-th flip and the (i-1) times of flipping before the i-th flip, and the (i-1) times of flipping include the j-th flip. Wherein, the j-th flip needs to satisfy: in a case where the difference corresponding to the j-th flip does not satisfy the first condition, the j+1-th flip is performed on the systematic bit vector, j≤(i-1), and j is an integer greater than or equal to 1.

[0207] That is to say, before the i-th flipping of the system bit vector, the system bit vector has experienced j times of flipping, and the difference value corresponding to any one of the j times of flipping does not satisfy the first condition, so that the j+1-th flipping of the system bit vector is performed to realize the i-th flipping of the system bit vector.

[0208] In S540, the decoding result corresponding to the i-th flipping is outputted and the difference value corresponding to the i-th flipping is determined based on the difference value between the encoding vector corresponding to the i-th flipping and the received vector and the first difference value.

[0209] It should be noted that the first difference value needs to be discussed in different cases.

[0210] For example, in one case, when i is equal to 1, the first difference value is the difference value between the first vector and the received vector.

[0211] For example, in another case, when i is greater than or equal to 2, the first difference value includes any one of the following: the difference value between the first encoding vector and the received vector, and the difference value between the first vector and the received vector, wherein the first encoding vector is the encoding vector corresponding to any one of the previous (i-1) times of flipping. For the related description of the first encoding vector, please refer to the foregoing description, which will not be repeated here.

[0212] Optionally, after step S540, the method can further include: S550a, outputting the decoding result corresponding to the i-th flipping as the final decoding result in the case that the difference value corresponding to the i-th flipping is less than the first value.

[0213] Optionally, after step S540, the method can further include: S550b, performing the (i+1)-th flipping on the bits in the system bit vector in the case that the difference value corresponding to the i-th flipping is not less than the first value.

[0214] The steps S540, S550a and S550b will be described in detail below in combination with specific examples.

[0215] Optionally, in a possible implementation, in the case that the difference value between the encoding vector corresponding to the i-th flipping and the received vector is less than the first difference value, the outputted decoding result corresponding to the i-th flipping is the encoding vector corresponding to the i-th flipping, and the determined difference value corresponding to the i-th flipping is the difference value between the encoding vector corresponding to the i-th flipping and the received vector.

[0216] For example, taking o=1, i=1 as an example, at this time, the first difference value is the difference value between the first vector and the received vector (denoted as X0), and the difference value between the encoding vector corresponding to the first flip and the received vector is denoted as X1. Specifically, in the case where the difference value between the encoding vector corresponding to the first flip and the received vector (X1) is less than the first difference value (X0), the decoding result corresponding to the first flip is output as the encoding vector corresponding to the first flip, and it is determined that the difference value corresponding to the first flip is the difference value between the encoding vector corresponding to the first flip and the received vector (X1).

[0217] Further, it is determined whether the determined difference value corresponding to the first flip (X1) is less than the first value to perform subsequent operations.

[0218] For example, in a possible implementation, in the case where the difference value corresponding to the first flip (X1) is less than the first value, the decoding end stops decoding and outputs the decoding result corresponding to the first flip as the final decoding result. That is, in this case, the final decoding result output is the encoding vector corresponding to the first flip.

[0219] For example, in a possible implementation, in the case where the difference value corresponding to the first flip (X1) is not less than the first value, the system bit vector is flipped for the (i+1)th time (i.e., the second flip). It should be noted that in the (i+1)th flip and the ith flip (i.e., in the second flip and the first flip), different bits in the system bit vector are selected to be flipped.

[0220] The specific case of the second flip in the first round of flipping will be described below in combination with a specific example.

[0221] For example, taking o=1, i=2 as an example, at this time, the first difference value includes any one of the following: the difference value between the encoding vector corresponding to the first flip and the received vector (X1), and the difference value between the first vector and the received vector (X0).

[0222] Optionally, taking the first difference value as the difference value between the encoding vector corresponding to the first flip and the received vector (X1) as an example, in the case where the difference value between the encoding vector corresponding to the second flip and the received vector (denoted as X2) is less than the first difference value (X1), the decoding result corresponding to the second flip is output as the encoding vector corresponding to the second flip, and it is determined that the difference value corresponding to the second flip is the difference value between the encoding vector corresponding to the second flip and the received vector (X2).

[0223] Optionally, taking the difference value between the first vector and the received vector (X0) as an example, in a case where the difference value between the second-flipped corresponding encoding vector and the received vector (denoted as X2) is less than the first difference value (X0), the second-flipped corresponding decoding result is output as the second-flipped corresponding encoding vector, and the second-flipped corresponding difference value is determined as the difference value between the second-flipped corresponding encoding vector and the received vector (X2).

[0224] Further, it is determined whether the second-flipped corresponding difference value is less than the first value, so as to perform a subsequent operation.

[0225] For example, in a possible implementation, in a case where the second-flipped corresponding difference value (X2) is less than the first value, the decoding end stops decoding, and outputs the second-flipped corresponding decoding result as the final decoding result. That is, in this case, the final decoding result output is the second-flipped corresponding encoding vector.

[0226] For example, in a possible implementation, in a case where the second-flipped corresponding difference value (X2) is not less than the first value, the system bit vector is flipped for the (i+1)th time (i.e., the third time). It should be noted that the obtaining of the (i+1)th-flipped corresponding decoding result and the (i+1)th-flipped corresponding difference value can refer to the obtaining process of the ith-flipped corresponding decoding result and the ith-flipped corresponding difference value described above.

[0227] Optionally, in a possible implementation, in a case where the difference value between the ith-flipped corresponding encoding vector and the received vector is greater than or equal to the first difference value, the ith-flipped corresponding decoding result output is a first decoding result, and the ith-flipped corresponding difference value determined is the first difference value, where the first decoding result is associated with the first difference value.

[0228] It should be noted that the first decoding result is associated with the first difference value, including the following examples.

[0229] Example 1: In a case where the first difference value is the difference value between the first vector and the received vector, the first decoding result is the first vector.

[0230] Example 2: In a case where the first difference value is the difference value between the first encoding vector and the received vector, the first decoding result is the first encoding vector. The first encoding vector is an encoding vector corresponding to any one of the previous (i-1) times of flipping. For related descriptions of the first encoding vector, refer to the foregoing description, which will not be repeated here.

[0231] The foregoing examples 1 and 2 are described in detail below by taking i=3 as an example.

[0232] In a case where the difference value between the encoding vector corresponding to the third flip and the received vector is greater than or equal to the first difference value, the output decoding result corresponding to the third flip is the first decoding result, and the determined difference value corresponding to the third flip is the first difference value, wherein the first decoding result is associated with the first difference value.

[0233] For example 1: in a case where the first difference value is the difference value (X0) between the first vector and the received vector, the first decoding result is the first vector.

[0234] For example, in a possible implementation, in a case where the difference value (X3) between the encoding vector corresponding to the third flip and the received vector is greater than or equal to the first difference value (X0), the decoding result corresponding to the third flip is output as the first vector, and the difference value corresponding to the third flip is determined as X0.

[0235] Further, it is determined whether the determined difference value (X0) corresponding to the third flip is less than the first value to perform a subsequent operation.

[0236] For example, in a possible implementation, in a case where the difference value (X0) corresponding to the third flip is less than the first value, the decoding end stops decoding and outputs the decoding result corresponding to the third flip as the final decoding result. That is, the output final decoding result is the first vector.

[0237] For example, in a possible implementation, in a case where the difference value (X0) corresponding to the third flip is not less than the first value, the system bit vector is flipped for the (i+1)th time (i.e., the fourth flip). It should be noted that the decoding result corresponding to the (i+1)th flip and the difference value corresponding to the (i+1)th flip can be obtained by referring to the decoding result corresponding to the ith flip and the difference value corresponding to the ith flip described above. Details are not described herein again.

[0238] For example 2: in a case where the first difference value is the difference value between the first encoding vector and the received vector, the decoding result corresponding to the third flip is the first encoding vector. In the case of example 2, the first encoding vector is the encoding vector corresponding to any one of the first two flips. For example, the first encoding vector includes any one of the following: the encoding vector corresponding to the first flip, the encoding vector corresponding to the second flip.

[0239] For example, in one possible implementation, taking the first encoded vector as the encoded vector corresponding to the first flipping, the first difference value is the difference value between the encoded vector corresponding to the first flipping and the received vector (i.e., X1). Specifically, in the case where the difference value (X3) between the encoded vector corresponding to the third flipping and the received vector is greater than or equal to the first difference value (X1), the decoded result corresponding to the third flipping is output as the decoded vector corresponding to the first flipping, and the difference value corresponding to the third flipping is the difference value (X1) between the decoded vector corresponding to the first flipping and the received vector.

[0240] Further, it is determined whether the determined difference value (X1) corresponding to the third flipping satisfies the condition of being less than the first value, so as to perform subsequent operations.

[0241] For example, in one possible implementation, in the case where the difference value (X1) corresponding to the third flipping is less than the first value, the decoding end stops decoding and outputs the decoded result corresponding to the third flipping as the final decoded result. That is, in this case, the final decoded result output is the decoded vector corresponding to the first flipping.

[0242] For example, in one possible implementation, in the case where the difference value (X1) corresponding to the third flipping is not less than the first value, the system bit vector is flipped for the (i+1)th time (i.e., the fourth time).

[0243] For example, in one possible implementation, taking the first encoded vector as the encoded vector corresponding to the second flipping, the first difference value is the difference value between the encoded vector corresponding to the second flipping and the received vector (i.e., X2). Specifically, in the case where the difference value (X3) between the encoded vector corresponding to the third flipping and the received vector is greater than or equal to the first difference value (X2), the decoded result corresponding to the third flipping is output as the decoded vector corresponding to the second flipping, and the difference value corresponding to the third flipping is the difference value (X2) between the decoded vector corresponding to the second flipping and the received vector.

[0244] Further, it is determined whether the determined difference value (X2) corresponding to the third flipping satisfies the condition of being less than the first value, so as to perform subsequent operations.

[0245] For example, in one possible implementation, in the case where the difference value (X2) corresponding to the third flipping is less than the first value, the decoding end stops decoding and outputs the decoded result corresponding to the third flipping as the final decoded result. That is, in this case, the final decoded result output is the decoded vector corresponding to the second flipping.

[0246] Exemplarily, in a possible implementation, in a case where the difference value corresponding to the third flipping is not less than the first value, the i+1th flipping (i.e., the fourth flipping) is performed on the system bit vector.

[0247] Optionally, in a possible implementation, the flipping order O described in the foregoing is less than or equal to the first value.

[0248] That is, the flipping order O is less than or equal to d / 2. Wherein, d is the minimum distance of the code word space formed by or corresponding to the encoding matrix G used for encoding the encoded vector.

[0249] According to the technical solution described above, under the same limitation of the maximum flipping order O, by the method of flipping the bits in the system bit vector round by round, the number of times of flipping for outputting the final decoding result can be less than the number of times of flipping in the prior art, thereby reducing the decoding complexity of the guess decoding. Moreover, the early stopping threshold (the difference value corresponding to the flipping is less than d / 2) can greatly reduce the average number of times of flipping.

[0250] An example of the detailed flow of the decoding method provided in the present application is given below in combination with FIG. 6.

[0251] As shown in FIG. 6, FIG. 6 is a flowchart of a decoding method provided in the present application. The flow shown in FIG. 6 can be performed by a decoding end.

[0252] S610, receiving a received vector.

[0253] S620, obtaining a system bit vector.

[0254] It should be noted that steps S610 and S620 are similar to steps S410 and S420 described in the foregoing, and are not described herein for the sake of simplicity.

[0255] S630, setting o=1, i=1, the maximum flipping order is O, and the maximum number of times of flipping corresponding to each round of flipping is Imax, wherein o≤O.

[0256] Wherein, the maximum flipping order O refers to the maximum number of rounds of flipping of the system bit vector. It should be noted that the maximum number of times of flipping Imax corresponding to different rounds of flipping is different. For example, the maximum number of times of flipping Imax corresponding to 1 round of flipping is k times, and the maximum number of times of flipping corresponding to 2 rounds of flipping is m times, wherein the value of m is k*(k-1) / 2, that is, m is not equal to k.

[0257] It should be noted that the current execution order of step S630 is only an example, and it should be understood that the execution order of step S630 can be before or after any one of the steps before step S680, and it should be understood that the present application does not limit this.

[0258] S640, encode the systematic bit vector to obtain a first vector.

[0259] It should be noted that step S640 is similar to step S440, and for the sake of brevity, will not be repeated here.

[0260] S650, determine a difference value between the first vector and the received vector.

[0261] S660, determine whether the difference value between the first vector and the received vector is less than a first value. The first value is one-half of a minimum distance d of the code word space corresponding to the encoding matrix G. That is, the first value is d / 2.

[0262] If the difference value between the first vector and the received vector is less than the first value, step S670 is performed.

[0263] If the difference value between the first vector and the received vector is not less than the first value, that is, if the difference value between the first vector and the received vector is greater than or equal to the first value, step S680 is performed.

[0264] S670, stop decoding and output the first vector as a final decoding result.

[0265] S680, perform the o-th round of flipping on the systematic bit vector, where o is an integer greater than or equal to 1.

[0266] For example, when o = 1, the first round of flipping is performed on the systematic bit vector; when o = 2, the second round of flipping is performed on the systematic bit vector; and so on.

[0267] It should be noted that the description of the o-th round of flipping can be referred to the foregoing description, and will not be repeated here.

[0268] S690, flip the i-th bit in the systematic bit vector and encode the flipped vector corresponding to the i-th flipping to obtain an encoding vector corresponding to the i-th flipping.

[0269] It should be noted that step S690 is similar to step S470 described above, and for the sake of brevity, will not be repeated here.

[0270] S6100, determine a difference value between the encoding vector corresponding to the i-th flipping and the received vector.

[0271] S6110, determine whether the difference value between the encoding vector corresponding to the i-th flipping and the received vector is less than a first difference value.

[0272] The first difference value needs to be discussed in different cases.

[0273] Exemplarily, in one case, when i equals 1, the first difference value is a difference value between the first vector and the received vector.

[0274] Exemplarily, in another case, when i is greater than or equal to 2, the first difference value comprises any one of a difference value between the first encoding vector and the received vector, and a difference value between the first vector and the received vector, wherein the first encoding vector is an encoding vector corresponding to any one of the previous (i-1) times of flipping.

[0275] If the difference value between the encoding vector corresponding to the i th time of flipping and the received vector is less than the first difference value, step S6120 is performed.

[0276] If the difference value between the encoding vector corresponding to the i th time of flipping and the received vector is not less than the first difference value, that is, if the difference value between the encoding vector corresponding to the i th time of flipping and the received vector is greater than or equal to the first difference value, step S6130 is performed.

[0277] S6120, determining that the decoding result corresponding to the i th time of flipping is the encoding vector corresponding to the i th time of flipping, and the difference value corresponding to the i th time of flipping is the difference value between the encoding vector corresponding to the i th time of flipping and the received vector.

[0278] S6130, determining that the decoding result corresponding to the i th time of flipping is the first decoding result, and the difference value corresponding to the i th time of flipping is the first difference value. The first decoding result is associated with the first difference value.

[0279] It should be noted that the association between the first decoding result and the first difference value includes the following examples.

[0280] Example 1, in the case where the first difference value is the difference value between the first vector and the received vector, the first decoding result is the first vector.

[0281] Example 2, in the case where the first difference value is the difference value between the first encoding vector and the received vector, the first decoding result is the first encoding vector. The first encoding vector is an encoding vector corresponding to any one of the previous (i-1) times of flipping.

[0282] It should be noted that the related description of steps S6120 and S6130 can refer to the related description of step S540 described above, which will not be repeated here.

[0283] S6140, judging whether the difference value corresponding to the i th time of flipping is less than the first value.

[0284] If the difference value corresponding to the i th time of flipping is less than the first value, step S6150 is performed.

[0285] If the difference value corresponding to the i-th flipping is not less than the first value, step S6160 is performed.

[0286] S6150, stopping decoding and outputting the decoding result corresponding to the i-th flipping as the final decoding result.

[0287] S6160, judging whether i is less than or equal to Imax.

[0288] If i is less than Imax, step S6170 is performed. Otherwise, step S6180 is performed. For example, if i is equal to Imax, step S6180 is performed.

[0289] S6170, setting i=i+1.

[0290] That is, the (i+1)-th flipping is performed on the system bit vector. It should be noted that how to obtain the decoding result corresponding to the (i+1)-th flipping and the difference value corresponding to the (i+1)-th flipping can refer to the obtaining process of the decoding result corresponding to the i-th flipping and the difference value corresponding to the i-th flipping described above. In this way, until the maximum number of flipping corresponding to the current round Imax is completed on the system bit vector.

[0291] S6180, judging whether o is less than or equal to O.

[0292] If o is less than O, step S6190 is performed. Otherwise, step S6200 is performed. For example, if o is equal to O, step S6200 is performed.

[0293] S6190, setting o=o+1.

[0294] That is, the (o+1)-th round of flipping is performed on the system bit vector. It should be noted that the specific process of the (o+1)-th round of flipping can refer to the specific process of the o-th round of flipping described above.

[0295] S6200, stopping decoding and outputting the decoding result corresponding to the last flipping as the final decoding result.

[0296] Judging whether the o-th round of flipping is the last round of flipping on the system bit vector (i.e., o=O) and performing the last round of flipping on the system bit vector. After the last flipping in the last round of flipping, decoding is stopped, and the decoding result corresponding to the last flipping is output as the final decoding result.

[0297] The decoding method provided by the another embodiment of the present application is described in detail above.

[0298] The following helps to understand by combining FIG. 7 and FIG. 8.

[0299] Referring to FIG. 7, FIG. 7 is a simulation comparison diagram of BLER of the existing guess decoding method and the guess decoding method provided in the present application. In FIG. 7, taking a bose-chaudhuri-hocquenghem (BCH) code as an example, the code length N = 127, the length k of the system bit vector = 106, M (the original order of the element) = 7, and T = 3 (the maximum correctable bit number, equal to the minimum code distance (d-1) / 2).

[0300] When the maximum flipping order o = 3 is limited:

[0301] As can be seen from FIG. 7, under the same symbol signal-to-noise ratio (EsN0), the decoding error packet rate (BLER) corresponding to the present application is basically the same as or slightly better than the decoding error packet rate (BLER) corresponding to the existing scheme.

[0302] Referring to FIG. 8, FIG. 8 is a simulation comparison diagram of complexity (for example, the average number of flips) of the existing guess decoding method and the guess decoding method provided in the present application. As can be seen from FIG. 8, under the same symbol signal-to-noise ratio (EsN0), the number of flips of the present application is much smaller than that of the existing scheme.

[0303] For example, in the case of a symbol signal-to-noise ratio (EsN0) of 5 dB, the average number of flips of the existing scheme is 2.5 e5 times, while the average number of flips of the present application is only 1.3 e5 times, that is, the average number of flips of the technical scheme of the present application is half of that of the existing scheme.

[0304] Therefore, the decoding method provided in the present application can reduce the decoding complexity of guess decoding.

[0305] The decoding method provided in the present application is described in detail above, and the decoding device provided in the present application is described below. It should be understood that the description of the device embodiment corresponds to the description of the method embodiment, and therefore, the content not described in detail can be referred to the method embodiment described above, and part of the content will not be described again for the sake of brevity.

[0306] Referring to FIG. 9, FIG. 9 is a schematic diagram of a decoding device 900 provided in the present application. As shown in FIG. 9, the decoding device 900 includes a processing unit 910 and a communication unit 920.

[0307] When the decoding device 900 is used to implement the function of the decoding end in the method embodiment shown in FIG. 3:

[0308] The processing unit 910 is configured to obtain a system bit vector.

[0309] The processing unit 910 is further configured to perform O rounds of flipping on bits in the system bit vector based on a flipping order O.

[0310] The communication unit 920 is configured to output a decoding result corresponding to the last flip of the Oth round of flipping as a final decoding result.

[0311] When the decoding apparatus 900 is configured to implement the function of the decoding end in the method embodiment shown in FIG. 5, the processing unit 910 is configured to:

[0312] The processing unit 910 is configured to obtain a system bit vector.

[0313] The processing unit 910 is further configured to flip the bits in the system bit vector i times in a case where a difference value between the first vector and the received vector is greater than or equal to a first value.

[0314] The processing unit 910 is further configured to output a decoding result corresponding to the i-th flip and determine a difference value corresponding to the i-th flip based on a difference value between the encoding vector corresponding to the i-th flip and the received vector and the first difference value.

[0315] The communication unit 920 is configured to:

[0316] In a case where the difference value corresponding to the i-th flip is less than the first value, output the decoding result corresponding to the i-th flip as a final decoding result; or,

[0317] In a case where the difference value corresponding to the i-th flip is greater than or equal to the first value, flip the bits in the system bit vector (i+1) times.

[0318] Optionally, in some embodiments, the processing unit 910 is further configured to, in a case where the difference value between the first vector and the received vector is less than the first value, output the first vector as a final decoding result.

[0319] Optionally, in some embodiments, the processing unit 910 is specifically configured to flip the bits in the system bit vector O rounds of flipping based on a flipping order O, the O rounds of flipping including i flips, the flipping order O corresponding to n flips, O being an integer greater than or equal to 1, n being an integer greater than 1, and i being less than or equal to n.

[0320] In one possible design, the above functions of the decoding apparatus 900 can be implemented by hardware, or by executing corresponding software by hardware.

[0321] As an example, the decoding apparatus 900 can include one or more processors configured to execute a computer program stored in a memory, so that the decoding apparatus 900 performs any one of the method embodiments provided in the present application.

[0322] Optionally, the memory for storing the computer program is located outside the decoding apparatus 900, and the one or more processors are connected with the memory through circuit and / or wire. The memory can be one or more.

[0323] Optionally, the decoding apparatus 900 further comprises one or more memories.

[0324] Further optionally, the decoding apparatus 900 further comprises one or more communication interfaces.

[0325] As some examples, the one or more communication interfaces can be input / output interface, or output interface circuit, which are not limited in the present application.

[0326] As another embodiment, the decoding apparatus 900 can also be implemented by hardware.

[0327] Referring to FIG. 10, FIG. 10 is a schematic structural diagram of the decoding apparatus 900 provided in the present application. As shown in FIG. 10, the decoding apparatus 900 comprises input interface circuit 901, logic circuit 902 and output interface circuit 903.

[0328] When the decoding apparatus 900 is used to implement the function of the decoding end in the method embodiment shown in FIG. 5, the input interface circuit 901 obtains the system bit vector; the logic circuit 902 is configured to perform o rounds of flipping on the bits in the system bit vector based on the flipping order o; and the output interface circuit 903 is configured to output the decoding result corresponding to the last flipping in the oth round of flipping as the final decoding result.

[0329] When the decoding apparatus 900 is used to implement the function of the decoding end in the method embodiment shown in FIG. 5, the input interface circuit 901 obtains the system bit vector; the logic circuit 902 is configured to perform i times of flipping on the bits in the system bit vector in the case that the difference value between the first vector and the received vector is greater than or equal to the first value; and output the decoding result corresponding to the ith flipping, and determine the difference value corresponding to the ith flipping, based on the difference value between the encoding vector corresponding to the ith flipping and the received vector, and the first difference value; and the output interface circuit 903 is configured to output the decoding result corresponding to the ith flipping as the final decoding result in the case that the difference value corresponding to the ith flipping is less than the first value.

[0330] When the decoding apparatus 900 is used to implement the function of the decoding end in the method embodiment shown in FIG. 5, the input interface circuit 901 obtains the system bit vector; the logic circuit 902 is configured to perform i times of flipping on the bits in the system bit vector in the case that the difference value between the first vector and the received vector is greater than or equal to the first value; and output the decoding result corresponding to the ith flipping, and determine the difference value corresponding to the ith flipping, based on the difference value between the encoding vector corresponding to the ith flipping and the received vector, and the first difference value; and the output interface circuit 903 is configured to output the decoding result corresponding to the ith flipping as the final decoding result in the case that the difference value corresponding to the ith flipping is less than the first value.

[0331] When the decoding apparatus 900 is used to implement the function of the decoding end in the method embodiment shown in FIG. 5, the input interface circuit 901 obtains the system bit vector; the logic circuit 902 is configured to perform i times of flipping on the bits in the system bit vector in the case that the difference value between the first vector and the received vector is greater than or equal to the first value; and output the decoding result corresponding to the ith flipping, and determine the difference value corresponding to the ith flipping, based on the difference value between the encoding vector corresponding to the ith flipping and the received vector, and the first difference value; and the output interface circuit 903 is configured to output the decoding result corresponding to the ith flipping as the final decoding result in the case that the difference value corresponding to the ith flipping is less than the first value.

[0332] Optionally, the decoding apparatus 900 can be a chip or an integrated circuit. For example, the chip can be a system on chip (SOC), or a baseband chip, etc.

[0333] Optionally, the decoding apparatus 900 can also be a device or module for implementing channel decoding in the decoding end. For example, a channel decoder or a channel decoding circuit, etc.

[0334] FIG. 11 is a schematic structural diagram of a decoder 1000 according to an embodiment of the present application. As shown in FIG. 11, the decoder 1000 includes one or more processors 1100, one or more memories 1200, and one or more communication interfaces 1300. The communication interface 1300 is configured to obtain a system bit vector, the memory 1200 is configured to store a computer program, and the processor 1100 is configured to call and run the computer program from the memory 1200, so that the decoder 1000 completes decoding by using the decoding method provided in the present application.

[0335] Further, the communication interface 1300 is further configured to output a final decoding result.

[0336] In addition, the decoding apparatus 900 shown in FIG. 9 can be implemented by the decoder 1000 shown in FIG. 11.

[0337] For example, the communication unit 930 can be implemented by the communication interface 1300 in FIG. 11, the processing unit 910 can be implemented by the processor 1100, etc.

[0338] Optionally, the memory and the processor in the apparatus embodiment can be integrated together, or can be physically separate units from each other.

[0339] In addition, the present application also provides a decoding apparatus, including a processor and an interface circuit, the interface circuit is configured to receive computer code or instructions, and transmit to the processor, the processor is configured to run the computer code or instructions, so as to execute the rearrangement decoding method of the polar code provided in the present application.

[0340] In addition, the present application provides a computer readable storage medium, the computer readable storage medium stores a computer program, when the computer program runs on the computer, so that the decoding method of the present application is realized.

[0341] The present application also provides a computer program product, the computer program product includes computer program code, when the computer program code runs on the computer, so that the decoding method of the present application is realized.

[0342] The present application also provides a chip, including one or more memories and one or more processors. The one or more memories are configured to store a computer program, and the one or more processors are configured to call and run the computer program from the one or more memories, so that the device installed with the chip executes the decoding method of the present application.

[0343] The application also provides a communication device, comprising the decoder 1000.

[0344] The decoding end in the present application is the receiving end of signals and / or data. Correspondingly, the sending end is the sending end of signals and / or data. Alternatively, the decoding end can be a network device (for example, a gNB of 5G or a gNB of 6G) in a communication system (including a future communication system), or a terminal device, and the scheme of the present application is not limited.

[0345] In the above embodiments, the processor can be a central processing unit (CPU), a general-purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, a microprocessor, or one or more integrated circuits for controlling the execution of programs of the present application, etc. For example, the processor can include a digital signal processor device, a microprocessor device, an analog-to-digital converter, a digital-to-analog converter, etc. The processor can distribute the functions of control and signal processing of the mobile device among these devices according to their respective functions. In addition, the processor can include the function of operating one or more software programs, which can be stored in the memory. The functions of the processor can be implemented by hardware or by executing corresponding software by hardware. The hardware or software includes one or more units corresponding to the above functions.

[0346] The memory can be a read-only memory (ROM) or other type of static storage device that can store static information and instructions, a random access memory (RAM) or other type of dynamic storage device that can store information and instructions, an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disk storage, a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer.

[0347] The terms "component," "module," "system" and the like are used to generally refer to computer-related entities, hardware, firmware, a combination of hardware and software, software, or software in execution. For example, a component can be a process running on a processor, a processor, an object, an executable, a thread of execution, a program, and / or a computer. Both an application running on a computing device and the computing device can be a component. One or more components can reside within a process and / or thread of execution. A component can be localized, co-resident, or distributed, among one computer or distributed across several computers or other devices. Also, these components can execute from various computer-readable media having various data structures stored thereon. The components can communicate via local and / or remote processes such as in accordance with a signal having one or more data packets (e.g., data from one component interacting with another component in a local system, distributed system, and / or across a network such as the Internet with other systems via the signal).

[0348] Those skilled in the art can clearly understand that the units and algorithm steps of the examples described in combination with the embodiments disclosed herein can be realized by electronic hardware or a combination of computer software and electronic hardware. Whether the functions are realized in hardware or software depends on the specific application and design constraints of the technical solution. The skilled person can use different methods to realize the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0349] Those skilled in the art can clearly understand that, for the convenience and brevity of the description, the specific working processes of the above-described system, device and unit can refer to the corresponding processes in the foregoing method embodiments, which will not be described here.

[0350] In several embodiments provided in the present application, it should be understood that the disclosed system, device and method can be realized by other ways. For example, the above-described device embodiments are only schematic, for example, the division of the units is only a logical function division, and actual implementation can have another division manner, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the shown or discussed units can be indirect coupling or communication connection through some interface, device or unit, and can be electrical, mechanical or other forms.

[0351] The units described as separate components can or can not be physically separate, and the components shown as units can or can not be physical units, i.e. can be located in one place or distributed on a plurality of network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

[0352] In addition, each functional unit in each embodiment of the present application can be integrated in one processing unit, or each unit can exist physically, or two or more units can be integrated in one unit.

[0353] If the functions are realized in the form of software functional units and sold or used as independent products, they can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application or the parts of the technical solutions that essentially contribute to the prior art can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in each embodiment of the present application. The aforementioned storage medium includes a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various media that can store program codes.

[0354] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A decoding method, comprising: The method comprises the following steps: obtaining a system bit vector, the system bit vector being composed of the first bit to the kth bit in the received vector, k being an integer greater than or equal to 1; performing O rounds of flipping on the bits in the system bit vector based on a flipping order O, the number of flipped bits corresponding to the O rounds of flipping increasing by 1 bit round by round, each round of flipping in the O rounds of flipping corresponding to one or more times of flipping, each time of flipping corresponding to a flipped vector, and each flipped vector corresponding to one encoded vector obtained through encoding, wherein O is an integer greater than or equal to 1; outputting a decoding result corresponding to the last time of flipping in the Oth round of flipping as a final decoding result; wherein the decoding result corresponding to the ith time of flipping in the O rounds of flipping satisfies the following conditions: in the case where the difference between the encoded vector corresponding to the ith time of flipping and the received vector is less than the difference corresponding to the (i-1)th time of flipping, the decoding result corresponding to the ith time of flipping is the encoded vector corresponding to the ith time of flipping; and in the case where the difference between the encoded vector corresponding to the ith time of flipping and the received vector is greater than or equal to the difference corresponding to the (i-1)th time of flipping, the decoding result corresponding to the ith time of flipping is the decoding result corresponding to the (i-1)th time of flipping, the decoding result corresponding to the (i-1)th time of flipping being associated with the difference corresponding to the (i-1)th time of flipping; wherein the difference corresponding to the (i-1)th time of flipping includes any one of the following: the difference between a first encoded vector and the received vector, and the difference between a first vector and the received vector, the first encoded vector being an encoded vector corresponding to any one of the first (i-1) times of flipping, the first vector being obtained by encoding the system bit vector, i being an integer greater than or equal to 1; wherein the decoding result corresponding to the first time of flipping is obtained based on the difference between the encoded vector corresponding to the first time of flipping and the received vector, and the difference between the first vector and the received vector.

2. The method of claim 1, wherein, the decoding result corresponding to the (i-1)th time of flipping being associated with the difference corresponding to the (i-1)th time of flipping includes: in the case where the difference corresponding to the (i-1)th time of flipping is the difference between the first vector and the received vector, the decoding result corresponding to the (i-1)th time of flipping is the first vector; and in the case where the difference corresponding to the (i-1)th time of flipping is the difference between the first encoded vector and the received vector, the decoding result corresponding to the (i-1)th time of flipping is the first encoded vector.

3. The method according to claim 1 or 2, characterized in that, The method comprises the following steps: in the case where the difference between the encoded vector corresponding to the first time of flipping and the received vector is less than the difference between the first vector and the received vector, the decoding result corresponding to the first time of flipping is the encoded vector corresponding to the first time of flipping; and in the case where the difference between the encoded vector corresponding to the first time of flipping and the received vector is greater than or equal to the difference between the first vector and the received vector, the decoding result corresponding to the first time of flipping is the first vector.

4. The method according to any one of claims 1 to 3, characterized in that, The number of times of flipping O is less than or equal to a first value, wherein the first value is one half of a minimum distance of a code word space corresponding to a code matrix used for encoding the encoded vector.

5. A decoding method, comprising: Comprise: Obtaining a system bit vector, the system bit vector being composed of 1st bit to kth bit in a received vector, k being an integer greater than or equal to 1; In a case where a difference value between the first vector and the received vector is greater than or equal to a first value, performing i times of flipping on bits in the system bit vector, each time of flipping corresponding to a flipped vector, each flipped vector being obtained by encoding, the first vector being obtained by encoding the system bit vector by a code matrix, the first value being one half of a minimum distance of a code word space corresponding to the code matrix, wherein i is an integer greater than or equal to 1; Based on a difference value between the i-th flipped vector and the received vector and a first difference value, outputting a decoding result corresponding to the i-th flipped vector and determining the difference value corresponding to the i-th flipped vector; In a case where the difference value corresponding to the i-th flipped vector is less than the first value, outputting the decoding result corresponding to the i-th flipped vector as a final decoding result; and, In a case where the difference value corresponding to the i-th flipped vector is greater than or equal to the first value, performing (i+1)th flipping on the bits in the system bit vector; Wherein, In a case where i is equal to 1, the first difference value is the difference value between the first vector and the received vector; and, In a case where i is greater than or equal to 2, the first difference value comprises any one of the following: A difference value between a first encoded vector and the received vector, the difference value between the first vector and the received vector, the first encoded vector being an encoded vector corresponding to any one of the previous (i-1) times of flipping.

6. The method of claim 5, wherein, In a case where i is an integer greater than or equal to 2, the i times of flipping comprises the i-th flipping and (i-1) times of flipping before the i-th flipping; The j-th flipping in the (i-1) times of flipping satisfies: In a case where the difference value corresponding to the j-th flipping is less than the first value, performing (j+1)th flipping on the bits in the system bit vector, j≤(i-1), and j being an integer greater than or equal to 1.

7. The method according to claim 5 or 6, characterized in that, The method of claim 1, wherein the outputting the decoding result corresponding to the i-th flipped vector and the determining the difference value corresponding to the i-th flipped vector based on the difference value between the i-th flipped vector and the received vector and the first difference value comprises: In a case where the difference value between the i-th flipped vector and the received vector is less than the first difference value, the outputted decoding result corresponding to the i-th flipped vector being the i-th flipped vector, and the determined difference value corresponding to the i-th flipped vector being the difference value between the i-th flipped vector and the received vector; and, In a case where a difference value between the i-th flipping corresponding encoding vector and the receiving vector is greater than or equal to the first difference value, the i-th flipping corresponding decoding result output is a first decoding result, and the i-th flipping corresponding difference value determined is the first difference value, wherein the first decoding result is associated with the first difference value.

8. The method of claim 7, wherein, The first decoding result is associated with the first difference value, including: In a case where the first difference value is a difference value between the first vector and the receiving vector, the first decoding result is the first vector; and In a case where the first difference value is a difference value between the first encoding vector and the receiving vector, the first decoding result is the first encoding vector.

9. The method according to any one of claims 5 to 8, characterized in that, The method further includes: In a case where a difference value between the first vector and the receiving vector is less than the first value, outputting the first vector as a final decoding result.

10. The method according to any one of claims 5 to 9, characterized in that, The i times flipping of the bits in the systematic bit vector includes: O rounds of flipping of the bits in the systematic bit vector based on a flipping order O, the O rounds of flipping including i times flipping, the flipping order O corresponding to n times flipping, O being an integer greater than or equal to 1, n being an integer greater than 1, and i being less than or equal to n, A number of flipped bits corresponding to the O rounds of flipping increases by 1 bit round by round, and each round of flipping in the O rounds of flipping corresponds to one or more times of flipping.

11. The method of claim 10, wherein, The flipping order O is less than or equal to the first value.

12. A decoding device, comprising: Including: A processing unit configured to: Obtain a systematic bit vector composed of the 1st bit to the kth bit in a receiving vector, k being an integer greater than or equal to 1; O rounds of flipping of the bits in the systematic bit vector based on a flipping order O, a number of flipped bits corresponding to the O rounds of flipping increasing by 1 bit round by round, and each round of flipping in the O rounds of flipping corresponding to one or more times of flipping, each time of flipping corresponding to a flipped backward vector, and each flipped backward vector being encoded to obtain an encoding vector, wherein O is an integer greater than or equal to 1; A communication unit configured to output a decoding result corresponding to a last time of flipping in the Oth round of flipping in the O rounds of flipping as a final decoding result; The decoding result corresponding to the i-th flipping satisfies the following conditions: In a case where a difference value between the i-th flipping corresponding encoding vector and the receiving vector is less than a difference value corresponding to the (i-1)-th flipping, the i-th flipping corresponding decoding result is the i-th flipping corresponding encoding vector; and In a case where a difference value between the i-th flipping corresponding encoding vector and the receiving vector is greater than or equal to the difference value corresponding to the (i-1)-th flipping, the i-th flipping corresponding decoding result is the (i-1)-th flipping corresponding decoding result, and the (i-1)-th flipping corresponding decoding result is associated with the difference value corresponding to the (i-1)-th flipping; The difference value corresponding to the (i-1)-th flipping includes any one of the following: a difference value between the first encoding vector and the received vector, and a difference value between the first vector and the received vector, the first encoding vector being an encoding vector corresponding to any one of the first (i-1) flips, the first vector being obtained by encoding the systematic bit vector, i being an integer greater than or equal to 1; wherein the decoding result corresponding to the first flip is obtained based on a difference value between the encoding vector corresponding to the first flip and the received vector, and a difference value between the first vector and the received vector.

13. The coding device of claim 12, wherein, The processing unit is specifically configured to: in a case where the difference value corresponding to the (i-1)th flip is the difference value between the first vector and the received vector, the decoding result corresponding to the (i-1)th flip is the first vector; and in a case where the difference value corresponding to the (i-1)th flip is the difference value between the first encoding vector and the received vector, the decoding result corresponding to the (i-1)th flip is the first encoding vector.

14. The decoding device of claim 12 or 13, wherein, in a case where the difference value between the encoding vector corresponding to the first flip and the received vector is less than the difference value between the first vector and the received vector, the decoding result corresponding to the first flip is the encoding vector corresponding to the first flip; and in a case where the difference value between the encoding vector corresponding to the first flip and the received vector is greater than or equal to the difference value between the first vector and the received vector, the decoding result corresponding to the first flip is the first vector.

15. The coding apparatus according to any one of claims 12 to 14, characterized in that, the flip order O is less than or equal to a first value, wherein the first value is one half of a minimum distance of a code word space corresponding to or formed by an encoding matrix used for encoding the encoded vector.

16. A decoding device, comprising: comprising: a processing unit configured to: obtain a systematic bit vector, the systematic bit vector being composed of a first bit to a kth bit in a received vector, k being an integer greater than or equal to 1; in a case where a difference value between a first vector and the received vector is greater than or equal to a first value, perform i flips on bits in the systematic bit vector, each flip corresponding to a flipped vector, each flipped vector being encoded to obtain an encoding vector, the first vector being obtained by encoding the systematic bit vector using an encoding matrix, the first value being one half of a minimum distance of a code word space corresponding to or formed by the encoding matrix, i being an integer greater than or equal to 1; output a decoding result corresponding to the i-th flip based on a difference value between the encoding vector corresponding to the i-th flip and the received vector, and the first difference value, and determine the difference value corresponding to the i-th flip; a communication unit configured to: in a case where the difference value corresponding to the i-th flip is less than the first value, output the decoding result corresponding to the i-th flip as a final decoding result; and in a case where the difference value corresponding to the i-th flip is greater than or equal to the first value, perform an (i+1)th flip on the bits in the systematic bit vector; wherein when i is equal to 1, the first difference value is the difference value between the first vector and the received vector; and when i is greater than 1, the first difference value is the difference value between the encoding vector corresponding to the (i-1)th flip and the received vector. The first difference value comprises any one of the following when i is greater than or equal to 2: A difference value between the first encoding vector and the received vector, a difference value between the first vector and the received vector, the first encoding vector being a corresponding encoding vector of any one of the previous (i-1) times of flipping.

17. The decoding apparatus of claim 16, wherein, The i times of flipping comprises the i th time of flipping and (i-1) times of flipping before the i th time of flipping when i is an integer greater than or equal to 2; The j th time of flipping in the (i-1) times of flipping satisfies: In a case where the difference value corresponding to the j th time of flipping is less than the first value, performing a (j+1) th time of flipping on the bits in the systematic bit vector, j≤(i-1), and j is an integer greater than or equal to 1.

18. The decoding device of claim 16 or 17, wherein, The processing unit is specifically configured to: In a case where the difference value between the encoding vector corresponding to the i th time of flipping and the received vector is less than the first difference value, outputting the decoding result corresponding to the i th time of flipping as the encoding vector corresponding to the i th time of flipping, and determining the difference value corresponding to the i th time of flipping as the difference value between the encoding vector corresponding to the i th time of flipping and the received vector; and, In a case where the difference value between the encoding vector corresponding to the i th time of flipping and the received vector is greater than or equal to the first difference value, outputting the decoding result corresponding to the i th time of flipping as a first decoding result, and determining the difference value corresponding to the i th time of flipping as the first difference value, wherein the first decoding result is associated with the first difference value.

19. The coding device of claim 18, wherein, The processing unit is specifically configured to: In a case where the first difference value is the difference value between the first vector and the received vector, the first decoding result is the first vector; and, In a case where the first difference value is the difference value between the first encoding vector and the received vector, the first decoding result is the first encoding vector.

20. The coding apparatus according to any one of claims 16 to 19, characterized in that, The communication unit is further configured to: In a case where the difference value between the first vector and the received vector is less than the first value, outputting the first vector as a final decoding result.

21. The coding apparatus according to any one of claims 16 to 20, characterized in that, The processing unit is specifically configured to: Performing O rounds of flipping on the bits in the systematic bit vector based on a flipping order O, the O rounds of flipping comprising i times of flipping, the flipping order O corresponding to n times of flipping, O being an integer greater than or equal to 1, n being an integer greater than 1, and i being less than or equal to n, A number of flipped bits corresponding to the O rounds of flipping increases by 1 bit round by round, and each round of flipping in the O rounds of flipping corresponds to one or more times of flipping.

22. The coding apparatus according to any one of claims 16 to 21, wherein, The flipping order O is less than or equal to the first value.

23. A decoding device, comprising: The decoding apparatus comprises at least one processor coupled with at least one memory, and the at least one processor is configured to execute a computer program or instructions stored in the at least one memory, so that the decoding apparatus performs the method of any one of claims 1 to 4 or performs the method of any one of claims 5 to 11.

24. A decoding device, comprising: comprising a processor and interface circuitry for receiving computer code or instructions and transmitting to the processor for execution of the computer code or instructions to perform the method of any one of claims 1 to 4 or to perform the method of any one of claims 5 to 11.

25. A computer readable storage medium having stored thereon a computer program or instructions, characterized in that, The computer program or instructions, when executed by a processor, cause the method of any one of claims 1 to 4 to be implemented or the method of any one of claims 5 to 11 to be implemented.

26. A computer program product comprising instructions, wherein: The computer program or instructions, when executed by a processor, cause the method of any one of claims 1 to 4 to be implemented or the method of any one of claims 5 to 11 to be implemented.

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