Clock synchronization system

Abstract

A clock synchronization (SYNC) system. The clock SYNC system comprises a trigger group (110) and a frequency divider group (120); the trigger group (110) comprises N triggers; the frequency divider group (120) comprises N frequency dividers; and the trigger group (110) receives N clock signals and one SYNC pulse signal, respectively transmits the N clock signals to the N frequency dividers, and respectively transmits to the N frequency dividers the N pulse signals outputted by the trigger group (110), wherein N is a positive integer greater than 1.

Description

Clock synchronization system

[0001] This application claims priority to the Chinese patent application No. 202410727626.6, filed on June 6, 2024, with the Chinese Patent Office, the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] Embodiments of the present application relate to the technical field of digital circuit, for example, to a clock synchronization system. BACKGROUND

[0003] The multi-phase clock can be used in application occasions requiring clock interleaving, such as time-interleaved analog-to-digital converters (ADCs), time-to-digital converter (TDC) modules, etc.

[0004] The clock synchronization system of the related art is usually implemented by synchronizing multiple clock signals simultaneously through one synchronization (SYNC) pulse signal, or by inputting multiple delay-adjustable SYNC pulse signals into multiple frequency dividers respectively.

[0005] In the way of synchronizing multiple clock signals simultaneously through one SYNC pulse signal, the rising edge of the SYNC pulse signal and one of the clock signals can be very close, which can cause the phase of the clock signal to be unstable.

[0006] In the way of inputting multiple delay-adjustable SYNC pulse signals into multiple frequency dividers respectively, the area and power consumption can be greatly increased. SUMMARY

[0007] Embodiments of the present application provide a clock synchronization system, which can reduce the risk of generating metastable states while reducing power consumption.

[0008] According to an aspect of the present application, a clock synchronization system is provided, which includes a flip-flop group and a frequency divider group, the flip-flop group including N flip-flops, and the frequency divider group including N frequency dividers.

[0009] The flip-flop group receives N clock signals and one SYNC pulse signal, transmits the N clock signals to the N frequency dividers respectively, and transmits the N SYNC pulse signals output by the flip-flop group to the N frequency dividers respectively, N being a positive integer greater than 1.

[0010] In some embodiments, the input of one flip-flop in the flip-flop group is a SYNC pulse signal and a corresponding clock signal, and the input of the rest of the flip-flops is a corresponding clock signal of a current flip-flop and a SYNC pulse signal output by an associated flip-flop, wherein the associated flip-flop is a flip-flop other than the current flip-flop in the flip-flop group, the phase difference between the rising edge of the SYNC pulse signal output by the associated flip-flop and the rising edge of the corresponding clock signal of the current flip-flop is greater than a difference threshold, and the corresponding associated flip-flop of each of the rest of the flip-flops is different.

[0011] In some embodiments, the input of each frequency divider is a SYNC pulse signal output by a corresponding flip-flop and a corresponding clock signal.

[0012] In some embodiments, the clock synchronization system further comprises a delay adjustment circuit.

[0013] The input of one flip-flop in the flip-flop group is a SYNC pulse signal and a corresponding clock signal, and the input of the rest of the flip-flops is a corresponding clock signal of a current flip-flop and a SYNC pulse signal output by a corresponding delay adjustment circuit, and the input of the delay adjustment circuit is a SYNC pulse signal output by a target flip-flop, wherein the target flip-flop is a flip-flop other than the current flip-flop in the flip-flop group, the phase difference between the rising edge of the SYNC pulse signal output by the corresponding delay adjustment circuit and the rising edge of the corresponding clock signal of the current flip-flop is greater than a difference threshold, and the corresponding target flip-flop of each of the rest of the flip-flops is different.

[0014] In some embodiments, the clock synchronization system further comprises a delay adjustment circuit.

[0015] The input of one flip-flop in the flip-flop group is a SYNC pulse signal and a corresponding clock signal, and the rest of the flip-flops include a first type of flip-flop and a second type of flip-flop, and the phase difference between the rising edge of the SYNC pulse signal output by at least one flip-flop in the flip-flop group and the rising edge of a corresponding clock signal of the first type of flip-flop is greater than a difference threshold, and the phase difference between the rising edge of the SYNC pulse signal output by any flip-flop in the flip-flop group and the rising edge of a corresponding clock signal of the second type of flip-flop is less than or equal to the difference threshold.

[0016] The input of the first type of flip-flop is a corresponding clock signal of a current flip-flop and a SYNC pulse signal output by a corresponding previous-stage flip-flop, wherein the corresponding previous-stage flip-flop of the first type of flip-flop is a flip-flop in the flip-flop group whose output SYNC pulse signal has a phase difference greater than a difference threshold with a corresponding clock signal of the first type of flip-flop.

[0017] The input of the second type of flip-flop is a clock signal corresponding to the current flip-flop and a SYNC pulse signal output by the delay adjustment circuit corresponding to the current flip-flop, and the input of the delay adjustment circuit is a SYNC pulse signal output by a previous flip-flop corresponding to the second type of flip-flop, wherein the previous flip-flop corresponding to the second type of flip-flop is a flip-flop whose phase difference between the rising edge of the output SYNC pulse signal and the rising edge of the clock signal corresponding to the second type of flip-flop is less than or equal to the difference threshold value.

[0018] The previous flip-flop corresponding to each of the remaining flip-flops is different.

[0019] In some embodiments, the delay adjustment circuit comprises a buffer.

[0020] In some embodiments, the clock synchronization system further comprises an inverter.

[0021] The output of the target frequency divider in the frequency divider group is connected to the input of the corresponding inverter, and the frequency-divided clock signal output by the target frequency divider needs to be phase-inverted.

[0022] In some embodiments, the clock phases of the N clock signals are different.

[0023] In some embodiments, the flip-flop is a CML flip-flop.

[0024] In some embodiments, the difference threshold value is determined according to the setup time and the hold time of the flip-flop. BRIEF DESCRIPTION OF DRAWINGS

[0025] FIG. 1 is a structural schematic diagram of a clock synchronization system in an embodiment of the present application;

[0026] FIG. 2 is a circuit timing diagram in an embodiment of the present application;

[0027] FIG. 3 is a circuit structural schematic diagram in an embodiment of the present application;

[0028] FIG. 4 is an output result timing diagram in an embodiment of the present application;

[0029] FIG. 5 is another circuit structural schematic diagram in an embodiment of the present application, in which three clock adjustment circuits are added;

[0030] FIG. 6 is another circuit structural schematic diagram in an embodiment of the present application, in which one clock adjustment circuit is added;

[0031] FIG. 7 is another circuit structural schematic diagram in an embodiment of the present application, in which an inverter is added. DETAILED DESCRIPTION

[0032] The terms "first", "second", and the like, as used in the specification and claims of the application and in the above Abstract, are used for distinguishing between similar objects and are not necessarily used to describe a particular sequential or chronological order. It is to be understood that the use of the terms so construed can interchange depending on the context in which it is used. It is also to be understood that the term "or" as used herein is used in the inclusive sense, and not the exclusive sense, unless otherwise specifically indicated. Additionally, the terms "include," "have," and "comprise" and their conjugates, as used in the specification and claims of the application, are used in the inclusive sense, such that any process, method, system, product, or apparatus that includes a list of steps or elements, or a list of steps or elements followed by other steps or elements, can include other steps or elements not expressly listed or other steps or elements that are inherent in the process, method, system, product, or apparatus. Furthermore, the term "comprising" does not exclude the presence of elements or steps other than those listed in a process, method, system, product, or apparatus, even if the other elements or steps are not expressly listed.

[0033] Before using the technical solutions disclosed in the embodiments of the present disclosure, the type of personal information involved in the present disclosure, the scope of use, the scenario of use, etc. should be informed to the user and the authorization of the user should be obtained according to relevant laws and regulations.

[0034] FIG. 1 is a structural schematic diagram of a clock synchronization system according to an embodiment of the present application. As shown in FIG. 1, the clock synchronization system comprises a flip-flop group 110 and a frequency divider group 120. The flip-flop group 110 comprises N flip-flops, and the frequency divider group 120 comprises N frequency dividers.

[0035] The flip-flop group 110 receives N clock signals and a SYNC pulse signal, and transmits the N clock signals to the N frequency dividers respectively, and transmits the N SYNC pulse signals output by the flip-flop group 110 to the N frequency dividers respectively. N is a positive integer greater than 1.

[0036] The flip-flop can be a current mode logic (CML) flip-flop, or a complementary metal-oxide-semiconductor (CMOS) flip-flop.

[0037] For example, as shown in FIG. 1, the flip-flop group 110 comprises N flip-flops (a first flip-flop, …, an Nth flip-flop), and the frequency divider group 120 comprises N frequency dividers (a first frequency divider, …, an Nth frequency divider). A SYNC pulse signal is input to the flip-flop group 110, the SYNC pulse signal output by the first flip-flop and a first clock signal are input to the first frequency divider, and the SYNC pulse signal output by the Nth flip-flop and an Nth clock signal are input to the Nth frequency divider.

[0038] Optionally, the input of one flip-flop in the flip-flop group 110 is a SYNC pulse signal and a corresponding clock signal, and the input of the rest of the flip-flops is the SYNC pulse signal output by the associated flip-flop and the corresponding clock signal, wherein the associated flip-flop is a flip-flop other than the current flip-flop in the flip-flop group 110, the phase difference between the rising edge of the SYNC pulse signal output by the associated flip-flop and the rising edge of the corresponding clock signal of the current flip-flop is greater than the difference threshold, and the corresponding associated flip-flop of each of the rest of the flip-flops is different.

[0039] The SYNC pulse signal and the corresponding clock signal as the input of any flip-flop in the flip-flop group 110, for example, if the SYNC pulse signal is used as the input of the first flip-flop in the flip-flop group 110, the input of the first flip-flop includes the SYNC pulse signal and the corresponding clock signal of the first flip-flop.

[0040] Optionally, the SYNC pulse signal input by each of the rest of the flip-flops in the flip-flop group 110 is the SYNC pulse signal output by another flip-flop. The phase difference between the rising edge of the SYNC pulse signal output by the flip-flop and the rising edge of the corresponding clock signal of the current flip-flop is greater than the difference threshold.

[0041] Optionally, the SYNC pulse signal input by each of the rest of the flip-flops in the flip-flop group 110 is the SYNC pulse signal output by another flip-flop. The phase difference between the rising edge of the SYNC pulse signal output by the flip-flop and the rising edge of the corresponding clock signal of the current flip-flop is greater than the difference threshold.

[0042] In some embodiments, the flip-flop group 110 includes four flip-flops. The input of the first flip-flop is a SYNC pulse signal and a first clock signal. The input of the second flip-flop is the SYNC pulse signal output by the first flip-flop and a second clock signal, and the phase difference between the rising edge of the SYNC pulse signal output by the first flip-flop and the rising edge of the second clock signal is greater than the difference threshold. The input of the third flip-flop is a third clock signal and the SYNC pulse signal output by the second flip-flop, and the phase difference between the rising edge of the SYNC pulse signal output by the second flip-flop and the rising edge of the third clock signal is greater than the difference threshold. The input of the fourth flip-flop is a fourth clock signal and the SYNC pulse signal output by the third flip-flop, and the phase difference between the rising edge of the SYNC pulse signal output by the third flip-flop and the rising edge of the fourth clock signal is greater than the difference threshold.

[0043] Optionally, the input of each frequency divider is the SYNC pulse signal output by the corresponding flip-flop and the corresponding clock signal.

[0044] For example, the input of the Xth frequency divider is the SYNC pulse signal outputted by the Xth flip-flop and the Xth clock signal, where X is a positive integer less than or equal to N.

[0045] In some embodiments, the flip-flop group 110 includes 4 flip-flops. The frequency divider group 120 includes 4 frequency dividers. The input of the first frequency divider is the SYNC pulse signal outputted by the first flip-flop and the first clock signal. The input of the second frequency divider is the SYNC pulse signal outputted by the second flip-flop and the second clock signal. The input of the third frequency divider is the SYNC pulse signal outputted by the third flip-flop and the third clock signal. The input of the fourth frequency divider is the SYNC pulse signal outputted by the fourth flip-flop and the fourth clock signal.

[0046] In other embodiments, the clock synchronization system includes: a flip-flop group 110 and a frequency divider group 120, the flip-flop group 110 includes: 4 flip-flops, the frequency divider group 120 includes: 4 frequency dividers, and the phases of the four clock signals are: 0°, 90°, 180° and 270°, respectively. First, timing design is performed according to the operating frequency. As shown in FIG. 2, taking the operating frequency of 10 GHz as an example, the clock period is 100 picoseconds (ps), and the delay of the CML flip-flop of the 0.18 micron germanium-silicon process varies in the range of about 35 ps to 55 ps. The 0° input is the first clock signal, the 90° input is the second clock signal, the 180° input is the third clock signal, and the 270° input is the fourth clock signal. The SYNC input is a SYNC pulse signal inputted to the flip-flop group 110, the CLKA output is the frequency-divided clock signal outputted by the first frequency divider, the internal SYNC1 is the SYNC pulse signal outputted by the first flip-flop, the CLKB output is the frequency-divided clock signal outputted by the second frequency divider, the internal SYNC2 is the SYNC pulse signal outputted by the second flip-flop, the CLKC output is the frequency-divided clock signal outputted by the third frequency divider, the internal SYNC3 is the SYNC pulse signal outputted by the third flip-flop, and the CLKD output is the frequency-divided clock signal outputted by the fourth frequency divider.

[0047] As shown in Fig. 2, the SYNC input is a unique SYNC input of the system, and the internal SYNC1 is outputted to the divider of the 90° input clock after 0° clock beat; the internal SYNC1 is outputted to the divider of the 180° input clock after 90° clock beat; the internal SYNC2 is outputted to the divider of the 270° input clock after 180° clock beat; and the internal SYNC3 is outputted to the divider of the 0° input clock after 270° clock beat. Thus, the multi-phase clock output can be synchronized through one SYNC input. Therefore, the rising edge of the SYNC pulse signal outputted by the first flip-flop is near the rising edge of the 270° phase clock, since the 270° phase clock signal is the fourth clock signal corresponding to the fourth flip-flop. Thus, the SYNC pulse signal outputted by the first flip-flop cannot be used as the SYNC pulse signal inputted by the fourth flip-flop, otherwise, the risk of generating a metastable state will be caused. Therefore, the SYNC pulse signal outputted by the first flip-flop can be used as the SYNC pulse signal inputted by the second flip-flop or the third flip-flop.

[0048] As shown in Fig. 3, the SYNC pulse signal outputted by the first flip-flop is used as the SYNC pulse signal inputted by the second flip-flop. In Fig. 3, DFF1 is the first flip-flop, DFF2 is the second flip-flop, DFF3 is the third flip-flop, and DFF4 is the fourth flip-flop. The SYNC pulse signal (SYNCI) and the clock signal (CLKI_0) are inputted into DFF1, the SYNC pulse signal outputted by DFF1 and the clock signal (CLKI_0) are inputted into the first divider, and the clock signal divided by the first divider is obtained. The SYNC pulse signal outputted by DFF1 and the clock signal (CLKI_90) are inputted into DFF2, the SYNC pulse signal outputted by DFF2 and the clock signal (CLKI_90) are inputted into the second divider, and the clock signal divided by the second divider is obtained. The SYNC pulse signal outputted by DFF2 and the clock signal (CLKI_180) are inputted into DFF3, the SYNC pulse signal outputted by DFF3 and the clock signal (CLKI_180) are inputted into the third divider, and the clock signal divided by the third divider is obtained. The SYNC pulse signal outputted by DFF3 and the clock signal (CLKI_270) are inputted into DFF4, the SYNC pulse signal outputted by DFF4 and the clock signal (CLKI_270) are inputted into the fourth divider, and the clock signal divided by the fourth divider is obtained.

[0049] For example, in the flip-flop group 110, the output SYNC pulse signal of each flip-flop except the Qth flip-flop (Q is a positive integer less than or equal to N) is used as the input SYNC pulse signal of another flip-flop, and the output SYNC pulse signal of the Qth flip-flop is not used as the input SYNC pulse signal of any flip-flop in the flip-flop group 110. That is, only one of the N flip-flops outputs a SYNC pulse signal that is not used as the input SYNC pulse signal of another flip-flop. In some embodiments, as shown in FIG. 3, the output SYNC pulse signal of the first flip-flop is used as the input SYNC pulse signal of the second flip-flop, the output SYNC pulse signal of the second flip-flop is used as the input SYNC pulse signal of the third flip-flop, the output SYNC pulse signal of the third flip-flop is used as the input SYNC pulse signal of the fourth flip-flop, and the output SYNC pulse signal of the fourth flip-flop is not used as the input SYNC pulse signal of any flip-flop.

[0050] In some embodiments, the divided clock signals output by the four dividers are as shown in FIG. 4, where CLKA is the divided clock signal output by the first divider, CLKB is the divided clock signal output by the second divider, CLKC is the divided clock signal output by the third divider, and CLKD is the divided clock signal output by the fourth divider. The phase difference between the divided clock signal output by the second divider and the divided clock signal output by the first divider is 225°, the phase difference between the divided clock signal output by the third divider and the divided clock signal output by the second divider is 360°+90°, and the phase difference between the divided clock signal output by the fourth divider and the divided clock signal output by the third divider is 360°+315°.

[0051] Optionally, the clock synchronization system further comprises a delay adjustment circuit, the input of one flip-flop in the flip-flop group 110 is a SYNC pulse signal and a corresponding clock signal, the input of the other flip-flops is a clock signal corresponding to the current flip-flop and a SYNC pulse signal output by a corresponding delay adjustment circuit, the input of the delay adjustment circuit is a SYNC pulse signal output by a target flip-flop, where the target flip-flop is a flip-flop in the flip-flop group 110 other than the current flip-flop, the phase difference between the rising edge of the SYNC pulse signal output by the corresponding delay adjustment circuit and the rising edge of the clock signal corresponding to the current flip-flop is greater than a threshold value, and the target flip-flop corresponding to each of the other flip-flops is different.

[0052] In some embodiments, if the phase difference between the rising edge of the SYNC pulse signal output by the Mth flip-flop in the flip-flop group 110 and the rising edge of the clock signal corresponding to the Ith flip-flop is less than or equal to the difference threshold value (where the difference threshold value is the setup time), there is a risk of generating a metastable state when the SYNC pulse signal output by the Mth flip-flop is used as the input SYNC pulse signal of the Ith flip-flop. Where M and I are positive integers less than or equal to N.

[0053] To reduce the risk of generating a metastable state, a delay adjustment circuit can be added between the output of each flip-flop in the flip-flop group 110 and the input of the corresponding flip-flop. This makes the phase difference between the rising edge of the SYNC pulse signal output by the corresponding flip-flop after being adjusted by the delay adjustment circuit and the rising edge of the clock signal corresponding to the flip-flop greater than the difference threshold value.

[0054] In some embodiments, to make the rising edge of the SYNC pulse signal avoid the rising edge of the clock signal, the delay can be adjusted by adding a delay adjustment circuit.

[0055] If the rising edge of the SYNC pulse signal just avoids the rising edge of the clock signal, there is no need to add a delay adjustment circuit. For example, if the phase difference between the rising edge of the SYNC pulse signal output by the Mth flip-flop in the flip-flop group 110 and the rising edge of the clock signal corresponding to the Ith flip-flop is greater than the difference threshold value (where the difference threshold value is determined according to the setup time, which includes the setup time and the hold time), the SYNC pulse signal output by the Mth flip-flop can be directly used as the input SYNC pulse signal of the Ith flip-flop. If the phase difference between the rising edge of the SYNC pulse signal output by the Mth flip-flop in the flip-flop group 110 and the rising edge of the clock signal corresponding to the Ith flip-flop is less than or equal to the difference threshold value, the SYNC pulse signal output by the Mth flip-flop needs to be first input to the delay adjustment circuit, and the SYNC pulse signal output by the delay adjustment circuit is used as the input SYNC pulse signal of the Ith flip-flop. By adding a delay adjustment circuit between the output of the Mth flip-flop and the input of the Ith flip-flop, the phase difference between the rising edge of the input SYNC pulse signal of the Ith flip-flop and the rising edge of the clock signal corresponding to the Ith flip-flop can be made greater than the difference threshold value, thereby reducing the risk of generating a metastable state.

[0056] In some embodiments, the delay adjustment circuit is provided to make the rising edge of the adjusted SYNC pulse signal avoid the rising edge of the clock signal.

[0057] Optionally, the delay adjustment circuit includes a buffer.

[0058] In some embodiments, the fixed delay characteristics and signal isolation capability of the buffer can be utilized to achieve precise delay control of the signal transmission time.

[0059] In some embodiments, the output of the first flip-flop in the flip-flop group 110 is connected to the input of the first delay adjustment circuit, the output of the first delay adjustment circuit is connected to the input of the Kth flip-flop, the phase difference between the rising edge of the SYNC pulse signal output by the first flip-flop and the rising edge of the corresponding clock signal of the Kth flip-flop is greater than the difference threshold value, and the phase difference between the rising edge of the SYNC pulse signal output by the first flip-flop after being adjusted by the first delay adjustment circuit and the rising edge of the corresponding Kth clock signal of the Kth flip-flop is greater than the difference threshold value, K is a positive integer greater than 1 and less than or equal to N.

[0060] In other embodiments, as shown in FIG. 5, the SYNC pulse signal output by the first flip-flop is taken as the SYNC pulse signal input by the second flip-flop. In FIG. 5, DFF1 is the first flip-flop, DFF2 is the second flip-flop, DFF3 is the third flip-flop, and DFF4 is the fourth flip-flop. A SYNC pulse signal (SYNCI) and a clock signal (CLKI_0) are input to DFF1, the output of DFF1 and a clock signal (CLKI_0) are input to a first frequency divider to obtain a clock signal after frequency division by the first frequency divider. The SYNC pulse signal output by DFF1 is taken as the input of the first delay adjustment circuit, the output of the first delay adjustment circuit and a clock signal (CLKI_90) are input to DFF2, the SYNC pulse signal output by DFF2 and a clock signal (CLKI_90) are input to a second frequency divider to obtain a clock signal after frequency division by the second frequency divider. The SYNC pulse signal output by DFF2 is taken as the input of the second delay adjustment circuit, the output of the second delay adjustment circuit and a clock signal (CLKI_180) are input to DFF3, the SYNC pulse signal output by DFF3 and a clock signal (CLKI_180) are input to a third frequency divider to obtain a clock signal after frequency division by the third frequency divider. The SYNC pulse signal output by DFF3 is taken as the input of the third delay adjustment circuit, the output of the third delay adjustment circuit and a clock signal (CLKI_270) are input to DFF4, the SYNC pulse signal output by DFF4 and a clock signal (CLKI_270) are input to a fourth frequency divider to obtain a clock signal after frequency division by the fourth frequency divider.

[0061] Optionally, the clock synchronization system further comprises: a delay adjustment circuit; the input of one flip-flop in the flip-flop group 110 is a SYNC pulse signal and a corresponding clock signal, the rest of the flip-flops comprise: a first type of flip-flop and a second type of flip-flop, there is at least one flip-flop in the flip-flop group 110 whose output SYNC pulse signal and the rising edge of the corresponding clock signal of the first type of flip-flop have a phase difference greater than the difference threshold value, and the rising edge of the SYNC pulse signal output by any flip-flop in the flip-flop group 110 and the rising edge of the corresponding clock signal of the second type of flip-flop have a phase difference less than or equal to the difference threshold value; the input of the first type of flip-flop is the corresponding clock signal of the current flip-flop and the SYNC pulse signal output by the corresponding previous stage flip-flop, wherein the corresponding previous stage flip-flop of the first type of flip-flop is the flip-flop in the flip-flop group 110 whose output SYNC pulse signal and the rising edge of the corresponding clock signal of the first type of flip-flop have a phase difference greater than the difference threshold value; the input of the second type of flip-flop is the corresponding clock signal of the current flip-flop and the SYNC pulse signal output by the delay adjustment circuit, and the input of the delay adjustment circuit is the SYNC pulse signal output by the corresponding previous stage flip-flop of the second type of flip-flop, wherein the corresponding previous stage flip-flop of the second type of flip-flop is the flip-flop in the flip-flop group 110 whose output SYNC pulse signal and the rising edge of the corresponding clock signal of the second type of flip-flop have a phase difference less than or equal to the difference threshold value; the corresponding previous stage flip-flop of each of the rest of the flip-flops is different.

[0062] In some embodiments, the previous stage flip-flop can be understood as a flip-flop in the signal transmission path before the current flip-flop.

[0063] For example, if the rising edge of the SYNC pulse signal output by the Mth flip-flop in the flip-flop group 110 and the rising edge of the corresponding clock signal of the Ith flip-flop have a phase difference greater than the difference threshold value, the Ith flip-flop can be determined as the first type of flip-flop. If the rising edge of the SYNC pulse signal output by each flip-flop in the flip-flop group 110 and the rising edge of the corresponding clock signal of the Ith flip-flop have a phase difference less than or equal to the difference threshold value, the Ith flip-flop can be determined as the second type of flip-flop.

[0064] In some embodiments, as shown in FIG. 6, since the phase difference between the rising edge of the SYNC pulse signal outputted by any flip-flop in the flip-flop group 110 and the rising edge of the clock signal corresponding to the flip-flop DFF2 is less than or equal to the difference threshold, the DFF2 is determined as the second type of flip-flop. Since the phase difference between the rising edge of the SYNC pulse signal outputted by the DFF2 and the rising edge of the clock signal corresponding to the flip-flop DFF3 is greater than the difference threshold, the DFF3 is determined as the first type of flip-flop. Since the phase difference between the rising edge of the SYNC pulse signal outputted by the DFF3 and the rising edge of the clock signal corresponding to the flip-flop DFF4 is greater than the difference threshold, the DFF4 is determined as the first type of flip-flop. Accordingly, a clock signal (CLKI_0) and a SYNC pulse signal (SYNCI) are inputted into the DFF1, the output of the DFF1 and the clock signal (CLKI_0) are inputted into the first frequency divider, and the clock signal after frequency division by the first frequency divider is obtained. The SYNC pulse signal outputted by the DFF1 is inputted into the delay adjustment circuit as an input, the output of the delay adjustment circuit and the clock signal (CLKI_90) are inputted into the DFF2, the SYNC pulse signal outputted by the DFF2 and the clock signal (CLKI_90) are inputted into the second frequency divider, and the clock signal after frequency division by the second frequency divider is obtained. The SYNC pulse signal outputted by the DFF2 and the clock signal (CLKI_180) are inputted into the DFF3, the SYNC pulse signal outputted by the DFF3 and the clock signal (CLKI_180) are inputted into the third frequency divider, and the clock signal after frequency division by the third frequency divider is obtained. The SYNC pulse signal outputted by the DFF3 and the clock signal (CLKI_270) are inputted into the DFF4, the SYNC pulse signal outputted by the DFF4 and the clock signal (CLKI_270) are inputted into the fourth frequency divider, and the clock signal after frequency division by the fourth frequency divider is obtained.

[0065] Optionally, the clock synchronization system further comprises inverters, the output of the target frequency divider in the frequency divider group 120 is connected to the input of the corresponding inverter, and the phase of the clock signal outputted by the target frequency divider needs to be flipped.

[0066] In some embodiments, the target frequency divider is a frequency divider whose output clock signal phase needs to meet a preset phase condition. The output clock signal of the target frequency divider can be phase-inverted by connecting the output of the target frequency divider to the input of the inverter. The preset phase condition can include at least one of the following: the phase difference between the output clock signal of the target frequency divider and the phase of other clock signals in the system meets a specific angle requirement; the phase of the output clock signal of the target frequency divider is synchronized with the phase of an externally input reference clock signal; and the phase of the output clock signal of the target frequency divider is inverted so that the phase distribution of multiple clock signals in the system meets a preset timing relationship.

[0067] In some embodiments, if the phase of the output clock signal of the frequency divider Y (Y is a positive integer less than or equal to N) needs to be inverted, the output of the frequency divider Y is connected to the input of the inverter, and the clock signal output by the inverter is used as the final output clock signal of the frequency divider Y.

[0068] In some embodiments, as shown in FIG. 7, the output of the second frequency divider is connected to the input of the first inverter, and the clock signal output by the first inverter is used as the final output clock signal of the second frequency divider. The output of the fourth frequency divider is connected to the input of the second inverter, and the clock signal output by the second inverter is used as the final output clock signal of the fourth frequency divider. Before adding the inverter, the output timing diagram is as shown in FIG. 4. After adding the inverter, the output of CLK A is 0° (unchanged), the output of CLK B is 45° (225°-180°), the output of CLK C is 90° (unchanged), and the output of CLK D is 135° (315°-180°).

[0069] FIG. 7 is only an example of adding an inverter. The output of the second frequency divider in FIG. 3 can also be connected to the input of the first inverter, and the clock signal output by the first inverter can be used as the final output clock signal of the second frequency divider. The output of the fourth frequency divider in FIG. 3 can also be connected to the input of the second inverter, and the clock signal output by the second inverter can be used as the final output clock signal of the fourth frequency divider.

[0070] Optionally, the difference threshold is determined according to the setup time and the hold time of the flip-flop.

[0071] Optionally, the clock phases of the N clock signals are different.

[0072] In some embodiments, the phase difference of the N clock signals can be the same or different. For example, the N clock signals can be 0°, 90°, 180°, 270°. The N clock signals can also be 0°, 45°, 90°, 180°.

[0073] Optionally, the flip-flop is a CML flip-flop.

[0074] The clock synchronization system in the embodiment includes a flip-flop group 110 and a frequency divider group 120, the flip-flop group 110 includes N flip-flops, and the frequency divider group 120 includes N frequency dividers; the flip-flop group 110 receives N clock signals and a pulse signal, transmits the N clock signals to the N frequency dividers respectively, and transmits N pulse signals output by the flip-flop group 110 to the N frequency dividers respectively, and N is a positive integer greater than 1. Through the above structure, the phase difference between the rising edge of the pulse signal input to the frequency divider and the rising edge of the clock signal input to the frequency divider is greater than a difference threshold, which can reduce the risk of generating a metastable state while reducing power consumption.

Claims

1. A clock synchronization system, comprising: A flip-flop group and a frequency divider group, the flip-flop group comprising N flip-flops, the frequency divider group comprising N frequency dividers; The flip-flop group receives N clock signals and a SYNC pulse signal, and transmits the N clock signals to the N frequency dividers respectively, and transmits the N SYNC pulse signals output by the flip-flop group to the N frequency dividers respectively, N being a positive integer greater than 1.

2. The system of claim 1, wherein, The input of one flip-flop in the flip-flop group is a SYNC pulse signal and a corresponding clock signal, and the input of the rest of the flip-flops is a clock signal corresponding to the current flip-flop and a SYNC pulse signal output by an associated flip-flop, wherein the associated flip-flop is a flip-flop other than the current flip-flop in the flip-flop group, the phase difference between the rising edge of the SYNC pulse signal output by the associated flip-flop and the rising edge of the clock signal corresponding to the current flip-flop is greater than a difference threshold, and the associated flip-flop corresponding to each of the rest of the flip-flops is different.

3. The system of claim 1, further comprising: A delay adjustment circuit; The input of one flip-flop in the flip-flop group is a SYNC pulse signal and a corresponding clock signal, and the input of the rest of the flip-flops is a clock signal corresponding to the current flip-flop and a SYNC pulse signal output by a corresponding delay adjustment circuit, the input of the delay adjustment circuit being a SYNC pulse signal output by a target flip-flop, wherein the target flip-flop is a flip-flop other than the current flip-flop in the flip-flop group, the phase difference between the rising edge of the SYNC pulse signal output by the corresponding delay adjustment circuit and the rising edge of the clock signal corresponding to the current flip-flop is greater than a difference threshold, and the target flip-flop corresponding to each of the rest of the flip-flops is different.

4. The system of claim 1, further comprising: A delay adjustment circuit; The input of one flip-flop in the flip-flop group is a SYNC pulse signal and a corresponding clock signal, and the rest of the flip-flops comprise a first type of flip-flop and a second type of flip-flop, the phase difference between the rising edge of the SYNC pulse signal output by at least one flip-flop in the flip-flop group and the rising edge of a clock signal corresponding to the first type of flip-flop being greater than a difference threshold, and the phase difference between the rising edge of the SYNC pulse signal output by any flip-flop in the flip-flop group and the rising edge of a clock signal corresponding to the second type of flip-flop being less than or equal to the difference threshold. The input of the first type of flip-flop is a clock signal corresponding to the current flip-flop and a SYNC pulse signal output by a corresponding previous-stage flip-flop, wherein the corresponding previous-stage flip-flop of the first type of flip-flop is a flip-flop in the flip-flop group whose output SYNC pulse signal has a phase difference greater than the difference threshold with the rising edge of a clock signal corresponding to the first type of flip-flop. The input of the second type of flip-flop is a clock signal corresponding to the flip-flop and a SYNC pulse signal output by a delay adjustment circuit corresponding to the flip-flop, the input of the delay adjustment circuit is a SYNC pulse signal output by a previous stage flip-flop corresponding to the second type of flip-flop, wherein the previous stage flip-flop corresponding to the second type of flip-flop is a flip-flop whose phase difference between a rising edge of a SYNC pulse signal output by the flip-flop and a rising edge of a clock signal corresponding to the flip-flop is less than or equal to a difference threshold value in the flip-flop group; The previous stage flip-flop corresponding to each of the remaining flip-flops is different.

5. The system of claim 1, wherein, The input of each frequency divider is a SYNC pulse signal output by a corresponding flip-flop and a corresponding clock signal.

6. The system of claim 1, wherein, The clock phases of the N clock signals are different.

7. The system of claim 3 or 4, wherein, The delay adjustment circuit comprises a buffer.

8. The system of any one of claims 1-6, further comprising: An inverter; The output of a target frequency divider in the frequency divider group is connected to the input of a corresponding inverter, and the phase of a divided clock signal output by the target frequency divider needs to be flipped.

9. The system of any one of claims 1-6, wherein, The flip-flop is a current mode logic flip-flop.

10. The system of any one of claims 2-4, wherein, The difference threshold value is determined according to the setup time and the hold time of the flip-flop.

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