Two-dimensional semiconductor device and manufacturing method therefor

Abstract

Disclosed in the present invention are a two-dimensional semiconductor device and a manufacturing method therefor. The device comprises a substrate, a two-dimensional semiconductor material layer and a gate structure, wherein the gate structure comprises a gate dielectric layer and a gate electrode layer; the gate dielectric layer comprises a portion covered by the bottom of a gate electrode and portions not covered by the bottom of the gate electrode; the portions not covered by the bottom of the gate electrode each extend outward along the surface of the semiconductor layer; the portions of the gate dielectric layer that are not covered by the bottom of the gate electrode and two sides of the gate electrode are covered with sidewalls; a support layer is arranged on the surface of each sidewall; and source-drain metal contact layers penetrate, from top to bottom, the support layers, the sidewalls located on the surface of the gate dielectric layer, the two-dimensional semiconductor material layer and the substrate. In the present invention, metallic yttrium is deposited on a two-dimensional semiconductor material layer, and cleaning is performed to leave yttrium seeds, such that the metal yttrium is used as seeds to obtain a high-performance gate structure, thereby significantly reducing the subthreshold swing and contact resistance of a device, effectively inhibiting the short-channel effect, and reducing channel defects. Therefore, the overall performance, yield and reliability of the device are significantly improved.

Description

A two-dimensional semiconductor device and a method for manufacturing the same TECHNICAL FIELD

[0001] The present application relates to a semiconductor structure and a method for manufacturing the same, and in particular to a two-dimensional semiconductor device and a method for manufacturing the same. BACKGROUND

[0002] With the continuous development of semiconductor technology, the process node of advanced silicon-based integrated circuit devices has already challenged 2nm. However, with the continuous shrinking of the process node, Moore's law gradually fails. Silicon-based integrated circuit technology is facing the bottleneck of process cost, physical limit and yield, etc. Especially in the case of continuous shrinking of device size, the trade-off between power consumption, performance and cost of traditional silicon-based technology becomes more complex and difficult. Therefore, the semiconductor industry urgently needs new materials and processing technology to promote the technology to continue to develop. Two-dimensional materials have become a promising candidate material in the post-Moore era due to their unique physical properties, which can effectively replace traditional silicon materials and solve many problems in current integrated circuit technology.

[0003] Two-dimensional materials such as molybdenum disulfide (MoS2) have excellent subthreshold swing characteristics and high electron mobility, so they have broad application prospects in future electronic devices. However, the traditional dry etching process technology has significant shortcomings in etching depth control, sidewall steepness and etching rate selectivity. Especially when processing two-dimensional materials, the existing etching method is difficult to achieve high precision control, which easily causes material damage or uneven etching, affecting the final performance of the device. In addition, because the thickness of two-dimensional materials is particularly thin, existing doping technology often causes damage to the channel, and a new method is needed for doping.

[0004] Therefore, an improved process flow is needed to reduce damage to the material and improve device yield. SUMMARY

[0005] The purpose of the present application is to provide a two-dimensional material semiconductor device that can improve the overall performance, yield and reliability of the device.

[0006] The second purpose of the present application is to provide a method for manufacturing the two-dimensional material semiconductor device described above.

[0007] Technical solution: The two-dimensional semiconductor device provided by the application comprises a substrate, a two-dimensional semiconductor material layer arranged on the substrate, and a gate structure arranged on the two-dimensional semiconductor material layer, wherein the gate structure comprises a gate dielectric layer and a gate electrode layer above the gate dielectric layer, the gate dielectric layer comprises a part covered by the bottom of the gate electrode layer and a part not covered by the bottom of the gate electrode layer, and the part not covered by the bottom of the gate electrode layer extends outward along the surface of the two-dimensional semiconductor material layer; the part of the gate dielectric layer not covered by the bottom of the gate electrode layer and the two sides of the gate electrode are both covered with a sidewall; the surface of the sidewall is provided with a support layer formed by a low dielectric constant material; the top of the support layer, the sidewall located on the surface of the gate dielectric layer, the two-dimensional semiconductor material layer, and the substrate are flush, and a source-drain metal contact layer penetrates through in the vertical direction of the support layer, the sidewall located on the surface of the gate dielectric layer, the two-dimensional semiconductor material layer, and the substrate.

[0008] The preparation method of the two-dimensional semiconductor device described above comprises the following steps:

[0009] (A) forming a two-dimensional semiconductor material layer on a substrate, depositing yttrium metal on the two-dimensional semiconductor material layer, and annealing in an inert atmosphere to perform yttrium sulfide metallization; after annealing, the yttrium metal layer is cleaned to leave a yttrium metal seed;

[0010] (B) forming a gate dielectric layer on the surface of the two-dimensional semiconductor material layer with the yttrium metal seed left, and forming a gate electrode layer on the surface of the gate dielectric layer to obtain a gate structure;

[0011] (C) using a photolithography method to divide the positions of the source and the drain, then etching away the gate electrode layer in the source-drain region, etching the gate dielectric layer downward to a certain depth, and then forming a sidewall on the exposed surface;

[0012] (D) depositing a low dielectric constant material on the surface of the sidewall to form a support layer for the source-drain metal;

[0013] (E) using CMP to planarize the structure obtained in step (D) and stop on the gate electrode layer, removing the excess support layer, and exposing the gate electrode layer;

[0014] (F) forming a recess in the support layer that has not been removed by etching downward, and the recess extends into the substrate;

[0015] (G) depositing source and drain metals into the recess to form ohmic contact with the two-dimensional semiconductor material layer; after deposition, the excess metal is removed to expose the gate structure, and the two-dimensional semiconductor device is prepared.

[0016] In step (A), yttrium metal is deposited in a high-vacuum environment by electron beam evaporation, and the deposition thickness of the yttrium metal is 1-2 nm.

[0017] In step (A), a mixture of argon and hydrogen is used during the annealing process to prevent oxidation and improve the activity of the seed.

[0018] In step (A), the annealing temperature is 240-300℃, and the time is 20-40min.

[0019] In step (A), the yttrium metal layer is removed by acid washing, and the yttrium metal seed is reserved.

[0020] In step (A), before depositing the yttrium metal, the surface of the two-dimensional semiconductor material is modified by using a low-power argon soft plasma or electron beam irradiation to treat the patterned local contact area, so as to generate active sites.

[0021] In step (A), the two-dimensional material is MoS2; before depositing the yttrium metal, the surface of the MoS2 is bombarded by using a low-power soft plasma to induce sulfur vacancy control on the surface of the MoS2, the bombardment time is 5S-30S, and the concentration is controlled to be between 5% and 20%.

[0022] In step (G), the deposition temperature is 200-250℃.

[0023] After step (G), the residual photoresist or hard mask material is removed, and the device is packaged.

[0024] Beneficial effects: Compared with the prior art, the present application has the following remarkable effects:

[0025] (1) The present application deposits yttrium metal on the two-dimensional semiconductor material layer, and then removes the yttrium metal layer by washing to leave a yttrium seed, uses the yttrium metal as a source-drain doping source for the two-dimensional material, and uses the yttrium metal as a seed to obtain a high-performance gate structure, which significantly reduces the subthreshold swing and contact resistance of the device, effectively suppresses the short channel effect, reduces the channel defects, and thus significantly improves the overall performance, yield and reliability of the device.(2) The present application etches a recess in the vertical direction of the support layer, the side wall located on the surface of the gate dielectric layer, the two-dimensional semiconductor layer and the substrate, and the recess extends into the substrate layer, which effectively protects the channel two-dimensional material and solves the problem of etching cutoff depth of the two-dimensional material.(3) The process is compatible with the existing silicon-based process and is suitable for large-scale production. Compared with traditional silicon-based field effect transistors, the present application can maintain excellent electrical performance at a smaller geometric size, thereby performing well in high-density integrated circuits.(4) The present application is suitable for field effect transistors (FET) based on two-dimensional materials (such as molybdenum disulfide or carbon nanotubes), and these devices can be applied to high-performance low-power integrated circuits, flexible electronic devices, sensors and next-generation computing and communication equipment. BRIEF DESCRIPTION OF DRAWINGS

[0026] Fig. 1 is a structural schematic diagram of a two-dimensional semiconductor device of the present application;

[0027] Figure 2 is a flow chart of the preparation method of the two-dimensional semiconductor device of the present application;

[0028] Figure 3 is a comparison of the performance of the two-dimensional semiconductor device of the present application and the two-dimensional semiconductor device obtained without any treatment of the surface of the two-dimensional semiconductor material layer. DETAILED DESCRIPTION

[0029] The present application will be further described in detail below.

[0030] As shown in Figure 1, the present application provides a two-dimensional semiconductor device, comprising a substrate 1, a two-dimensional semiconductor material layer 2 provided on the substrate 1, and a gate structure provided on the two-dimensional semiconductor material layer 2, the gate structure comprising a gate dielectric layer 3 and a gate electrode layer 4 above the gate dielectric layer 3, the gate dielectric layer 3 comprising a portion covered by the bottom of the gate electrode layer and a portion not covered by the bottom of the gate electrode layer, the portion not covered by the bottom of the gate electrode layer extending outward along the surface of the two-dimensional semiconductor material layer 2 respectively; the portion of the gate dielectric layer 3 not covered by the bottom of the gate electrode layer and the two sides of the gate electrode are covered with a side wall 5; the surface of the side wall 5 is provided with a support layer 6 formed of a low dielectric constant material; the top of the support layer 6, the side wall 5 located on the surface of the gate dielectric layer 3, the two-dimensional semiconductor material layer 2, and the substrate 1 are flush, and a source-drain metal contact layer 7 penetrates through from top to bottom.

[0031] The above-mentioned preparation method of the two-dimensional semiconductor device, as shown in Figure 2, comprises the following steps:

[0032] 1. Material stacking and layer structure preparation

[0033] (1) First, a two-dimensional semiconductor material layer 2 is grown on a silicon oxide substrate 1 by CVD method, the two-dimensional semiconductor material of this embodiment is molybdenum disulfide MoS2, and the thickness can be 1-5 nm; the CVD method can also be replaced by PVD, mechanical transfer, etc.

[0034] (2) The patterned local contact area is treated with low-power argon soft plasma to change the contact interface and produce active sites; this low-power soft plasma filters high-energy particles on the surface of the top MoS2 layer to induce a small amount of sulfur vacancy without damaging the overall lattice of the 2D MoS2; in the experiment, as the bombardment time increases, the sulfur vacancy defect concentration increases, and the crystal structure is gradually destroyed, so it is necessary to reasonably control the sulfur vacancy defect concentration to achieve the best doping; the bombardment intensity of this embodiment is 30w, and the bombardment time is 20s;

[0035] (3) Yttrium metal Y is deposited on the surface of the two-dimensional semiconductor material layer 2 in a high-vacuum environment by electron beam evaporation. The deposition thickness of yttrium is maintained between 1-2 nanometers, 0.3A per second deposition; a mixture of argon and hydrogen gas is used during the annealing process to prevent oxidation and improve the activity of the seed crystal;

[0036] (4) Yttrium metalization at 240°C under inert gas to reduce defect formation and ensure uniformity and quality of the two-dimensional material layer, forming an effective ohmic contact point;

[0037] (5) Subsequent acid washing to remove the yttrium metal layer, leaving the seed; after depositing the yttrium metal, clean it off with dilute hydrochloric acid; this can also remove some of the contaminants on the channel surface at the same time;

[0038] To further optimize the deposition of yttrium as a seed, the deposition thickness and uniformity of yttrium can be controlled to ensure the growth of a high-quality top gate layer. During annealing, the temperature and atmosphere are adjusted appropriately to promote uniform distribution of yttrium, reduce interface defects, and enhance the bonding strength between the top gate and the two-dimensional material. The time for acid washing to remove the metal layer also needs to be adjusted according to the deposition thickness of yttrium.

[0039] 2. Deposit gate dielectric layer 3 and metal gate layer 4 to obtain the gate structure:

[0040] (1) With the help of the yttrium seed, deposit a high dielectric constant material, i.e., High-k material, to obtain gate dielectric layer 3 using atomic layer deposition (ALD) technology. Gate dielectric layer 3 can reduce defects between the channel and the insulating layer; use the precursor tetraethylcyclopentadiene hafnium (abbreviated as TEMAH) and cooperate with the oxidizing agent O3 for deposition, control the deposition temperature at 250°C, achieve atomic-level thickness control, ensure uniform coverage and reduce leakage current; this atomic layer deposition method is prior art; the precursor can also be replaced with hafnium chloride (HfCl4), and the oxidizing agent can be replaced with H2O.

[0041] (2) Deposit a metal gate on the surface of gate dielectric layer 3 to form a gate stack dielectric layer, i.e., a gate structure.

[0042] 3. Metal gate formation

[0043] Use photolithography technology to pattern the sample and divide the positions of the source and drain. Then, use a dry etching process to remove the metal gate and part of the gate dielectric layer 3 in the source and drain regions. Gate dielectric layer 3 plays a protective role in this process to prevent damage to the two-dimensional material layer. The etching process uses plasma-enhanced reactive ion etching (RIE) technology, controls the gas flow and radio frequency power to achieve high-selectivity etching and reduce damage to the two-dimensional material.

[0044] 4. Spacer deposition

[0045] The exposed surface of the structure obtained in step 3 is deposited with a low dielectric constant material, i.e. a low-k material, to form a sidewall 5 structure. This step helps to reduce parasitic capacitance, improve switching speed and electrical performance of the device. The thickness of the deposited low-k material should be controlled within a suitable range to ensure mechanical strength and electrical isolation effect of the sidewall 5.

[0046] 5. Deposition of support layer

[0047] Silicon oxide is deposited on both sides of the source-drain region to form a support layer 6 for the source-drain metal. This avoids collapse of the source-drain metal during deposition. The deposition of silicon oxide can be performed using a chemical vapor deposition (CVD) process, with a thickness controlled to be in the range of 20-30 nm, to achieve effective isolation while not affecting the scaling of the device. Silicon oxide can be replaced by other low dielectric constant materials.

[0048] 6. CMP polishing to metal gate

[0049] The entire structure is planarized using a CMP technique to remove excess support layer 6, ensuring that the source-drain metal region achieves consistent flatness, thereby improving the accuracy of subsequent deposition processes. During the CMP process, a soft pad is used and the polishing speed is optimized to reduce damage to sensitive layers, ensuring planarization effect and improving manufacturing yield.

[0050] 7. Trenching and source / drain metal deposition

[0051] Dry etching technology is used to form deep trenches along both sides of the gate and in the isolation layer, i.e. support layer 6, sidewall 5 on the surface of gate dielectric layer 3, two-dimensional semiconductor layer 2, and vertical etching of substrate 1 to form a recess for the deposition of source and drain metals; the recess is in the form of an inverted trapezoid. Since the two-dimensional material layer is extremely thin, the etching depth is difficult to control, and etching to the substrate 1 layer is required to achieve edge contact. During the etching process, real-time etching monitoring is used, such as optical emission spectroscopy (OES) technology, to accurately control the etching depth and reduce the impact of over-etching on the two-dimensional material, thereby improving the yield of the device.

[0052] 8. Deposition of metal to form ohmic contact

[0053] Source and drain metals are deposited in the etched region to form good ohmic contact with the two-dimensional material layer. The specific deposition method is known in the art. For example, physical vapor deposition (PVD) technology can be used, with a deposition temperature controlled in the range of 200-250°C and precise control of gas flow to ensure uniformity and density of the metal thin film. After completing the metal deposition, excess metal is removed by lithography and dry etching to ensure that the metal is only retained in the source-drain region, reducing parasitic resistance and improving switching performance.

[0054] The material of the source-drain metal contact layer 7 is known in the art and can be a single or multi-layer metal or metal compound material such as Ti, Al, TiN, Ta, TaN, TiAl, TiAlN, TiAlSc, AlSc, TiSc, TiPd, AlPd. The combination of the layers of materials; the thickness of which is determined by the requirements of the device.

[0055] 9. Post-processing

[0056] After the etching is completed, the remaining photoresist or hard mask material needs to be removed, and an oxygen plasma cleaning technique is used to remove the residues. Oxygen plasma can effectively remove the remaining organic photoresist, ensuring the smooth progress of subsequent processes.

[0057] 10. Packaging process

[0058] Finally, the device is subjected to a packaging process to ensure its mechanical strength and electrical stability. The packaging material can be silicon oxide or polyimide to ensure the isolation effect of the device from the environment and provide mechanical support. This step ensures the compatibility of the device with other components in the subsequent process, meeting the integration requirements of advanced processes.

[0059] As shown in FIG. 3, where "after" in FIG. 3 represents a two-dimensional material semiconductor field effect transistor obtained by using the method of the present application, and "before" represents a two-dimensional material semiconductor field effect transistor obtained by omitting steps (2) to (5) in the above-mentioned step 1 of the present application, so that the surface of the two-dimensional semiconductor material layer is not subjected to any treatment. Compared with the two, it can be seen that the sub-threshold swing of the two-dimensional material semiconductor field effect transistor of the present application is obviously improved.

Claims

1. A two-dimensional semiconductor device comprising a substrate (1), a layer (2) of two-dimensional semiconductor material provided on the substrate (1), and a gate structure provided on the layer (2) of two-dimensional semiconductor material, the gate structure comprising a gate dielectric layer (3), a gate electrode layer (4) above the gate dielectric layer (3), characterized in that The gate dielectric layer (3) includes a part covered by the bottom of the gate layer (4) and a part not covered by the bottom of the gate layer (4), and the part not covered by the bottom of the gate layer (4) extends outward along the surface of the two-dimensional semiconductor material layer (2) respectively; the part of the gate dielectric layer (3) not covered by the bottom of the gate layer (4) and both sides of the gate are covered with a side wall (5); the surface of the side wall (5) is provided with a support layer (6) formed by a low dielectric constant material; the support layer (6), the side wall (5) and the top of the gate are flush, and the source-drain metal contact layer (7) penetrates through the support layer (6), the side wall (5) on the surface of the gate dielectric layer (3), the two-dimensional semiconductor material layer (2) and the substrate (1) in the vertical direction.

2. A method of producing a two-dimensional semiconductor device according to claim 1, characterized by, The method comprises the following steps: (A) forming a two-dimensional semiconductor material layer (2) on a substrate (1), depositing yttrium metal on the two-dimensional semiconductor material layer (2), and annealing in an inert atmosphere to perform yttrium sulfide metallization; after annealing, the yttrium metal layer is cleaned to leave a yttrium metal seed; (B) forming a gate dielectric layer (3) on the surface of the two-dimensional semiconductor material layer (2) with the yttrium metal seed left, forming a gate layer (4) on the surface of the gate dielectric layer (3) to obtain a gate structure; (C) using photolithography to divide the positions of the source and the drain, then etching away the gate layer (4) in the source-drain region, and etching the gate dielectric layer (3) downward to a certain depth, then forming a side wall (5) on the exposed surface; (D) depositing a low dielectric constant material on the surface of the side wall (5) to form a support layer (6) for the source-drain metal; (E) using CMP to planarize the structure obtained in step (D) and stop on the gate layer (4), removing the excess support layer (6) to expose the gate layer (4); (F) forming a recess in the support layer (6) not removed by etching downward, and the recess extends into the substrate (1); (G) depositing source and drain metals into the recess to form ohmic contact with the two-dimensional semiconductor material layer (2); After deposition, the excess metal is removed to expose the gate structure, and the two-dimensional semiconductor device is obtained.

3. The method of claim 2, wherein the method further comprises: In step (A), the yttrium metal is deposited by electron beam evaporation in a high vacuum environment, and the deposition thickness of the yttrium metal is 1-2 nm.

4. The method of claim 2, wherein In step (A), a mixture of argon and hydrogen is used during annealing to prevent oxidation and improve the activity of the seed.

5. The method of claim 2, wherein In step (A), the annealing temperature is 240-300℃, and the time is 20-40 min.

6. The method of producing a two-dimensional semiconductor device according to claim 2, wherein In step (A), the yttrium metal layer is removed by acid washing to leave the yttrium metal seed.

7. The method of claim 2, wherein the semiconductor material is selected from the group consisting of silicon, germanium, silicon-germanium, gallium arsenide, indium arsenide, indium phosphide, and combinations thereof. In step (A), before depositing the yttrium metal, the two-dimensional semiconductor material is surface-modified by using a low-power argon soft plasma or electron beam irradiation to treat the patterned local contact area, thereby generating active sites.

8. The method of producing a two-dimensional semiconductor device according to claim 2, wherein In step (A), the two-dimensional material is MoS2; before depositing the yttrium metal, the MoS2 surface is bombarded by a low-power soft plasma to induce sulfur vacancy control on the surface of the MoS2, the bombardment time is 5S-30S, and the concentration is controlled between 5% and 20%.

9. The method of producing a two-dimensional semiconductor device according to claim 2, wherein In step (G), the deposition temperature is 200-250℃.

10. The method of producing a two-dimensional semiconductor device according to claim 2, wherein After step (G), the remaining photoresist or hard mask material is removed and the device is packaged.

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