Equalization device

Abstract

This equalization device: executes equalization processing which is processing for equalizing an input signal and generating an output signal, error calculation processing for calculating the difference between the output signal and a symbol determination signal based on the input signal, and outlier determination processing for determining, on the basis of the absolute value of the difference and a prescribed threshold, whether or not the input signal is an outlier; and does not update a tap coefficient in the equalization processing when it is determined that the input signal is an outlier in the outlier determination processing.

Description

equalizer

[0001] The present invention relates to an equalization device.

[0002] Because radio waves are absorbed and attenuated extremely well underwater, wireless communication using radio waves, like on land, is difficult. For this reason, underwater wireless communication often uses sound waves of 1 MHz or less, which have little absorption and attenuation. In underwater acoustic communication, multipath waves are generated due to factors such as sea surface reflection. Furthermore, Doppler shift occurs due to fluctuations in the sea surface and the movement of the transmitting and receiving terminals. As a result, the impulse response of the transmission path fluctuates over time.

[0003] To ensure stable communication over a transmission path where the impulse response fluctuates over time, it is necessary to adaptively control the filter coefficients of the equalizer to track the temporal fluctuations. Methods for controlling the filter coefficients include the least mean square (LMS) algorithm and the recursive least square (RLS) algorithm. Both methods operate to minimize the squared error between the realized value at the equalizer output and the ideal signal value (Non-Patent Document 1).

[0004] M. Stojanovic, JA Catipovic and JG Proakis, "Phase-coherent digital communications for underwater acoustic channels," in IEEE Journal of Oceanic Engineering, vol. 19, no. 1, pp. 100-111, Jan. 1994.

[0005] However, impulsive noise can sometimes be superimposed on the received signal. When this happens, the squared error can be momentarily overestimated, causing the control of the filter coefficients to become unstable and diverge. This divergence of the filter coefficients can cause burst errors and degrade the BER (Bit Error Rate) characteristics. As a result, there is a risk of communication quality deteriorating.

[0006] In view of the above circumstances, an object of the present invention is to provide a technique for stabilizing equalization operations and improving communication quality.

[0007] One aspect of the present invention is an equalization device that performs an equalization process that equalizes an input signal and generates an output signal, an error calculation process that calculates the difference between the output signal and a symbol decision signal based on the input signal, and an outlier determination process that determines whether the input signal is an outlier based on the absolute value of the difference and a predetermined threshold, and does not update tap coefficients in the equalization process if the input signal is determined to be an outlier in the outlier determination process.

[0008] According to the present invention, it is possible to stabilize the equalization operation and improve the communication quality.

[0009] FIG. 1 is a diagram illustrating a configuration of a communication system according to the present embodiment. FIG. 2 is a diagram illustrating a flow of signal processing according to the first embodiment. FIG. 3 is a diagram illustrating an example of equalization processing 21 according to the present embodiment. FIG. 4 is a diagram illustrating a flow of signal processing according to the second embodiment. FIG. 5 is a diagram illustrating a flowchart of signal processing according to the second embodiment. FIG. 6 is a diagram illustrating a flow of signal processing according to the third embodiment. FIG. 7 is a diagram illustrating signal points when the modulation method is BPSK. FIG. 8 is a diagram illustrating a signal points when the modulation method is QPSK. FIG. 9 is a diagram illustrating an example of a hardware configuration of an equalization device 20 in an embodiment.

[0010] (Overall Configuration) Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. Fig. 1 is a diagram showing the configuration of a communication system 1 according to this embodiment. The communication system 1 includes transmitting / receiving devices 10-1 and 10-2, and equalization devices 20-1 and 20-2.

[0011] The transmitting / receiving device 10-1 and the transmitting / receiving device 10-2 transmit and receive signals. The equalizer 20-1 performs equalization processing on the signal received by the transmitting / receiving device 10-1. The equalizer 20-2 performs equalization processing on the signal received by the transmitting / receiving device 10-2.

[0012] (First embodiment) Signal processing by the equalization devices 20-1 and 20-2 will be described in detail below. Fig. 2 is a diagram illustrating the flow of signal processing according to the first embodiment. The signal processing according to the first embodiment includes equalization processing 21, error calculation processing 22, and outlier determination processing 23.

[0013] The equalization process 21 is a process for equalizing an input signal to generate an output signal y(n). The output signal y(n) is a complex number, and y(n)∈C １ It can be expressed as follows: C denotes the set of complex numbers.

[0014] The equalization process 21 generates a symbol decision signal f(n) based on the output signal y(n). The symbol decision signal f(n) is a complex number, and f(n)∈C １ The equalization processing 21 controls the filter processing based on the determination result by the outlier determination processing 23. A method for generating the symbol determination signal f(n) and a method for controlling the processing content based on the determination result will be described later.

[0015] The error calculation process 22 is a process for calculating the difference between the output signal y(n) and the symbol decision signal f(n). The difference calculated here between the output signal y(n) and the symbol decision signal f(n) is defined as an error signal e(n). The error signal e(n) is a complex number, and e(n)∈C １ It can be expressed as:

[0016] The outlier determination process 23 is a process for determining whether the square of the absolute value of the error signal e(n) is equal to or greater than a predetermined threshold. The outlier determination process 23 is a process for determining that the input signal represents an outlier if the square of the absolute value of the error signal e(n) is equal to or greater than a predetermined threshold, and is a process for determining that the input signal does not represent an outlier if the square of the absolute value of the error signal e(n) is less than the predetermined threshold. The determination result by the outlier determination process 23 is used for control in the equalization process 21.

[0017] The outlier determination process 23 may be a process of determining whether or not the absolute value of the error signal is equal to or greater than a predetermined threshold value.

[0018] n indicates the iteration, which is the number of times the equalization process 21, the error calculation process 22, and the outlier determination process 23 are repeated. For example, the equalization process 21 generates an output signal y(2) and a symbol determination signal f(2), generates an error signal e(2), the outlier determination process 23 determines the error signal e(2), and the determination result is used for control in the equalization process 21. Thereafter, the equalization process 21 generates an output signal y(3).

[0019] 3 is a flowchart of signal processing according to the first embodiment. The equalizer 20 performs equalization processing 21 on a signal received by the transceiver 10 and input to the equalizer 20 (step S11). The equalizer 20 then performs error calculation processing 22 to generate an error signal e(n), which is the difference between the output signal y(n) generated by the equalization processing and the symbol decision signal f(n) (step S12). The equalizer 20 then performs outlier determination processing 23 to determine whether the square of the absolute value of the error signal e(n) is greater than or equal to a predetermined threshold, thereby determining whether the input signal represents an outlier (step S13). The equalizer 20 then controls the equalizer 21 based on the determination result (step S14).

[0020] The equalization device 20 repeats steps S11 to S14 to generate an output signal y(n) corresponding to the input signal and control the equalization process 21.

[0021] 4 is a diagram illustrating an example of the equalization processing 21 according to this embodiment. The equalization processing 21 includes a multiplication processing 211, a feedforward filtering processing 212, an addition processing 213, a symbol determination processing 214, a feedback filtering processing 215, a coefficient control processing 216, and a DPLL processing 217.

[0022] The multiplication process 211 multiplies the input signal by a phase control amount determined by the DPLL process 217 (described later) to generate a signal u(n). u(n) is a 1×M matrix with complex numbers as components, and u(n)=(u[n],...,u[n-M+1])∈C １×Ｍ M is a positive integer that is arbitrarily set by the user of the equalization device 20.

[0023] The feedforward filtering process 212 applies the feedforward filter coefficients w to the signal u(n). ＦＦ (n) is applied. ＦＦ (n) is an M × 1 matrix whose elements are complex numbers, and w ＦＦ (n)∈C Ｍ×１ The feedforward filtering 212 can be expressed as follows: Ｈ ＦＦ (n)u(n) is generated, where the superscript H denotes the Hermitian transpose.

[0024] The addition process 213 is a process of adding the processing result of the feedforward filter process 212 and the processing result of the feedback filter process 215. The addition process 213 calculates an output signal y(n). The output signal y(n) is expressed by equation (1).

[0025] The symbol decision process 214 is a process for making a symbol decision on the output signal y(n), and generates a symbol decision signal f(n).

[0026] The feedback filter processing 215 applies the feedback filter coefficients w to the feedback signal F(n). ＦＢ The feedback signal F(n) is a 1×L matrix with components f(n−1) to f(n−L), where F(n)=(f(n−1),...,f(n−L))∈C １×Ｌ where L is a positive integer that is arbitrarily set by the user of the equalization device 20. ＦＢ (n) is an L × 1 matrix whose components are complex numbers, and w ＦＢ (n)∈C Ｌ×１ It can be expressed as:

[0027] The feedback filter processing 215 generates the signal w Ｈ ＦＢ (n) F(n) is calculated.

[0028] The coefficient control process 216 controls the coefficient w ＦＦ(n) and the coefficient w in the feedback filtering process 215 ＦＢ The coefficient control process 216 controls the coefficient w (n) based on the result of the outlier determination process 23. ＦＦ (n) and w ＦＢ The coefficient control process 216 controls the coefficient w(n) when the result of the outlier determination process 23 indicates that the input signal is an outlier. ＦＦ (n) and w ＦＢ The coefficient control process 216 is a process that does not update the coefficient w(n) when the result of the outlier determination process 23 is that the input signal does not show an outlier. ＦＦ (n) and w ＦＢ The coefficient control process 216 is a process for updating the coefficient w(n) when using the LMS algorithm, for example. ＦＦ (n) and w ＦＢ (n) is updated using equation (2).

[0029] W(n) is the tap coefficient in the nth iteration. W(n) is the tap coefficient w ＦＦ (n) and tap coefficient w ＦＢ (n), W(n) = (w ＦＦ (n), w ＦＢ (n))∈C （Ｌ＋Ｍ）×１ It is expressed as:

[0030] In equation (2), μ is an arbitrary update coefficient. U(n) is the input signal to the filter at the nth iteration, and U(n) = (u(n), F(n)) ∈ C. （Ｌ＋Ｍ）×１ The superscript * indicates a complex conjugate. Equation (1) can also be written as equation (3).

[0031] The DPLL processing 217 is a process using a DPLL (Digital Phase Locked Loop) and determines the amount of phase control to be fed back to the input side based on the error signal e(n).

[0032] As described above, in the signal processing according to the first embodiment, when the square of the absolute value of the error signal e(n) is equal to or greater than a predetermined threshold, the tap coefficients of the filter in the equalization processing 21 are not updated. This makes it possible to prevent the tap coefficients from fluctuating significantly when impulsive noise is included in the input signal.

[0033] 5 is a diagram illustrating the flow of signal processing according to a second embodiment. The signal processing according to the second embodiment includes a sample recording process 24 and a threshold determination process 25 in addition to the signal processing according to the first embodiment.

[0034] The sample recording process 24 records the error signal e(n) calculated in each iteration. The threshold determination process 25 determines a threshold based on the recorded error signal e(n). The outlier determination process 23 determines whether the error signal e(n) is equal to or greater than the threshold determined by the threshold determination process 25.

[0035] The threshold determination process 25 determines the threshold based on, for example, a cumulative distribution function calculated from the recorded error signal e(n). The threshold determination process 25 determines the threshold T using equation (4).

[0036] In equation (4), Pr(|e(m)| ２ ) is a cumulative distribution function derived from the error signal e(m) (m = 1, ..., M). x indicates the criterion for determining an outlier. In other words, the threshold T is an arbitrary cumulative distribution frequency value calculated based on the cumulative distribution function obtained from the sample values ​​of the error signal e(m), and the threshold determination process 25 is a process that determines the top x% of the error signal as an outlier using equation (4).

[0037] The threshold value determination process 25 may be a process of determining a value that is a predetermined number of degrees away from a sample variance value calculated from the collected error signal e(n) as the threshold value. ２ is calculated by equation (5), and the threshold T is calculated by equation (6).

[0038] In equation (6), the right-hand side is a value N frequencies away from the sample variance value.

[0039] Sample variance σ ２ may be the square of the median of the recorded error signal e(n).

[0040] FIG. 6 is a flowchart of signal processing according to the second embodiment. The equalizer 20 performs equalization processing 21 on the signal received by the transceiver 10 and input to the equalizer 20 (step S21). The equalizer 20 generates an error signal e(n), which is the difference between the output signal y(n) generated by the equalization processing and the symbol decision signal f(n), using an error calculation processing 22 (step S22). The equalizer 20 records the generated error signal e(n) using a sample recording processing 24 (step S23). Before recording the error signal e(n), a predetermined number of error signals, such as e(n-1) collected in the previous iteration, have already been recorded. The number of error signals recorded and used to calculate the threshold may be limited. For example, when recording a newly generated error signal, the oldest recorded error signal may be deleted from the device that stores the error signals, thereby updating the error signal data set.

[0041] The equalization device 20 determines a threshold value based on the error signal e(n) recorded by the threshold determination process 25. The equalization device 20 determines whether the square of the absolute value of the error signal e(n) is equal to or greater than the determined threshold value by the outlier determination process 23, and determines whether the input signal represents an outlier (step S25). The equalization device 20 controls the equalization process 21 based on the determination result (step S26).

[0042] The equalization device 20 repeats steps S21 to S26 to generate an output signal y(n) corresponding to the input signal and control the equalization process 21.

[0043] In the signal processing according to the second embodiment, in addition to the first embodiment, a threshold value serving as a criterion for outlier detection can be calculated based on an error signal, which allows the equalization method to be adapted to the environment in which the transceiver 10 transmits and receives signals, thereby improving the accuracy of outlier detection.

[0044] 7 is a diagram illustrating the flow of signal processing according to a third embodiment. The signal processing according to the third embodiment includes a threshold determination process 26 in addition to the signal processing according to the first embodiment.

[0045] In the third embodiment, the threshold determination process 26 is a process for determining a threshold based on the modulation method used by the transceiver 10. The modulation method is, for example, quadrature amplitude modulation (QAM) or phase-shift-keying (PSK).

[0046] In the third embodiment, the outlier determination process 23 determines whether an outlier has been detected based on the distance between the output signal y(n) and the symbol decision signal f(n), which is the absolute value of the error signal e(n).

[0047] The threshold for the distance between signal points is determined by the size of the smallest radius when two circles with the same radius and centered at each signal point intersect. Figure 8 shows signal points when the modulation method is BPSK. When the modulation method is BPSK, the size of the smallest radius when two circles with the same radius and centered at two signal points intersect is 1. Therefore, when the signal point indicated by the symbol decision signal is F, the output signal indicated by point Y1 is determined to be not an outlier, but the output signal indicated by point Y2 is determined to be an outlier. In this case, the outlier decision process 23 is a process for determining whether the square of the absolute value of the error signal e(n) is 1 or greater.

[0048] 9 is a diagram showing signal points when the modulation method is QPSK. When the modulation method is QPSK, the smallest radius when two circles with the same radius and centered on four signal points are tangent is 1 / √2. In this case, outlier determination process 23 determines whether the square of the absolute value of error signal e(n) is 1 / 2 or more.

[0049] In the third embodiment, the equalizer 20 acquires the modulation scheme used by the transceiver 10 through a threshold determination process 26. In the third embodiment, the equalizer 20 references a storage device through the threshold determination process 26 and determines a threshold corresponding to the acquired modulation scheme. The storage device referenced here stores the modulation scheme and the corresponding threshold. The storage device may be provided in the equalizer 20 or may be provided externally to the equalizer 20.

[0050] In the signal processing according to the third embodiment, in addition to the first embodiment, a threshold value that serves as a criterion for outlier detection can be calculated based on the modulation method used by the transceiver 10. This allows the equalization method to be adapted to the modulation method used by the transceiver 10, thereby improving the accuracy of outlier detection.

[0051] (Other Embodiments) The above-described embodiments are not limited to underwater communications, but are applicable to communications in all environments where impulsive noise occurs.

[0052] Although an embodiment of the present invention has been described in detail above with reference to the drawings, the specific configuration is not limited to this embodiment, and includes designs within the scope of the present invention that do not deviate from the gist of the present invention.

[0053] 10 is a diagram showing an example of the hardware configuration of the equalization device 20 according to the embodiment. The equalization device 20 includes a control unit 11 having a processor 91 and a memory 92 connected by a bus, and executes a program. By executing the program, the equalization device 20 functions as a device including the control unit 11, an interface unit 12, and a storage unit 13.

[0054] More specifically, the processor 91 reads out a program stored in the storage unit 13 and stores the read out program in the memory 92. The processor 91 executes the program stored in the memory 92, whereby the equalization device 20 functions as a device including the control unit 11, the interface unit 12, and the storage unit 13.

[0055] The control unit 11 controls the operation of each functional unit included in the equalization device 20. The control unit 11 acquires, for example, information stored in the memory unit 13. The process of acquiring information stored in the memory unit 13 is specifically reading. The control unit 11 may, for example, output various information to the memory unit 13. The memory unit 13 records the information output to the memory unit 13. The control unit 11 acquires, for example, information acquired by the interface unit 12. The control unit 11 controls, for example, the interface unit 12 to transmit the information to be transmitted to the destination.

[0056] The control unit 11 executes, for example, an equalization process, an error calculation process, and an outlier determination process.

[0057] The interface unit 12 includes a communication interface for connecting the equalization device 20 to an external device. The interface unit 12 communicates with the external device via wired or wireless communication. The external device is, for example, a device that transmits network information. The interface unit 12 acquires network information by communicating with the device that transmits the network information.

[0058] The interface unit 12 may be configured to include input devices such as a mouse, a keyboard, a touch panel, etc. The interface unit 12 may be configured as an interface that connects these input devices to the equalization device 20. In this way, the input devices of the interface unit 12 accept input of various information to the equalization device 20 via wired or wireless connections. Note that various information such as network information does not necessarily have to be input to the communication interface of the interface unit 12, and may also be input to the input devices of the interface unit 12.

[0059] The interface unit 12 outputs, for example, various types of information. The interface unit 12 includes a display device such as a CRT (Cathode Ray Tube) display, a liquid crystal display, an organic EL (Electro-Luminescence) display, or a three-dimensional display, and a speaker. The interface unit 12 may be configured as an interface that connects these display devices or speakers to the equalization device 20. Therefore, the display device and speaker included in the interface unit 12 output, for example, information input to an input device of the interface unit 12 as an image, a three-dimensional video, or sound.

[0060] The control unit 11 may, for example, control the operation of a display device or speaker that constitutes the interface unit 12 to output the estimation results and the like.

[0061] The storage unit 13 is configured using a non-transitory computer-readable recording medium such as a magnetic hard disk drive or a semiconductor storage device. The storage unit 13 stores various information related to the equalization device 20. The storage unit 13 stores, for example, error signals and output signals. The storage unit 13 may exist on, for example, a cloud.

[0062] 1 Communication system, 10 Transmitter / receiver, 11 Control unit, 12 Interface unit, 13 Storage unit, 20 Equalizer

Claims

1. An equalization device comprising: a control unit that executes an equalization process that equalizes an input signal and generates an output signal; an error calculation process that calculates the difference between the output signal and a symbol decision signal based on the output signal; and an outlier determination process that determines whether the input signal indicates an outlier based on the absolute value of the difference and a predetermined threshold; and wherein if the input signal is determined to be an outlier in the outlier determination process, the tap coefficients in the equalization process are not updated.

2. The equalization device according to claim 1, wherein the predetermined threshold is an arbitrary cumulative distribution frequency value calculated based on a cumulative distribution function obtained from sample values ​​of the difference.

3. The equalization device according to claim 1, wherein the predetermined threshold is a value that is a predetermined number of degrees away from a sample variance or a median.

4. The equalization device according to claim 1, wherein the predetermined threshold value is a value determined by the size of a circle centered on each signal point in a modulation method.

Images