Method and apparatus for link reestablishment after pcie link equalization failure, and device, storage medium and computer program product

Abstract

The present application relates to the technical field of computer communications. Disclosed are a method and apparatus for link reestablishment after a PCIe link equalization failure. The method comprises: determining a current state of a state machine and a state previous to the current state; when the current state is a speed recovery state and the previous state is an equalization recovery state, generating an initial reset request signal; after the initial reset request signal is generated, assigning a preset non-zero count value to a predefined counter, and starting decrement counting; and when the count value is not zero, generating a target reset pulse signal, wherein the target reset pulse signal is used for enabling the state machine to jump to a reset state. The present application uses direct hardware control, without the need for scheduling by a central processing unit; therefore, central processing unit and memory resources are not consumed, the impact on the overall system performance is relatively small, and a higher link reestablishment speed and a higher efficiency are achieved.

Description

Method and device for rebuilding PCIe link after equalization failure, equipment, storage medium and computer program product

[0001] Cross-reference to related applications

[0002] The present application claims priority from the Chinese patent application No. 202411319818.X entitled "Method and device for rebuilding PCIe link after equalization failure" and filed with the China Patent Office on September 20, 2024, the whole content of which is incorporated herein by reference. TECHNICAL FIELD

[0003] The present application relates to the field of computer communication technology, in particular to a method and device for rebuilding PCIe link after equalization failure, equipment, storage medium and computer program product. BACKGROUND

[0004] PCIe (Peripheral Component Interconnect Express, abbreviated as PCIe) is a high-speed serial computer expansion bus standard that can provide a high-bandwidth, low-latency data transmission channel, enabling various peripheral devices such as storage devices, network cards, graphics cards, etc. to effectively exchange data with the central processing unit (CPU). The design of PCIe adopts the mechanisms of full-duplex transmission, packet-based transmission and differential signal transmission, significantly improving the data transmission efficiency and the anti-interference ability of the signal, ensuring the stability of data transmission. To achieve high-speed and stable data communication, it is necessary to establish a reliable PCIe link between two communicating devices through link training according to the protocol specified process.

[0005] The establishment and stable operation of PCIe link are crucial to ensure the efficiency and reliability of data transmission, and this process is usually automatically completed by LTSSM (Link Training and Status State Machine). In the process of establishing PCIe link, in order to ensure the stability and reliability of data transmission, it is also necessary to equalize the signals on the link. However, during the equalization process, PCIe link may also fail to meet the requirements of bit error rate, resulting in the failure of equalization and the inability of data transmission on the link to achieve the expected performance standards.

[0006] In order to solve the problem of equalization failure in PCIe link establishment, the commonly used method is to use software intervention for scheduling after equalization failure, control the link to re-speed up and equalize, but if software configuration is to be realized, the equalization failure event needs to be monitored, and a signal is sent to the central processor when equalization failure occurs, and the central processor reconfigures the register related signal after monitoring the equalization failure, so the efficiency is not high, and the central processor and memory resources are consumed, affecting the overall system performance. SUMMARY

[0007] Therefore, the present application provides a PCIe link equalization failure reconstruction method and device to solve the problem of low efficiency of the reconstruction method by the central processor in the prior art.

[0008] In a first aspect, the present application provides a PCIe link equalization failure reconstruction method, which comprises:

[0009] determining the current state of the state machine and the previous state of the current state;

[0010] generating an initial reset request signal when the current state is a speed recovery state and the previous state is an equalization recovery state;

[0011] after generating the initial reset request signal, assigning a pre-defined counter to a preset non-zero count value and starting to count down;

[0012] generating a target reset pulse signal when the count value is not zero, the target reset pulse signal being used to make the state machine jump to a reset state.

[0013] For the problem of equalization failure in PCIe link establishment, the present application continuously obtains the current running state and the previous running state of LTSSM during equalization by hardware to determine whether the equalization is successful, generates a reset request signal with a configurable pulse width after determining the equalization failure, and generates a reset pulse signal to control the reset of LTSSM and the corresponding module. The method provided in the embodiment directly operates at the physical layer and is directly controlled by hardware, without the need for CPU scheduling, so it will not consume CPU and memory resources, and has less impact on the overall system performance. Compared with the traditional method, the reconstruction and equalization are directly controlled according to the state of LTSSM, without the need for software intervention to detect the link state and configure the related registers, so the method is faster and more efficient in handling the equalization failure scenario. The traditional method needs software participation, which is affected by the CPU state and other processes, so the hardware control is usually more stable and reliable.

[0014] In an alternative embodiment, the preset non-zero count value is set according to the width of the reset pulse, and the target reset pulse signal is disabled when the count value is decremented to zero. In this way, the length of the reset pulse can be configured to meet different startup or reset requirements.

[0015] In an alternative embodiment, the initial reset request signal includes a PCIe controller initial reset request signal and a PCIe physical layer initial reset request signal; the counter includes a PCIe controller counter and a PCIe physical layer counter; and the target reset pulse signal includes a PCIe controller target reset pulse signal and a PCIe physical layer target reset pulse signal.

[0016] After the initial reset request signal is generated, a preset counter is assigned a preset non-zero count value, including:

[0017] After the PCIe controller initial reset request signal is generated, the PCIe controller counter is assigned a preset non-zero count value.

[0018] After the PCIe physical layer initial reset request signal is generated, the PCIe physical layer counter is assigned a preset non-zero count value.

[0019] When the count value of the PCIe controller counter is not zero, the PCIe controller target reset pulse signal is generated, and the PCIe controller target reset pulse signal is used to make the state machine jump back to the link connection detection state.

[0020] When the count value of the PCIe physical layer counter is not zero, the PCIe physical layer target reset pulse signal is generated, and the PCIe physical layer target reset pulse signal is used to reset each channel of the physical layer.

[0021] In this embodiment, the operation is directly performed at the physical layer, and the re-linking and equalization are directly controlled according to the state of the LTSSM, without the need for software intervention to detect the link state and configure the related registers. When handling the equalization failure scenario, the method is faster and more efficient than the method requiring software intervention.

[0022] In an alternative embodiment, the state machine automatically jumps from the equalization recovery state to the speed recovery state in the case of link equalization failure. In this way, re-equalization is achieved, and the equalization success probability is improved.

[0023] In an alternative embodiment, the equalization recovery state includes a plurality of equalization sub-stages, and the state machine directly jumps to the next equalization sub-stage in the case of equalization success in one of the equalization sub-stages.

[0024] In an alternative embodiment, in the case that the equalization sub-stage is the last equalization sub-stage, the state machine jumps to the next preset state.

[0025] The method uses the characteristic that the equalization failure probability is small, and multiple attempts can be successful equalization, but compared with the related art, the method controls the re-linking without sending hardware information to the CPU, and does not need the CPU to configure the register according to the hardware state to control the state machine jump, but directly determines whether the equalization is successful and whether the reset signal needs to be generated according to the state machine jump condition, and then realizes the purpose of re-equalization after equalization failure. Without CPU scheduling, CPU and memory resources are not consumed, and the influence on the overall system performance is small.

[0026] In a second aspect, the application provides a device for re-linking after PCIe link equalization failure, the device comprising:

[0027] A determination module is configured to determine the current state of the state machine and the previous state of the current state.

[0028] A request generation module is configured to generate an initial reset request signal when the current state is a speed recovery state and the previous state is an equalization recovery state.

[0029] A counting module is configured to assign a pre-defined counter to a preset non-zero count value after the initial reset request signal is generated, and start counting down.

[0030] A reset generation module is configured to generate a target reset pulse signal when the count value is not zero, the target reset pulse signal being used to make the state machine jump to a reset state.

[0031] In a third aspect, the application provides a computer device, comprising a memory and a processor, the memory and the processor being in communication connection with each other, the memory storing computer instructions, and the processor executing the computer instructions to perform the PCIe link equalization failure re-linking method of the first aspect or any of the corresponding embodiments thereof.

[0032] In a fourth aspect, the application provides a computer readable storage medium, the computer readable storage medium storing computer instructions, the computer instructions being used to make the computer execute the PCIe link equalization failure re-linking method of the first aspect or any of the corresponding embodiments thereof.

[0033] In a fifth aspect, the application provides a computer program product, comprising computer instructions, the computer instructions being used to make the computer execute the PCIe link equalization failure re-linking method of the first aspect or any of the corresponding embodiments thereof.

[0034] It should be noted that the computer device and the computer readable storage medium provided by the application after the PCIe link equalization failure of the reestablishment chain device are corresponding to the PCIe link equalization failure of the reestablishment chain method described above. Therefore, the beneficial effects of the PCIe link equalization failure of the reestablishment chain device, the computer device and the computer readable storage medium are described in the corresponding beneficial effects of the PCIe link equalization failure of the reestablishment chain method, and will not be described here. BRIEF DESCRIPTION OF DRAWINGS

[0035] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the drawings needed in the description of the embodiments or the prior art will be briefly introduced. Obviously, the drawings in the following description are some embodiments of the present application, and those skilled in the art can obtain other drawings according to these drawings without creative labor.

[0036] Fig. 1 is a schematic diagram of LTSSM state jump in the related art;

[0037] Fig. 2 is a flowchart of a PCIe link equalization failure of a reestablishment chain method according to an embodiment of the present application;

[0038] Fig. 3 is a schematic diagram of a reestablishment chain method according to an embodiment of the present application;

[0039] Fig. 4 is a timing diagram of reestablishment chain after recovery.eq0 failure according to an embodiment of the present application;

[0040] Fig. 5 is a timing diagram of reestablishment chain after recovery.eq1 failure according to an embodiment of the present application;

[0041] Fig. 6 is a structural block diagram of a PCIe link equalization failure of a reestablishment chain device according to an embodiment of the present application;

[0042] Fig. 7 is a hardware structure diagram of a computer device according to an embodiment of the present application. DETAILED DESCRIPTION

[0043] In order to make the purpose, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some embodiments of the present application, not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0044] The establishment of the PCIe link is generally automatically completed by the LTSSM, and the states of the LTSSM are composed of eleven states of Detect, Polling, Configuration, Recovery, L0, L0s, L1, L2, Disabled, Loopback, and Hot Reset. Each state specifically means as follows, Detect: detecting link connection, Polling: waiting for link to be ready, Configuration: configuring link parameters, Recovery: link recovery state, L0: link working state, L0s: link low-power state, L1: link low-power mode, L2: link further low-power mode, Disabled: link being disabled, Loopback: link loopback test, and Hot Reset: link hot reset state. These states jump in the order shown in FIG. 1 as follows to complete the link training. When the link training is completed, the following goals are achieved: Bit Lock, Symbol Lock, Block Lock, determining Link Width, Lane Reversal, Polarity Inversion, Data Rate, and Lane-to-Lane De-skew. Among them, successfully completing the Data Rate negotiation is the main goal of the present application.

[0045] After an initial power-on reset, the PCIe performs link training based on a data rate of 2.5 GT / s to run in the L0 state. If both devices at both ends of the link support a higher rate, the link training needs to be switched to the Recovery state to run at the supported maximum rate. In the process of switching to a higher rate, signal distortion gradually becomes serious, and the error rate becomes high. Therefore, in the Recovery state, in addition to the speed upgrade, there is a Recovery.Equalization sub-state to perform equalization operation to improve the data of the sending end and the receiving end and reduce the influence of signal distortion on communication performance.

[0046] However, in the equalization process of the PCIe link, the equalization may fail due to the error rate not meeting the requirements all the time. This situation has a very small probability, but if the equalization fails and is not processed, the data transmission on the link will not be able to achieve the expected performance standard, such as being unable to perform data transmission and reception at the highest rate. In this case, the PCIe link will not be able to run in the most efficient state.

[0047] In order to solve the problem of equalization failure in PCIe link establishment, the existing method uses software intervention to schedule and control the link to re-enter the Recovery state for speed-up and equalization after equalization failure. The principle of this method is that the probability of equalization failure is extremely low, so it is almost impossible to have multiple equalization failures. However, this method has some problems in controlling the re-equalization.

[0048] According to the PCIe protocol, the LTSSM state transition sequence of a successful speed-up and equalization is as follows: L0-Recovery.Rcvrlock-Recovery.Rcvrcfg-Recovery.Speed-Recovery.Equalization (EQ0)-Recovery.Equalization (EQ1)-Recovery.Equalization (EQ2)-Recovery.Equalization (EQ3)-Recovery.Rcvrlock-Recovery.Rcvrcfg-Recovery.Idle-L0. In the above process, the link enters the Recovery.Speed state for speed-up, and enters the Recovery.Equalization state for equalization at the new speed. After successful equalization, the LTSSM state jumps from the Recovery state to the L0 state to run at the new speed.

[0049] The existing implementation scheme is as follows: after power-on reset, if the highest speed supported by both ends of the link is not Gen1 (Generation 1, referring to the first generation standard of PCIe), the LTSSM will be controlled to enter the Recovery state from L0 to perform speed upgrade and equalization according to the above LTSSM state transition sequence during link establishment. If equalization fails, the Recovery.equalization state will not transition to Recovery.Rcvrlock, but will transition to Recovery.speed state, and the original speed will be reduced in the Recovery.speed state, and then the Recovery.lock, Recovery.cfg, Recovery.idle states will be returned to L0 to run at the original speed. At this time, the link is not established at the highest speed, but it is not possible to jump to Recovery for speed upgrade through hardware, so it is necessary to control the LTSSM to enter Recovery from L0 for speed negotiation and link establishment through software control, that is, register configuration related signals. However, if software configuration is to be implemented, the equalization failure event needs to be monitored, and a signal needs to be sent to the CPU when equalization fails. The CPU will configure the register related signals after monitoring the equalization failure to control the LTSSM to enter the Recovery state from L0 again to perform speed upgrade and equalization operation. As can be seen, this method needs software intervention. After detecting equalization failure, the state machine is controlled to jump through register configuration, so as to re-execute speed upgrade and equalization to complete link establishment. Therefore, the efficiency is not high, and CPU and memory resources are consumed, which affects the overall system performance.

[0050] Therefore, according to the embodiments of the present application, a PCIe link equalization failure reconstruction method is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a state machine such as a group of computer executable instructions, and although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0051] In this embodiment, a PCIe link equalization failure reconstruction method is provided, which can be executed by a state machine. FIG. 2 is a flowchart of a PCIe link equalization failure reconstruction method according to an embodiment of the present application. As shown in FIG. 2, the flowchart includes the following steps:

[0052] Step S101, determine the current state of the state machine and the previous state of the current state. As described above, the establishment of the PCIe link is generally automatically completed by the LTSSM, and the states of the LTSSM consist of eleven states of Detect, Polling, Configuration, Recovery, L0, L0s, L1, L2, Disabled, Loopback, and Hot Reset. Among them, the equalization process usually occurs in the Recovery state to perform link equalization operations, optimize signal quality, and ensure stable link performance. And the LTSSM is in the physical layer of the PCIe bus, that is, the above-mentioned states are all completed in the physical layer of the PCIe bus.

[0053] For example, in the following link equalization jump sequence: L0-Recovery.Rcvrlock-Recovery.Rcvrcfg-Recovery.Speed-Recovery.Equalization (EQ0)-Recovery.Equalization (EQ1)-Recovery.Equalization (EQ2)-Recovery.Equalization (EQ3)-Recovery.Rcvrlock-Recovery.Rcvrcfg-Recovery.Idle-L0, except the L0 state, the others occur in the Recovery state. Therefore, the state machine state determined in the embodiment is preferably the equalization jump state in the Recovery state.

[0054] Step S102, generate an initial reset request signal when the current state is the speed recovery state and the previous state is the equalization recovery state. Among them, the speed recovery state in the embodiment refers to the state of the state machine for performing the link rate promotion operation, for example, “Recovery.Speed” in the above jump sequence; the equalization recovery state refers to the process of gradually equalizing at the new rate, trying different equalization stages to optimize the signal quality, for example, Equalization (EQ0), Recovery.Equalization (EQ1), Recovery.Equalization (EQ2), Recovery.Equalization (EQ3) in the above jump sequence.

[0055] In the embodiment, if the equalization stage fails, the state machine directly enters the Recovery.Speed state, which is different from the state transition sequence of the LTSSM state machine when the equalization succeeds. According to the state transition characteristics, whether the equalization succeeds or fails can be determined by judging the state transition sequence. If the equalization succeeds, no processing is performed; if the equalization fails, an initial reset request signal is generated for a certain time. In the embodiment, the initial reset request signal is generated when the current state is Recovery.Speed and the previous state is Equalization (EQ0), and the initial reset request signal is used to send a reset request.

[0056] In step S103, after the initial reset request signal is generated, a preset counter is assigned a preset nonzero count value, and the counter starts to count down.

[0057] In the embodiment, after the initial reset request signal is generated, a nonzero count value of the counter can be assigned according to a required reset pulse width, and the count value affects the final reset request duration and further controls the reset pulse width. After the preset nonzero count value is assigned, the count value of the counter is not 0, and the counter starts to count down.

[0058] In step S104, the target reset pulse signal is generated when the count value is not 0, and the target reset pulse signal is used to make the state machine jump to the reset state. In the embodiment, the target reset pulse signal is continuously generated when the count value is not 0, and the generation of the target reset pulse signal is stopped when the count value is 0. The target reset pulse signal can make the link jump to the Detect state and reset the state machine. That is, after the initial reset request signal is detected, the target reset pulse signal is generated to reset the LTSSM and related modules. After the LTSSM returns to the Detect state, the link establishment is restarted, so that the equalization is reestablished and the equalization success probability is improved.

[0059] For the problem of equalization failure in PCIe link establishment, the method continuously obtains the current running state and the last running state of LTSSM in equalization by hardware to determine whether the equalization is successful. After determining the equalization failure, a reset request signal with a configurable pulse width is generated to generate a reset pulse signal to control the reset of LTSSM and the corresponding module. The method provided in the embodiment directly operates at the physical layer and directly controls by hardware, without the need of CPU scheduling, so that the CPU and memory resources are not consumed, and the influence on the overall system performance is small. Compared with the traditional method, the re-link establishment and equalization are directly controlled according to the state of LTSSM without software intervention to detect the link state and configure the related registers, so that the method is faster and more efficient in processing the equalization failure scenario. The traditional method needs software participation, which is affected by the CPU state and other processes, so the hardware control is usually more stable and reliable.

[0060] In some optional embodiments, the preset non-zero count value is set according to the reset pulse width, and the target reset pulse signal is invalid in the case that the count value is decremented to zero, at which time the link starts to re-establish the link.

[0061] In the embodiment, the initial value of the counter can be set according to the requirement to generate the reset request signal with a configurable pulse width, and the reset pulse signal with a configurable pulse width can be generated according to the reset request signal. In this way, the length of the reset pulse can be configured to meet different start or reset requirements.

[0062] In some optional embodiments, the initial reset request signal includes a PCIe controller initial reset request signal and a PCIe physical layer initial reset request signal; the counter includes a PCIe controller counter and a PCIe physical layer counter; and the target reset pulse signal includes a PCIe controller target reset pulse signal and a PCIe physical layer target reset pulse signal.

[0063] After the initial reset request signal is generated, the preset non-zero count value is assigned to the counter, including:

[0064] After the PCIe controller initial reset request signal is generated, the PCIe controller counter is assigned to the preset non-zero count value.

[0065] After the PCIe physical layer initial reset request signal is generated, the PCIe physical layer counter is assigned to the preset non-zero count value.

[0066] In the case that the count value of the PCIe controller counter is not zero, the PCIe controller target reset pulse signal is generated, and the PCIe controller target reset pulse signal is used to make the state machine jump back to the detection of the link connection state.

[0067] In the case that the count value of the PCIe physical layer counter is not zero, a PCIe physical layer target reset pulse signal is generated, which is used to reset each channel of the physical layer.

[0068] In the embodiment, in the case that the current state is the speed recovery state and the previous state is the equalization recovery state, two reset request signals, i.e., a PCIe controller initial reset request signal and a PCIe physical layer initial reset request signal, are generated simultaneously. The PCIe controller initial reset request signal is a reset request signal for the PCIe controller, and the PCIe physical layer initial reset request signal is a reset request signal for the PCIe PHY, i.e., the physical layer of the PCIe. The PCIe controller is usually integrated in the chipset of the motherboard or as a separate chip on the expansion card, which connects the PCIe protocol with other parts of the computer system, such as the CPU, the memory, etc. The PCIe PHY, i.e., the physical layer, is usually integrated in the chip matched with the PCIe controller or exists as a separate physical layer chip. It is directly connected with the electrical connection of the PCIe link, responsible for converting data from digital signals to electrical signals and transmitting on the physical medium. The PCIe controller and the PCIe physical layer work together to ensure that the PCIe system can stably and quickly transmit data.

[0069] Referring to FIG. 3, first, the method is controlled by an enable signal, and if the method is enabled, the equalization failure reset request enable signal needs to be valid. After the method is enabled, the current state and the previous state of the LTSSM are continuously judged. If the previous state of the LTSSM is Recovery.Equalization.EQ0 and the current state is Recovery.Speed, or the previous state of the LTSSM is Recovery.Equalization.EQ1 and the current state is Recovery.Speed, a valid PCIe controller initial reset request signal and a PCIe_PHY initial reset request signal are generated. Otherwise, the PCIe controller initial reset request signal and the PCIe_PHY initial reset request signal are invalid.

[0070] Then, two counters, i.e., a PCIe controller counter and a PCIe physical layer counter, are defined, which are used to generate the final PCIe controller reset request signal and the PCIe_PHY reset request signal, respectively. The generation principle is as follows: when the PCIe controller initial reset request signal and the PCIe_PHY initial reset request signal are valid, a non-zero initial value is assigned to the two counters (the initial value will affect the final reset request duration, and then control the reset pulse width). Otherwise, if both initial reset request signals are invalid and the count value of the counter is not 0, the two counters start to count down.

[0071] The count values of the two counters are judged, and when the count values of the two counters are not equal to 0, valid PCIe controller reset pulse signals and PCIe_PHY reset pulse signals are respectively generated. Otherwise, when the two counters are decremented to 0, the two reset pulse signals become invalid. Thus, the initial values of the counters can be set according to requirements, and the reset request signals with configurable pulse width are realized, and according to the reset request signals, the reset pulse signals with configurable pulse width can be generated. The timing diagrams of the above process are shown in FIG. 4 and FIG. 5, FIG. 4 is a timing diagram of reestablishing a link after recovery.eq0 fails, and FIG. 5 is a timing diagram of reestablishing a link after recovery.eq1 fails. Wherein, ltssm_state is the current state of the LTSSM, ltssm_state_d is the last state of the LTSSM, ini_reset_req_phy is the initial reset request signal of the PCIe_PHY, ini_reset_req_ctrl is the initial reset request signal of the PCIe controller, cnt_phy is the PCIe controller counter for generating the final PCIe_PHY reset pulse signal, cnt_ctrl is the PCIe physical layer counter for generating the final PCIe controller reset pulse signal, final_reset_req_phy is the final PCIe_PHY target reset pulse signal, and final_reset_req_ctrl is the final PCIe controller target reset pulse signal.

[0072] When the final PCIe controller target reset pulse signal is valid, the valid PCIe controller reset pulse signal can be generated, and after reset, the state machine jumps back to the Detect.Quiet state; when the PCIe_PHY reset request pulse signal is valid, the valid PCIe_PHY reset pulse signal can be generated, and then the channels of the PCIE_PHY are reset. Thus, the link can be reestablished from the Detect state after the equalization fails.

[0073] In the embodiment, the operation is directly performed at the physical layer, the reestablishment and equalization are directly controlled according to the state of the LTSSM, and the software intervention is not needed to detect the link state and configure the related registers. The method is faster and more efficient than the method needing software intervention when processing the equalization failure scenario.

[0074] In some optional embodiments, the state machine automatically jumps from the equalization recovery state to the speed recovery state in the case of link equalization failure. The state machine can be automatically set to jump from the equalization recovery state to the speed recovery state in the case of link equalization failure before determining the current state of the state machine and the last state of the current state.

[0075] If the equalization fails when the link is built, the state machine enters a Recovery.Speed state. According to the state transition characteristics, whether the equalization is successful can be determined by judging the state transition sequence. If the equalization is successful, no processing is performed; if the equalization fails, a reset request signal is generated for a certain time. After the reset request signal is detected, a reset pulse signal is generated to reset the LTSSM and related modules. After the LTSSM returns to the Detect state, the link is built again, so that the equalization is re-performed, and the equalization success probability is improved.

[0076] In some optional embodiments, the equalization recovery state includes a plurality of equalization sub-stages. If the equalization is successful in one of the equalization sub-stages, the state machine directly jumps to the next equalization sub-stage.

[0077] In some optional embodiments, if the equalization sub-stage is the last equalization sub-stage, the state machine jumps to the next preset state.

[0078] As shown above, the equalization can include different equalization stages. If the equalization fails when the link is built, according to the time when the link fails, the equalization can be divided into EQ0 stage failure and EQ1 stage failure, etc. If the EQ0 stage fails, the state machine does not enter the EQ1 stage, but enters the Recovery.Speed state; if the EQ1 stage fails, the state machine does not enter the EQ2 stage, but enters the Recovery.Speed state, and so on. This is different from the state transition sequence of the LTSSM state machine when the equalization is successful. According to the state transition characteristics, whether the equalization is successful can be determined by judging the state transition sequence. If the equalization is successful, no processing is performed, and the state machine continues to jump to the next state; if the equalization fails, a reset request is generated for a certain time. After the reset request is detected, a reset pulse signal is generated to reset the LTSSM and related modules. After the LTSSM returns to the Detect state, the link is built again, so that the equalization is re-performed, and the equalization success probability is improved.

[0079] The method uses the feature that the equalization failure probability is small. The equalization can be successfully performed after multiple attempts. However, compared with related technologies, the method does not need to send hardware information to the CPU to control the state machine jump, and does not need the CPU to configure the registers according to the hardware state to control the state machine jump. Instead, whether the equalization is successful and whether a reset signal needs to be generated are determined according to the state machine jump, so that the purpose of re-equalization after equalization failure is achieved. The CPU does not need to be scheduled, so CPU and memory resources are not consumed, and the influence on the overall system performance is small.

[0080] The embodiment also provides a PCIe link reestablishment device after equalization failure, which is used for implementing the above-mentioned embodiment and preferred implementation, and details are not repeated. As used below, the term "module" can be a combination of software and / or hardware that implements a predetermined function. Although the device described in the following embodiment is preferably implemented in software, implementation of hardware, or a combination of software and hardware, is also possible and is contemplated.

[0081] The embodiment provides a PCIe link reestablishment device after equalization failure, as shown in FIG. 6, the device comprises:

[0082] A determination module 201 is configured to determine a current state of the state machine and a previous state of the current state.

[0083] A request generation module 202 is configured to generate an initial reset request signal when the current state is a speed recovery state and the previous state is an equalization recovery state.

[0084] A counting module 203 is configured to assign a predefined counter to a preset nonzero counting value after the initial reset request signal is generated, and start counting down.

[0085] A reset generation module 204 is configured to generate a target reset pulse signal when the counting value is not zero, and the target reset pulse signal is used to make the state machine jump to a reset state.

[0086] The PCIe link reestablishment device after equalization failure in the embodiment is presented in the form of functional units, where the units refer to ASIC circuits, processors and memories that execute one or more software or fixed programs, and / or other devices that can provide the above-mentioned functions.

[0087] Further function descriptions of the above-mentioned modules and units are the same as those of the corresponding embodiments, and are not repeated here.

[0088] The embodiment also provides a computer device with the PCIe link reestablishment device after equalization failure shown in FIG. 6.

[0089] Referring to FIG. 7, FIG. 7 is a structural diagram of a computer device according to an optional embodiment of the present application. As shown in FIG. 7, the computer device includes one or more processors 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. The various components communicate with each other using different buses, and can be mounted on a common main board or mounted in other manners as needed. The processor can process instructions executed within the computer device, including instructions stored in the memory or on the memory to display graphical information of a GUI on an external input / output device (such as a display device coupled to the interface). In some optional embodiments, multiple processors and / or multiple buses can be used with multiple memories and multiple memory banks, if necessary. Also, multiple computer devices can be connected, each providing part of the necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). One processor 10 is taken as an example in FIG. 7.

[0090] The processor 10 can be a central processor, a network processor, or a combination thereof. The processor 10 can further include a hardware chip. The hardware chip can be an application specific integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device can be a complex programmable logic device, a field programmable logic device, a general array logic, or any combination thereof.

[0091] The memory 20 stores instructions executable by the at least one processor 10, so that the at least one processor 10 executes the method shown in the above embodiments.

[0092] The memory 20 can include a program storage area and a data storage area. The program storage area can store an operating system and application programs required by at least one function; the data storage area can store data created according to the use of the computer device, etc. In addition, the memory 20 can include a high-speed random access memory, and can also include a non-transitory memory, such as at least one magnetic disk storage device, a flash memory device, or other non-transitory solid-state memory device. In some optional embodiments, the memory 20 can optionally include a memory remotely arranged with respect to the processor 10, and these remote memories can be connected to the computer device through a network. Examples of the network include but are not limited to the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof.

[0093] The memory 20 can include a volatile memory, such as a random access memory; the memory can also include a non-volatile memory, such as a flash memory, a hard disk, or a solid-state disk; and the memory 20 can further include a combination of the above kinds of memories.

[0094] The computer device also comprises a communication interface 30 for communication of the computer device with other devices or communication networks.

[0095] The embodiments of the present application further provide a computer readable storage medium, and the method according to the embodiments of the present application can be implemented in hardware, firmware, or recorded in a storage medium, or be implemented as computer code originally stored in a remote storage medium or non-transitory machine readable storage medium and downloaded to a local storage medium and stored in the local storage medium, so that the method described herein can be processed by such software on a storage medium using a general purpose computer, a special purpose processor, or programmable or special hardware. The storage medium can be a magnetic disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk, or a solid state disk, etc. Further, the storage medium can also include a combination of the above-mentioned memories. It can be understood that the computer, the processor, the microprocessor controller, or the programmable hardware includes a storage component that can store or receive software or computer code, when the software or computer code is accessed and executed by the computer, the processor, or the hardware, the method shown in the above embodiments is implemented.

[0096] Part of the present application can be applied as a computer program product, for example, computer program instructions, when executed by a computer, through the operation of the computer, the method and / or technical solutions according to the present application can be invoked or provided. Those skilled in the art should understand that the form of computer program instructions in a computer readable medium includes but is not limited to source files, executable files, installation package files, etc. Correspondingly, the way of computer program instructions executed by a computer includes but is not limited to: the computer directly executes the instructions, or the computer executes the corresponding compiled program after compiling the instructions, or the computer reads and executes the instructions, or the computer reads and installs the instructions and then executes the corresponding installed program. Here, the computer readable medium can be any available computer readable storage medium or communication medium accessible to the computer.

[0097] Although the embodiments of the present application are described in conjunction with the accompanying drawings, various modifications and changes can be made by those skilled in the art without departing from the spirit and scope of the present application, and such modifications and changes fall within the scope defined by the appended claims.

Claims

1. A method for reestablishing a link after a PCIe link equalization failure, the method comprising: The method comprises: determining a current state of a state machine and a previous state of the current state; generating an initial reset request signal in a case where the current state is a speed recovery state and the previous state is an equalization recovery state; after the initial reset request signal is generated, assigning a predefined counter with a preset non-zero count value and starting self-decrement counting; generating a target reset pulse signal in a case where the count value is not zero, the target reset pulse signal being used to make the state machine jump to a reset state.

2. The method of claim 1, wherein, The preset non-zero count value is set according to a reset pulse width, and the target reset pulse signal is disabled in a case where the count value is decremented to zero.

3. The method of claim 1, wherein, The initial reset request signal comprises a PCIe controller initial reset request signal and a PCIe physical layer initial reset request signal; the counter comprises a PCIe controller counter and a PCIe physical layer counter; and the target reset pulse signal comprises a PCIe controller target reset pulse signal and a PCIe physical layer target reset pulse signal. The step of assigning the predefined counter with the preset non-zero count value after the initial reset request signal is generated comprises: assigning the PCIe controller counter with the preset non-zero count value after the PCIe controller initial reset request signal is generated; assigning the PCIe physical layer counter with the preset non-zero count value after the PCIe physical layer initial reset request signal is generated; generating the PCIe controller target reset pulse signal in a case where the count value of the PCIe controller counter is not zero, the PCIe controller target reset pulse signal being used to make the state machine jump back to a link connection detection state; generating the PCIe physical layer target reset pulse signal in a case where the count value of the PCIe physical layer counter is not zero, the PCIe physical layer target reset pulse signal being used to reset each channel of the physical layer.

4. The method of claim 1, wherein, The state machine automatically jumps from the equalization recovery state to the speed recovery state in a case where link equalization fails.

5. The method of claim 1, wherein, The equalization recovery state comprises a plurality of equalization sub-stages, and the state machine directly jumps to a next equalization sub-stage in a case where equalization succeeds in one of the equalization sub-stages.

6. The method of claim 5, wherein, The state machine jumps to a next preset state in a case where the equalization sub-stage is a last equalization sub-stage.

7. A link reconstruction device after PCIe link equalization failure, characterized in that, The apparatus comprises: a determining module configured to determine a current state of a state machine and a previous state of the current state; a request generating module configured to generate an initial reset request signal in a case where the current state is a speed recovery state and the previous state is an equalization recovery state; a counting module configured to assign a predefined counter with a preset non-zero count value and start self-decrement counting after the initial reset request signal is generated; a reset generating module configured to generate a target reset pulse signal in a case where the count value is not zero, the target reset pulse signal being used to make the state machine jump to a reset state.

8. A computer device, comprising: The apparatus comprises: A memory and a processor, which are connected in communication with each other, the memory storing computer instructions, and the processor executing the computer instructions to perform the method of claim 1-6.

9. A computer-readable storage medium, characterized in that, The computer readable storage medium stores computer instructions for causing the computer to perform the method of claim 1-6.

10. A computer program product, characterised in that, Computer instructions for causing a computer to perform the method of claim 1-6.

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