Display device

Abstract

[Problem] To further improve display quality. [Solution] This display device is provided with a plurality of pixel circuits each comprising: a light emitting element; a capacitor that holds a luminance signal as a voltage; a first transistor that supplies a current corresponding to the luminance signal to the light emitting element; a second transistor that supplies and holds the luminance signal; a third transistor that initializes a voltage applied to the light emitting element; and a fourth transistor that controls light emission of the light emitting element by controlling a current flowing through the first transistor. Channels of a pair of transistors of the same type included in two adjacent pixel circuits are arranged alongside each other such that the respective directions in which a current flows therethrough are opposite, and a drain of one transistor of the pair and a source of the other transistor face each other across an inter-element separation region.

Description

display device

[0001] FIELD Embodiments of the present disclosure relate to a display device.

[0002] A display device driven by a so-called active matrix system generally has a configuration in which pixel circuits, each consisting of a light-emitting element and a drive circuit for driving the light-emitting element, are provided at positions corresponding to the intersections of scan lines extending along the lateral direction (hereinafter also referred to as the horizontal direction) of the display surface and arranged in a plurality of rows in the longitudinal direction (hereinafter also referred to as the vertical direction) of the display surface, and data lines (signal lines) extending along the vertical direction and arranged in a plurality of rows in the horizontal direction. One pixel circuit corresponds to one pixel or subpixel. By changing the potentials of the scan lines and signal lines at appropriate times, the on / off of active elements (e.g., transistors) provided in the drive circuit within the pixel circuit is appropriately controlled, thereby controlling the light emission of the light-emitting element in the pixel circuit. As an example of a display device driven by the active matrix system, a display device using organic light-emitting diodes (OLEDs) as light-emitting elements (hereinafter also referred to as an organic electroluminescence (EL) display device) has been developed (see, for example, Patent Document 1).

[0003] The display surface of a display device driven by the active matrix method is configured by arranging a plurality of pixel circuits in a matrix.

[0004] Patent No. 7185733

[0005] However, with this configuration, there is a concern that a parasitic capacitance may be formed between the active region of the diffusion layer in one pixel circuit and the active region of the diffusion layer in another adjacent pixel circuit, causing coupling between the active regions via the parasitic capacitance. If coupling occurs, the operation of one pixel circuit will affect the operation of the other adjacent pixel circuit, which may result in a failure to obtain the desired light emission brightness and lead to a deterioration in display quality.

[0006] In recent years, organic EL display devices have been considered for incorporation into wearable devices. For such applications, in order to reduce the size and weight of wearable devices, organic EL display devices are also required to be smaller and lighter. However, when attempting to make organic light-emitting display devices smaller, it is necessary to further shorten the distance between adjacent pixel circuits, which makes the above-mentioned coupling effect more pronounced. Therefore, there has been a strong demand for technology to suppress the coupling effect between adjacent pixel circuits, particularly in small organic light-emitting display devices.

[0007] Therefore, the present disclosure provides a display device that can further improve display quality.

[0008] In order to solve the above-mentioned problems, according to the present disclosure, there is provided a display device comprising a plurality of pixel circuits each having a light-emitting element, a capacitor that holds a luminance signal as a voltage, a first transistor that supplies a current corresponding to the luminance signal to the light-emitting element, a second transistor that supplies and holds the luminance signal, a third transistor that initializes an applied voltage to the light-emitting element, and a fourth transistor that controls the light emission of the light-emitting element by controlling the current flowing in the first transistor, wherein the channels of pairs of like transistors included in two adjacent pixel circuits are arranged side by side so that the current flows in opposite directions, and the drain of one transistor of the pair and the source of the other transistor face each other across an inter-element isolation region.

[0009] Each transistor of the pair may be provided so as to protrude toward the opposing pixel circuit, and the pair may be arranged side by side in a direction substantially perpendicular to a direction in which the adjacent pixel circuits are adjacent to each other.

[0010] The pixel circuit may be a pixel circuit of one of a plurality of sub-pixels included in one pixel, and the pair may be arranged to fit within the width of one of the sub-pixels in a direction substantially perpendicular to the adjoining direction of the adjacent pixel circuits.

[0011] The direction of current flow in the channel of the first transistor and the direction of current flow in the channel of the third transistor may be substantially the same.

[0012] A channel width on a source side of the first transistor may be different from a channel width on a channel side of the first transistor.

[0013] Between adjacent pairs, the channels of the same type of transistors may be arranged side by side so that the current flows in the same direction.

[0014] The pair may be the third transistor pair.

[0015] The pair may be the fourth transistor pair.

[0016] The gates of the pair of transistors of the same type may be a connection gate that is connected across a plurality of the pixel circuits.

[0017] The semiconductor device may further include a contact electrically connected to the connection gate at an end of the connection gate.

[0018] The display device may further include a display panel having a plurality of pixels each including the pixel circuit, and the contact may be electrically connected to the connecting gate at an edge of the display panel.

[0019] Each transistor of the pair may have one diffusion layer to which a fixed potential is supplied.

[0020] The diffusion layer to which the fixed potential is supplied may be adjacent to the diffusion layer of the first transistor via an inter-element isolation region.

[0021] The direction of current flow in the channel of the first transistor and the direction of current flow in the channel of the third transistor may differ by approximately 90°.

[0022] The two adjacent pixel circuits comprising the pair may be arranged in a mirror-inverted manner.

[0023] 1 is a schematic diagram showing the overall configuration of a display device according to the present embodiment; FIG. 2 is a schematic diagram showing the configurations of a pixel section, a scanning section, and a selection section shown in FIG. 1 in more detail; FIG. 3 is a schematic diagram showing the configuration of a pixel circuit shown in FIG. 2; FIG. 4 is a circuit diagram showing an example of parasitic capacitance generated in a pixel circuit; FIG. 5 is a layout diagram showing an example of the configuration of a general pixel circuit; FIG. 6 is a cross-sectional view showing an example of the configuration of a general pixel circuit; FIG. 7 is a layout diagram showing an example of the configuration of a pixel circuit according to the first embodiment; FIG. 8 is a cross-sectional view showing an example of the configuration of a pixel circuit according to the first embodiment; FIG. 9 is a layout diagram showing an example of the configuration of a pixel circuit according to the second embodiment; FIG. 10 is a circuit diagram showing an example of the configuration of a pixel circuit according to the third embodiment; FIG. 11 is a circuit diagram showing an example of the configuration of a pixel circuit according to the third embodiment; FIG. 12 is a layout diagram showing an example of the configuration of a pixel circuit according to the fourth embodiment; FIG. 13 is a layout diagram showing an example of the configuration of a pixel circuit according to a first modified example of the fourth embodiment; FIG. 14 is a layout diagram showing an example of the configuration of a pixel circuit according to the fifth embodiment; FIG. 15 is a layout diagram showing an example of the configuration of a pixel circuit according to the sixth embodiment; FIG. 16 is a circuit diagram showing an example of the configuration of a pixel; FIG. 17 is a circuit diagram showing an example of the configuration of a pixel; FIG. 18 is a circuit diagram showing an example of the configuration of a pixel; FIG. 1 is an external view of a head-mounted display which is an application example 1 of the display system (electronic device). FIG. 2 is an external view of a head-mounted display which is an application example 2 of the display system (electronic device). FIG. 3 is a front view of a digital camera which is an application example 3 of the display system (electronic device). FIG. 4 is a rear view of a digital camera. FIG. 5 is an external view of a television device which is an application example 4 of the display system (electronic device). FIG. 6 is an external view of a smartphone which is an application example 5 of the display system (electronic device). FIG. 7 is a view of the interior of a vehicle as seen from the rear of the vehicle which is an application example 6 of the display system (electronic device). FIG. 8 is a view of the interior of a vehicle as seen from the left rear of the vehicle.

[0024] Hereinafter, an embodiment of a display device will be described with reference to the drawings. The following description will focus on the main components of the display device, but the display device may include components and functions that are not shown or described. The following description does not exclude components and functions that are not shown or described.

[0025] 1. Overall Configuration of Display Device The overall configuration of a display device according to an embodiment of the present disclosure will be described with reference to Figures 1 and 2. Figure 1 is a schematic diagram showing the overall configuration of a display device according to this embodiment. Figure 2 is a schematic diagram showing in more detail the configurations of the pixel unit, scanning unit, and selection unit shown in Figure 1.

[0026] Referring to FIG. 1 , the display device 1 according to this embodiment is configured by arranging a pixel unit 20, a scanning unit 30, and a selection unit 40 on a display panel 10. As shown in FIG. 2 , the pixel unit 20 is configured by arranging a plurality of pixel circuits 210 in a matrix. Note that, for convenience, the pixel circuit 210 is referred to as a pixel circuit 210, but the "pixel circuit 210" shown in FIG. 2 indicates a portion of the pixel circuit 210 excluding the wiring layer. In reality, the pixel circuit 210 can be configured by connecting each wiring (such as wiring extending from the scanning unit 30 and the selection unit 40, which will be described later, and a power supply line 332) to the "pixel circuit 210" shown in FIG. 2. In other words, these wirings can be provided in common to a plurality of pixel circuits 210, but can also constitute part of the pixel circuit 210. Therefore, for convenience, the portion of the pixel circuit 210 excluding the wiring layer is illustrated as the pixel circuit 210 in FIG. 2 . In this specification, when the pixel circuit 210 is referred to, it may refer to only the portion excluding the wiring layer, for the sake of convenience.

[0027] One pixel circuit 210 corresponds to one sub-pixel. Here, the display device 1 is a display device capable of color display, and one pixel, which is a unit for forming a color image, is composed of multiple sub-pixels. Specifically, one pixel is composed of three sub-pixels: a sub-pixel that emits red light, a sub-pixel that emits green light, and a sub-pixel that emits blue light. In FIG. 2 , the colors (R, G, B) corresponding to each sub-pixel are written on each pixel circuit 210 for illustrative purposes. By appropriately controlling the light emission of each pixel circuit 210 (i.e., each sub-pixel), a desired image is displayed in the pixel section 20. In this way, the pixel section 20 corresponds to the display surface of the display device 1.

[0028] However, in this embodiment, the combination of sub-pixels constituting one pixel is not limited to the combination of sub-pixels of the three primary colors of RGB. For example, it is also possible to configure one pixel by adding sub-pixels of one or more colors to the three primary color sub-pixels. Specifically, for example, it is also possible to configure one pixel by adding sub-pixels that emit white light to the three primary color sub-pixels to improve brightness, or by adding at least one sub-pixel that emits complementary color light to the three primary color sub-pixels to expand the color reproduction range. Alternatively, the display device 1 may be configured without sub-pixels, with one pixel circuit 210 corresponding to one pixel. Furthermore, the display device 1 does not have to be capable of color display and may be capable of monochrome display.

[0029] The scanning unit 30 is disposed on one side of the pixel unit 20 in the horizontal direction. A plurality of wirings arranged in a vertical direction extend from the scanning unit 30 in the horizontal direction toward the pixel unit 20. Specifically, as shown in FIG. 2 , the scanning unit 30 is composed of a write scanning unit 301, a first drive scanning unit 311, and a second drive scanning unit 321. A plurality of scanning lines 302 extend from the write scanning unit 301 toward each row of the pixel circuits 210, a plurality of first drive lines 312 extend from the first drive scanning unit 311 toward each row of the pixel circuits 210, and a plurality of second drive lines 322 extend from the second drive scanning unit 321 toward each row of the pixel circuits 210. These plurality of wirings (scanning lines 302, first drive lines 312, and second drive lines 322) are connected to each pixel circuit 210. The write scanning unit 301, the first drive scanning unit 311, and the second drive scanning unit 321 appropriately change the potentials of these multiple wirings to control the operation of each pixel circuit 210 so that a desired image can be displayed on the entire display surface. Details of the connection state between the scanning lines 302, the first drive lines 312, and the second drive lines 322 and the pixel circuits 210, as well as the functions of the write scanning unit 301, the first drive scanning unit 311, and the second drive scanning unit 321 will be described later with reference to FIG.

[0030] The selection unit 40 is disposed on one side of the pixel unit 20 in the vertical direction. A plurality of wirings arranged in the horizontal direction extend from the selection unit 40 in the vertical direction toward the pixel unit 20. Specifically, as shown in FIG. 2 , the selection unit 40 is composed of a signal output unit 401. A plurality of signal lines 402 extend from the signal output unit 401 toward each column of pixel circuits 210. These signal lines 402 are connected to each pixel circuit 210 in the pixel unit 20. The signal output unit 401 controls the operation of each pixel circuit 210 by appropriately changing the potential of these signal lines 402 so that a desired image can be displayed across the entire display surface. Details of the connection state between the signal lines 402 and the pixel circuits 210 and the function of the signal output unit 401 will be described later with reference to FIG. 3 .

[0031] In this way, wiring extending in the horizontal direction from the scanning unit 30 is provided corresponding to each row of the pixel circuits 210 arranged in a matrix, and is connected to each pixel circuit 210. Furthermore, wiring extending in the vertical direction from the selection unit 40 is provided corresponding to each column of the pixel circuits 210 arranged in a matrix, and is connected to each pixel circuit 210. The scanning unit 30 and the selection unit 40 then appropriately change the potentials of these multiple wirings, thereby controlling the operation of each pixel circuit in the pixel unit 20.

[0032] 2. Pixel Circuit Configuration The configuration of the pixel circuit 210 shown in Fig. 2 will be described with reference to Fig. 3. Fig. 3 is a schematic diagram showing the configuration of the pixel circuit 210 shown in Fig. 2. Fig. 3 shows the circuit configuration of one pixel circuit 210 out of the multiple pixel circuits 210 shown in Fig. 2, and also shows the connection state of a scanning line 302, a first drive line 312, a second drive line 322, and a signal line 402 to the pixel circuit 210. Note that Fig. 3 shows, for example, an example of a micro OLED (M-OLED) pixel circuit.

[0033] 3 , the pixel circuit 210 is composed of an organic light-emitting diode 211, which is a light-emitting element, and a drive circuit that drives the organic light-emitting diode 211 by passing a current through the organic light-emitting diode 211. The drive circuit is composed of four transistors, which are active elements (a drive transistor Drv, a sampling transistor WS, a light-emitting control transistor DS, and an auto-zero transistor AZ), and capacitance elements (a storage capacitance Cs and an auxiliary capacitance Csub). The pixel circuit 210 is composed of these elements connected to various wirings (the above-mentioned scanning line 302, first drive line 312, second drive line 322, and signal line 402, as well as a power supply line 332, which will be described later, etc.).

[0034] Note that an organic light-emitting diode having a general structure can be used as the organic light-emitting diode 211. The driving transistor Drv, the sampling transistor WS, the light-emission control transistor DS, and the auto-zero transistor AZ are P-channel four-terminal (source / gate / drain / backgate) transistors formed on a semiconductor such as silicon, and their structures may be similar to those of a general P-channel four-terminal transistor. Therefore, detailed descriptions of the structures of the organic light-emitting diode 211, the driving transistor Drv, the sampling transistor WS, the light-emission control transistor DS, and the auto-zero transistor AZ will be omitted here.

[0035] The cathode electrode of the organic light emitting diode 211 is connected to a common power supply line 331 (potential: V ＣＡＴＨ The anode electrode of the organic light emitting diode 211 is connected to the drain electrode of the drive transistor Drv.

[0036] The source electrode of the driving transistor Drv is connected to the drain electrode of the light-emitting control transistor DS, and the source electrode of the light-emitting control transistor DS is connected to a power supply line 332 (potential: VCCP, VCCP is the power supply potential). In addition, the gate electrode of the driving transistor Drv is connected to the drain electrode of the sampling transistor WS, and the source electrode of the sampling transistor WS is connected to a signal line 402.

[0037] Therefore, by making the sampling transistor WS conductive, a potential corresponding to the potential of the signal line 402 is applied to the gate electrode of the drive transistor Drv (the potential of the signal line 402 is written), and the drive transistor Drv is made conductive. At this time, by making the light-emission control transistor DS conductive, a potential corresponding to the signal potential VCCP is applied to the source electrode of the drive transistor Drv, and a drain-source current I ｄｓ is generated, and the organic light-emitting diode 211 is driven. At this time, the drain-source current I ｄｓ The magnitude of the gate potential V of the driving transistor Drv ｇ Since the gate potential V of the driving transistor Drv changes depending on ｇ That is, the light emission brightness of the organic light emitting diode 211 is controlled in accordance with the potential of the signal line 402 written by the sampling transistor WS.

[0038] In this way, the drive transistor Drv has a drain-source current I ｄｓ The sampling transistor WS has a function of controlling the gate voltage of the drive transistor Drv in accordance with the potential of the signal line 402, that is, by controlling the on / off of the drive transistor Drv, thereby writing the potential of the signal line 402 to the pixel circuit 210 (that is, sampling the pixel circuit 210 that writes the potential of the signal line 402). The light-emission control transistor DS also controls the potential of the source electrode of the drive transistor Drv, thereby sampling the drain-source current I ｄｓ and controls whether the organic light emitting diode 211 emits light or not.

[0039] The storage capacitor Cs is connected between the gate electrode of the driving transistor Drv (i.e., the drain electrode of the sampling transistor WS) and the source electrode of the driving transistor Drv. That is, the storage capacitor Cs is connected between the gate and source voltage V ｇｓThe auxiliary capacitance Csub is connected between the source electrode of the driving transistor Drv and the power supply line 332. The auxiliary capacitance Csub acts to suppress fluctuations in the source potential of the driving transistor Drv when the potential of the signal line 402 is written.

[0040] The signal output unit 401 writes the potential of the signal line 402 (signal line voltage Data) to the pixel circuit 210 by appropriately controlling the potential of the signal line 402 (specifically, as described above, the potential of the signal line 402 is written to the pixel circuit 210 selected by the sampling transistor WS). In this embodiment, the signal output unit 401 outputs a signal voltage V corresponding to a video signal via the signal line 402. ｓｉｇ and the first reference voltage V ｒｅｆ and the second reference voltage V ｏｆｓ Here, the first reference voltage V ｒｅｆ is a reference voltage for reliably turning off the organic light emitting diode 211. In addition, the second reference voltage V ｏｆｓ is the signal voltage V corresponding to the video signal ｓｉｇ This is a reference voltage (for example, a voltage corresponding to the black level of the video signal) and is used when performing a threshold correction operation, which will be described later.

[0041] A scanning line 302 is connected to the gate electrode of the sampling transistor WS. The write scanning unit 301 controls the on / off of the sampling transistor WS by changing the potential (scanning line voltage) of the scanning line 302, and controls the potential of the signal line 402 (for example, a signal voltage V corresponding to a video signal) described above. ｓｉｇ ) to the pixel circuits 210. In practice, as described with reference to FIG. 2 , a plurality of scanning lines 302 extend to each row of a plurality of pixel circuits 210 arranged in a matrix. When writing the potential of the signal line 402 to each pixel circuit 210, the write scanning unit 301 sequentially supplies a scanning line voltage of a predetermined value to the plurality of scanning lines 302, thereby scanning each pixel circuit 210 in sequence row by row.

[0042] 2, a plurality of signal lines 402 are actually extended to each column of a plurality of pixel circuits 210 arranged in a matrix. ｓｉｇ , the first reference voltage V ｒｅｆ , and the second reference voltage V ｏｆｓ is written to each pixel circuit 210 via a plurality of signal lines 402 in units of pixel rows selected by scanning by the write scanning unit 301. In other words, the signal output unit 401 writes the potential of the signal lines 402 in units of rows.

[0043] A first drive line 312 is connected to the gate electrode of the emission control transistor DS. The first drive scanning unit 311 controls the on / off of the emission control transistor DS by changing the potential (first drive line voltage) of the first drive line 312, thereby executing the process of controlling the emission / non-emission of the organic light-emitting diode 211 described above. In practice, as described with reference to FIG. 2 , a plurality of first drive lines 312 are extended to each row of a plurality of pixel circuits 210 arranged in a matrix. The first drive scanning unit 311 sequentially supplies a first drive line voltage of a predetermined value to the plurality of first drive lines 312 in synchronization with scanning by the write scanning unit 301, thereby appropriately controlling the emission / non-emission of each pixel circuit 210.

[0044] Furthermore, in the pixel circuit 210, the source electrode of the auto-zero transistor AZ is connected to the anode electrode of the organic light-emitting diode 211. The drain electrode of the auto-zero transistor AZ is connected to a ground line 333 (potential: VSSP, VSSP is the ground potential). The current path formed by the auto-zero transistor AZ allows the current flowing through the drive transistor Drv during the non-emitting period of the organic light-emitting diode 211 to flow to the ground line 333.

[0045] Here, as will be described later, when driving the pixel circuit 210 according to this embodiment, the threshold voltage V ｔｈIn addition, a threshold correction preparation operation is performed as a preliminary step before the threshold correction operation. In the threshold correction preparation operation, the gate potential V of the driving transistor Drv is corrected. ｇ and the source potential V ｓ As a result, the gate-source voltage V of the driving transistor Drv is ｇｓ is the threshold voltage V of the drive transistor Drv ｔｈ This is because the gate-source voltage V of the drive transistor Drv ｇｓ the threshold voltage V of the driving transistor Drv ｔｈ This is because the threshold correction operation cannot be performed normally unless the threshold is set to a value greater than the threshold.

[0046] Therefore, the gate potential V of the driving transistor Drv ｇ and the source potential V ｓ When the operation of initializing the organic light emitting diode 211 is performed, the anode potential V ａｎｏ is the threshold voltage V of the organic light-emitting diode 211 ｔｈｅｌ If this occurs, a current will flow from the drive transistor Drv to the organic light emitting diode 211, causing the organic light emitting diode 211 to emit light even during a non-light emitting period.

[0047] Therefore, in this embodiment, in order to prevent this phenomenon, a current circuit using the auto-zero transistor AZ is provided, which causes the current from the drive transistor Drv to flow into this current circuit without flowing into the organic light-emitting diode 211, making it possible to prevent the organic light-emitting diode 211 from emitting light unintentionally.

[0048] A second drive line 322 is connected to the gate electrode of the auto-zero transistor AZ. The second drive scanning unit 321 controls the on / off of the auto-zero transistor AZ by changing the potential of the second drive line 322 (second drive line voltage). Specifically, the second drive scanning unit 321 appropriately changes the second drive line voltage to perform at least a threshold correction preparation operation during the non-emission period, and adjusts the gate-source voltage V of the drive transistor Drv. ｇｓ is the threshold voltage V of the driving transistor Drv ｔｈ During the period when the voltage Vcc is greater than 0.01V, the auto-zero transistor AZ is made conductive, thereby opening the above-mentioned current circuit. In practice, as described with reference to FIG. 2, multiple second drive lines 322 are extended to each row of the multiple pixel circuits 210 arranged in a matrix. The second drive scanning unit 321 sequentially supplies a predetermined second drive line voltage to the multiple second drive lines 322 in synchronization with the scanning by the write scanning unit 301, thereby appropriately controlling the driving of the auto-zero transistor AZ so that the auto-zero transistor AZ is made conductive during the above-mentioned period.

[0049] The write scanning unit 301, the first drive scanning unit 311, the second drive scanning unit 321 and the signal output unit 401 can be configured using known techniques with various circuits that can realize the above-mentioned functions, such as a shift register circuit, so detailed explanation of their circuit configuration will be omitted here.

[0050] The configuration of the pixel circuit 210 according to this embodiment has been described above.

[0051] 3. Parasitic Capacitance FIG. 4 is a circuit diagram showing an example of the parasitic capacitance Cp generated in the pixel circuit 210. As shown in FIG.

[0052] 4 may be formed in the diffusion layer connected to the organic light-emitting diode 211 and anode electrode of the adjacent pixel circuit 210. The parasitic capacitance Cp may cause the pixel circuit 210 to malfunction. Details of the parasitic capacitance Cp will be described later with reference to FIGS. 5 and 6.

[0053] 4. Layout of the pixel circuit The layout of the diffusion layer, which is the layer in which each transistor of the pixel circuit 210 according to the present embodiment described above is formed, will be described. Here, in order to clarify the effects obtained by the layout according to the present embodiment, a general existing layout will first be described.

[0054] <4-1. General Layout> A case where the diffusion layer of the pixel circuit 210 according to this embodiment is configured in a general layout will be considered. Fig. 5 is a top view that schematically shows an example of the layout when the diffusion layer of the pixel circuit 210 according to this embodiment is configured in a general layout. In reality, a plurality of pixel circuits 210 are arranged in a matrix in the pixel section 20 of the display device 1, but for the sake of explanation, Fig. 5 illustrates the layout of pixel circuits 210 corresponding to three adjacent pixels. Note that Fig. 5 shows the layout of a portion of the pixel circuit 210.

[0055] In the pixel circuit 210 according to this embodiment, each transistor of the pixel circuit 210 is formed on a silicon substrate (the pixel circuit 210 is formed on a so-called silicon backplane). Fig. 5 illustrates a simplified layout of the diffusion layer, with active regions of the diffusion layer corresponding to the source and drain regions of each transistor constituting the pixel circuit 210 and gate regions functioning as gate electrodes of each transistor being represented by different hatching. In the drawing, regions within the subpixel that are not hatched are isolation regions in which oxide is formed by various known methods, such as STI (Shallow Trench Isolation) or LOCOS (Local Oxidation of Silicon).

[0056] In each pixel, the drain region of the drive transistor Drv and the source region of the auto-zero transistor AZ are regions to which the anode electrode of the organic light-emitting diode 211 formed above the transistor layer shown in the figure is connected (see also Figure 3 above).

[0057] Next, the relationship between the parasitic capacitance Cp and the layout of the diffusion layer shown in FIG. 4 will be described.

[0058] As described above, Fig. 5 is a layout diagram showing an example of the configuration of a general pixel circuit 210. Fig. 6 is a cross-sectional view showing an example of the configuration of a general pixel circuit 210. Fig. 6 is a cross-sectional view corresponding to the cross section shown by line A-A in Fig. 5.

[0059] FIG. 5 shows the drive transistors Drv (three drive transistors Drv1 to Drv3) and auto-zero transistors AZ (three auto-zero transistors AZ1 to AZ3) of the pixel circuits 210. Organic light-emitting diodes 211 are connected to the diffusion layer on the drain side (D side) of the drive transistor Drv, and different voltages are applied to each pixel circuit 210 depending on the desired brightness. A parasitic capacitance Cp, as shown in FIG. 6 , is formed in the diffusion layer connected to the organic light-emitting diodes 211 and anodes of adjacent pixel circuits 210. Note that while FIG. 6 illustrates the parasitic capacitance Cp in the inter-element isolation region (insulating layer 520, such as STI) that separates the diffusion layers 510 on the S side of the auto-zero transistors AZ, the parasitic capacitance between the organic light-emitting diodes 211 and the diffusion layer connected to the anodes is also formed in the substrate and wiring layer.

[0060] As the distance between pixel circuits 210 becomes shorter due to miniaturization, the influence of the parasitic capacitance Cp increases, and there is a risk that the pixel circuits 210 will not operate normally due to the parasitic capacitance Cp.

[0061] <4-2. Layout According to the Present Embodiment> In the present embodiment, the inconveniences that may arise in the general layout described above can be resolved by devising the layout. The layout of the diffusion layer of the pixel circuit 210 according to the present embodiment will be described with reference to Fig. 7. Fig. 7 is a top view that schematically shows an example of the layout of the diffusion layer of the pixel circuit 210 according to the present embodiment.

[0062] First Embodiment Fig. 7 is a layout diagram showing an example of the configuration of a pixel circuit 210 according to a first embodiment. Fig. 8 is a cross-sectional view showing an example of the configuration of a pixel circuit 210 according to the first embodiment. Fig. 8 is a cross-sectional view corresponding to the cross section shown on line BB in Fig. 7.

[0063] Pairs of transistors (of the same type) with the same function in adjacent pixel circuits 210 are arranged side by side so that their channel currents flow in opposite directions. Specifically, the auto-zero transistors AZ are arranged so that the channel current of the auto-zero transistor AZ2 flows in the opposite direction to that of the auto-zero transistors AZ1 and AZ3. That is, pairs of transistors of the same type are pairs of auto-zero transistors AZ arranged horizontally on the page in FIG. 7 . Parasitic capacitances Cp1, Cp2, Cp3, and Cp4 are formed between the organic light-emitting diodes 211 and the diffusion layers connected to the anodes of adjacent pixel circuits 210, and the D-side diffusion layer of the drive transistor Drv2 may not achieve the desired potential due to coupling. For example, even though a low potential needs to be maintained when the organic light-emitting diode 211 is not emitting light, the potential of the D-side diffusion layer of the drive transistor Drv2 rises due to coupling when the organic light-emitting diode 211 of the adjacent pixel is emitting light. In response to this, the potential of the D-side diffusion layer of the drive transistor Drv2 is prevented from rising via the parasitic capacitance Cp7 formed between the D-side diffusion layer of the auto-zero transistor AZ2, to which a fixed potential (e.g., VSSP) is applied, and the D-side diffusion layer of the drive transistor Drv2.

[0064] The drain of one transistor of the pair and the source of the other transistor face each other with an element isolation region (for example, an insulating layer 520 such as STI) sandwiched therebetween.

[0065] 7, the drain of the auto-zero transistor AZ2 is fixed to the potential VSSP. The drain of the auto-zero transistor AZ2 is adjacent to the drain of the drive transistor Drv and the like via an element isolation region. The drain of the auto-zero transistor AZ2 forms parasitic capacitances Cp5, Cp6, Cp7, Cp8, and Cp9 with the source of the auto-zero transistor AZ1, the drain of the drive transistor Drv1, the drain of the drive transistor Drv2, the drain of the drive transistor Drv3, and the source of the auto-zero transistor AZ3, respectively. The parasitic capacitances Cp5, Cp6, Cp7, Cp8, and Cp9 suppress fluctuations in the drain voltage of the drive transistor Drv2 due to the parasitic capacitances Cp1, Cp2, Cp3, and Cp4.

[0066] As described above, according to the first embodiment, the channels of a pair of transistors of the same type (e.g., auto-zero transistors AZ) in adjacent pixel circuits 210 are arranged side by side so that the current flows in opposite directions. The drain of one transistor of the pair and the source of the other transistor face each other across an inter-element isolation region. This allows for the parasitic capacitance formed between the diffusion layer to which a fixed potential is supplied and the diffusion layer of the transistor (e.g., drive transistor Drv) to suppress fluctuations in the potential of the diffusion layer of the transistor (e.g., drive transistor Drv) via parasitic capacitance from other adjacent pixel circuits. As a result, display quality can be further improved.

[0067] The organic light-emitting diode 211, which is a light-emitting element, is not limited to this, and may be, for example, an LED used in a micro LED (Light Emitting Diode) display.

[0068] Another method of suppressing coupling has been proposed, in which a well tap for fixing a well potential is disposed between the diffusion layers of adjacent pixel circuits 210, and the coupling is suppressed by the fixed potential (see, for example, Patent Document 1). However, this method requires the formation of a separate diffusion layer between the transistors of adjacent pixel circuits 210, which makes it difficult to miniaturize the pixel circuits 210 and reduce the spacing between the pixel circuits 210 due to the width of the diffusion layer and the space between the diffusion layers. In other words, it is difficult to achieve high definition.

[0069] In contrast to this, in the first embodiment, no well tap is provided, and it is possible to suppress changes in the potential of the diffusion layer via parasitic capacitance, thereby improving display quality without hindering higher definition.

[0070] 9 is a layout diagram showing an example of the configuration of a pixel circuit 210 according to a second embodiment. In the second embodiment, the arrangement of the auto-zero transistor AZ is different from that in the first embodiment.

[0071] The pair of identical transistors is a pair of auto-zero transistors AZ arranged in the vertical direction of the paper surface of FIG.

[0072] The direction of current flow in the channel of the drive transistor Drv and the direction of current flow in the channel of the auto-zero transistor AZ differ by approximately 90°.

[0073] Mirror inversion (mirror arrangement) is a technique for achieving high definition. In the example shown in Figure 9, auto-zero transistors AZ, such as auto-zero transistors AZ1 and AZ2, are arranged so that channel currents flow in opposite directions between vertically adjacent pixel circuits 210. This prevents the potential of the S-side diffusion layer of auto-zero transistor AZ4 from becoming an unintended potential, for example, due to the D-side diffusion layer of auto-zero transistor AZ3 to which a fixed potential VSSP is applied, via parasitic capacitances Cp1 and Cp2 formed between the D-side diffusion layers of auto-zero transistors AZ2 and AZ3 to which a fixed potential (e.g., VSSP) is applied and the source-side (S-side) diffusion layer of auto-zero transistor AZ4 connected to the organic light-emitting diode 211 and anode.

[0074] The arrangement of the auto-zero transistor AZ may be changed as in the second embodiment. The display device 1 according to the second embodiment can obtain the same effects as the first embodiment.

[0075] 10 is a layout diagram showing an example of the configuration of a pixel circuit 210 according to a third embodiment. Fig. 11 is a circuit diagram showing an example of the configuration of a pixel circuit 210 according to the third embodiment. In the third embodiment, the arrangement of the auto-zero transistor AZ is different from that in the second embodiment.

[0076] The pair of transistors of the same type is a pair of auto-zero transistors AZ that are included in the pixel circuits 210 adjacent to each other in the vertical direction of the paper surface of FIG.

[0077] Each transistor in the pair is provided so as to protrude toward the opposing pixel circuit 210. The pair is arranged side by side in a direction substantially perpendicular to the direction in which the adjacent pixel circuits 210 adjoin each other.

[0078] The direction of current flow in the channel of the drive transistor Drv and the direction of current flow in the channel of the auto-zero transistor AZ are substantially the same.

[0079] 9 according to the second embodiment, the drive transistor Drv and the auto-zero transistor AZ of the same pixel circuit 210 are arranged so that the directions of their channel currents flow are rotated by 90 degrees from each other. In contrast, in FIG. 10 according to the third embodiment, the drive transistor Drv and the auto-zero transistor AZ of the same pixel circuit 210 are arranged so that the directions of their channel currents flow are the same, but the channel currents of the auto-zero transistors AZ in vertically adjacent pixel circuits 210 are arranged in a mirror-inverted manner so that they flow in opposite directions. Furthermore, to fit the width of the pair of two auto-zero transistors AZ within the width of one pixel circuit 210, the width of the auto-zero transistor AZ is narrowed and protrudes into the area where the other pixel circuit 210 is formed, thereby maintaining the width of the pixel circuit 210. In this case, the potential of the S-side diffusion layers of the auto-zero transistor AZ1 and the auto-zero transistor AZ4 is prevented from becoming an unintended potential through the parasitic capacitances Cp1 and Cp2 formed between the D-side diffusion layer of the auto-zero transistor AZ4, to which a fixed potential (e.g., VSSP) is applied, and the S-side diffusion layers of the auto-zero transistor AZ1 and the auto-zero transistor AZ4, which are connected to the organic light-emitting diode 211 and the anode.

[0080] In some cases, the auto-zero transistor AZ does not require high driving capability in terms of circuit operation. In this case, the channel width of the auto-zero transistor AZ can be reduced, and the auto-zero transistors AZ can be arranged side by side in the horizontal direction of the paper in FIG. 10. This allows the two pixel circuits 210 arranged side by side in the vertical direction of the paper in FIG. 10 to be arranged closer together in the vertical direction of the paper. This allows for higher resolution.

[0081] The pixel circuit 210 may be the pixel circuit of one of multiple subpixels included in one pixel. One pixel includes, for example, three subpixels of red, blue, and green. Three subpixels (pixel circuits 210) aligned in the horizontal direction of the paper in FIG. 10 constitute one pixel. Two pairs of auto-zero transistors AZ of two pixel circuits 210 aligned in the vertical direction of the paper are arranged so as to fit within the width of one subpixel in the horizontal direction of the paper (a direction approximately perpendicular to the direction in which adjacent pixel circuits 210 adjoin each other).

[0082] The arrangement of the auto-zero transistor AZ may be changed as in the third embodiment. The display device 1 according to the third embodiment can obtain the same effects as the second embodiment.

[0083] 12 is a layout diagram showing an example of the configuration of a pixel circuit 210 according to a fourth embodiment. In the fourth embodiment, the channel width of the drive transistor Drv is different from that of the third embodiment. Note that FIG. 12 also shows a portion of the upper layer wiring W connected to the ground line 333.

[0084] The channel width on the source side of the drive transistor Drv is different from the channel width on the channel side of the drive transistor Drv. In the example shown in FIG. 12, the channel width on the source side of the drive transistor Drv is larger than the channel width on the channel side of the drive transistor Drv.

[0085] In FIG. 12 , the channel width of the drive transistor Drv is narrower on the drain side than on the source side. This reduces the parasitic capacitance of the drive transistor Drv, resulting in a pixel circuit 210 that is robust to front-plane characteristics. Also, in FIG. 10 according to the third embodiment, the distance between the gate electrode of the drive transistor Drv1 and the drain diffusion layer of the auto-zero transistor AZ2 is determined by the sum (D1 + D2) of the distance D1 between the gate polysilicon electrode (G) and the edge of the active region and the distance D2 between the active regions. In contrast, in the layout of FIG. 12 according to the fourth embodiment, the distance is determined only by the distance D3 between the gate polysilicon electrode (G) and the active region, thereby further reducing misalignment and enabling higher transistor integration. This means that the pixel circuit 210 can be made more compact. Furthermore, the drain-side diffusion layer of the drive transistor Drv is recessed below the gate polysilicon electrode, which helps to prevent coupling between the drain-side diffusion layers of adjacent pixel circuits 210.

[0086] The channel width of the drive transistor Drv may be changed as in the fourth embodiment. The display device 1 according to the fourth embodiment can achieve the same effects as the third embodiment.

[0087] 13 is a layout diagram showing an example of the configuration of a pixel circuit 210 according to a first modification of the fourth embodiment. In the first modification of the fourth embodiment, the arrangement of the auto-zero transistor AZ is different from that of the fourth embodiment. Note that FIG. 13 also shows a portion of the upper layer wiring W connected to the ground line 333.

[0088] 13, the channel width of the drive transistor Drv is changed as described in the fourth embodiment. However, as shown in FIG. 10 according to the third embodiment, the channel width of the drive transistor Drv does not have to be changed.

[0089] In adjacent pairs, the channels of the same type of transistors are arranged side by side so that the current flows in the same direction. In the example shown in Figure 13, the channels of the auto-zero transistors AZ in adjacent pairs are arranged side by side so that the current flows in the same direction.

[0090] As shown in FIG. 13 , the wiring layout of the wiring layer may be emphasized, and the diffusion layer on the drain side of the auto-zero transistor AZ to which a fixed potential is applied may be adjacent. The wiring layer is, for example, a layer above the layer shown in FIG. 13 . The wiring in the wiring layer is arranged in the horizontal direction of FIG. 13 . The wiring in the wiring layer is, for example, the upper layer wiring W connected to the ground line 333. The wiring in the wiring layer is also connected to a contact (via) connected to the drain of the auto-zero transistor AZ. Therefore, the wiring in the wiring layer is arranged to extend in a zigzag pattern so as to pass through the drain of the auto-zero transistor AZ when viewed perpendicular to the plane of FIG. 13 .

[0091] 12 according to the fourth embodiment, the wiring in the wiring layer (e.g., the upper layer wiring W) is arranged so as to bend in a zigzag pattern for every auto-zero transistor AZ. In contrast, in FIG. 13 according to the first modification of the fourth embodiment, the wiring in the wiring layer is arranged so as to bend in a zigzag pattern for every two auto-zero transistors AZ. This reduces the number of bends in the wiring in the wiring layer, further simplifying the wiring layout.

[0092] As in the first modification of the fourth embodiment, the arrangement of the auto-zero transistor AZ may be changed. The display device 1 according to the first modification of the fourth embodiment can obtain the same effects as the fourth embodiment.

[0093] 14 is a layout diagram showing an example of the configuration of a pixel circuit 210 according to a fifth embodiment. The fifth embodiment differs from the fourth embodiment in that the gate electrodes of the auto-zero transistors AZ are connected together.

[0094] 14, the channel width of the drive transistor Drv is changed as described in the fourth embodiment. However, as shown in FIG. 10 according to the third embodiment, the channel width of the drive transistor Drv does not have to be changed.

[0095] In FIG. 14 , the gate electrodes of the auto-zero transistors AZ are connected to multiple pixel circuits. A connecting gate CG is provided by connecting multiple gate electrodes across multiple pixel circuits 210. The gate electrodes may be connected partially or entirely from one end of the panel to the other. This reduces the gate resistance and improves the flexibility of the wiring layout of the wiring layer by reducing the number of contacts C connected to the gate electrodes. The contacts C connected to the gate electrodes may be connected only to the end of the connecting gate CG or the end of the display panel 10.

[0096] The auto-zero transistors AZ1 to AZ6 are driven simultaneously. The auto-zero transistors AZ do not need to pass a high current, and their resistance does not need to be that low. This allows the number of contacts C to be reduced, and the wiring connected to the gates of the auto-zero transistors AZ1 to AZ6 to be simplified.

[0097] The gate electrodes of the auto-zero transistors AZ may be connected as in the fifth embodiment, and the display device 1 according to the fifth embodiment can achieve the same effects as the fourth embodiment.

[0098] 15 is a layout diagram showing an example of the configuration of a pixel circuit 210 according to a sixth embodiment. The sixth embodiment differs from the third embodiment in that, instead of the auto-zero transistor AZ, a light-emission control transistor DS is arranged so that the channel currents of the pair flow in opposite directions.

[0099] The pair of transistors of the same type is a pair of emission control transistors DS included in pixel circuits 210 adjacent in the vertical direction of the page of Fig. 15. As shown in Fig. 3, the S-side diffusion layer of the emission control transistor DS is connected to a power supply line 332 that supplies VCCP, which is a fixed potential. The S-side diffusion layer of the emission control transistor DS is adjacent to the S-side diffusion layer of the drive transistor Drv via an inter-element isolation region.

[0100] The layout of this embodiment may be adopted for the light-emitting control transistor DS of the pixel circuit 210 in Fig. 3, as shown in Fig. 15. The parasitic capacitances Cp1 and Cp2 prevent the diffusion layer on the S side of the drive transistor Drv from reaching an unintended potential.

[0101] As in the sixth embodiment, the light-emission control transistors DS may be arranged so that the channel currents of the pair flow in opposite directions. The display device 1 according to the sixth embodiment can achieve the same effects as the third embodiment.

[0102] 5. Example of Pixel Configuration The pixel circuit 210 is not limited to the circuit example shown in Fig. 3. For example, if a transistor whose drain is connected to the organic light-emitting diode 211 and whose source is connected to a fixed potential (for example, VSSP) is included, a similar effect can be obtained by adopting a similar layout for the transistor.

[0103] The following describes other configuration examples of the pixel circuit 210 (sub-pixel). Note that, hereinafter, the pixel circuit 210 (sub-pixel) is referred to as a pixel PIX.

[0104] 16 shows another example of the configuration of pixel PIX. This pixel PIX has a capacitor C21, transistors MN22 to MN25, and a light-emitting element EL. Transistors MN22 to MN25 are N-type MOSFETs. The gate of transistor MN22 is connected to a control line WSL, the other of its source and drain is connected to a signal line SGL, and one of its source and drain is connected to the gate of transistor MN24 and one end of capacitor C21. One end of capacitor C21 is connected to one of the source and drain of transistor MN22 and the gate of transistor MN24, and the other end is connected to one of the source and drain of transistor MN24, the other of the source and drain of transistor MN25, and the anode of light-emitting element EL. The gate of transistor MN23 is connected to a control line DSL, the other of its source and drain is connected to a power supply line VCCP, and one of its source and drain is connected to the other of the source and drain of transistor MN24. The gate of transistor MN24 is connected to one of the source and drain of transistor MN22 and one end of capacitor C21, the other of the source and drain is connected to one of the source and drain of transistor MN23, one of the source and drain is connected to the other end of capacitor C21, the other of the source and drain of transistor MN25, and the anode of the light-emitting element EL. The gate of transistor MN25 is connected to control line AZSL, the other of the source and drain is connected to one of the source and drain of transistor MN24, the other end of capacitor C21, and the anode of the light-emitting element EL, and one of the source and drain is connected to power supply line VSS.

[0105] With this configuration, in pixel PIX, when transistor MN22 is turned on, the voltage across capacitor C21 is set based on the pixel signal supplied from signal line SGL. Transistor MN23 is turned on and off based on the signal on control line DSL. While transistor MN23 is on, transistor MN24 passes a current corresponding to the voltage across capacitor C21 through light-emitting element EL. The light-emitting element EL emits light based on the current supplied from transistor MN24. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. Transistor MN25 is turned on and off based on the signal on control line AZSL. While transistor MN25 is on, the anode voltage of light-emitting element EL is initialized by being set to the voltage of power supply line VSS.

[0106] The transistors MN22 to MN25 may be transistors using low temperature polysilicon (LTPS), and at least one of the transistors MN22 and MN25 may be a transistor using an oxide semiconductor.

[0107] In the circuit diagram shown in FIG. 17, for example, this embodiment is applied to a transistor MN25 that operates in the same manner as the auto-zero transistor AZ according to the first to fifth embodiments, or a transistor MN23 that operates in the same manner as the light-emitting control transistor DS according to the sixth embodiment.

[0108] 17 shows another example of the configuration of pixel PIX. This pixel PIX has a capacitor C31, transistors MP32 to MP36, and a light-emitting element EL. Transistors MP32 to MP36 are P-type MOSFETs. The gate of transistor MP32 is connected to a control line WSL, one of its source and drain is connected to a signal line SGL, and the other of its source and drain is connected to the gate of transistor MP33, the other of the source and drain of transistor MP34, and the other end of capacitor C31. One end of capacitor C31 is connected to a power supply line VCCP, and the other end is connected to the other of the source and drain of transistor MP32, the gate of transistor MP33, and the other of the source and drain of transistor MP34. The gate of transistor MP34 is connected to control line AZSL1, one of its source and drain is connected to the other of the source and drain of transistor MP33 and one of the source and drain of transistor MP35, the other of its source and drain is connected to the other of the source and drain of transistor MP32, the gate of transistor MP33, and the other end of capacitor C31. The gate of transistor MP35 is connected to control line DSL, one of its source and drain is connected to the other of the source and drain of transistor MP33 and one of the source and drain of transistor MP34, and the other of its source and drain is connected to one of the source and drain of transistor MP36 and the anode of the light-emitting element EL. The gate of transistor MP36 is connected to control line AZSL2, one of its source and drain is connected to the other of the source and drain of transistor MP35 and the anode of the light-emitting element EL, and the other of its source and drain is connected to the power supply line VSS.

[0109] With this configuration, in pixel PIX, when transistor MP32 is turned on, the voltage across capacitor C31 is set based on the pixel signal supplied from signal line SGL. Transistor MP35 is turned on and off based on the signal on control line DSL. While transistor MP35 is on, transistor MP33 passes a current corresponding to the voltage across capacitor C31 through light-emitting element EL. The light-emitting element EL emits light based on the current supplied from transistor MP33. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. Transistor MP34 is turned on and off based on the signal on control line AZSL1. While transistor MP34 is on, the drain and gate of transistor MP33 are connected to each other. Transistor MP36 is turned on and off based on the signal on control line AZSL2. While transistor MP36 is on, the anode voltage of light-emitting element EL is initialized by being set to the voltage of power supply line VSS.

[0110] The transistors MP32 to MP36 may be transistors using low temperature polysilicon (LTPS), and at least one of the transistors MP32, MP34, and MP36 may be a transistor using an oxide semiconductor.

[0111] In the circuit diagram shown in FIG. 17, for example, this embodiment is applied to a transistor MN36 that operates in the same manner as the auto-zero transistor AZ according to the first to fifth embodiments, or a transistor MN33 that operates in the same manner as the light-emitting control transistor DS according to the sixth embodiment.

[0112] 18 shows another example of the configuration of pixel PIX. One end of capacitor C48 is connected to signal line SGL1, and the other end is connected to power supply line VSS. One end of capacitor C49 is connected to signal line SGL1, and the other end is connected to signal line SGL2. Transistor MP49 is a P-type MOSFET, with its gate connected to control line WSL2, one of its source and drain connected to signal line SGL1, and the other connected to signal line SGL2.

[0113] The pixel PIX includes a capacitor C41, transistors MP42 to MP46, and a light-emitting element EL. The transistors MP42 to MP46 are P-type MOSFETs. The gate of transistor MP42 is connected to a control line WSL1, one of its source and drain is connected to a signal line SGL2, and the other of its source and drain is connected to the gate of transistor MP43 and the other end of capacitor C41. One end of capacitor C41 is connected to a power supply line VCCP, and the other end is connected to the other of the source and drain of transistor MP42 and the gate of transistor MP43. The gate of transistor MP43 is connected to the other of the source and drain of transistor MP42 and the other end of capacitor C41, one of its source and drain is connected to the power supply line VCCP, and the other of its source and drain is connected to one of the sources and drains of transistors MP44 and MP45. The gate of transistor MP44 is connected to control line AZSL1, one of its source and drain is connected to the other of the source and drain of transistor MP43 and one of the source and drain of transistor MP45, and the other of its source and drain is connected to signal line SGL2. The gate of transistor MP45 is connected to control line DSL, one of its source and drain is connected to the other of the source and drain of transistor MP43 and one of the source and drain of transistor MP44, and the other of its source and drain is connected to one of the source and drain of transistor MP46 and the anode of the light-emitting element EL. The gate of transistor MP46 is connected to control line AZSL2, one of its source and drain is connected to the other of the source and drain of transistor MP45 and the anode of the light-emitting element EL, and the other of its source and drain is connected to power supply line VSS.

[0114] With this configuration, in pixel PIX, when transistor MP42 is turned on, the voltage across capacitor C41 is set based on the pixel signal supplied to signal line SGL1. Transistor MP45 is turned on and off based on the signal on control line DSL. While transistor MP45 is on, transistor MP43 passes a current corresponding to the voltage across capacitor C41 through light-emitting element EL. The light-emitting element EL emits light based on the current supplied from transistor MP43. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. Transistor MP44 is turned on and off based on the signal on control line AZSL1. While transistor MP44 is on, the drain of transistor MP43 and signal line SGL2 are connected to each other. Transistor MP46 is turned on and off based on the signal on control line AZSL2. While transistor MP46 is on, the anode voltage of light-emitting element EL is initialized by being set to the voltage of power supply line VSS.

[0115] The transistors MP42 to MP46 and MP49 may be transistors using low temperature polysilicon (LTPS). At least one of the transistors MP42, MP46 and MP49 may be a transistor using an oxide semiconductor.

[0116] In the circuit diagram shown in FIG. 18, for example, this embodiment is applied to a transistor MN46 that operates in the same manner as the auto-zero transistor AZ according to the first to fifth embodiments, or a transistor MN43 that operates in the same manner as the light-emitting control transistor DS according to the sixth embodiment.

[0117] 19 shows another example of the configuration of the pixel PIX. A plurality of pixels PIX are arranged in a matrix in a display area 100, and the display area 100 is provided between a first control unit 40 and a second control unit 70.

[0118] The first control unit 40 includes transmission gates TG45 and TG46, transistors MP56 and MP57, and a capacitor C61. Transistors MP56 and MP57 are P-type MOSFETs. One end of the transmission gate TG45 receives a pixel signal, and the other end is connected to the signal line 14a. One end of the transmission gate TG46 is connected to the signal line 14b, and the other end is connected to the power supply line Vorst. One end of the capacitor C61 is connected to the signal line 14a, and the other end is connected to the power supply line VSS1. The gate of the transistor MP56 is connected to the control line INIL, one of the source and drain is connected to the power supply line Vini, and the other is connected to the signal line 14b. The gate of the transistor MP57 is connected to the control line ELL, one of the source and drain is connected to the power supply line Vel, and the other is connected to the signal line 14b.

[0119] The second control unit 70 has a transmission gate TG72, a transistor MP73, and a capacitor C82. The transistor MP73 is a P-type MOSFET. One end of the transmission gate TG72 is connected to the signal line 14a, and the other end is connected to the other of the source and drain of the transistor MP73 and one end of the capacitor C82. The gate of the transistor MP73 is connected to the control line REFL, one of the source and drain is connected to the power supply line Vref, and the other of the source and drain is connected to the other end of the transmission gate TG72 and one end of the capacitor C82. One end of the capacitor C82 is connected to the other end of the transmission gate TG72 and the other of the source and drain of the transistor MP73, and the other end is connected to the signal line 14b.

[0120] The pixel PIX includes a capacitor C132, transistors MP121 to MP125, and a light-emitting element EL. The transistors MP121 to MP125 are P-type MOSFETs. The gate of the transistor MP122 is connected to the control line WSL, one of the source and drain is connected to the signal line 14b, and the other of the source and drain is connected to the gate of the transistor MP121 and the other end of the capacitor C132. One end of the capacitor C132 is connected to the power supply line Vel, and the other end is connected to the other of the source and drain of the transistor MP122 and the gate of the transistor MP121. The gate of the transistor MP121 is connected to the other of the source and drain of the transistor MP122 and the other end of the capacitor C132, one of the source and drain is connected to the power supply line Vel, and the other of the source and drain is connected to one of the sources and drains of the transistors MP123 and MP124. The gate of transistor MP123 is connected to the control line AZSL, one of its source and drain is connected to the other of the source and drain of transistor MP121 and one of the source and drain of transistor MP124, and the other of its source and drain is connected to signal line 14b. The gate of transistor MP124 is connected to the control line DSL, one of its source and drain is connected to the other of the source and drain of transistor MP121 and one of the source and drain of transistor MP123, and the other of its source and drain is connected to one of the source and drain of transistor MP125 and the anode of the light-emitting element 130. The gate of transistor MP125 is connected to the control line AZSL, the other of its source and drain is connected to the power supply line Vorst, and one of its source and drain is connected to the other of the source and drain of transistor MP124 and the anode of the light-emitting element 130.

[0121] With this configuration, in pixel PIX, when transistor MP122 is turned on, the voltage across capacitor C132 is set based on the pixel signal supplied to one end of transmission gate TG45. Transistor MP124 is turned on and off based on the signal on control line DSL. While transistor MP124 is on, transistor MP121 passes a current corresponding to the voltage across capacitor C132 through light-emitting element EL. Light-emitting element EL emits light based on the current supplied from transistor MP121. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. Transistors MP123 and MP125 are turned on and off based on the signal on control line AZSL. While transistor MP123 is on, the other of the source and drain of transistor MP121 and one of the source and drain of transistor MP124 are connected to signal line 14b. While transistor MP125 is on, the voltage of the anode of light-emitting element EL is initialized by being set to the voltage of power supply line Vorst. Furthermore, transistor MP56 is turned on and off based on the signal on control line INIL, transistor MP57 is turned on and off based on the signal on control line ELL, and transistor MP73 is turned on and off based on the signal on control line REFL. When transistor MP56 is turned on, signal line 14b is set to the voltage of power supply line Vini, and when transistor MP57 is turned on, signal line 14b is set to the voltage of power supply line Vel. When transistor MP73 is turned on, one end of capacitor C82 is set to the voltage of power supply line Vref, thereby being initialized.

[0122] The transistors MP121 to MP125, MP56, and MP57 may be transistors using low temperature polysilicon (LTPS), and at least one of the transistors MP122 and MP125 may be a transistor using an oxide semiconductor.

[0123] In the circuit diagram shown in FIG. 19, for example, this embodiment is applied to a transistor MP125 that operates in the same manner as the auto-zero transistor AZ according to the first to fifth embodiments, or a transistor MP121 that operates in the same manner as the light-emitting control transistor DS according to the sixth embodiment.

[0124] 20 shows another example of the configuration of pixel PIX. This pixel PIX has a capacitor C51, transistors MP52 to MP60, and a light-emitting element EL. Transistors MP52 to MP60 are P-type MOSFETs. The gate of transistor MP52 is connected to a control line WSL, one of its source and drain is connected to a signal line SGL, and the other of its source and drain is connected to the other of the source and drain of transistor MP53 and one of the source and drain of transistor MP54. The gate of transistor MP53 is connected to a control line DSL, one of its source and drain is connected to a power supply line VCCP, and the other of its source and drain is connected to the other of the source and drain of transistor MP52 and one of the source and drain of transistor MP54. The gate of transistor MP54 is connected to one of the source and drain of transistor MP55, the other of the source and drain of transistor MP57, and the other end of capacitor C51, with one of its source and drain connected to the other of the sources and drains of transistors MP52 and MP53, and the other connected to one of the sources and drains of transistors MP58 and MP59. Capacitor C51 has one end connected to the power supply line VCCP, and the other end connected to the gate of transistor MP54, one of the source and drain of transistor MP55, and the other of the source and drain of transistor MP57. Capacitor C51 may include two capacitors connected in parallel. The gate of transistor MP55 is connected to control line AZSL1, with one of its source and drain connected to the gate of transistor MP54, the other of the source and drain of transistor MP57, and the other end of capacitor C51, and the other connected to one of the source and drain of transistor MP56. The gate of the transistor MP56 is connected to the control line AZSL1, one of the source and drain is connected to the other of the source and drain of the transistor MP55, and the other of the source and drain is connected to the power supply line VSS.The gate of transistor MP57 is connected to the control line WSL, the other of its source and drain is connected to the gate of transistor MP54, one of the source and drain of transistor MP55, and the other end of capacitor C51, and one of its source and drain is connected to the other of the source and drain of transistor MP58. The gate of transistor MP58 is connected to the control line WSL, the other of its source and drain is connected to one of the source and drain of transistor MP57, and one of its source and drain is connected to the other of the source and drain of transistor MP54 and one of the source and drain of transistor MP59. The gate of transistor MP59 is connected to the control line DSL, one of its source and drain is connected to the other of the source and drain of transistor MP54 and one of the source and drain of transistor MP58, and the other of its source and drain is connected to one of the source and drain of transistor MP60 and the anode of the light-emitting element EL. The gate of the transistor MP60 is connected to the control line AZSL2, one of the source and drain is connected to the other of the source and drain of the transistor MP59 and the anode of the light-emitting element EL, and the other of the source and drain is connected to the power supply line VSS.

[0125] With this configuration, in pixel PIX, transistors MP52, MP54, MP58, and MP57 are turned on, and the voltage across capacitor C51 is set based on the pixel signal supplied from signal line SGL. Transistors MP53 and MP59 are turned on and off based on the signal on control line DSL. While transistors MP53 and MP59 are on, transistor MP54 passes a current corresponding to the voltage across capacitor C51 through light-emitting element EL. The light-emitting element EL emits light based on the current supplied from transistor MP54. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. Transistors MP55 and MP56 are turned on and off based on the signal on control line AZSL1. While transistors MP55 and MP56 are on, the gate voltage of transistor MP54 is initialized by being set to the voltage of power supply line VSS. Transistor MP60 is turned on and off based on the signal on control line AZSL2. During the period in which the transistor MP60 is in the on state, the voltage of the anode of the light-emitting element EL is initialized by being set to the voltage of the power supply line VSS.

[0126] The transistors MP52 to MP60 may be transistors using low temperature polysilicon (LTPS), and at least one of the transistors MP55 to MP58 and MP60 may be a transistor using an oxide semiconductor.

[0127] In the circuit diagram shown in FIG. 20, for example, this embodiment is applied to a transistor MP60 that operates in the same manner as the auto-zero transistor AZ according to the first to fifth embodiments, or a transistor MP53 that operates in the same manner as the light-emitting control transistor DS according to the sixth embodiment.

[0128] 21 shows another example of the configuration of the pixel PIX. The signal on the control line WSNL and the signal on the control line WSPL are mutually inverted signals.

[0129] The pixel PIX includes capacitors C61 and C62, transistors MN63, MP64, and MN65 to MN67, and a light-emitting element EL. The transistors MN63, MN65 to MN67 are N-type MOSFETs, and the transistor MP64 is a P-type MOSFET. The gate of the transistor MN63 is connected to a control line WSNL, and the other of its source and drain is connected to a signal line SGL and one of the source and drain of the transistor MP64, and one of its source and drain is connected to the other of the source and drain of the transistor MP64, one end of the capacitors C61 and C62, and the gate of the transistor MN65. The gate of the transistor MP64 is connected to a control line WSPL, and one of its source and drain is connected to the signal line SGL and the other of the source and drain of the transistor MN63, and the other of the source and drain is connected to one of the source and drain of the transistor MN63, one end of the capacitors C61 and C62, and the gate of the transistor MN65. The capacitor C61 is configured using, for example, a metal oxide metal (MOM) capacitor, with one end connected to one of the source and drain of transistor MN63, the other of the source and drain of transistor MP64, one end of capacitor C62, and the gate of transistor MN65, and the other end connected to the power supply line VSS2. The capacitor C61 may be configured using, for example, a metal oxide metal (MOS) capacitor or a metal insulator metal (MIM) capacitor. The capacitor C62 is configured using, for example, a MOS capacitor, with one end connected to one of the source and drain of transistor MN63, the other of the source and drain of transistor MP64, one end of capacitor C61, and the gate of transistor MN65, and the other end connected to the power supply line VSS2. The capacitor C62 may be configured using, for example, a MOM capacitor or a MIM capacitor. The other end of capacitor C62 may be connected to the power supply line VSS3 (not shown).The gate of transistor MN65 is connected to one of the source and drain of transistor MN63, the other of the source and drain of transistor MP64, and one end of capacitors C61 and C62, the other of its source and drain is connected to the power supply line VCCP, and one of its source and drain is connected to the other of the sources and drains of transistors MN66 and MN67. The gate of transistor MN66 is connected to control line AZL, the other of its source and drain is connected to one of the source and drain of transistor MN65 and the other of the source and drain of transistor MN67, and one of its source and drain is connected to power supply line VSS1. The gate of transistor MN67 is connected to control line DSL, the other of its source and drain is connected to one of the source and drain of transistor MN65 and the other of the source and drain of transistor MN66, and one of its source and drain is connected to the anode of the light-emitting element EL. Alternatively, the transistor MN67 and the control line DSL may be omitted, and one of the source and drain of the transistor MN65 may be connected to the other of the source and drain of the transistor MN66 and the anode of the light-emitting element EL.

[0130] With this configuration, in pixel PIX, when at least one of transistors MN63 and MP64 is turned on, the voltage across capacitors C61 and C62 is set based on the pixel signal supplied from signal line SGL. Transistor MN67 is turned on and off based on the signal on control line DSL. While transistor MN67 is on, transistor MN65 passes a current corresponding to the voltage across capacitors C61 and C62 through light-emitting element EL. Light-emitting element EL emits light based on the current supplied from transistor MP65. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. Transistor MN66 may be turned on and off based on the signal on control line AZL. Transistor MN66 may also function as a resistor element having a resistance value corresponding to the signal on control line AZL. In this case, transistors MN65 and MN66 form a so-called source follower circuit.

[0131] The transistors MN63, MP64, MN65 to MN67 may be transistors using low temperature polysilicon (LTPS), and at least one of the transistors MN63, MP64, and MN66 may be a transistor using an oxide semiconductor.

[0132] In the circuit diagram shown in FIG. 21, for example, this embodiment is applied to a transistor MN66 that operates in the same manner as the auto-zero transistor AZ according to the first to fifth embodiments.

[0133] 22 shows another example of the configuration of pixel PIX. This pixel PIX has a capacitor C71, transistors MN72 to MN77, and a light-emitting element EL. Transistors MN72 to MN77 are N-type MOSFETs. The gate of transistor MN72 is connected to a control line WSL, the other of its source and drain is connected to a signal line SGL, and one of its source and drain is connected to one of the source and drain of transistor MN74 and the other of the source and drain of transistor MN75. One end of capacitor C71 is connected to the gate of transistor MN74 and one of the source and drain of transistor MN76, and the other end is connected to the other of the source and drain of transistor MN77, one of the source and drain of transistor MN75, and the anode of the light-emitting element EL. The gate of transistor MN73 is connected to control line DLS1, the other of its source and drain is connected to power supply line VCCP, one of its source and drain is connected to the other of transistor MN74 and the other of transistor MN76. The gate of transistor MN74 is connected to one of the source and drain of transistor MN76 and one end of capacitor C71, the other of its source and drain is connected to one of the source and drain of transistor MN73 and the other of the source and drain of transistor MN76, one of its source and drain is connected to one of the source and drain of transistor MN72 and the other of the source and drain of transistor MN75. The gate of transistor MN75 is connected to control line DSL2, the other of its source and drain is connected to one of the source and drain of transistor MN72 and one of the source and drain of transistor MN74, and one of its source and drain is connected to the other end of capacitor C71, the other of the source and drain of transistor MN77, and the anode of light-emitting element EL.The gate of transistor MN76 is connected to control line AZSL, the other of its source and drain is connected to one of the source and drain of transistor MN73 and the other of the source and drain of transistor MN74, one of its source and drain is connected to the gate of transistor MN74 and one end of capacitor C71. The gate of transistor MN77 is connected to control line AZSL, the other of its source and drain is connected to the other end of capacitor C71, one of the source and drain of transistor MN75, and the anode of light-emitting element EL, and one of its source and drain is connected to power supply line VSS.

[0134] With this configuration, in pixel PIX, transistors MN72, MN74, and MN76 are turned on, and the voltage across capacitor C71 is set based on the pixel signal supplied from signal line SGL. Transistor MN73 is turned on and off based on the signal on control line DSL1, and transistor MN75 is turned on and off based on the signal on control line DSL2. While transistors MN73 and MN75 are on, transistor MN74 passes a current corresponding to the voltage across capacitor C71 through light-emitting element EL. Light-emitting element EL emits light based on the current supplied from transistor MN74. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. Transistor MN77 is turned on and off based on the signal on control line AZSL. While transistor MN77 is on, the anode voltage of light-emitting element EL is initialized by being set to the voltage of power supply line VSS.

[0135] The transistors MN72 to MN77 may be transistors using low temperature polysilicon (LTPS), and the transistor MN76 may be a transistor using an oxide semiconductor.

[0136] In the circuit diagram shown in FIG. 22, for example, this embodiment is applied to a transistor MN77 that operates in the same manner as the auto-zero transistor AZ according to the first to fifth embodiments, or a transistor MN73 that operates in the same manner as the light-emitting control transistor DS according to the sixth embodiment.

[0137] 6. Application Examples Next, application examples of the display systems described in the above embodiments and modifications will be described.

[0138] 23 shows an example of the appearance of a head-mounted display 110. The head-mounted display 110 has, for example, ear hooks 112 for wearing on the user's head on both sides of a glasses-shaped display unit 111. The techniques according to the above-described embodiments and the like can be applied to such a head-mounted display 110.

[0139] (Application Example 2) FIG. 24 shows an example of the appearance of another head-mounted display 120. The head-mounted display 120 is a see-through head-mounted display having a main body 121, an arm 122, and a lens barrel 123. This head-mounted display 120 is attached to eyeglasses 128. The main body 121 has a control board and a display unit for controlling the operation of the head-mounted display 120. The display unit emits image light of a display image. The arm 122 connects the main body 121 to the lens barrel 123 and supports the lens barrel 123. The lens barrel 123 projects the image light supplied from the main body 121 via the arm 122 toward the user's eyes via lenses 129 of the eyeglasses 128. The techniques according to the above-described embodiments and the like can be applied to such a head-mounted display 120.

[0140] The head-mounted display 120 is a so-called light guide plate type head-mounted display, but is not limited to this and may be, for example, a so-called birdbath type head-mounted display. The birdbath type head-mounted display includes, for example, a beam splitter and a partially transparent mirror. The beam splitter outputs light encoded with image information toward the mirror, and the mirror reflects the light toward the user's eyes. Both the beam splitter and the partially transparent mirror are partially transparent. This allows light from the surrounding environment to reach the user's eyes.

[0141] (Application Example 3) Figures 25A and 25B show an example of the appearance of a digital still camera 130, with Figure 25A showing a front view and Figure 25B showing a rear view. This digital still camera 130 is a single-lens reflex camera with interchangeable lenses and includes a camera body 131, a photographing lens unit 132, a grip 133, a monitor 134, and an electronic viewfinder 135. The photographing lens unit 132 is an interchangeable lens unit and is provided near the center of the front of the camera body 311. The grip 133 is provided on the left side of the front of the camera body 311, and is held by the photographer. The monitor 134 is provided to the left of the center of the back of the camera body 131. The electronic viewfinder 135 is provided above the monitor 14 on the back of the camera body 131. By looking through this electronic viewfinder 135, the photographer can visually confirm the optical image of the subject guided by the photographing lens unit 132 and determine the composition. The techniques according to the above-described embodiments and the like can be applied to the electronic viewfinder 135.

[0142] 26 shows an example of the appearance of a television device 140. The television device 140 has an image display screen unit 141 including a front panel 142 and a filter glass 143. The techniques according to the above-described embodiments and the like can be applied to this image display screen unit 141.

[0143] 27 shows an example of the appearance of a smartphone 150. The smartphone 150 has a display unit 151 that displays various information and an operation unit 152 that includes buttons and the like that accept operation inputs from a user. The techniques according to the above-described embodiments and the like can be applied to this display unit 151.

[0144] (Application Example 6) Figures 28A and 28B show an example configuration of a vehicle to which the technology of the present disclosure is applied, where Figure 28A shows an example of the interior of the vehicle as seen from the rear of vehicle 200, and Figure 28B shows an example of the interior of the vehicle as seen from the left rear of vehicle 200.

[0145] The vehicle in Figures 28A and 28B has a center display 201, a console display 202, a head-up display 203, a digital rearview mirror 204, a steering wheel display 205, and a rear entertainment display 106.

[0146] The center display 201 is disposed on the dashboard 261 in a position facing the driver's seat 262 and the passenger's seat 263. While FIG. 28A illustrates an example of a horizontally elongated center display 201 extending from the driver's seat 262 side to the passenger's seat 263 side, the screen size and location of the center display 201 are not limited to this. The center display 201 can display information detected by various sensors. As a specific example, the center display 201 can display an image captured by an image sensor, a distance image to obstacles in front of or to the side of the vehicle measured by a ToF sensor, and the body temperature of an occupant detected by an infrared sensor. The center display 201 can be used to display, for example, at least one of safety-related information, operation-related information, a life log, health-related information, authentication / identification-related information, and entertainment-related information.

[0147] The safety-related information includes information based on sensor detection results, such as detection of drowsiness, distraction, child mischief, whether a seatbelt is fastened, and whether a passenger is abandoned. The operation-related information includes gesture information related to passenger operations detected by sensors. The gestures may include operations of various vehicle equipment, such as air conditioning, navigation, audiovisual (AV) equipment, and lighting. The life log includes life logs of all passengers. For example, the life log includes a record of each passenger's behavior. By acquiring and storing the life log, it is possible to determine the condition of the passengers at the time of an accident. The health-related information includes the passenger's body temperature detected using a temperature sensor and information on the passenger's health condition estimated based on the detected body temperature. Alternatively, the passenger's health condition information may be estimated based on the passenger's face captured by an image sensor. Furthermore, the passenger's health condition information may be estimated based on the passenger's responses obtained through an automated voice conversation with the passenger. The authentication / identification-related information includes information on a keyless entry function that uses a sensor to perform facial authentication, a function that automatically adjusts the seat height and position by facial recognition, etc. The entertainment-related information includes information on AV device operations by occupants detected by the sensor, and information on content to be displayed that is appropriate for the occupants detected and recognized by the sensor.

[0148] The console display 202 can be used to display, for example, life log information. The console display 202 is disposed near a shift lever 265 on a center console 264 between a driver's seat 262 and a passenger seat 263. The console display 202 can also display information detected by various sensors. The console display 202 may also display an image of the vehicle's surroundings captured by an image sensor, or an image showing the distance to an obstacle around the vehicle.

[0149] The head-up display 203 is virtually displayed behind a windshield 266 in front of the driver's seat 262. The head-up display 203 can be used to display, for example, at least one of safety-related information, operation-related information, a life log, health-related information, authentication / identification-related information, and entertainment-related information. Since the head-up display 203 is often virtually disposed in front of the driver's seat 262, it is suitable for displaying information directly related to vehicle operation, such as the vehicle speed, the remaining fuel level, and the remaining battery level.

[0150] The digital rearview mirror 204 can not only display the rear of the vehicle, but also display the state of passengers in the rear seats, and can therefore be used to display life log information of passengers in the rear seats, for example.

[0151] The steering wheel display 205 is disposed near the center of the vehicle's steering wheel 267. The steering wheel display 205 can be used to display at least one of, for example, safety-related information, operation-related information, a life log, health-related information, authentication / identification-related information, and entertainment-related information. In particular, because the steering wheel display 205 is located near the driver's hands, it is suitable for displaying life log information such as the driver's body temperature, and for displaying information related to the operation of AV equipment, air conditioning equipment, etc.

[0152] The rear entertainment display 206 is attached to the back side of the driver's seat 262 and the passenger seat 263 and is intended for viewing by rear seat passengers. The rear entertainment display 206 can be used to display at least one of, for example, safety-related information, operation-related information, a life log, health-related information, authentication / identification-related information, and entertainment-related information. In particular, since the rear entertainment display 206 is located in front of the rear seat passengers, information related to the rear seat passengers is displayed on the rear entertainment display 206. The rear entertainment display 206 may display, for example, information related to the operation of an AV device or an air conditioning system, or may display the results of measurements of the body temperature of the rear seat passengers by the temperature sensor 5.

[0153] The techniques according to the above-described embodiments can be applied to the center display 201, console display 202, head-up display 203, digital rearview mirror 204, steering wheel display 205, and rear entertainment display 206.

[0154] The present technology can be configured as follows: (1) A display device including a plurality of pixel circuits each including: a light-emitting element; a capacitor that holds a luminance signal as a voltage; a first transistor that supplies a current corresponding to the luminance signal to the light-emitting element; a second transistor that supplies and holds the luminance signal; a third transistor that initializes an applied voltage to the light-emitting element; and a fourth transistor that controls light emission of the light-emitting element by controlling a current flowing in the first transistor, wherein channels of a pair of transistors of the same type included in two adjacent pixel circuits are arranged side by side so that currents flow in opposite directions, and a drain of one transistor of the pair and a source of the other transistor face each other across an inter-element isolation region. (2) The display device according to (1), wherein each transistor of the pair is arranged to protrude toward the opposing pixel circuit, and the pair is arranged side by side in a direction approximately perpendicular to the direction in which the adjacent pixel circuits adjoin. (3) The display device according to (2), wherein the pixel circuit is a pixel circuit of one of a plurality of subpixels included in one pixel, and the pair is arranged to fit within the width of one of the subpixels in a direction approximately perpendicular to a direction in which adjacent pixel circuits are adjacent to each other. (4) The display device according to (2), wherein a direction in which a current flows in the channel of the first transistor and a direction in which a current flows in the channel of the third transistor are approximately the same. (5) The display device according to (2), wherein a channel width on the source side of the first transistor is different from a channel width on the channel side of the first transistor. (6) The display device according to (2), wherein channels of transistors of the same type between adjacent pairs are arranged side by side so that a current flows in the same direction. (7) The display device according to any one of (1) to (6), wherein the pair is a pair of the third transistors. (8) The display device according to any one of (1) to (6), wherein the pair is a pair of the fourth transistors.(9) The display device according to any one of (1) to (8), wherein gates of the same type of transistors in the pair are connecting gates connected across a plurality of the pixel circuits. (10) The display device according to (9), further comprising a contact electrically connected to the connecting gate at an end of the connecting gate. (11) The display device according to (10), further comprising a display panel having a plurality of pixels including the pixel circuits, wherein the contact is electrically connected to the connecting gate at an end of the display panel. (12) The display device according to any one of (1) to (11), wherein each transistor in the pair has one diffusion layer to which a fixed potential is supplied. (13) The display device according to (12), wherein the diffusion layer to which the fixed potential is supplied is adjacent to the diffusion layer of the first transistor via an inter-element isolation region. (14) The display device according to any one of (1) to (13), wherein the direction of current flow in the channel of the first transistor and the direction of current flow in the channel of the third transistor differ by approximately 90°. (15) The display device according to any one of (1) to (14), wherein two adjacent pixel circuits including the pair are arranged in a mirror-inverted manner.

[0155] The aspects of the present disclosure are not limited to the individual embodiments described above, but include various modifications that may be conceived by those skilled in the art, and the effects of the present disclosure are not limited to the above-described contents. In other words, various additions, modifications, and partial deletions are possible within the scope of the conceptual idea and spirit of the present disclosure, which is derived from the contents defined in the claims and their equivalents.

[0156] 1 display device, 10 display panel, 20 pixel section, 210 pixel circuit, 211 organic light emitting diode, Drv driving transistor, WS sampling transistor, DS light emission control transistor, AZ auto-zero transistor, C contact, CG connection gate

Claims

1. A display device comprising a plurality of pixel circuits each having: a light-emitting element; a capacitor that holds a luminance signal as a voltage; a first transistor that supplies a current corresponding to the luminance signal to the light-emitting element; a second transistor that supplies and holds the luminance signal; a third transistor that initializes an applied voltage to the light-emitting element; and a fourth transistor that controls the light emission of the light-emitting element by controlling the current flowing in the first transistor, wherein the channels of pairs of like transistors included in two adjacent pixel circuits are arranged side by side so that the current flows in opposite directions, and the drain of one transistor of the pair and the source of the other transistor face each other across an inter-element isolation region.

2. The display device according to claim 1, wherein each transistor of the pair is provided so as to protrude toward the opposing pixel circuit, and the pair is arranged side by side in a direction substantially perpendicular to the direction in which the adjacent pixel circuits adjoin.

3. The display device according to claim 2, wherein the pixel circuit is a pixel circuit of one of a plurality of sub-pixels included in one pixel, and the pair is arranged so as to fit within the width of one of the sub-pixels in a direction substantially perpendicular to the adjoining direction of the adjacent pixel circuits.

4. The display device according to claim 2, wherein the direction of current flow in the channel of said first transistor and the direction of current flow in the channel of said third transistor are substantially the same.

5. The display device according to claim 2, wherein the channel width on the source side of said first transistor is different from the channel width on the channel side of said first transistor.

6. The display device according to claim 2, wherein the channels of the same type of transistors between adjacent pairs are arranged side by side so that the current flows in the same direction.

7. The display device according to claim 1, wherein the pair is the third transistor pair.

8. The display device according to claim 1, wherein the pair is the fourth transistor pair.

9. The display device according to claim 1, wherein the gates of the transistors of the same type as the pair are connecting gates that are connected across a plurality of the pixel circuits.

10. The display device according to claim 9, further comprising a contact electrically connected to the connecting gate at an end of the connecting gate.

11. The display device according to claim 10, further comprising a display panel having a plurality of pixels each including the pixel circuit, wherein the contact is electrically connected to the connecting gate at an edge of the display panel.

12. The display device according to claim 1, wherein each of the pair of transistors has one diffusion layer to which a fixed potential is supplied.

13. The display device according to claim 12, wherein the diffusion layer to which the fixed potential is supplied is adjacent to the diffusion layer of the first transistor via an inter-element isolation region.

14. The display device according to claim 1, wherein the direction of current flow in the channel of the first transistor and the direction of current flow in the channel of the third transistor differ by approximately 90°.

15. The display device according to claim 1, wherein two adjacent pixel circuits comprising the pair are arranged in a mirror-inverted manner.

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