Imaging device

Abstract

The present invention increases the driving force of an amplification transistor provided in a pixel.　An imaging device according to the present invention includes: a first pixel provided with a first lateral overflow storage capacitor; a second pixel located adjacent to the first pixel and provided with a second lateral overflow storage capacitor; and an amplification transistor located in the first pixel and the second pixel so that a gate electrode crosses a boundary between the first pixel and the second pixel. The amplification transistor may be located in the first pixel and the second pixel so as to be mirror symmetrical with respect to a boundary between the first pixel and the second pixel.

Description

Imaging device

[0001] The present technology relates to an imaging device, and more particularly to an imaging device in which an amplifier transistor that amplifies a pixel signal is provided in each pixel.

[0002] In order to amplify and output a pixel signal, an amplifier transistor may be provided in the pixel. For example, an imaging device has been disclosed in which an amplifier transistor is provided in the pixel as an input part of a source follower circuit that reads out a signal corresponding to the charge held in the floating diffusion (see, for example, Patent Document 1).

[0003] International Publication No. 2022 / 264939

[0004] However, in the above-mentioned conventional technology, the driving force of the amplifying transistor is small because the size of the amplifying transistor is small, which may lead to an increase in noise.

[0005] This technology was developed in light of these circumstances, and aims to increase the driving power of the amplification transistor while suppressing an increase in pixel size.

[0006] The present technology has been made to solve the above-mentioned problems, and a first aspect thereof is an imaging device including: a first pixel provided with a first horizontal overflow storage capacitor; a second pixel arranged adjacent to the first pixel and provided with a second horizontal overflow storage capacitor; and amplification transistors arranged in the first pixel and the second pixel such that a gate electrode crosses a boundary between the first pixel and the second pixel. This brings about an effect of increasing the size of the amplification transistor while suppressing an increase in pixel size.

[0007] In the first aspect, the amplifier transistor may be arranged in the first pixel and the second pixel so as to be mirror-symmetric with respect to the boundary between the first pixel and the second pixel, thereby suppressing a decrease in pixel layout efficiency and increasing the size of the amplifier transistor shared by the first pixel and the second pixel.

[0008] In the first aspect, a pixel isolation region may be provided at a boundary between the first pixel and the second pixel, and the gate electrode of the amplification transistor may be disposed in the first pixel and the second pixel so as to straddle the pixel isolation region, thereby providing an effect of increasing the size of the amplification transistor shared by the first pixel and the second pixel without using wiring for connecting the amplification transistors disposed in the first pixel and the second pixel.

[0009] In the first aspect, the amplification transistor may include a first amplification transistor disposed in the first pixel and the second pixel so as to cross the boundary between the first pixel and the second pixel, and a second amplification transistor disposed in the first pixel or the second pixel and connected to the first amplification transistor via a wiring, thereby achieving an effect of increasing the size of the amplification transistor while suppressing an increase in pixel size.

[0010] In the first aspect, the first pixel may include a first overflow control transistor that controls an overflow of the first horizontal overflow storage capacitor, and the second pixel may include a second overflow control transistor that controls an overflow of the second horizontal overflow storage capacitor, thereby improving the controllability of the overflow of the first horizontal overflow storage capacitor and the second horizontal overflow storage capacitor.

[0011] In the first aspect, the first overflow control transistor and the second overflow control transistor may be arranged in the first pixel and the second pixel, respectively, to be mirror-symmetric with respect to the boundary between the first pixel and the second pixel, thereby improving the controllability of the overflow of the first lateral overflow storage capacitor and the second lateral overflow storage capacitor while suppressing a decrease in pixel layout efficiency.

[0012] In addition, in the first aspect, the first pixel may include a first selection transistor that selects readout from the first pixel, the second pixel may include a second selection transistor that selects readout from the second pixel, and the first selection transistor and the second selection transistor may be arranged in the first pixel and the second pixel, respectively, to be mirror-symmetric with each other with respect to the boundary between the first pixel and the second pixel. This brings about an effect that the readout timing of the first pixel and the second pixel is selected while suppressing a decrease in pixel layout efficiency.

[0013] In addition, in the first aspect, the first pixel may include a selection transistor that selects readout from the first pixel or the second pixel, the second pixel may include an amplification transistor shared by the first pixel and the second pixel, and the selection transistor and the amplification transistor may be arranged in the first pixel and the second pixel, respectively, so as to be mirror-symmetric with each other with respect to the boundary between the first pixel and the second pixel. This brings about the effects of reducing the layout area of ​​the pixel, increasing the driving force of the amplification transistor, and realizing selection of the first pixel and the second pixel.

[0014] In a first aspect, the first pixel may include a first photodiode, a first floating diffusion connected to a gate of the amplifying transistor, and a first transfer transistor configured to transfer charge accumulated in the first photodiode to the first floating diffusion, the second pixel may include a second photodiode, a second floating diffusion connected to a gate of the amplifying transistor, and a second transfer transistor configured to transfer charge accumulated in the second photodiode to the second floating diffusion, the first transfer transistor and the second transfer transistor may be spaced apart from the pixel isolation region, and the first floating diffusion and the second floating diffusion may be disposed adjacent to the amplifying transistor. This allows the first pixel and the second pixel to share the amplifying transistor without using wiring to connect the amplifying transistors disposed in the first pixel and the second pixel, and prevents an increase in capacitance of the first floating diffusion and the second floating diffusion.

[0015] In the first aspect, the first horizontal overflow storage capacitor and the second horizontal overflow storage capacitor may be pulse-driven based on a control power supply voltage, thereby reducing dark currents in the first horizontal overflow storage capacitor and the second horizontal overflow storage capacitor.

[0016] In the first aspect, the channel of the amplifier transistor may be inclined at 45 degrees with respect to the boundary between the first pixel and the second pixel in a horizontal plane in which the first pixel and the second pixel are arranged, thereby achieving an effect of increasing the channel width of the amplifier transistor without increasing the sizes of the first pixel and the second pixel.

[0017] In the first aspect, the channel of the amplifier transistor may be oriented in a <110> direction, and the boundary between the first pixel and the second pixel may be oriented in a <100> direction, thereby suppressing an increase in burst noise of the amplifier transistor, increasing the channel width, and reducing the interface state at the boundary between the first pixel and the second pixel.

[0018] In the first aspect, the first pixel and the second pixel may be arranged in a clear bit arrangement, thereby providing an effect of reducing the pixel pitch without reducing the pixel size.

[0019] A second aspect of the present invention is an imaging device including a plurality of pixels separated from one another by a pixel isolation region, and an amplifier transistor shared by the plurality of pixels and having a channel tilted at 45 degrees with respect to the pixel isolation region, thereby achieving an effect of expanding the channel width of the amplifier transistor without increasing the pixel size.

[0020] In the second aspect, the channel of the amplifier transistor may be oriented in a <110> direction, and the pixel isolation region may be oriented in a <100> direction, thereby suppressing an increase in burst noise of the amplifier transistor, increasing the channel width, and reducing the interface state density of the pixel isolation region.

[0021] In the second aspect, the plurality of pixels may be arranged in a clear bit manner, thereby reducing the pixel pitch without reducing the pixel size.

[0022] 1 is a block diagram showing an example of the configuration of an imaging device according to a first embodiment. FIG. 2 is a block diagram showing an example of the configuration of a solid-state imaging device according to the first embodiment. FIG. 3 is a diagram showing an example of the circuit configuration of a pixel provided in the solid-state imaging device according to the first embodiment. FIG. 4 is a plan view showing an example of a layout of a pixel according to the first embodiment. FIG. 5 is a plan view showing a cutting position in the example of the layout of a pixel according to the first embodiment. FIG. 6 is a cross-sectional view showing a first example of a pixel isolation region according to the first embodiment. FIG. 7 is a cross-sectional view showing a second example of a pixel isolation region according to the first embodiment. FIG. 8 is a cross-sectional view showing a third example of a pixel isolation region according to the first embodiment. FIG. 9 is a timing chart showing a first example of a waveform in a first H period of a shutter row according to the first embodiment. FIG. 10 is a timing chart showing a first example of a waveform in a first H period of a read row according to the first embodiment. FIG. 11 is a timing chart showing a first example of a waveform in a second H period of a shutter row according to the first embodiment. FIG. 12 is a timing chart showing a first example of a waveform in a second H period of a read row according to the first embodiment. 10 is a diagram showing an example of a circuit configuration of a pixel provided in a solid-state imaging device according to a second embodiment. FIG. 11 is a plan view showing an example of a pixel layout according to the second embodiment. FIG. 12 is a diagram showing an example of a circuit configuration of a pixel provided in a solid-state imaging device according to a third embodiment. FIG. 13 is a plan view showing an example of a pixel layout according to the third embodiment. FIG. 14 is a block diagram showing an example of a configuration of a solid-state imaging device according to a fourth embodiment. FIG. 15 is a plan view showing an example of a pixel layout according to the fourth embodiment. FIG. 16 is a diagram showing an example of a circuit configuration of a pixel provided in a solid-state imaging device according to a fifth embodiment. FIG. 17 is a plan view showing an example of a pixel layout according to the fifth embodiment. FIG. 18 is a timing chart showing an example of a waveform in a 1H period of a shutter row according to the fifth embodiment. FIG. 19 is a timing chart showing an example of a waveform in a 1H period of a read row according to the fifth embodiment. FIG. 19 is a timing chart showing an example of a waveform in a 2H period of a shutter row according to the fifth embodiment. FIG. 19 is a timing chart showing an example of a waveform in a 2H period of a read row according to the fifth embodiment.FIG. 13 is a diagram showing an example of a circuit configuration of a pixel provided in a solid-state imaging device according to a sixth embodiment. FIG. 14 is a plan view showing an example of a pixel layout according to the sixth embodiment. FIG. 15 is a diagram showing an example of a circuit configuration of a pixel provided in a solid-state imaging device according to a seventh embodiment. FIG. 16 is a plan view showing an example of a pixel layout according to the seventh embodiment. FIG. 17 is a diagram showing an example of a circuit configuration of a pixel provided in a solid-state imaging device according to an eighth embodiment. FIG. 18 is a plan view showing an example of a pixel layout according to the eighth embodiment. FIG. 19 is a plan view showing an example of a pixel layout according to a ninth embodiment. FIG. 19 is a perspective view showing an example of a stacking of a solid-state imaging device according to a tenth embodiment. FIG. 20 is a block diagram showing a schematic configuration example of a vehicle control system. FIG. 21 is an explanatory diagram showing an example of an installation position of an imaging unit.

[0023] Hereinafter, modes for implementing the present technology (hereinafter referred to as embodiments) will be described. The description will be made in the following order: 1. First embodiment (an example in which gate electrodes of amplifier transistors are shared in LOFIC (Lateral Overflow Integration Capacitor) pixels adjacent in the column direction) 2. Second embodiment (an example in which amplifier transistors are arranged in parallel and share gate electrodes in LOFIC pixels adjacent in the column direction) 3. Third embodiment (an example in which amplifier transistors are arranged diagonally and share gate electrodes in LOFIC pixels adjacent in the column direction) 4. Fourth embodiment (an example in which gate electrodes of amplifier transistors are shared in LOFIC pixels arranged in a clear bit configuration) 5. Fifth embodiment (an example in which gate electrodes of amplifier transistors are shared in LOFIC pixels adjacent in the column direction, and a capacitance reset transistor is added to one of the LOFIC pixels) 6. Sixth embodiment (an example in which gate electrodes of amplifier transistors are shared in LOFIC pixels adjacent in the column direction, and a gate capacitance is added to one of the LOFIC pixels) 7. 7. Seventh embodiment (an example in which LOFIC pixels adjacent in the column direction share a gate electrode of an amplification transistor, and a gate capacitance is added to one of the LOFIC pixels, and an amplification transistor is added to the other LOFIC pixel) 8. Eighth embodiment (an example in which LOFIC pixels adjacent in the column direction share a gate electrode of an amplification transistor, and a capacitance reset transistor and a gate capacitance are added to one of the LOFIC pixels) 9. Ninth embodiment (an example in which LOFIC pixels adjacent in the column direction share a gate electrode of an amplification transistor, and share a gate electrode of an overflow control transistor shifted by one pixel in the column direction) 10. Tenth embodiment (an example in which pixel array units are stacked) 11. Application to a moving body

[0024] 1. First Embodiment FIG. 1 is a block diagram showing an example of the configuration of an imaging device according to a first embodiment.

[0025] In the figure, the imaging device 100 includes an optical system 101, a solid-state imaging device 102, an imaging control unit 103, an image processing unit 104, a storage unit 105, a display unit 106, and an operation unit 107. The imaging control unit 103, the image processing unit 104, the storage unit 105, the display unit 106, and the operation unit 107 are connected to one another via a bus 108. The imaging device 100 may be used as a standalone device, or may be incorporated into a mobile terminal such as a smartphone, an authentication device, a monitoring device, a vehicle, or a drone.

[0026] The optical system 101 causes light from a subject to be incident on the solid-state imaging device 102, and forms an optical image on the light-receiving surface of the solid-state imaging device 102. The optical system 101 may include, for example, a focus lens, a zoom lens, and an aperture. The optical system 101 may also include multiple lenses, such as a wide-angle lens, a standard lens, and a telephoto lens.

[0027] The solid-state imaging device 102 converts an optical image formed on the light-receiving surface into an electrical signal for each pixel, digitizes the electrical signal, and outputs it. The solid-state imaging device 102 is, for example, a complementary metal oxide semiconductor (CMOS) image sensor. The CMOS image sensor may be a back-illuminated image sensor or a front-illuminated image sensor.

[0028] The imaging control unit 103 controls imaging by the solid-state imaging device 102 based on instructions from the operation unit 107. At this time, the imaging control unit 103 can control the exposure time, exposure amount, imaging timing, etc. of the solid-state imaging device 102.

[0029] The image processing unit 104 performs image processing based on the output from the solid-state imaging device 102. The image processing includes, for example, gamma correction, white balance processing, sharpness processing, and tone conversion processing. The image processing unit 104 may include a processor that executes processing based on software.

[0030] The storage unit 105 stores images captured by the solid-state imaging device 102 and stores imaging parameters of the solid-state imaging device 102. The storage unit 105 can also store a program that operates the imaging device 100 based on software. The storage unit 105 may include a read-only memory (ROM), a random access memory (RAM), and a memory card.

[0031] The display unit 106 displays captured images and various information that supports the image capturing operation. The display unit 106 may be a liquid crystal display, an organic EL (Electro Luminescence) display, or a micro LED display.

[0032] The operation unit 107 provides a user interface for operating the imaging device 100. The operation unit 107 may include, for example, buttons, dials, and switches provided on the imaging device 100. The operation unit 107 may be configured as a touch panel together with the display unit 106.

[0033] Depending on the configuration of the imaging device 100, some of the above functions may not be present, or conversely, the imaging device 100 may further include functions that are not disclosed.

[0034] FIG. 2 is a block diagram showing an example of the configuration of the solid-state imaging device according to the first embodiment.

[0035] In the figure, the solid-state imaging device 102 includes a pixel array section 111, a vertical scanning circuit 112, a column readout circuit 113, a column signal processing section 114, a horizontal scanning circuit 115, and a control circuit 116.

[0036] The pixel array unit 111 includes a plurality of pixels PXA and PXB. These pixels PXA and PXB are arranged in a matrix along the row direction (also referred to as the horizontal direction) and the column direction (also referred to as the vertical direction). The pixels PXA and PXB are arranged adjacent to each other in the column direction. The pixels PXA and PXB can be arranged alternately in the column direction. Each pixel PXA and PXB may include a capacitor that accumulates charge overflowing from a photodiode. This capacitor may be a lateral overflow accumulation capacitor. Each pixel PXA and PXB may constitute a lateral overflow integration capacitor (LOFIC) pixel. Each pixel PXA and PXB may include a plurality of photodiodes with different sensitivities.

[0037] Each pixel PXA, PXB can form a source follower with the column readout circuit 113 when reading out a signal. In this case, each pixel PXA, PXB can share the gate electrode of the amplification transistor that forms the source follower with the column readout circuit 113. The amplification transistor can be arranged in the pixels PXA, PXB so that the gate electrode crosses the boundary between the pixels PXA, PXB. A pixel isolation region that separates the pixels PXA, PXB can be provided at the boundary between the pixels PXA, PXB. In this case, the amplification transistor can be arranged in each pixel PXA, PXB so that the gate electrode spans the pixel isolation region. Furthermore, the pixels PXA, PXB can be arranged so as to be mirror-symmetrical with respect to the boundary between the pixels PXA, PXB.

[0038] Each pixel PXA, PXB is connected to a horizontal drive line 131 for each row, and to a vertical signal line 132 for each column. The horizontal drive line 131 drives each pixel PXA, PXB for each row when reading out a signal from each pixel 120. The vertical signal line 132 transmits a potential based on a current that flows when reading out a signal from each pixel PXA, PXB to the column signal processing unit 114 for each column.

[0039] The pixels PXA and PXB may be arranged in a Bayer array or a quad-Bayer array. The light received by the pixels PXA and PXB may be visible light, near infrared light (NIR), short wavelength infrared light (SWIR), ultraviolet light, X-rays, or the like.

[0040] The vertical scanning circuit 112 scans the pixels PXA and PXB to be read in the column direction. The vertical scanning circuit 112 may be configured using vertical registers. The vertical scanning circuit 112 may also include a decoder that specifies the pixels PXA and PXB to be read.

[0041] The column readout circuit 113 can configure a source follower between each pixel PXA and PXB when reading out a signal from each pixel PXA and PXB. At this time, the column readout circuit 113 can change the potential of each vertical signal line 132 based on the charge held in each pixel PXA and PXB.

[0042] The column signal processing unit 114 processes signals transmitted in the column direction from each pixel PXA, PXB. For example, the column signal processing unit 114 can perform correlated double sampling (CDS) processing based on the signals transmitted in the column direction from each pixel PXA, PXB. The column signal processing unit 114 can also perform AD (Analog to Digital) conversion processing based on the signals transmitted in the column direction from each pixel PXA, PXB, and output an image pickup signal Gout.

[0043] The column signal processing unit 114 includes a column ADC unit 114A. The column ADC unit 114A can perform AD conversion processing in parallel for each column. At this time, the column ADC unit 114A can perform AD conversion for each column based on the result of comparing the pixel signals read from each pixel PXA, PXB with a reference signal.

[0044] The horizontal scanning circuit 115 scans the pixels PXA and PXB to be read in the row direction. The horizontal scanning circuit 115 may be configured using a horizontal register.

[0045] The control circuit 116 controls the vertical scanning circuit 112, the column readout circuit 113, the column signal processing unit 114, and the horizontal scanning circuit 115. For example, the control circuit 116 can control the scanning timing in the column direction, the scanning timing in the row direction, the operation timing of the column readout circuit 113, and the processing timing of the column signal processing unit 114. At this time, the control circuit 116 can coordinate the vertical scanning circuit 112, the column readout circuit 113, the column signal processing unit 114, and the horizontal scanning circuit 115 so that the accumulation operation, the shutter operation, and the read operation are performed for each row in each frame. Furthermore, the control circuit 116 can set multiple readout periods corresponding to different conversion efficiencies for each pixel PXA and PXB in each 1H period (horizontal period).

[0046] FIG. 3 is a diagram showing an example of a circuit configuration of a pixel provided in the solid-state imaging device according to the first embodiment.

[0047] In the figure, pixels PXA and PXB are arranged adjacent to each other in the column direction in the pixel array section 111. At this time, pixels PXA and PXB can be paired to form cell CEL1. In cell CEL1, the pixels PXA and PXB share the gate electrodes of amplifier transistors 124A and 124B and the gate electrodes of select transistors 125A and 125B. At this time, the gate electrodes of amplifier transistors 124A and 124B are connected to floating diffusions FDA and FDB.

[0048] The pixel PXA includes a photodiode PDA, a transfer transistor 122A, a reset transistor 123A, an amplifier transistor 124A, a selection transistor 125A, and a floating diffusion FDA. The pixel PXA further includes a capacitor 126A, a pass transistor 127A, a switching transistor 128A, and an overflow control transistor 130A. The transfer transistor 122A, the reset transistor 123A, the amplifier transistor 124A, the selection transistor 125A, the pass transistor 127A, the switching transistor 128A, and the overflow control transistor 130A may be MOS (Metal Oxide Semiconductor) transistors. The capacitor 126A may be a metal-insulation-metal (MIM) capacitor. The capacitor 126A may also be a three-dimensional MIM capacitor. The capacitor 126A may also be a high-dielectric capacitor.

[0049] The photodiode PDA performs photoelectric conversion and stores the photoelectrically converted charge. The capacitor 126A stores charge that overflows from the photodiode PDA. The capacitor 126A may be light-shielded. One end of the capacitor 126A is connected to a control power supply voltage MVDD, and the other end of the capacitor 126A is connected to the cathode of the photodiode PDA via an overflow control transistor 130A.

[0050] The transfer transistor 122A transfers the charge accumulated in the photodiode PDA to the floating diffusion FDA. The reset transistor 123A resets the photodiode PDA and the floating diffusion FDA. The amplifier transistor 124A outputs a signal according to the potential of the floating diffusion FDA. The selection transistor 125A selects the output of the amplifier transistor 124A. The pass transistor 127A sets a path for transferring the charge accumulated in the capacitor 126A to the floating diffusion FDA. The switching transistor 128A switches the conversion efficiency of the amplifier transistors 124A and 124B. The overflow control transistor 130A controls the overflow of charge from the photodiode PDA to the capacitor 126A.

[0051] The transfer transistor 122A is connected between the cathode of the photodiode PDA and the floating diffusion FDA. The reset transistor 123A is connected between the power supply voltage VDD and the switching transistor 128A. The amplification transistor 124A and the selection transistor 125A are connected in series. The drain of the amplification transistor 124A is connected to the power supply voltage VDD. The gate of the amplification transistor 124A is connected to the floating diffusions FDA and FDB. The source of the selection transistor 125A is connected to the vertical signal line 132.

[0052] The pass transistor 127A is connected between the connection point of the overflow control transistor 130A and the capacitor 126A and the connection point of the reset transistor 123A and the switching transistor 128A. The switching transistor 128A is connected between the reset transistor 123A and the transfer transistor 122A. The overflow control transistor 130A is connected between the photodiode PDA and the capacitor 126A.

[0053] A transfer signal TGA is applied to the gate of the transfer transistor 122A. A reset signal RST is applied to the gate of the reset transistor 123A. A select signal SEL is applied to the gate of the select transistor 125A. A pass setting signal FCGA is applied to the gate of the pass transistor 127A. A switching signal FDGA is applied to the gate of the switching transistor 128A. An overflow control voltage OFG is applied to the gate of the overflow control transistor 130A. A control power supply voltage MVDD is applied to the capacitor 126A. The transfer signal TGA, reset signal RST, select signal SELA, pass setting signal FCGA, switching signal FDGA, overflow control voltage OFG, and control power supply voltage MVDD can be transmitted to pixel PXA via the horizontal drive line 131 of FIG. 2. The overflow control voltage OFG may be a fixed voltage.

[0054] The pixel PXB includes a photodiode PDB, a transfer transistor 122B, a reset transistor 123B, an amplifier transistor 124B, a selection transistor 125B, and a floating diffusion FDB. The pixel PXB further includes a capacitor 126B, a pass transistor 127B, a switching transistor 128B, and an overflow control transistor 130B. The transfer transistor 122B, the reset transistor 123B, the amplifier transistor 124B, the selection transistor 125B, the pass transistor 127B, the switching transistor 128B, and the overflow control transistor 130B may be MOS transistors. The capacitor 126B may be an MIM capacitor. The capacitor 126B may also be a three-dimensional MIM capacitor. The capacitor 126B may also be a high-dielectric capacitor.

[0055] The photodiode PDB performs photoelectric conversion and stores the photoelectrically converted charge. The capacitor 126B stores charge that overflows from the photodiode PDB. The capacitor 126B may be light-shielded. One end of the capacitor 126B is connected to a control power supply voltage MVDD, and the other end of the capacitor 126B is connected to the cathode of the photodiode PDB via the overflow control transistor 130B.

[0056] The transfer transistor 122B transfers the charge accumulated in the photodiode PDB to the floating diffusion FDB. The reset transistor 123B resets the photodiode PDB and the floating diffusion FDB. The amplifier transistor 124B outputs a signal according to the potential of the floating diffusion FDB. The selection transistor 125B selects the output of the amplifier transistor 124B. The pass transistor 127B sets a path for transferring the charge accumulated in the capacitor 126B to the floating diffusion FDB. The switching transistor 128B switches the conversion efficiency of the amplifier transistors 124A and 124B. The overflow control transistor 130B controls the overflow of charge from the photodiode PDB to the capacitor 126B.

[0057] The transfer transistor 122B is connected between the cathode of the photodiode PDB and the floating diffusion FDB. The reset transistor 123B is connected between the power supply voltage VDD and the switching transistor 128B. The amplification transistor 124B and the selection transistor 125B are connected in series. The drain of the amplification transistor 124B is connected to the power supply voltage VDD. The gate of the amplification transistor 124B is connected to the floating diffusions FDA and FDB. The source of the selection transistor 125B is connected to the vertical signal line 132.

[0058] The pass transistor 127B is connected between the connection point of the overflow control transistor 130B and the capacitor 126B and the connection point of the reset transistor 123B and the switching transistor 128B. The switching transistor 128B is connected between the reset transistor 123B and the transfer transistor 122B. The overflow control transistor 130B is connected between the photodiode PDB and the capacitor 126B.

[0059] A transfer signal TGB is applied to the gate of the transfer transistor 122B. A reset signal RST is applied to the gate of the reset transistor 123B. A select signal SEL is applied to the gate of the select transistor 125B. A pass setting signal FCGB is applied to the gate of the pass transistor 127B. A switching signal FDGB is applied to the gate of the switching transistor 128B. An overflow control voltage OFG is applied to the gate of the overflow control transistor 130B. A control power supply voltage MVDD is applied to the capacitor 126B. The transfer signal TGB, reset signal RST, select signal SELB, pass setting signal FCGB, switching signal FDGB, overflow control voltage OFG, and control power supply voltage MVDD can be transmitted to pixel PXB via horizontal drive line 131 in FIG. 2.

[0060] 4 is a plan view showing an example of a pixel layout according to the first embodiment. Note that the pixel layout according to the following embodiments will be described using a back-illuminated CMOS image sensor as an example.

[0061] In the figure, the semiconductor substrate SUB is separated into pixels PXA and PXB by a pixel isolation region ISG. The pixel isolation region ISG may be full-thickness front deep trench isolation (FFTI), front deep trench isolation (FDTI), or rear deep trench isolation (RDTI). Photodiodes PDA and PDB are formed on the back surface side of the semiconductor substrate SUB for each pixel PXA and PXB. Active regions AK are provided on the front surface side of the semiconductor substrate SUB, and the active regions AK are isolated by element isolation regions ISA. The element isolation regions ISA may be shallow trench isolation (STI). A channel region and an impurity diffusion layer are formed in the active region AK. Floating diffusions FDA and FDB, and source and drain layers of the pixel transistors are formed in the impurity diffusion layer. The pixel transistors may include transfer transistors 122A, 122B, reset transistors 123A, 123B, amplifying transistors 124A, 124B, select transistors 125A, 125B, pass transistors 127A, 127B, switching transistors 128A, 128B, and overflow control transistors 130A, 130B.

[0062] In pixel PXA, gate electrodes GA3 to GA7 are formed on the channel region of the active region AK via a gate insulating film. The gate electrode GA3 can be used for the reset transistor 123A. The gate electrode GA4 can be used for the transfer transistor 122A. The gate electrode GA5 can be used for the switching transistor 128A. The gate electrode GA6 can be used for the pass transistor 127A. The gate electrode GA7 can be used for the overflow control transistor 130A.

[0063] In pixel PXB, gate electrodes GB3 to GB7 are formed on the channel region of active region AK via a gate insulating film. Gate electrode GB3 can be used for reset transistor 123B. Gate electrode GB4 can be used for transfer transistor 122B. Gate electrode GB5 can be used for switching transistor 128B. Gate electrode GB6 can be used for pass transistor 127B. Gate electrode GB7 can be used for overflow control transistor 130B.

[0064] In pixels PXA and PXB, the gate electrode G1 can be shared by the amplification transistors 124A and 124B. In this case, the gate electrode G1 can be disposed in each pixel PXA and PXB across the boundary between the pixels PXA and PXB. The gate electrode G2 can be shared by the selection transistors 125A and 125B. In this case, the gate electrode G2 can be disposed in each pixel PXA and PXB across the boundary between the pixels PXA and PXB.

[0065] Here, the layout of each pixel transistor of each pixel PXA, PXB can be mirror-symmetrical with respect to the boundary between each pixel PXA, PXB. A pixel isolation region ISG can be arranged at the boundary between each pixel PXA, PXB. In this case, the gate electrode G1 of the amplification transistors 124A, 124B is arranged in each pixel PXA, PXB so as to straddle the pixel isolation region ISG. The gate electrode G2 of the selection transistors 125A, 125B is arranged in each pixel PXA, PXB so as to straddle the pixel isolation region ISG.

[0066] Furthermore, the gate electrodes GA4 and GB4 of the transfer transistors 122A and 122B can be arranged apart from the pixel isolation region ISG. In this case, the gate electrodes GA4 and GB4 of the transfer transistors 122A and 122B can be arranged in the centers of the pixels PXA and PXB, respectively.

[0067] The ends of the gate electrodes GA3 and GB3 of each reset transistor 123A, the gate electrodes GA5 and GB5 of each switching transistor 128A and 128B, and the gate electrodes GA6 and GB6 of each pass transistor 127A and 127B can be arranged on the pixel isolation region ISG. In this case, the gate electrodes GA3 and GB3 of each reset transistor 123A, the gate electrodes GA5 and GB5 of each switching transistor 128A and 128B, and the gate electrodes GA6 and GB6 of each pass transistor 127A and 127B can be arranged around the gate electrodes GA4 and GB4 of each transfer transistor 122A and 122B, respectively.

[0068] Furthermore, the floating diffusion FDA can be disposed between the gate electrode GA4 of the transfer transistor 122A and the gate electrode GA5 of the switching transistor 128A, and adjacent to the gate electrode G1 of the amplifier transistor 124A. The floating diffusion FDB can be disposed between the gate electrode GB4 of the transfer transistor 122B and the gate electrode GB5 of the switching transistor 128B, and adjacent to the gate electrode G1 of the amplifier transistor 124B. This allows the amplifier transistors 124A and 124B to share the gate electrode G1, while reducing the distance between the gate electrodes G1 of the amplifier transistors 124A and 124B and each of the floating diffusions FDA and FDB. This makes it possible to suppress an increase in the capacitance of the floating diffusions FDA and FDB when a high conversion efficiency is set, thereby reducing noise.

[0069] The material of the semiconductor substrate SUB may be Si, InGaAs, InP, InSb, HgCdTe, etc. The material of the gate electrodes G1, G2, GA3 to GA7, GB3 to GB7 may be, for example, polycrystalline silicon.

[0070] Fig. 5 is a plan view showing cutting positions in an example of a pixel layout according to the first embodiment, and Fig. 6 to Fig. 8 are cross-sectional views showing examples of the configuration of a pixel isolation region according to the first embodiment. Note that Fig. 6 to Fig. 8 show examples cut along lines A1-A2, B1-B2, C1-C2, and D1-D2 in Fig. 5, respectively.

[0071] 6A to 6D, FFTI is formed on the semiconductor substrate SUB as a pixel isolation region ISG. STI is also formed on the semiconductor substrate SUB as an element isolation region ISA. A gate electrode G1 is formed on the semiconductor substrate SUB via a gate insulating film GZ so as to straddle the pixel isolation region ISG. Gate electrodes GA6 and GB6 are also formed on the semiconductor substrate SUB via the gate insulating film GZ so as to be separated at the position of the pixel isolation region ISG. In this case, the channel width of the amplifier transistors 124A and 124B can be given as 2×W1. Therefore, by sharing the gate electrode G1 between the amplifier transistors 124A and 124B in each pixel PXA and PXB, the driving force of the amplifier transistors 124A and 124B can be increased without increasing the size of the amplifier transistors 124A and 124B in each pixel PXA and PXB.

[0072] 7A to 7D, FFTI and DTI are formed as pixel isolation regions ISG' on the semiconductor substrate SUB. At this time, DTI can be formed in the formation regions of the amplifier transistors 124A and 124B. Furthermore, STI is formed as element isolation regions ISA on the semiconductor substrate SUB. A gate electrode G1 is formed on the semiconductor substrate SUB via a gate insulating film GZ at a position spaced apart from the pixel isolation region ISG'. Gate electrodes GA6 and GB6 are formed on the semiconductor substrate SUB via the gate insulating film GZ so as to be separated at the position of the pixel isolation region ISG'. At this time, the channel width of the amplifier transistors 124A and 124B can be given as W2. Therefore, compared to a configuration in which the formation regions of the amplifier transistors 124A and 124B are formed using FFTI, the channel width W2 of the amplifier transistors 124A and 124B can be increased by the width of the pixel isolation region ISG', thereby increasing the driving force of the amplifier transistors 124A and 124B accordingly.

[0073] 8A to 8D, FFTI and DTI are formed as pixel isolation regions ISG' in the semiconductor substrate SUB. At this time, DTI can be formed in the formation regions of the amplifier transistors 124A and 124B. Also, STI is formed as element isolation regions ISA in the semiconductor substrate SUB. Gate electrode G1' is formed on the semiconductor substrate SUB via a gate insulating film GZ' so as to be embedded in the semiconductor substrate SUB at a position above the pixel isolation region ISG'. Gate electrodes GA6 and GB6 are formed on the semiconductor substrate SUB via a gate insulating film GZ' so as to be separated at the position of the pixel isolation region ISG'. In this case, if the depth of the embedded position of gate electrode G1' is D1, the channel width of the amplifier transistors 124A and 124B can be given by 2×W1 + 2×D1. Therefore, compared to a configuration in which the formation regions of the amplifier transistors 124A and 124B are formed using FFTI, the channel width of the amplifier transistors 124A and 124B can be increased by twice the depth D1 of the embedded position of the gate electrode G1', and the driving force of the amplifier transistors 124A and 124B can be increased accordingly.

[0074] 9 and 11 are timing charts showing first examples of waveforms in the 1H period and the 2H period of the shutter row according to the first embodiment, and FIGS. 10 and 12 are timing charts showing first examples of waveforms in the 1H period and the 2H period of the read row according to the first embodiment. The 2H period is set subsequent to the 1H period. Also, pixel PXA is selected in the shutter row and the read row during the 1H period, and pixel PXB is selected in the shutter row and the read row during the 2H period.

[0075] 9 to 12, the conversion efficiency is changed over three stages in each of the 1H period and the 2H period. At this time, a low-efficiency P-phase individual readout period K11, a high-efficiency P-phase individual readout period K12, a high-efficiency D-phase individual readout period K13, a low-efficiency D-phase individual readout period K14, a D-phase batch readout period K15, and a P-phase batch readout period K16 are provided in the shutter rows and readout rows of each of the 1H period and the 2H period. Individual readout is signal reading from each photodiode PDA, PDB. Batch readout is signal reading from each photodiode PDA, PDB and each capacitor 126A, 126B.

[0076] At this time, CDS processing can be performed based on signals read out during the low-efficiency P-phase individual read period K11 and the high-efficiency P-phase individual read period K12. CDS processing can be performed based on signals read out during the high-efficiency D-phase individual read period K13 and the low-efficiency D-phase individual read period K14. DDS (Double Data Sampling) processing can be performed based on signals read out during the D-phase batch read period K15 and the P-phase batch read period K16.

[0077] 9 , during the shutter row of the 1H period, the path setting signal FCGB and the overflow control voltage OFG are always set to a low level. Then, during the low-efficiency P-phase individual read period K11 and the high-efficiency P-phase individual read period K12, the transfer signals TGA and TGB and the path setting signal FCGA are set to a low level, and the reset signal RST and the switching signals FDGA and FDGB are set to a high level. At this time, the reset transistors 123A and 123B and the switching transistors 128A and 128B are turned on, discharging the charges in the floating diffusions FDA and FDB and reducing the conversion efficiency of the amplifier transistors 124A and 124B. During the low-efficiency P-phase individual read period K11, the control power supply voltage MVDD rises and is applied to the capacitors 126A and 126B. Here, by pulse-driving the capacitors 126A and 126B based on the control power supply voltage MVDD, the dark current of the capacitors 126A and 126B can be reduced.

[0078] Next, during the high-efficiency D-phase single read period K13, the transfer signal TGA rises, and the charge in the photodiode PDA is transferred to the floating diffusions FDA and FDB. After the transfer signal TGA falls, the switching signals FDGA and FDGB fall, and then the reset signal RST falls, after which the switching signals FDGA and FDGB rise again. Here, by temporarily lowering the switching signals FDGA and FDGB before the reset signal RST falls, the floating diffusions FDA and FDB can be coupled to the switching transistors 128A and 128B. This increases the potential of the floating diffusions FDA and FDB, facilitating the transfer of charge from the photodiode PDA.

[0079] Next, during the low-efficiency D-phase individual readout period K14, the transfer signal TGA rises again, and the charge in the photodiode PDA is transferred to the floating diffusions FDA and FDB. Here, during the low-efficiency D-phase individual readout period K14, the reset signal RST is set to a low level, and the reset transistors 123A and 123B are turned off. This causes the floating diffusions FDA and FDB to be in a floating state, allowing the floating diffusions FDA and FDB to be coupled to the transfer transistors 122A and 122B. This allows the potential of the floating diffusions FDA and FDB to be boosted, making it easier to extract charge from the photodiode PDA.

[0080] Next, in a D-phase batch read period K15, the reset signal RST and the path setting signal FCGA rise, turning on the reset transistors 123A and 123B and the path transistor 127A. At this time, the capacitor 126A and the floating diffusions FDA and FDB are reset.

[0081] Next, in a P-phase batch read period K16, the reset signal RST, the switching signals FDGA and FDGB, and the path setting signal FCGA fall, turning off the reset transistors 123A and 123B, the switching transistors 128A and 128B, and the path transistor 127A.

[0082] In FIG. 10, in the read row of the first H period, the path setting signal FCGB, transfer signal TGB, and overflow control voltage OFG are always set to low levels. Then, during the low-efficiency P-phase single read period K11, when the reset signal RST is high, the switching signals FDGA and FDGB fall, then the reset signal RST falls, and then the switching signals FDGA and FDGB rise again. At this time, as the switching signals FDGA and FDGB fall, the selection signal SEL rises, turning on the selection transistors 125A and 125B. Furthermore, the control power supply voltage MVDD rises and is applied to the capacitors 126A and 126B. At this time, the charge in the floating diffusions FDA and FDB is discharged, and the conversion efficiency of the amplification transistors 124A and 124B is reduced. Here, the outputs of the amplification transistors 124A and 124B are applied to the vertical signal line 132 via the selection transistors 125A and 125B, and based on the potential of the vertical signal line 132, AD conversion processing for low-efficiency P-phase single readout of the pixel PXA is performed.

[0083] Next, during a high-efficiency P-phase individual readout period K12, the switching signals FDGA and FDGB fall. At this time, the selection transistors 125A and 125B are turned off, and the conversion efficiency of the amplification transistors 124A and 124B increases. Here, the outputs of the amplification transistors 124A and 124B are applied to the vertical signal line 132 via the selection transistors 125A and 125B, and AD conversion processing for high-efficiency P-phase individual readout of pixel PXA is performed based on the potential of the vertical signal line 132.

[0084] Next, during a high-efficiency D-phase individual readout period K13, the selection signal SEL falls and the transfer signal TGA rises. At this time, the selection transistors 125A and 125B are turned off and the transfer transistor 122A is turned on, transferring the charge of the photodiode 121A to the floating diffusions FDA and FDB. Then, the selection signal SEL rises and the transfer signal TGA falls, turning on the selection transistors 125A and 125B and turning off the transfer transistor 122A. The outputs of the amplification transistors 124A and 124B are applied to the vertical signal line 132 via the selection transistors 125A and 125B, and AD conversion processing for high-efficiency D-phase individual readout of pixel PXA is performed based on the potential of the vertical signal line 132. Then, the switching signals FDGA and FDGB rise, turning on the switching transistors 128A and 128B. At this time, the conversion efficiency of the amplifier transistors 124A and 124B decreases.

[0085] Next, during a low-efficiency D-phase individual readout period K14, the selection signal SEL falls and the transfer signal TGA rises. At this time, the selection transistors 125A and 125B are turned off and the transfer transistor 122A is turned on, transferring the charge of the photodiode 121A to the floating diffusions FDA and FDB. Then, the selection signal SEL rises and the transfer signal TGA falls, turning on the selection transistors 125A and 125B and turning off the transfer transistor 122A. The outputs of the amplification transistors 124A and 124B are applied to the vertical signal line 132 via the selection transistors 125A and 125B, and AD conversion processing for low-efficiency D-phase individual readout of pixel PXA is performed based on the potential of the vertical signal line 132. Then, the selection signal SEL falls and the selection transistors 125A and 125B are turned off.

[0086] Next, in a D-phase batch readout period K15, the selection signal SEL and the pass setting signal FCGA rise, turning on the selection transistors 125A, 125B and the pass transistor 127A. Here, the outputs of the amplification transistors 124A, 124B are applied to the vertical signal line 132 via the selection transistors 125A, 125B, and AD conversion processing for the D-phase batch readout of pixel PXA is performed based on the potential of the vertical signal line 132. Thereafter, the selection signal SEL falls, turning off the selection transistors 125A, 125B.

[0087] Next, during a P-phase batch readout period K16, the reset signal RST rises, turning on the reset transistors 123A and 123B. At this time, the charges in the floating diffusions FDA and FDB and the capacitor 126A are discharged. Then, the reset signal RST falls, turning off the reset transistors 123A and 123B. Then, the selection signal SEL rises, turning on the selection transistors 125A and 125B. The outputs of the amplification transistors 124A and 124B are applied to the vertical signal line 132 via the selection transistors 125A and 125B. Based on the potential of the vertical signal line 132, AD conversion processing for the P-phase batch readout of pixel PXA is performed. Then, the selection signal SEL, the path setting signal FCGA, and the switching signals FDGA and FDGB fall.

[0088] 11 , during the shutter row of the second H period, the path setting signal FCGA and the overflow control voltage OFG are always set to a low level. Then, during the low-efficiency P-phase individual read period K11 and the high-efficiency P-phase individual read period K12, the transfer signals TGA and TGB and the path setting signal FCGB are set to a low level, and the reset signal RST and the switching signals FDGA and FDGB are set to a high level. At this time, the reset transistors 123A and 123B and the switching transistors 128A and 128B are turned on, discharging the charges in the floating diffusions FDA and FDB and reducing the conversion efficiency of the amplifier transistors 124A and 124B. During the low-efficiency P-phase individual read period K11, the control power supply voltage MVDD rises and is applied to the capacitors 126A and 126B.

[0089] Next, in a high-efficiency D-phase single readout period K13, the transfer signal TGB rises, and the charge of the photodiode PDB is transferred to the floating diffusions FDA and FDB. After the transfer signal TGB falls, the switching signals FDGA and FDGB fall, and then the reset signal RST falls, after which the switching signals FDGA and FDGB rise again.

[0090] Next, in the low-efficiency D-phase single read period K14, the transfer signal TGB rises again, and the charge of the photodiode PDB is transferred to the floating diffusions FDA and FDB.

[0091] Next, in a D-phase batch read period K15, the reset signal RST and the path setting signal FCGB rise, turning on the reset transistors 123A and 123B and the path transistor 127B. At this time, the capacitor 126B and the floating diffusions FDA and FDB are reset.

[0092] Next, in a P-phase batch read period K16, the reset signal RST, the switching signals FDGA and FDGB, and the path setting signal FCGB fall, turning off the reset transistors 123A and 123B, the switching transistors 128A and 128B, and the path transistor 127B.

[0093] In FIG. 12, in the read row of the second H period, the path setting signal FCGA, transfer signal TGA, and overflow control voltage OFG are always set to low level. Then, during the low-efficiency P-phase single read period K11, when the reset signal RST is high level, the switching signals FDGA and FDGB fall, then the reset signal RST falls, and then the switching signals FDGA and FDGB rise again. At this time, as the switching signals FDGA and FDGB fall, the selection signal SEL rises, turning on the selection transistors 125A and 125B. Furthermore, the control power supply voltage MVDD rises and is applied to the capacitors 126A and 126B. At this time, the charge in the floating diffusions FDA and FDB is discharged, and the conversion efficiency of the amplification transistors 124A and 124B is reduced. Here, the outputs of the amplification transistors 124A and 124B are applied to the vertical signal line 132 via the selection transistors 125A and 125B, and based on the potential of the vertical signal line 132, AD conversion processing for low-efficiency P-phase single readout of the pixel PXB is performed.

[0094] Next, during a high-efficiency P-phase individual readout period K12, the switching signals FDGA and FDGB fall. At this time, the selection transistors 125A and 125B are turned off, and the conversion efficiency of the amplification transistors 124A and 124B increases. Here, the outputs of the amplification transistors 124A and 124B are applied to the vertical signal line 132 via the selection transistors 125A and 125B, and AD conversion processing for high-efficiency P-phase individual readout of pixel PXB is performed based on the potential of the vertical signal line 132.

[0095] Next, during a high-efficiency D-phase individual readout period K13, the selection signal SEL falls and the transfer signal TGB rises. At this time, the selection transistors 125A and 125B are turned off and the transfer transistor 122B is turned on, transferring the charge of the photodiode 121B to the floating diffusions FDA and FDB. Then, the selection signal SEL rises and the transfer signal TGB falls, turning on the selection transistors 125A and 125B and turning off the transfer transistor 122B. The outputs of the amplification transistors 124A and 124B are applied to the vertical signal line 132 via the selection transistors 125A and 125B, and AD conversion processing for high-efficiency D-phase individual readout of pixel PXB is performed based on the potential of the vertical signal line 132. Then, the switching signals FDGA and FDGB rise, turning on the switching transistors 128A and 128B. At this time, the conversion efficiency of the amplifier transistors 124A and 124B decreases.

[0096] Next, during a low-efficiency D-phase individual readout period K14, the selection signal SEL falls and the transfer signal TGB rises. At this time, the selection transistors 125A and 125B are turned off and the transfer transistor 122B is turned on, transferring the charge of the photodiode 121B to the floating diffusions FDA and FDB. Then, the selection signal SEL rises and the transfer signal TGB falls, turning on the selection transistors 125A and 125B and turning off the transfer transistor 122B. The outputs of the amplification transistors 124A and 124B are applied to the vertical signal line 132 via the selection transistors 125A and 125B, and AD conversion processing for low-efficiency D-phase individual readout of pixel PXB is performed based on the potential of the vertical signal line 132. Then, the selection signal SEL falls and the selection transistors 125A and 125B are turned off.

[0097] Next, in a D-phase batch readout period K15, the selection signal SEL and the pass setting signal FCGB rise, turning on the selection transistors 125A, 125B and the pass transistor 127B. Here, the outputs of the amplification transistors 124A, 124B are applied to the vertical signal line 132 via the selection transistors 125A, 125B, and AD conversion processing for the D-phase batch readout of pixel PXB is performed based on the potential of the vertical signal line 132. Thereafter, the selection signal SEL falls, turning off the selection transistors 125A, 125B.

[0098] Next, during a P-phase batch readout period K16, the reset signal RST rises, turning on the reset transistors 123A and 123B. At this time, the charges in the floating diffusions FDA and FDB and the capacitor 126A are discharged. Then, the reset signal RST falls, turning off the reset transistors 123A and 123B. Then, the selection signal SEL rises, turning on the selection transistors 125A and 125B. The outputs of the amplification transistors 124A and 124B are applied to the vertical signal line 132 via the selection transistors 125A and 125B. Based on the potential of the vertical signal line 132, AD conversion processing for the P-phase batch readout of pixel PXB is performed. Then, the selection signal SEL, the path setting signal FCGB, and the switching signals FDGA and FDGB fall.

[0099] 9 to 12, the switching signals FDGA and FDGB of each pixel PXA and PXB are simultaneously turned on and off. This increases the parasitic capacitance added to the floating diffusions FDA and FDB of each pixel PXA and PXB in the read row of the low-efficiency D-phase individual readout period K14. This ensures a capacitance sufficient to receive the charge when the photodiodes PDA and FDB are saturated, enabling miniaturization of each pixel PXA and PXB.

[0100] 13 and 14 are timing charts showing a second example of waveforms in the first H period and the second H period of the read row according to the first embodiment.

[0101] 13, in the read row of the 1H period, the switching signal FDGB falls during the low-efficiency P-phase single read period K11 and is maintained at a low level. The falling of the levels of other signals is the same as in the timing charts of FIGS. 9 and 10.

[0102] 14, in the read row of the second H period, the switching signal FDGA falls during the low-efficiency P-phase single read period K11 and is maintained at a low level. The falling of the levels of other signals is the same as in the timing charts of FIGS. 11 and 12.

[0103] 13 and 14, when a signal is read from each pixel PXA, PXB, the switching signals FDGA, FDGB of the other pixel PXA, PXB are turned off. This makes it possible to increase the conversion efficiency of each pixel PXA, PXB and reduce noise in the read rows of the low-efficiency P-phase individual readout period K11 and the low-efficiency D-phase individual readout period K14.

[0104] As described above, in the first embodiment, the gate electrodes G1 of the amplifier transistors 124A and 124B of the pixels PXA and PXB adjacent to each other in the column direction are arranged so as to cross the pixel isolation region ISG between the pixels PXA and PXB. This allows the amplifier transistors 124A and 124B to be shared by the pixels PXA and PXB without using wiring to connect the amplifier transistors 124A and 124B arranged in each pixel PXA and PXB, and it is possible to increase the driving force of the amplifier transistors 124A and 124B while suppressing an increase in the size of the pixels PXA and PXB.

[0105] Furthermore, the layout of each pixel transistor of each pixel PXA, PXB is mirror-symmetric with respect to the pixel isolation region ISG between the pixels PXA, PXB. This allows the amplifier transistors 124A, 124B to share the gate electrode G1, while reducing the distance between the gate electrode G1 of the amplifier transistors 124A, 124B and each floating diffusion FDA, FDB. This makes it possible to suppress an increase in the capacitance value of the floating diffusions FDA, FDB when set to high conversion efficiency, thereby reducing noise.

[0106] 2. Second Embodiment In the first embodiment described above, the gate electrodes G1 of the amplifier transistors 124A and 124B of the pixels PXA and PXB adjacent in the column direction are arranged to cross the pixel isolation region ISG between the pixels PXA and PXB. In this second embodiment, in the LOFIC pixels adjacent in the column direction, the amplifier transistors are arranged in parallel to share the gate electrode.

[0107] FIG. 15 is a diagram showing an example of a circuit configuration of a pixel provided in a solid-state imaging device according to the second embodiment.

[0108] In the figure, this solid-state imaging device includes a cell CEL2 instead of the cell CEL1 of the first embodiment described above. The cell CEL2 includes pixels PXA2 and PXB2 instead of the pixels PXA and PXB of the first embodiment described above. Furthermore, the cell CEL2 includes amplification transistors 124A2 and 124B2 in addition to the cell CEL1 of the first embodiment described above. In the cell CEL2, the gate electrodes of the amplification transistors 124A, 124B, 124A2, and 124B2 are shared by the pixels PXA2 and PXB2. At this time, the gate electrodes of the amplification transistors 124A, 124B, 124A2, and 124B2 are connected to the floating diffusions FDA and FDB.

[0109] Furthermore, the selection transistor 125A is removed from pixel PXA2, and the reset transistor 123B is removed from pixel PXB2. In this case, the selection transistor 125B and the reset transistor 123A can be shared by pixels PXA2 and PXB2. Other circuit configurations of pixels PXA2 and PXB2 of the second embodiment are similar to the circuit configurations of pixels PXA and PXB of the first embodiment described above.

[0110] FIG. 16 is a plan view showing an example of a pixel layout according to the second embodiment.

[0111] In the figure, the pixels PXA2 and PXB2 have an active region AK2, an element isolation region ISA2, and gate electrodes G21 and G22 instead of the active region AK, element isolation region ISA, and gate electrodes G1 and G2 of the first embodiment. The rest of the layout configuration of the pixels PXA2 and PXB2 of the second embodiment is the same as the layout configuration of the pixels PXA and PXB of the first embodiment.

[0112] In pixels PXA2 and PXB2, gate electrodes G21 and G22 are arranged parallel to each other in the row direction. Each gate electrode G21 and G22 can be shared by amplifier transistors 124A and 124B. Here, each gate electrode G21 and G22 can be arranged in each pixel PXA2 and PXB2 across the boundary between the pixels PXA2 and PXB2. In this case, each gate electrode G21 and G22 can be arranged in each pixel PXA2 and PXB2 so as to straddle the pixel isolation region ISG.

[0113] The gate electrode GB3 can be used for the selection transistor 125B. By allocating the gate electrode GB3 to the selection transistor 125B, the gate electrode G22 can be disposed at the position of the gate electrode G2 in the first embodiment.

[0114] In this way, in the second embodiment described above, the amplifier transistors 124A, 124B, 124A2, and 124B2 are arranged in parallel in the pixels PXA2 and PXB2 adjacent to each other in the column direction, respectively, and share the gate electrodes G21 and G22. This makes it possible to increase the driving force of the amplifier transistors 124A, 124B, 124A2, and 124B2 while suppressing an increase in the size of the pixels PXA2 and PXB2.

[0115] 3. Third Embodiment In the first embodiment described above, the gate electrodes G1 of the amplifier transistors 124A and 124B of the pixels PXA and PXB adjacent in the column direction are arranged so as to cross the pixel isolation region ISG between the pixels PXA and PXB. In this third embodiment, the amplifier transistors in the pixels PXA and PXB adjacent in the column direction are arranged diagonally to share the gate electrode.

[0116] FIG. 17 is a diagram showing an example of a circuit configuration of a pixel provided in a solid-state imaging device according to the third embodiment.

[0117] In the figure, this solid-state imaging device includes a cell CEL3 instead of the cell CEL1 of the first embodiment described above. The cell CEL3 includes pixels PXA3 and PXB3 instead of the pixels PXA and PXB of the first embodiment described above. In the cell CEL3, the gate electrodes of the amplifier transistors 124A and 124B are shared by the pixels PXA3 and PXB3. At this time, the gate electrodes of the amplifier transistors 124A and 124B are connected to the floating diffusions FDA and FDB.

[0118] Furthermore, the selection transistor 125A is removed from pixel PXA3, and the reset transistor 123B is removed from pixel PXB3. In this case, the selection transistor 125B and the reset transistor 123A can be shared by pixels PXA3 and PXB3. Other circuit configurations of pixels PXA3 and PXB3 of the third embodiment are similar to the circuit configurations of pixels PXA and PXB of the first embodiment described above.

[0119] FIG. 18 is a plan view showing an example of a pixel layout according to the third embodiment.

[0120] In the figure, a semiconductor substrate SUB is separated into pixels PXA3 and PXB3 by pixel isolation regions ISG. Photodiodes PDA and PDB are formed for each pixel PXA3 and PXB3 on the back surface side of the semiconductor substrate SUB. An active area AK3 is provided on the front surface side of the semiconductor substrate SUB, and the active area AK3 is isolated by element isolation regions ISA3.

[0121] In pixel PXA3, gate electrodes GA33 to GA37 are formed on the channel region of active region AK3 via a gate insulating film. Gate electrode GA33 can be used for reset transistor 123A. Gate electrode GA34 can be used for transfer transistor 122A. Gate electrode GA35 can be used for switching transistor 128A. Gate electrode GA36 can be used for pass transistor 127A. Gate electrode GA37 can be used for overflow control transistor 130A.

[0122] In pixel PXB, gate electrodes GB33 to GB37 are formed on the channel region of active region AK3 via a gate insulating film. Gate electrode GB33 can be used for selection transistor 125B. Gate electrode GB34 can be used for transfer transistor 122B. Gate electrode GB35 can be used for switching transistor 128B. Gate electrode GB36 can be used for pass transistor 127B. Gate electrode GB37 can be used for overflow control transistor 130B.

[0123] In the pixels PXA and PXB, the gate electrode G31 can be shared by the amplifier transistors 124A and 124B. In this case, the gate electrode G31 can be disposed in each of the pixels PXA3 and PXB3 across the boundary between the pixels PXA3 and PXB3.

[0124] Here, the layout of each pixel transistor of each pixel PXA3, PXB3 can be mirror-symmetric with respect to the boundary between each pixel PXA3, PXB3. In this case, the gate electrodes G31 of the amplifier transistors 124A, 124B are arranged in each pixel PXA3, PXB3 so as to straddle the pixel isolation region ISG. Furthermore, the channels of the gate electrodes G31 of the amplifier transistors 124A, 124B can be arranged at an angle of 45° with respect to the arrangement direction of the pixel isolation region ISG. Here, in order to arrange the gate electrodes G31 of the amplifier transistors 124A, 124B of each pixel PXA3, PXB3 in mirror symmetry, the gate electrodes G31 can be bent by 90° at the boundary position between the pixels PXA3, PXB3. In this case, the planar shape of the gate electrodes G31 can be V-shaped.

[0125] It is desirable to arrange the channels of the amplifier transistors 124A and 124B in the <110> direction and the pixel isolation region ISG in the <100> direction. This makes it possible to increase the number of carriers in the amplifier transistors 124A and 124B while widening the channel width and reducing the interface state density in the pixel isolation region ISG. This makes it possible to suppress the dark current in the pixel isolation region ISG while suppressing an increase in burst noise in the amplifier transistors 124A and 124B.

[0126] Furthermore, the gate electrodes GA34, GB34 of each transfer transistor 122A, 122B and the gate electrodes GA35, GB35 of each switching transistor 128A, 128B can be arranged away from the pixel isolation region ISG. In this case, the gate electrodes GA34, GB34 of each transfer transistor 122A, 122B can be arranged in the center of the pixel PXA3, PXB3, respectively. Furthermore, to improve layout efficiency, the channel directions of the transfer transistor 122A and the switching transistor 128A may be orthogonal to the channel direction of the amplifier transistor 124A, and the channel directions of the transfer transistor 122B and the switching transistor 128B may be orthogonal to the channel direction of the amplifier transistor 124B.

[0127] The ends of the gate electrode GA33 of the reset transistor 123A, the gate electrode GB32 of the select transistor 125B, and the gate electrodes GA36 and GB36 of each of the pass transistors 127A and 127B can be arranged on the pixel isolation region ISG. In this case, the gate electrode GA33 of the reset transistor 123A, the gate electrode GB32 of the select transistor 125B, and the gate electrodes GA36 and GB36 of each of the pass transistors 127A and 127B can be arranged around the gate electrodes GA4 and GB4 of each of the transfer transistors 122A and 122B, respectively.

[0128] Furthermore, the floating diffusion FDA can be disposed between the gate electrode GA34 of the transfer transistor 122A and the gate electrode GA35 of the switching transistor 128A, and adjacent to the gate electrode G31 of the amplifier transistor 124A. The floating diffusion FDB can be disposed between the gate electrode GB34 of the transfer transistor 122B and the gate electrode GB35 of the switching transistor 128B, and adjacent to the gate electrode G31 of the amplifier transistor 124B. This allows the amplifier transistors 124A and 124B to share the gate electrode G31 by arranging it diagonally, while reducing the distance between the gate electrode G31 of the amplifier transistors 124A and 124B and each of the floating diffusions FDA and FDB. This improves the driving force of the amplifier transistors 124A and 124B, suppresses an increase in the capacitance of the floating diffusions FDA and FDB when set to high conversion efficiency, and reduces noise.

[0129] In this way, in the third embodiment described above, in the pixels PXA3 and PXB3 adjacent to each other in the column direction, the amplifier transistors 124A and 124B are arranged diagonally to share the gate electrode G31. This makes it possible to increase the gate widths of the amplifier transistors 124A and 124B while suppressing an increase in the size of the pixels PXA3 and PXB3, thereby increasing the driving force of the amplifier transistors 124A and 124B.

[0130] In the third embodiment described above, the configuration in which the amplifier transistors 124A and 124B are arranged diagonally to share the gate electrode G31 is applied to the LOFIC pixel. The configuration in which the amplifier transistors 124A and 124B are arranged diagonally to share the gate electrode G31 is not necessarily limited to the LOFIC pixel, but may also be applied to a pixel without LOFIC. In a pixel without LOFIC, the capacitors 126A and 126B, the pass transistors 127A and 127B, the switching transistors 128A and 128B, and the overflow control transistors 130A and 130B can be removed.

[0131] 4. Fourth Embodiment In the first embodiment described above, the gate electrode G1 of the amplification transistors 124A and 124B is shared in the pixels PXA and PXB arranged in a square. In this fourth embodiment, the gate electrode of the amplification transistor is shared in pixels arranged in a clear bit configuration.

[0132] FIG. 19 is a block diagram showing an example of the configuration of a solid-state imaging device according to the fourth embodiment.

[0133] In the figure, this solid-state imaging device 402 includes a pixel array section 411 instead of the pixel array section 111 of the first embodiment described above. Other configurations of the solid-state imaging device 402 of the fourth embodiment are similar to the configurations of the solid-state imaging device 102 of the first embodiment described above.

[0134] The pixel array unit 411 includes pixels PXC and PXD instead of the pixels PXA and PXB of the first embodiment. Other configurations of the pixel array unit 411 of the fourth embodiment are similar to the configuration of the pixel array unit 111 of the first embodiment.

[0135] The pixels PXC and PXD are arranged in a clear bit configuration. In the clear bit configuration, the pixels PXC and PXD are rotated by 45° and arranged in the row and column directions. In a configuration in which the gate electrodes of the amplification transistors 124A and 124B of the pixels PXC and PXD are shared, the pixels PXC and PXD can be rotated 45° as a pair so that the gate electrodes of the amplification transistors 124A and 124B are not separated. In the clear bit configuration, the pixel pitch can be set to 1 / √2, thereby improving resolution while maintaining sensitivity. The circuit configuration of each pixel PXC and PXD is the same as the circuit configuration of the pixels PXA3 and PXB3 of the third embodiment described above.

[0136] FIG. 20 is a plan view showing an example of a pixel layout according to the fourth embodiment.

[0137] In the figure, the clear bit arrangement of pixels PXC and PXD is the same as the configuration of pixels PXA3 and PXB3 in the third embodiment described above, rotated 45°. Here, pixels PXA3 and PXB3 can be configured as a pair to form cell CELA. In this case, pixels PXC and PXD can be mirror-symmetric with respect to the boundary between pixels PXC and PXD. Furthermore, if cells CELA and CELB are adjacent in a diagonal direction, cells CELA and CELB can also be mirror-symmetric with respect to the boundary between cells CELA and CELB. In this case, it is desirable to arrange the channels of amplifier transistors 124A and 124B in the <110> direction and arrange pixel isolation region ISG in the <100> direction. In a configuration in which the channels of amplifier transistors 124A and 124B are arranged in the <110> direction, the channel direction of pixel PXC can coincide with the column direction, and the channel direction of pixel PXD can coincide with the row direction.

[0138] In this way, in the fourth embodiment described above, the pixels PXC and PXD in the clear bit arrangement share the gate electrode G31 of the amplifier transistors 124A and 124B. This makes it possible to increase the driving force of the amplifier transistors 124A and 124B while suppressing an increase in the size of the pixels PXA3 and PXB3, and also improve the resolution while maintaining the sensitivity.

[0139] In the fourth embodiment described above, the configuration in which the gate electrode G31 of the amplifier transistors 124A and 124B is shared in the pixels PXC and PXD in the clear bit arrangement is applied to the LOFIC pixel. The configuration in which the gate electrode G31 of the amplifier transistors 124A and 124B is shared in the pixels PXC and PXD in the clear bit arrangement is not necessarily limited to the LOFIC pixel, and may be applied to a pixel without LOFIC.

[0140] 5. Fifth Embodiment In the first embodiment described above, the pixels PXA and PXB adjacent in the column direction share the gate electrode G1 of the amplification transistors 124A and 124B. In this fifth embodiment, the LOFIC pixels adjacent in the column direction share the gate electrode G1 of the amplification transistors 124A and 124B, and a capacitance reset transistor is added to one of the LOFIC pixels.

[0141] FIG. 21 is a diagram showing an example of a circuit configuration of a pixel provided in a solid-state imaging device according to the fifth embodiment.

[0142] In the figure, this solid-state imaging device includes a cell CEL5 instead of the cell CEL1 of the first embodiment described above. The cell CEL5 includes a pixel PXA5 instead of the pixel PXA of the first embodiment described above. The pixel PXA5 includes a capacitance reset transistor 140A instead of the reset transistor 123A of the first embodiment described above. The other circuit configurations of the pixel PXA5 of the fifth embodiment are the same as the circuit configuration of the pixel PXA of the first embodiment described above.

[0143] The capacitance reset transistor 140A resets the capacitors 126A and 126B. In this case, the capacitance reset transistor 140A can be shared by the pixels PXA5 and PXB. The capacitance reset transistor 140A is connected between the connection point of each of the capacitors 126A and 126B and the control power supply voltage MVDD and the power supply voltage VDD. A capacitance reset signal FCR is applied to the gate of the capacitance reset transistor 140A.

[0144] FIG. 22 is a plan view showing an example of a pixel layout according to the fifth embodiment.

[0145] In the figure, the layout pattern of the pixels PXA5 and PXB can be configured similarly to the layout pattern of the pixels PXA and PXB of the first embodiment described above, except that in the pixel PXA5, the gate electrode GA3 can be assigned to the capacitance reset transistor 140A.

[0146] Figures 23 and 25 are timing charts showing examples of waveforms in the 1st and 2nd H periods of a shutter row according to the fifth embodiment, and Figures 24 and 26 are timing charts showing examples of waveforms in the 1st and 2nd H periods of a read row according to the fifth embodiment.

[0147] 23 to 26, in the shutter rows and read rows of the 1H period and the 2H period, the capacitance reset signal FCR rises in the D-phase batch read period K15 and falls in the P-phase batch read period K16. The falls of the levels of the other signals are the same as those in the timing charts of FIGS.

[0148] In this way, in the fifth embodiment described above, the gate electrode G1 of the amplification transistors 124A and 124B is shared between the pixels PXA5 and PXB adjacent to each other in the column direction, and the capacitance reset transistor 140A is added to the pixel PXA5. This allows the capacitors 126A and 126B to be reset at the start of the D-phase batch read period K15, thereby speeding up the resetting of the capacitors 126A and 126B.

[0149] In the fifth embodiment described above, the gate electrode G1 is shared by the amplification transistors 124A and 124B, and the capacitance reset transistor 140A is added to the pixel PXA5. The configuration in which the capacitance reset transistor 140A is added to the pixel may be applied to the third or fourth embodiment described above.

[0150] 6. Sixth Embodiment In the first embodiment described above, the pixels PXA and PXB adjacent in the column direction share the gate electrode G1 of the amplification transistors 124A and 124B. In this sixth embodiment, the LOFIC pixels adjacent in the column direction share the gate electrode G1 of the amplification transistors 124A and 124B, and a gate capacitance is added to one of the LOFIC pixels.

[0151] FIG. 27 is a diagram showing an example of a circuit configuration of a pixel provided in a solid-state imaging device according to the sixth embodiment.

[0152] In the figure, this solid-state imaging device includes a cell CEL6 instead of the cell CEL1 of the first embodiment described above. The cell CEL6 includes a pixel PXA6 instead of the pixel PXA of the first embodiment described above. The pixel PXA6 includes a gate capacitor 601A instead of the reset transistor 123A of the first embodiment described above. In this case, the reset transistor 123A can be shared by the pixels PXA6 and PXB. The rest of the circuit configuration of the pixel PXA6 of the sixth embodiment is the same as the circuit configuration of the pixel PXA of the first embodiment described above.

[0153] The gate capacitance 601A can be configured with a MOS transistor and can be connected to the connection point of the pass transistor 127A and the switching transistor 128A. A control voltage CI is applied to the gate of the gate capacitance 601A.

[0154] FIG. 28 is a plan view showing an example of a pixel layout according to the sixth embodiment.

[0155] In the figure, the pixels PXA6 and PXB have a gate electrode GA63 instead of the gate electrode GA3 of the first embodiment described above. The gate electrode GA63 can be used as a gate capacitor 601A. In this case, a source layer may be provided on one side of the gate electrode GA63, and a drain layer may not be provided on the other side of the gate electrode GA63. The other layout configurations of the pixels PXA6 and PXB of the sixth embodiment are similar to the layout configurations of the pixels PXA and PXB of the first embodiment described above.

[0156] In this way, in the sixth embodiment described above, the gate electrode G1 of the amplification transistors 124A and 124B is shared between the pixels PXA6 and PXB adjacent to each other in the column direction, and the gate capacitance 601A is added to the pixel PXA6. This allows the charge overflowing from the floating diffusions FDA and FDB to be stored in the gate capacitance 601A, thereby increasing the amount of charge stored in the low-efficiency D-phase individual readout period K14.

[0157] In the sixth embodiment described above, the gate electrode G1 is shared by the amplification transistors 124A and 124B, and the gate capacitance 601A is added to the pixel PXA6. The configuration in which the gate capacitance 601A is added to the pixel may be applied to the third or fourth embodiment described above.

[0158] 7. Seventh Embodiment In the first embodiment described above, the pixels PXA and PXB adjacent in the column direction share the gate electrode G1 of the amplification transistors 124A and 124B. In this seventh embodiment, the LOFIC pixels adjacent in the column direction share the gate electrode G1 of the amplification transistors 124A and 124B, and a gate capacitance is added to one of the LOFIC pixels, and an amplification transistor is added to the other LOFIC pixel.

[0159] FIG. 29 is a diagram showing an example of a circuit configuration of a pixel provided in a solid-state imaging device according to the seventh embodiment.

[0160] In the figure, this solid-state imaging device includes a cell CEL7 instead of the cell CEL6 of the sixth embodiment. The cell CEL7 includes pixels PXA7 and PXB7 instead of the pixels PXA6 and PXB of the sixth embodiment. In the cell CEL7, the gate electrodes of the amplification transistors 124A, 124B, and 124B2 are shared by the pixels PXA7 and PXB7. At this time, the gate electrodes of the amplification transistors 124A, 124B, and 124B2 are connected to the floating diffusions FDA and FDB.

[0161] The pixel PXA7 has a gate electrode specific to the select transistor 125A, instead of the gate electrode shared by the select transistors 125A and 125B of the sixth embodiment. The pixel PXB7 has an amplifier transistor 124B2, instead of the select transistor 125B of the sixth embodiment. In this case, the select transistor 125A can be shared by the pixels PXA7 and PXB7. The other circuit configurations of the pixels PXA7 and PXB7 of the seventh embodiment are similar to the circuit configurations of the pixels PXA6 and PXB of the sixth embodiment.

[0162] FIG. 30 is a plan view showing an example of a pixel layout according to the seventh embodiment.

[0163] In the same figure, pixel PXA7 has a gate electrode GA2 instead of gate electrode G2 in the sixth embodiment described above. Gate electrode GA2 can be used for selection transistor 125A. Pixel PXB7 has a gate electrode GB2 instead of gate electrode G2 in the sixth embodiment described above. Gate electrode GB2 can be used for amplification transistor 124B2. Gate electrode GB2 can be connected to gate electrode G1 via wiring. Other layout configurations of pixels PXA7 and PXB7 in the seventh embodiment are similar to the layout configurations of pixels PXA6 and PXB in the sixth embodiment described above.

[0164] In this way, in the seventh embodiment described above, the gate electrode G1 of the amplifier transistors 124A and 124B is shared between the pixels PXA7 and PXB7 adjacent to each other in the column direction, and a gate capacitance 601A is added to the pixel PXA7, and an amplifier transistor 124B2 is added to the pixel PXB7. This makes it possible to increase the driving force of the amplifier transistors 124A, 124B, and 124B2 while suppressing an increase in the size of the pixels PXA7 and PXB7, and also to increase the amount of charge stored in the low-efficiency D-phase individual readout period K14.

[0165] In the seventh embodiment described above, the gate capacitor 601A is added to the pixel PXA7, and the amplifier transistor 124B2 is added to the pixel PXB7. The configuration in which the gate capacitor 601A is added to one pixel and the amplifier transistor 124B2 is added to the other pixel may be applied to the third or fourth embodiment described above.

[0166] 8. Eighth Embodiment In the seventh embodiment described above, the pixels PXA7 and PXB7 adjacent to each other in the column direction share the gate electrode G1 of the amplification transistors 124A and 124B, and a gate capacitor 601A is added to the pixel PXA7, and an amplification transistor 124B2 is added to the pixel PXB7. In this eighth embodiment, the LOFIC pixels adjacent to each other in the column direction share the gate electrodes of the amplification transistors, and a capacitance reset transistor and a gate capacitor are added to one of the LOFIC pixels.

[0167] FIG. 31 is a diagram showing an example of a circuit configuration of a pixel provided in a solid-state imaging device according to the eighth embodiment.

[0168] In the figure, this solid-state imaging device includes a cell CEL8 instead of the cell CEL7 of the seventh embodiment. The cell CEL8 includes pixels PXA8 and PXB8 instead of the pixels PXA7 and PXB7 of the seventh embodiment. In the cell CEL8, the gate electrodes of the amplifier transistors 124A and 124B are shared by the pixels PXA8 and PXB8. At this time, the gate electrodes of the amplifier transistors 124A and 124B are connected to the floating diffusions FDA and FDB.

[0169] The pixel PXA8 includes a capacitance reset transistor 140A instead of the selection transistor 125A of the seventh embodiment described above. The capacitance reset transistor 140A is shared by the pixels PXA8 and PXB8. The pixel PXB8 includes a selection transistor 125B instead of the amplification transistor 124B2 of the seventh embodiment described above. In this case, the selection transistor 125B can be shared by the pixels PXA8 and PXB8. Other circuit configurations of the pixels PXA8 and PXB8 of the eighth embodiment are similar to the circuit configurations of the pixels PXA7 and PXB7 of the seventh embodiment described above.

[0170] FIG. 32 is a plan view showing an example of a pixel layout according to the eighth embodiment.

[0171] In the figure, the layout patterns of the pixels PXA8 and PXB8 can be configured similarly to the layout patterns of the pixels PXA7 and PXB7 of the seventh embodiment. However, in the pixel PXA8, the gate electrode GA2 can be assigned to the capacitance reset transistor 140A. In the pixel PXB8, the gate electrode GB2 can be assigned to the reset transistor 123B. In addition, in the pixel PXB8, the gate electrode GB3 can be assigned to the selection transistor 125B.

[0172] In this way, in the eighth embodiment described above, the gate electrode G1 of the amplification transistors 124A and 124B is shared between the pixels PXA8 and PXB8 adjacent to each other in the column direction, and a capacitance reset transistor 140A and a gate capacitance 601A are added to the pixel PXA8. This makes it possible to increase the driving force of the amplification transistors 124A, 124B, and 124B2 while suppressing an increase in the size of the pixels PXA7 and PXB7, and also makes it possible to increase the amount of charge stored in the low-efficiency D-phase single read period K14 while speeding up the resetting of the capacitors 126A and 126B.

[0173] In the above-described eighth embodiment, the gate electrode G1 is shared by the amplification transistors 124A and 124B, and a capacitance reset transistor 140A and a gate capacitance 601A are added to the pixel PXA8. The configuration in which the capacitance reset transistor 140A and the gate capacitance 601A are added to the pixel may be applied to the above-described third or fourth embodiment.

[0174] 9. Ninth Embodiment In the first embodiment described above, the pixels PXA and PXB adjacent in the column direction share the gate electrode G1 of the amplification transistors 124A and 124B. In this ninth embodiment, the LOFIC pixels adjacent in the column direction share the gate electrode of the amplification transistor, and also share the gate electrode of the overflow control transistor shifted by one pixel in the column direction.

[0175] FIG. 33 is a plan view showing an example of a pixel layout according to the ninth embodiment.

[0176] In the figure, pixels PXA9 and PXB9 are arranged adjacent to each other in the column direction. Instead of the gate electrodes GA7 and GB7 of the first embodiment described above, pixels PXA9 and PXB9 include a gate electrode G7. In this case, the gate electrode G7 can be arranged in each pixel PXA9, PXB9 across the boundary between the pixels PXA9, PXB9. However, the gate electrode G7 is shared by pixels PXA9, PXB9 that are shifted by one pixel in the column direction from the pixels PXA9, PXB9 that share the gate electrode G1. Other configurations of pixels PXA9, PXB9 of the ninth embodiment are similar to those of pixels PXA, PXB of the first embodiment described above.

[0177] As described above, in the ninth embodiment, the pixels PXA9 and PXB9 adjacent to each other in the column direction share the gate electrode G1 of the amplifier transistors 124A and 124B, and also share the gate electrode G7 of the overflow control transistors 130A and 130B, which are shifted by one pixel in the column direction. This makes it possible to increase the driving force of the amplifier transistors 124A and 124B while suppressing an increase in the size of the pixels PXA9 and PXB9, and also to reduce the space required for wiring connected to the overflow control transistors 130A and 130B.

[0178] 10. Tenth Embodiment In the first embodiment described above, the gate electrode G1 of the amplification transistors 124A and 124B is shared between the pixels PXA and PXB adjacent to each other in the column direction. In this tenth embodiment, semiconductor chips each having a pixel array portion in which pixels are arranged in a matrix are stacked.

[0179] FIG. 34 is a perspective view showing an example of lamination of a pixel array unit according to the tenth embodiment.

[0180] In the figure, the solid-state imaging device includes semiconductor chips 921 and 922. The semiconductor chip 922 is stacked on the semiconductor chip 921.

[0181] A pixel array section 923 is formed in the semiconductor chip 922. In the pixel array section 923, pixels 931 are arranged in a matrix in the row and column directions. The pixels 931 may be any of the pixels in the first to ninth embodiments described above. Pad electrodes 932 and via electrodes 933 are formed around the pixel array section 923. The via electrodes 933 penetrate the semiconductor chip 922 and can electrically connect the semiconductor chips 921 and 922 to each other.

[0182] A peripheral circuit 924 is formed on the semiconductor chip 921. A column readout circuit 925, a column ADC 926, a communication interface 927, and a control circuit 928 are formed in the peripheral circuit 924. The column readout circuit 925 and the column ADC 926 may be formed so as to correspond to positions on both sides of the pixel array unit 923 in the column direction.

[0183] The semiconductor chips 921 and 922 may be directly bonded to each other. Hybrid bonding can be used for directly bonding the semiconductor chips 921 and 922. In this case, the semiconductor chips 921 and 922 may be electrically connected based on Cu-Cu bonding. The material of the semiconductor substrate used for the semiconductor chips 921 and 922 may be Si, InGaAs, or InP.

[0184] As described above, in the tenth embodiment, the semiconductor chip 922 on which the pixel array unit 923 is formed is stacked on the semiconductor chip 921 on which the peripheral circuit 924 is formed. This makes it possible to increase the sensitivity of the solid-state imaging device while suppressing an increase in the mounting area of ​​the semiconductor chip on which the solid-state imaging device is formed.

[0185] 11. Application Examples to Mobile Bodies The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0186] FIG. 35 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0187] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 35, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (interface) 12053.

[0188] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0189] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0190] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0191] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0192] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0193] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, vehicle lane departure warning, etc.

[0194] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0195] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0196] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle of information. In the example of Fig. 35, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0197] FIG. 36 is a diagram showing an example of the installation position of the imaging unit 12031.

[0198] In FIG. 36, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0199] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0200] 36 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0201] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0202] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which runs autonomously without relying on driver operation.

[0203] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0204] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0205] An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the imaging unit 12031 of the above-described configuration. Specifically, for example, the imaging devices according to the first to tenth embodiments described above can be applied to the imaging unit 12031. By applying the technology according to the present disclosure to the vehicle control system 12000, it is possible to achieve high image quality while suppressing an increase in the size of the imaging device.

[0206] Note that the above-described embodiment shows an example for realizing the present technology, and the matters in the embodiment and the matters specifying the invention in the claims correspond to each other. Similarly, the matters specifying the invention in the claims and the matters in the embodiment of the present technology with the same title correspond to each other. However, the present technology is not limited to the embodiment, and can be realized by applying various modifications to the embodiment within the scope of the gist. Furthermore, the effects described in this specification are merely examples and are not limited, and other effects may also be present.

[0207] The present technology may also be configured as follows: (1) An imaging device comprising: a first pixel provided with a first horizontal overflow storage capacitor; a second pixel arranged adjacent to the first pixel and provided with a second horizontal overflow storage capacitor; and amplification transistors arranged in the first pixel and the second pixel such that a gate electrode crosses the boundary between the first pixel and the second pixel. (2) The imaging device described in (1), wherein the amplification transistors are arranged in the first pixel and the second pixel so as to be mirror-symmetric with respect to the boundary between the first pixel and the second pixel. (3) The imaging device described in (1) or (2), further comprising: a pixel isolation region provided at the boundary between the first pixel and the second pixel; and a gate electrode of the amplification transistor is arranged in the first pixel and the second pixel so as to straddle the pixel isolation region. (4) The imaging device according to any one of (1) to (3), wherein the amplification transistor comprises: a first amplification transistor arranged in the first pixel and the second pixel so as to cross the boundary between the first pixel and the second pixel; and a second amplification transistor arranged in the first pixel or the second pixel and connected to the first amplification transistor via a wiring. (5) The imaging device according to any one of (1) to (4), wherein the first pixel comprises a first overflow control transistor that controls overflow of the first lateral overflow storage capacitor, and the second pixel comprises a second overflow control transistor that controls overflow of the second overflow storage capacitor. (6) The imaging device according to (5), wherein the first overflow control transistor and the second overflow control transistor are arranged in the first pixel and the second pixel, respectively, so as to be mirror-symmetric to each other with respect to the boundary between the first pixel and the second pixel.(7) The imaging device according to any one of (1) to (6), wherein the first pixel comprises a first selection transistor that selects readout from the first pixel, the second pixel comprises a second selection transistor that selects readout from the second pixel, the first selection transistor and the second selection transistor being arranged in the first pixel and the second pixel, respectively, to be mirror-symmetric with respect to each other with respect to the boundary between the first pixel and the second pixel. (8) The imaging device according to any one of (1) to (7), wherein the first pixel comprises a selection transistor that selects readout from the first pixel or the second pixel, the second pixel comprises an amplification transistor shared by the first pixel and the second pixel, the selection transistor and the amplification transistor being arranged in the first pixel and the second pixel, respectively, to be mirror-symmetric with respect to each other with respect to the boundary between the first pixel and the second pixel. (9) The imaging device according to (3), wherein the first pixel comprises: a first photodiode, a first floating diffusion connected to a gate of the amplifying transistor, and a first transfer transistor that transfers charge accumulated in the first photodiode to the first floating diffusion, the second pixel comprises: a second photodiode, a second floating diffusion connected to a gate of the amplifying transistor, and a second transfer transistor that transfers charge accumulated in the second photodiode to the second floating diffusion, the first transfer transistor and the second transfer transistor are spaced apart from the pixel isolation region, and the first floating diffusion and the second floating diffusion are disposed adjacent to the amplifying transistor. (10) The imaging device according to any of (1) to (10), wherein the first lateral overflow storage capacitor and the second lateral overflow storage capacitor are pulse-driven based on a control power supply voltage. (11) The imaging device described in any one of (1) to (10), wherein in a horizontal plane in which the first pixel and the second pixel are arranged, the channel of the amplification transistor is inclined at 45 degrees with respect to the boundary between the first pixel and the second pixel.(12) The imaging device according to (11), wherein the channel of the amplifier transistor is arranged in the <110> direction, and the boundary between the first pixel and the second pixel is arranged in the <100> direction. (13) The imaging device according to (11) or (12), wherein the first pixel and the second pixel are arranged in a clear bit arrangement. (14) An imaging device comprising: a pixel separated by a pixel isolation region; and an amplifier transistor provided in the pixel, the amplifier transistor having a channel arranged at an angle of 45 degrees with respect to the pixel isolation region. (15) The imaging device according to (14), wherein the channel of the amplifier transistor is arranged in the <110> direction, and the pixel isolation region is arranged in the <100> direction. (16) The imaging device according to (14) or (15), wherein the pixel is arranged in a clear bit arrangement.

[0208] REFERENCE SIGNS LIST 100 Imaging device 101 Optical system 102 Solid-state imaging device 103 Imaging control unit 104 Image processing unit 105 Memory unit 106 Display unit 107 Operation unit 108 Bus 111 Pixel array unit 112 Vertical scanning circuit 113 Column readout circuit 114 Column signal processing unit 115 Horizontal scanning circuit 116 Control circuit PXA, PXB Pixel 131 Horizontal drive line 132 Vertical signal line PDA, PDB Photodiode FDA, FDB Floating diffusion 122A, 122B Transfer transistor 123A, 123B Reset transistor 124A, 124B Amplification transistor 125A, 125B Selection transistor 126A, 126B Capacitor 127A, 127B Pass transistor 128A, 128B Switching transistor SUB Semiconductor substrate ISG Pixel isolation region ISA Element isolation region G1, G2, GA3 to GA7, GB3 to GB7 Gate electrodes

Claims

1. An imaging device comprising: a first pixel provided with a first horizontal overflow storage capacitor; a second pixel arranged adjacent to the first pixel and provided with a second horizontal overflow storage capacitor; and amplification transistors arranged in the first pixel and the second pixel such that a gate electrode crosses the boundary between the first pixel and the second pixel.

2. The imaging device according to claim 1, wherein the amplifying transistors are arranged in the first pixel and the second pixel so as to be mirror-symmetric with respect to the boundary between the first pixel and the second pixel.

3. The imaging device according to claim 1, further comprising a pixel isolation region provided at the boundary between the first pixel and the second pixel, and wherein the gate electrode of the amplification transistor is arranged in the first pixel and the second pixel so as to straddle the pixel isolation region.

4. The imaging device according to claim 1, wherein the amplification transistor comprises: a first amplification transistor arranged in the first pixel and the second pixel so as to cross the boundary between the first pixel and the second pixel; and a second amplification transistor arranged in the first pixel or the second pixel and connected to the first amplification transistor via a wiring.

5. The imaging device according to claim 1, wherein the first pixel comprises a first overflow control transistor that controls the overflow of the first horizontal overflow storage capacitor, and the second pixel comprises a second overflow control transistor that controls the overflow of the second type overflow storage capacitor.

6. The imaging device according to claim 5, wherein the first overflow control transistor and the second overflow control transistor are arranged in the first pixel and the second pixel, respectively, so as to be mirror-symmetric with respect to the boundary between the first pixel and the second pixel.

7. The imaging device according to claim 1, wherein the first pixel comprises a first selection transistor that selects readout from the first pixel, and the second pixel comprises a second selection transistor that selects readout from the second pixel, and the first selection transistor and the second selection transistor are respectively arranged in the first pixel and the second pixel so as to be mirror-symmetric to each other with respect to the boundary between the first pixel and the second pixel.

8. The imaging device according to claim 1, wherein the first pixel comprises a selection transistor that selects readout from the first pixel or the second pixel, the second pixel comprises an amplification transistor shared by the first pixel and the second pixel, and the selection transistor and the amplification transistor are arranged in the first pixel and the second pixel, respectively, so as to be mirror-symmetric to each other with respect to the boundary between the first pixel and the second pixel.

9. The imaging device of claim 3, wherein the first pixel comprises a first photodiode, a first floating diffusion connected to the gate of the amplifying transistor, and a first transfer transistor that transfers charges accumulated in the first photodiode to the first floating diffusion; the second pixel comprises a second photodiode, a second floating diffusion connected to the gate of the amplifying transistor, and a second transfer transistor that transfers charges accumulated in the second photodiode to the second floating diffusion; the first transfer transistor and the second transfer transistor are spaced apart from the pixel isolation region; and the first floating diffusion and the second floating diffusion are arranged adjacent to the amplifying transistor.

10. The imaging device according to claim 1, wherein the first horizontal overflow storage capacitor and the second horizontal overflow storage capacitor are pulse-driven based on a control power supply voltage.

11. The imaging device according to claim 1, wherein in a horizontal plane in which the first pixel and the second pixel are arranged, the channel of the amplification transistor is inclined at 45 degrees with respect to the boundary between the first pixel and the second pixel.

12. The imaging device according to claim 11, wherein the channel of the amplifying transistor is oriented in the <110> direction, and the boundary between the first pixel and the second pixel is oriented in the <100> direction.

13. The imaging device according to claim 11, wherein the first pixel and the second pixel are arranged in a clear bit manner.

14. An imaging device comprising: a plurality of pixels separated from one another via a pixel isolation region; and an amplifying transistor shared by the plurality of pixels, the channel of which is arranged at an angle of 45 degrees with respect to the pixel isolation region.

15. The imaging device according to claim 14, wherein the channel of the amplifying transistor is oriented in the <110> direction, and the pixel isolation region is oriented in the <100> direction.

16. The imaging device according to claim 14, wherein the plurality of pixels are arranged in a clear bit pattern.

Images