Semiconductor device and preparation method therefor, and dynamic random access memory

Abstract

A semiconductor device and a preparation method therefor, and a three-dimensional dynamic random access memory. The semiconductor device comprises: a substrate; a channel structure, which is disposed on the substrate in a first direction; bit lines, which are disposed between the channel structure and the substrate, are electrically connected to the channel structure and extend in a second direction; and word lines, which are disposed on at least one side of the channel structure and extend in a third direction, wherein the first direction intersects the substrate, the second direction is parallel to the substrate, and the third direction is parallel to the substrate and intersects the second direction; and the channel structure comprises a filling material and an oxide semiconductor layer disposed on the outer surface of the filling material.

Description

Semiconductor devices and their fabrication methods, dynamic random access memory

[0001] This disclosure is based on and claims priority to Chinese Patent Application No. 202410806141.6, filed on June 20, 2024, entitled “Programmable Device, Programmable Device Array and Operating Method Thereof, Memory”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device and its fabrication method, and a dynamic random access memory. Background Technology

[0003] Dynamic Random Access Memory (DRAM) is a type of semiconductor memory. Compared to static random access memory (SRAM), DRAM has advantages such as simpler structure, lower manufacturing cost, and higher capacity density. With technological advancements, the application of DRAM is becoming increasingly widespread.

[0004] A vertical channel transistor (VCT) is a semiconductor structure in which the active pillar extends from the substrate in a direction roughly perpendicular to the substrate plane. In the fabrication of semiconductor devices containing VCTs (such as DRAM), because the bit lines need to be buried under the channel, processes such as atomic layer deposition, etching, and high-temperature annealing are required. Furthermore, the material fabrication process involves first creating trenches in the substrate and then depositing the material within those trenches, making the fabrication process complex. The resulting bit lines are also prone to open circuits, severely impacting the performance of the semiconductor device.

[0005] Summary of the Invention

[0006] According to a first aspect of the present disclosure, a semiconductor device is provided, comprising:

[0007] The substrate; a channel structure disposed on the substrate along a first direction; a bit line disposed between the channel structure and the substrate and electrically connected to the channel structure, the bit line extending along a second direction; a word line disposed on at least one side of the channel structure and extending along a third direction; the first direction intersects the substrate, the second direction is parallel to the substrate, and the third direction is parallel to the substrate and intersects the second direction; wherein the channel structure includes a filling material and an oxide semiconductor layer disposed on the outer surface of the filling material.

[0008] In some embodiments, the material of the oxide semiconductor layer is selected from one or more of indium gallium zinc oxide, zinc oxide, or indium zinc oxide.

[0009] In some embodiments, the fill material is silicon oxide or aluminum oxide.

[0010] In some embodiments, the word line surrounds the channel structure.

[0011] In some embodiments, the semiconductor device further comprises a storage node disposed on and electrically connected to the channel structure.

[0012] In some embodiments, the storage node comprises one or more of a capacitor, a magnetoresistive storage, a phase change storage, and a ferroelectric storage.

[0013] In some embodiments, the semiconductor device further comprises a first electrode disposed on the channel structure; wherein a projection of the first electrode on the substrate along the first direction has a larger area than a projection of the channel structure on the substrate along the first direction.

[0014] In some embodiments, the semiconductor device further comprises a first spacer layer disposed between the first electrode and the word line.

[0015] In some embodiments, the first spacer layer and the word line overlap in projection on the substrate along the first direction.

[0016] In some embodiments, the semiconductor device further comprises a second spacer block disposed in the same layer as the first electrode and spaced apart from the first electrode along a third direction.

[0017] In some embodiments, a projection of the second spacer block on the substrate along the first direction coincides with a projection of the word line on the substrate along the second direction.

[0018] According to a second aspect of embodiments of the present disclosure, a dynamic random access memory is provided, and has the following features.

[0019] Any of the semiconductor devices, sub-word line drivers, and sensitive amplifiers described above.

[0020] According to a third aspect of embodiments of the present disclosure, a method for manufacturing a semiconductor device is provided, and has the following features.

[0021] A substrate is provided.

[0022] A bit line extending along a second direction is formed on the substrate.

[0023] A channel structure extending along a first direction is formed on the bit line; wherein the channel structure is formed with a fill material and an oxide semiconductor layer formed on an outer surface of the fill material.

[0024] A word line extending along a third direction is formed on at least one side of the channel structure.

[0025] The first direction intersects the substrate, the second direction is parallel to the substrate, and the third direction is parallel to the substrate and intersects the second direction.

[0026] In some embodiments, forming the channel structure comprises:

[0027] forming an intermediate layer on the substrate with the bit line, forming a hole in the intermediate layer at a corresponding position, and forming a first oxide semiconductor material layer on the sidewall and the bottom of the hole;

[0028] forming a filling material in the hole with the oxide semiconductor layer, and forming a second oxide semiconductor material layer on the surface of the filling material;

[0029] The first oxide semiconductor material layer and the second oxide semiconductor material layer form the oxide semiconductor layer.

[0030] In some embodiments, the method for manufacturing the semiconductor device further comprises:

[0031] forming a first spacer layer on the channel structure, and forming a first electrode on the first spacer layer.

[0032] In the embodiments of the present disclosure, since the semiconductor material layer in the formed channel structure is wrapped with the filling material in the middle of the outer surface, the semiconductor material layer can be made very thin, so that the transistor has good switching performance. Since the semiconductor material layer is fully wrapped, combined with the fully surrounding gate, the effective channel has a large channel width and can also ensure a large contact area with the source and drain, reduce the contact resistance, and ensure the performance of the contact device. Since the area of the second electrode is larger than the area of the channel structure, the contact effect with the storage node can be ensured, the process window is improved, and the generation of defective products is reduced. The first spacer layer between the second electrode and the word line can effectively prevent the mutual influence between the word lines. BRIEF DESCRIPTION OF DRAWINGS

[0033] FIG. 1 is a schematic diagram of a dynamic random access memory according to an example embodiment;

[0034] FIGS. 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, and 28 are schematic diagrams of a cross section of a partial structure along a word line direction and passing through a channel structure position in a semiconductor device manufacturing process according to an example embodiment;

[0035] FIGS. 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, and 27 are schematic diagrams of a cross section of a partial structure along a bit line direction and passing through a channel structure position in a semiconductor device manufacturing process according to an example embodiment;

[0036] FIG. 30 is a schematic diagram of a top view of a step in a semiconductor device manufacturing process according to an example embodiment. DETAILED DESCRIPTION

[0037] The technical solutions of the present disclosure will be described in further detail below in conjunction with the accompanying drawings and embodiments. Although the exemplary implementation methods of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the implementation described herein. On the contrary, these implementations are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0038] The present disclosure will be described in more detail in the following paragraphs with reference to the accompanying drawings and embodiments. The advantages and features of the present disclosure will be more apparent from the following description and claims. It should be noted that the accompanying drawings are very simplified and use non-precise proportions, only for the purpose of facilitating, clarifying and assisting in the description of the embodiments of the present disclosure.

[0039] It can be understood that the meanings of "on", "above" and "over" of the present disclosure should be interpreted in the broadest way, so that "on" not only means the meaning of "on" something with no intervening features or layers therebetween (i.e. directly on something), but also includes the meaning of "on" something with intervening features or layers therebetween.

[0040] In the embodiments of the present disclosure, the terms "first", "second", "third" and the like are used to distinguish similar objects, and do not necessarily have to describe a specific order or sequence.

[0041] In the embodiments of the present disclosure, the term "layer" refers to a portion of material that includes a region having a thickness. The layer can extend over the entirety of the underlying or overlying structure, or can have a scope that is less than the scope of the underlying or overlying structure. Further, a layer can be a region of a homogeneous or inhomogeneous continuous structure having a thickness that is less than the thickness of the continuous structure. For example, a layer can be located between the top surface and the bottom surface of a continuous structure, or the layer can be between any pair of horizontal planes at the top surface and the bottom surface of the continuous structure. The layer can extend horizontally, vertically, and / or along an inclined surface. The layer can include a plurality of sub-layers.

[0042] It should be noted that the technical solutions described in the embodiments of the present disclosure can be combined arbitrarily without conflict.

[0043] According to a first aspect of embodiments of the present disclosure, as shown in FIG. 1, a first direction D1 intersects with a substrate 100, a second direction D2 is parallel to the substrate, and a third direction D3 is parallel to the substrate and intersects with the second direction, a dynamic random access memory 1000 is provided, comprising: a semiconductor device 10, a sub-word line driver SWD, and a sensitive amplifier SA. The sub-word line driver is electrically connected to a word line in the semiconductor device, and is configured to control the semiconductor device to work by transmitting a driving signal. The sensitive amplifier is electrically connected to a bit line in the semiconductor device, and is configured to amplify an electrical signal transmitted in the bit line.

[0044] In some embodiments, the sub-word line driver is disposed in the substrate 100 and is electrically connected to the word line through a wire. Optionally, the sub-word line driver is disposed between the semiconductor device structure and the substrate, and the projection of the sub-word line driver on the substrate along the first direction overlaps the semiconductor device structure, or is separately disposed in a region outside the semiconductor device structure.

[0045] In some embodiments, the sub-word line driver is disposed on another substrate, and the another substrate is connected to the semiconductor device through bonding. The sub-word line driver is electrically connected to the word line of the semiconductor device through bonding and a wire.

[0046] In some embodiments, the sensitive amplifier is disposed in the substrate 100 and is electrically connected to the bit line through a wire. Optionally, the sensitive amplifier is disposed between the semiconductor device structure and the substrate, and the projection of the sensitive amplifier on the substrate along the first direction overlaps the semiconductor device structure, or is separately disposed in a region outside the semiconductor device structure.

[0047] In some embodiments, the sensitive amplifier is disposed on another substrate, and the another substrate is connected to the semiconductor device through bonding. The sensitive amplifier is electrically connected to the bit line of the semiconductor device through bonding and a wire.

[0048] In some embodiments, the sub-word line driver and the sensitive amplifier are jointly disposed on another substrate, and the sub-word line driver and the sensitive amplifier are respectively electrically connected to the word line and the bit line of the semiconductor device through bonding and a wire. The bonding mode is selected from bump bonding or hybrid bonding.

[0049] In some embodiments, as shown in FIG. 1 and FIG. 28-30, the semiconductor device comprises: a substrate 100, a channel structure 500, a bit line 200, a word line 300; the channel structure is distributed in an array along a first direction on the substrate; the bit line extends along a second direction, and is spaced apart from the channel structure and the substrate along a third direction and electrically connected to the channel structure; the word line extends along the third direction, and is spaced apart from at least one side of the channel structure along the second direction, that is, a plurality of word lines and a plurality of bit lines form a mesh structure, and a plurality of independent channel structures are arranged near the intersection of the mesh structure; the word line and the channel structure form a transistor, and the word line serves as a gate to control the channel structure to be turned on or turned off; optionally, the word line is arranged on one side of the channel structure, that is, a single-gate transistor is formed. Or the word line is arranged on two sides of the channel structure, which can be opposite sides or adjacent sides, that is, a double-gate transistor is formed. Or the word line is arranged on three sides of the channel structure, forming a triple-gate transistor. Preferably, the word line surrounds the channel structure to form a ring-gate transistor; wherein the channel structure comprises a filling material 520 and an oxide semiconductor layer 510 arranged on the outer surface of the filling material.

[0050] In some embodiments, the material of the oxide semiconductor layer on the outer surface of the channel structure is selected from one or more of indium gallium zinc oxide, zinc oxide or indium zinc oxide. Preferably, the material of the oxide semiconductor layer is indium gallium zinc oxide.

[0051] In some embodiments, the material of the oxide semiconductor layer on the outer surface of the channel structure is indium gallium zinc oxide, and has other elements for doping. Preferably, the two ends of the channel structure along the first direction have doping elements, which can be the same or different. The doping elements are selected from one or more of silicon, tin, phosphorus, arsenic, boron, copper, cadmium, aluminum or carbon, for changing the conductivity of the indium gallium zinc oxide.

[0052] In some embodiments, the filling material of the channel structure is selected from silicon oxide or aluminum oxide.

[0053] In some embodiments, the channel structure is in the shape of a cylinder, or a cube, or a cuboid.

[0054] In some embodiments, the thickness of the oxide semiconductor layer in the channel structure is uniform. Optionally, the thickness of the oxide semiconductor layer is different, and the thickness of the oxide semiconductor layer at one end away from the substrate along the first direction is different from the thickness of the side surface and the bottom surface.

[0055] In some embodiments, the oxide semiconductor layer in the channel structure is composed of two layers of junction, the side surface and the bottom surface are composed of one layer, and the space surrounded by the side surface and the bottom surface is filled with the filling material, and another layer is arranged on the top surface to form a closed space with the side surface to wrap the filling material therein.

[0056] In some embodiments, the semiconductor device further comprises a storage node 600 disposed on and electrically connected to the channel structure; optionally, the storage node is directly connected to the channel structure; optionally, the storage node is electrically connected to the channel structure through the first electrode 400 to transmit electrical signals.

[0057] In some embodiments, the first electrode is disposed between the storage node and the channel structure in the first direction; optionally, the symmetry axis of the storage node in the first direction does not coincide with the symmetry axis of the channel structure in the first direction; optionally, the symmetry axis of the storage node in the first direction coincides with the symmetry axis of the channel structure in the first direction.

[0058] In some embodiments, the first electrode is disposed on the channel structure, and the projected area of the first electrode on the substrate in the first direction is larger than the projected area of the channel structure on the substrate in the first direction. Optionally, the projected area of the first electrode on the substrate in the second direction is wider than the projected area of the channel structure on the substrate, or the projected area of the first electrode on the substrate in the third direction is wider than the projected area of the channel structure on the substrate. Preferably, the projected area of the first electrode on the substrate in the second direction and the third direction is wider than the projected area of the channel structure on the substrate, i.e., the projection of the first electrode completely covers the projection of the channel structure.

[0059] In some embodiments, the contact point of the storage node and the first electrode on the substrate in the first direction is beyond the projection range of the channel structure on the substrate in the first direction.

[0060] In some embodiments, the storage node comprises one or more of a capacitor, a magnetoresistive storage, a phase change storage, and a ferroelectric storage.

[0061] In some embodiments, the semiconductor device further comprises a first spacer layer 700 disposed between the first electrode and the word line. In this embodiment, the length of the channel structure in the first direction is longer than the length of the word line in the first direction, i.e., there is a distance between the end of the first electrode in contact with the channel structure and the region where the word line coincides with the channel structure, and the first spacer layer is disposed in this space.

[0062] In some embodiments, when the word line surrounds the channel structure to form a ring gate transistor, the first spacer layer is disposed on the word line and in contact with the channel structure, forming a shape surrounding the channel structure. That is, the channel structure penetrates the word line and the first spacer layer.

[0063] In some embodiments, the word line is disposed on one side of the channel structure to form a single-gate transistor; or the word line is disposed on two sides of the channel structure, which can be opposite two sides or adjacent two sides, to form a double-gate transistor; or the word line is disposed on three sides of the channel structure to form a triple-gate transistor. Optionally, the first spacer layer is disposed on the word line, covering the upper surface of the word line, and has the same shape as the word line, and also surrounds one side of the channel structure, or surrounds two sides of the channel structure, or surrounds three sides of the channel structure. Optionally, the first spacer layer is disposed on the word line, and the first spacer layer surrounds the channel structure, that is, a through hole is formed in the first spacer layer, and the channel structure is disposed in the through hole, and the projection of the first spacer layer on the substrate in the first direction covers the projection of the word line on the substrate in the first direction.

[0064] In some embodiments, when the projection area of the first electrode on the substrate in the first direction is greater than the projection area of the channel structure on the substrate in the first direction, the part of the first electrode that exceeds the channel structure is disposed on the first spacer layer. Optionally, the projection area of the first spacer layer on the substrate in the first direction is greater than the projection area of the first electrode on the substrate in the first direction.

[0065] In some embodiments, the first spacer layer overlaps the word line in the projection on the substrate in the first direction, that is, the first spacer layer covers the upper surface of the word line.

[0066] In some embodiments, the semiconductor device further comprises a second spacer block 800, which is disposed in the same layer as the first electrode and is spaced apart from the first electrode in the third direction. That is, the second spacer block is disposed between the plurality of first electrodes on the same word line to isolate the plurality of first electrodes from each other. Optionally, the thickness of the second spacer block is the same as the thickness of the first electrode, so that the upper surfaces of the first electrode and the second spacer block on the same word line form a flat plane.

[0067] In some embodiments, the projection of the second spacer block on the substrate in the first direction coincides with the projection of the word line on the substrate in the first direction in the second direction. That is, the width of the second spacer block is the same as the width of the word line, and the second spacer block is aligned with the edge of the word line in the direction of the width of the word line.

[0068] In some embodiments, the first spacer layer is disposed between the first electrode and the word line, covering the upper surface of the word line, and the second spacer block is disposed on the first spacer layer. The projection of the second spacer block on the substrate in the first direction coincides with the projection of the first spacer layer on the substrate in the first direction in the second direction.

[0069] According to a second aspect of the embodiments of the present disclosure, a method for manufacturing the semiconductor device is provided, as shown in FIGS. 2-30, a substrate is provided, which can be made of a single crystal silicon, a germanium-silicon, a silicon carbide, or other semiconductor materials, and can include other previously prepared structures, such as a transistor disposed in the substrate; a bit line extending in a second direction is formed on the substrate, which can be formed by depositing a bit line material film layer on a surface of the substrate, patterning a mask by a patterning process, and etching the bit line material film layer to form the bit line 200 by an etching process.

[0070] In some embodiments, the patterning process includes forming a photoresist on the bit line film layer, exposing and developing the photoresist to form a photoresist with a preset pattern, and etching the bit line material film layer through the patterned photoresist to form the bit line.

[0071] In some embodiments, the patterning process further includes forming a hard mask on the bit line material film layer, forming a photoresist on the hard mask, exposing and developing the photoresist to form a photoresist with a preset pattern, etching the hard mask through the patterned photoresist to transfer the preset pattern to the hard mask, stripping the photoresist, and etching the bit line material film layer through the patterned hard mask to form the bit line.

[0072] In some embodiments, as the semiconductor manufacturing process develops, the integration level increases, and the size shrinks. A single patterning process cannot form the first preset width and the second preset width required, and multiple patterning processes are needed to form the same. For example, a twice exposure and etching process (LELE), or a self-aligned double patterning process (SADP), or a self-aligned quadruple patterning process (SAQP), etc.

[0073] In some embodiments, the deposition process of the bit line material film layer can be selected from a physical vapor deposition (PVD) method, an atomic layer deposition (ALD) method, a pulsed laser deposition (PLD) method, a chemical vapor deposition (CVD), vacuum evaporation, furnace tube deposition, or a Damascus process, etc.

[0074] In some embodiments, the material of the bit line material film layer can include a metal, a metal nitride, a metal oxide, a metal silicide, a conductive carbon, and a combination thereof; such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), titanium nitride (TiN), titanium aluminum nitride (TiAlN), titanium carbonitride (TiCN), tantalum (Ta), tantalum nitride (TaN), tantalum aluminum nitride (TaAlN), tantalum carbonitride (TaCN), ruthenium (Ru), platinum (Pt), or a combination thereof, or a polysilicon, a gallium-indium-tin oxide, a tin-indium oxide, or a combination thereof. Preferably, the material of the bit line material film layer is titanium nitride.

[0075] After forming the bit lines, a dielectric layer M1 is formed between the bit lines. Optionally, the dielectric layer is formed on the surface of the bit lines to prevent the bit lines from being damaged in subsequent processes. Specifically, the method for forming the dielectric layer includes forming a dielectric layer material layer, planarizing the dielectric layer material layer, and obtaining the dielectric layer.

[0076] In some embodiments, the dielectric layer material layer includes a dielectric material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.

[0077] In some embodiments, the method for forming the dielectric layer material layer is selected from physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), chemical vapor deposition (CVD), vacuum evaporation, furnace tube deposition, and the like.

[0078] In some embodiments, the planarization of the dielectric layer material layer can be achieved by chemical mechanical polishing (CMP). The dielectric layer material layer formed by a deposition process has a rough surface. The planarization can be achieved by controlling the polishing time. Optionally, if a protective layer is needed on the surface of the bit lines, the polishing is stopped when the dielectric layer reaches a preset thickness, thereby forming the protective layer and the dielectric layer. Optionally, if only the dielectric layer is needed, the polishing is stopped when the bit lines are exposed.

[0079] Further, as shown in FIGS. 2-3, a trench structure is formed on the bit lines in a first direction. Specifically, a sacrificial layer M2 and a sacrificial layer M3 are deposited on the substrate with the bit lines and the dielectric layer, and a via V1 is formed at a position corresponding to the trench structure by a patterning process.

[0080] Optionally, the material of the sacrificial layer M2 and the sacrificial layer M3 is selected from one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride. Preferably, the sacrificial layer M2 is silicon oxide, and the sacrificial layer M3 is silicon nitride or silicon oxycarbonitride.

[0081] Optionally, the deposition method of the sacrificial layer M2 and the sacrificial layer M3 is selected from physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), chemical vapor deposition (CVD), or vacuum evaporation. Preferably, the deposition method of the sacrificial layer M2 and the sacrificial layer M3 is chemical vapor deposition (CVD).

[0082] Optionally, the patterning process for forming the via V1 includes forming a photoresist on the sacrificial layer M3, exposing and developing the photoresist to form a photoresist with a preset pattern, and etching the sacrificial layer M2 and the sacrificial layer M3 through the patterned photoresist to form the via V1. Similarly, a hard mask can be formed first, a patterning process is performed on the hard mask, and then the pattern in the patterned hard mask is transferred to the sacrificial layer M2 and the sacrificial layer M3.

[0083] In some embodiments, the method of etching the sacrificial layer M2 and the sacrificial layer M3 to form the via V1 comprises anisotropic etching or isotropic etching, such as dry etching or wet etching.

[0084] In some embodiments, when the via V1 is formed, the protective layer is removed together, so that the bit line is exposed at the bottom of the via V1.

[0085] Further, as shown in FIG. 4-5, a first oxide semiconductor material layer C1 is deposited on the substrate with the via V1, and the first oxide semiconductor material layer C1 covers the surface of the sacrificial layer M3 and the sidewall and bottom surface of the via V1.

[0086] Optionally, the material of the first oxide semiconductor material layer C1 is selected from one or more of indium gallium zinc oxide, zinc oxide or indium zinc oxide. Preferably, the material of the first oxide semiconductor material layer C1 is indium gallium zinc oxide.

[0087] Optionally, the deposition method of the first oxide semiconductor material layer C1 is selected from physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), chemical vapor deposition (CVD), vacuum evaporation, furnace tube deposition, etc. Preferably, the deposition method of the first oxide semiconductor material layer C1 is atomic layer deposition (ALD).

[0088] In some embodiments, before the first oxide semiconductor material layer C1 is formed, a contact layer is formed on the surface of the bit line exposed at the bottom of the via V1, and the conductivity of the contact layer is between the first oxide semiconductor material layer C1 and the bit line, so as to reduce the contact resistance.

[0089] In some embodiments, a part of the first oxide semiconductor material layer C1 at the bottom of the via V1 is subjected to a doping treatment to form a film layer with higher conductivity than the first oxide semiconductor material layer C1, so as to reduce the contact resistance between the first oxide semiconductor material layer C1 and the bit line. Optionally, the doping ions are selected from one or more of silicon, tin, phosphorus, arsenic, boron, copper, cadmium, aluminum or carbon. Optionally, the doping method is ion implantation.

[0090] As shown in FIGS. 6-7, a fill material layer C2 is formed on the substrate with the first oxide semiconductor material layer Cl. Optionally, the fill material layer C2 is selected from one or more of silicon oxide, aluminum oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride. Preferably, the fill material layer C2 is silicon oxide or aluminum oxide. Optionally, the fill material layer C2 is deposited by a method selected from physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), chemical vapor deposition (CVD), and vacuum evaporation. Preferably, the fill material layer C2 is deposited by chemical vapor deposition (CVD), and then planarized by chemical mechanical polishing. Optionally, the fill material layer C2 is further polished to remove the portion of the fill material layer C2 on the surface of the sacrificial layer M3, exposing the sacrificial layer M3.

[0091] As shown in FIGS. 8-9, the substrate with the fill material layer C2 is etched back, leaving the remaining fill material layer C2 as the fill material in the final structure. Optionally, the upper surface of the remaining fill material layer C2 is lower than the upper surface of the sacrificial layer M3. Optionally, the upper surface of the remaining fill material layer C2 is lower than the upper surface of the sacrificial layer M2. Optionally, the fill material layer C2 is etched back by a dry etching method.

[0092] As shown in FIGS. 10-11, a second oxide semiconductor material layer C3 is deposited on the surface of the substrate after the fill material layer C2 is etched back, covering the surface of the remaining fill material layer C2 and the upper surface of the first semiconductor material layer Cl. Optionally, the second oxide semiconductor material layer C3 is selected from one or more of indium gallium zinc oxide, zinc oxide, and indium zinc oxide. Preferably, the second oxide semiconductor material layer C3 and the first oxide semiconductor material layer Cl are both indium gallium zinc oxide.

[0093] Optionally, the second oxide semiconductor material layer C3 is deposited by a method selected from physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), chemical vapor deposition (CVD), vacuum evaporation, and furnace tube deposition. Preferably, the second oxide semiconductor material layer C3 is deposited by atomic layer deposition (ALD).

[0094] In some embodiments, the second oxide semiconductor material layer C3 is doped to form a film layer with higher conductivity than the second oxide semiconductor material layer C3. Optionally, the dopant ions are selected from one or more of silicon, tin, phosphorus, arsenic, boron, copper, cadmium, aluminum, and carbon. Optionally, the doping method is ion implantation.

[0095] As shown in FIGS. 12-13, the substrate with the second oxide semiconductor material layer C3 formed thereon is ground to remove the second oxide semiconductor material layer C3 and the first oxide semiconductor material layer C1 on the upper surface of the sacrificial layer M3 in sequence to expose the sacrificial layer M3, and the remaining second oxide semiconductor material layer C3 and the first oxide semiconductor material layer C1 form an oxide semiconductor layer. The space surrounded by the oxide semiconductor layer is filled with a filling material to form a complete channel structure with the filling material and the oxide semiconductor layer formed on the outer surface of the filling material. Optionally, the grinding method is chemical mechanical grinding (CMP).

[0096] In some embodiments, the upper surface of the substrate with the complete channel structure formed thereon is subjected to a doping process to make the upper surface of the channel structure have a film layer with higher conductivity than the second oxide semiconductor material layer C3. Optionally, the doping ions are selected from one or more of silicon, tin, phosphorus, arsenic, boron, copper, cadmium, aluminum, or carbon. Optionally, the doping method is ion implantation.

[0097] As shown in FIGS. 14-15, a sacrificial layer M4 is deposited on the surface of the substrate with the channel structure formed thereon, and the sacrificial layer M4 covers the channel structure and the upper surface of the sacrificial layer M3. Optionally, the material of the sacrificial layer M4 is selected from one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride. Preferably, the material of the sacrificial layer M4 is the same as that of the sacrificial layer M3, i.e., silicon nitride or silicon oxycarbonitride. Optionally, the deposition method of the sacrificial layer M4 is selected from physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), chemical vapor deposition (CVD), or vacuum evaporation. Preferably, the deposition method of the sacrificial layer M4 is chemical vapor deposition (CVD).

[0098] Further, as shown in FIGS. 16-17, a trench T1 is formed between the positions corresponding to the positions of the word lines by a patterning process, i.e., the trench T1 is formed along the first direction, and the trench T1 intersects the bit lines. It can be understood that the patterning process is similar to the aforementioned patterning process, and the trench T1 is formed by photoresist patterning etching, which will not be repeated here. Optionally, the method of etching the trench T1 is dry etching.

[0099] As shown in FIGS. 18-19, the sacrificial layer M2 is removed to form a cavity R1. The cavity R1 is formed below the sacrificial layer M3 and between the channel structures. Optionally, the method of removing the sacrificial layer M2 is wet etching, and the etching liquid is brought into contact with the sacrificial layer M2 through the trench T1 and reacts with the sacrificial layer M2 to remove it. Optionally, the etching rate of the etching liquid for the sacrificial layer M2 is higher than the etching rate of the etching liquid for the dielectric layer M1, the oxide semiconductor layer, the bit lines, the sacrificial layer M3, and the sacrificial layer M4.

[0100] As shown in FIGS. 20-21, a word line material layer Wl is formed in the cavities Rl. Optionally, forming the word line material layer Wl includes post-deposition polishing. It is understood that a gate insulating layer (not shown) is formed in the cavities Rl and on the surface of the substrate before forming the word line material layer Wl. In particular, the material of the word line material layer Wl can include metal, metal nitride, metal oxide, metal silicide, conductive carbon, and combinations thereof; such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), titanium nitride (TiN), titanium aluminum nitride (TiAlN), titanium carbon nitride (TiCN), tantalum (Ta), tantalum nitride (TaN), tantalum aluminum nitride (TaAlN), tantalum carbon nitride (TaCN), ruthenium (Ru), platinum (Pt), or combinations thereof, or non-metallic materials such as polysilicon, gallium indium tin oxide, indium tin oxide, or combinations thereof. Preferably, the material of the word line material layer Wl is titanium nitride.

[0101] Optionally, the deposition process of the word line material layer Wl can be selected from physical vapor deposition (PVD) method, atomic layer deposition (ALD) method, pulsed laser deposition (PLD) method, chemical vapor deposition (CVD), vacuum evaporation, furnace tube deposition, or damascene process, etc. Preferably, the deposition process of the word line material layer Wl is atomic layer deposition (ALD) method.

[0102] Optionally, the material of the gate insulating layer is formed of or includes at least one of hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. The gate insulating layer is formed by atomic layer deposition (ALD) method.

[0103] Optionally, the polishing method for forming the word line material layer Wl is chemical mechanical polishing (CMP) to remove excess word line material and gate insulating material, and to expose the sacrificial layer M4.

[0104] Further, as shown in FIGS. 22-23, a trench T2 is formed in the substrate having the word line material layer Wl, and the trench T2 is substantially aligned with the trench Tl. In particular, an anisotropic etching process is performed on the substrate having the word line material layer Wl. Optionally, an anisotropic etching process having a higher selectivity for the word line material layer Wl relative to the sacrificial layer M4 is selected to remove a portion of the word line material layer Wl to form the trench T2. The remaining word line material layer Wl forms a word line.

[0105] Further, as shown in FIGS. 24-25, a dielectric layer M5 is formed in the trench T2, and an anisotropic etching is performed on the substrate with the dielectric layer M5 to remove the sacrificial layer M4 and expose the sacrificial layer M3 and the upper surface of the channel structure, and the remaining sacrificial layer M3 forms the first spacer layer. Specifically, the formation of the dielectric layer M5 includes depositing a material layer of the dielectric layer M5, and grinding to remove the excess material layer of the dielectric layer M5 and expose the sacrificial layer M4, and the dielectric layer M5 is formed, and the upper surface of the dielectric layer M5 is higher than the first spacer layer. Optionally, the material layer of the dielectric layer M5 includes a dielectric material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.

[0106] Optionally, the method of forming the material layer of the dielectric layer M5 is selected from physical vapor deposition (PVD) method, atomic layer deposition (ALD) method, pulsed laser deposition (PLD) method, chemical vapor deposition (CVD), vacuum evaporation, furnace tube deposition, etc.

[0107] Optionally, the planarization of the material layer of the dielectric layer M5 can be achieved by chemical mechanical grinding (CMP).

[0108] Optionally, the method of removing the sacrificial layer M4 includes anisotropic etching, and it is understood that the selected anisotropic etching method has a higher etching rate for the sacrificial layer M4 than for the dielectric layer M5.

[0109] Further, as shown in FIGS. 26-27, a first electrode is formed on the substrate with the first spacer layer. Specifically, a first electrode material layer is first deposited on the substrate with the first spacer layer, and the first electrode material layer is ground to remove the excess material and form a first electrode layer and expose the dielectric layer M5, and the first electrode layer is patterned by a patterning process and expose the first spacer layer, and a first electrode 400 is formed.

[0110] Optionally, the material of the first electrode material layer is selected from metal, metal nitride, metal oxide, metal silicide, conductive carbon, and combinations thereof; such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), titanium nitride (TiN), titanium aluminum nitride (TiAlN), titanium carbonitride (TiCN), tantalum (Ta), tantalum nitride (TaN), tantalum aluminum nitride (TaAlN), tantalum carbonitride (TaCN), ruthenium (Ru), platinum (Pt), or combinations thereof, or polycrystalline silicon, gallium indium tin oxide, indium tin oxide, and other non-metallic materials or combinations thereof. Preferably, the material of the first electrode material layer is titanium nitride.

[0111] Optionally, the deposition process of the first electrode material layer can be selected from physical vapor deposition (PVD) method, atomic layer deposition (ALD) method, pulsed laser deposition (PLD) method, chemical vapor deposition (CVD), vacuum evaporation, furnace tube deposition, or damascene process, etc.

[0112] Optionally, the grinding of the first electrode material layer can be achieved by chemical mechanical grinding (CMP).

[0113] Optionally, the patterning of the first electrode layer is achieved by a patterning process, which is similar to the patterning process described above. After the photoresist is patterned, etching is performed. Here, the etching process is not repeated. It can be understood that the etching process can be selected from anisotropic etching or isotropic etching, and an etching method with an etching rate greater than the etching rate of the dielectric layer M5 and the first spacer layer is selected for the first electrode material layer, so as to retain the dielectric layer M5 and the first spacer layer as much as possible.

[0114] Further, as shown in FIGS. 28-30, a second spacer block is formed on the substrate with the first electrode. Specifically, a second spacer material layer is formed on the substrate with the first electrode. The second spacer material layer is ground to expose the first electrode and the dielectric layer M5, thereby forming the second spacer block 800.

[0115] Optionally, the second spacer material layer is selected from one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride. Preferably, the second spacer material layer is the same as the material of the sacrificial layer M4, which is silicon nitride or silicon oxycarbonitride. Optionally, the deposition method of the second spacer material layer is selected from physical vapor deposition (PVD) method, atomic layer deposition (ALD) method, pulsed laser deposition (PLD) method, chemical vapor deposition (CVD), or vacuum evaporation. Preferably, the deposition method of the second spacer material layer is chemical vapor deposition (CVD).

[0116] Optionally, the grinding of the second spacer material layer can be achieved by chemical mechanical grinding (CMP).

[0117] In some embodiments, the channel structure with the filling material and the oxide semiconductor layer disposed on the outer surface of the filling material can control the thickness of the oxide semiconductor layer by controlling the deposition process of the first oxide semiconductor material layer and the second oxide semiconductor material layer, thereby adjusting the performance of the transistor of the final structure.

[0118] In some embodiments, the channel structure with the filling material and the oxide semiconductor layer disposed on the outer surface of the filling material has a larger contact area on the bottom surface and the top surface, and thus is more conducive to improving the yield of the product and improving the reliability of the product.

[0119] In some embodiments, the channel structure with the filling material and the oxide semiconductor layer disposed on the outer surface of the filling material is easy to control the thickness of the oxide semiconductor layer, and has a larger contact surface for connecting the electrode, thereby ensuring the switching performance of the transistor and the reliability of the electrical connection.

[0120] In some embodiments, forming a larger first electrode on the channel structure can improve the fault tolerance rate of alignment with the storage node, expand the process window, and thus improve product yield.

[0121] In some embodiments, ion doping the upper and / or lower surfaces of the channel structure can reduce contact resistance, reduce product power consumption, and improve product reliability.

[0122] In some embodiments, providing a first spacing layer between the channel structure and the first electrode can improve product reliability and prevent leakage.

[0123] In some embodiments, providing a second spacing block between the first electrodes can flatten the substrate surface, facilitate subsequent process manufacturing, and also serve as an insulating function between the first electrodes to prevent leakage.

[0124] The various semiconductor devices shown in the specific embodiments can be used in electronic devices with storage functions. The electronic device can be a terminal device, such as a mobile phone, a tablet computer, a smart bracelet, or a personal computer (PC), a server, a workstation, etc. The storage function in the electronic device can be implemented by a dynamic random access memory (DRAM), a ferroelectric random access memory (FRAM), a phase change memory (PCM), a magnetic random access memory (MRAM), or a resistive random access memory (RRAM).

[0125] The above merely provides a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A semiconductor device (10), characterized in that, include: Substrate (100); A channel structure (500) is disposed on the substrate along a first direction (D1); Bit line (200), the bit line is disposed between the channel structure and the substrate and is electrically connected to the channel structure, the bit line extends along a second direction (D2); A character line (300) is disposed on at least one side of the channel structure and extends in a third direction (D3); The first direction intersects the substrate, the second direction is parallel to the substrate, and the third direction is parallel to the substrate and intersects the second direction; The channel structure includes a filling material (520) and an oxide semiconductor layer (510) disposed on the outer surface of the filling material.

2. The semiconductor device according to claim 1, characterized in that, The material of the oxide semiconductor layer is selected from one or more of indium gallium zinc oxide, zinc oxide, or indium zinc oxide.

3. The semiconductor device according to claim 1, characterized in that, The filler material is silicon dioxide or aluminum oxide.

4. The semiconductor device according to claim 1, characterized in that, The letter lines surround the channel structure.

5. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes a memory node (600) disposed on the channel structure and electrically connected to the channel structure.

6. The semiconductor device according to claim 5, characterized in that, The storage node includes one or more of the following: capacitor, magnetoresistive storage, phase change storage, and ferroelectric storage.

7. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes a first electrode (400) disposed on the channel structure; wherein, when projected onto the substrate along the first direction, the projected area of ​​the first electrode is larger than the projected area of ​​the channel structure.

8. The semiconductor device according to claim 7, characterized in that, The semiconductor device further includes a first spacer layer (700) disposed between the first electrode and the word line.

9. The semiconductor device according to claim 8, characterized in that, The first spacer layer overlaps with the projection of the word line onto the substrate along the first direction.

10. The semiconductor device according to claim 7, characterized in that, The semiconductor device further includes a second spacer block (800), which is disposed on the same layer as the first electrode and spaced apart between the first electrodes along the third direction.

11. The semiconductor device according to claim 10, characterized in that, The projection of the second spacer block onto the substrate is along the first direction, and the projection of the second spacer block coincides with the projection of the word line in the second direction.

12. A dynamic random access memory (1000), characterized in that, include: The semiconductor device, sub-word line driver (SWD), and sensitive amplifier (SA) of any one of claims 1-11.

13. A method for fabricating a semiconductor device, characterized in that, include: Provide substrate; Bit lines extending in a second direction are formed on the substrate; A channel structure is formed along a first direction on the bit line; wherein the channel structure is formed with a filling material and an oxide semiconductor layer formed on the outer surface of the filling material; A letter line extending in a third direction is formed on at least one side of the channel structure; The first direction intersects the substrate, the second direction is parallel to the substrate, and the third direction is parallel to the substrate and intersects the second direction.

14. The method for fabricating a semiconductor device according to claim 13, characterized in that, The formation of the channel structure includes: An intermediate layer is formed on the substrate on which the bit lines are formed, a hole (V1) is formed at a corresponding position in the intermediate layer, and a first oxide semiconductor material layer (C1) is formed on the sidewall and bottom of the hole. The filling material is formed in the hole in which the oxide semiconductor layer is formed, and a second oxide semiconductor material layer (C3) is formed on the surface of the filling material; The oxide semiconductor layer is formed by a first oxide semiconductor material layer and a second oxide semiconductor material layer.

15. The method for fabricating a semiconductor device according to claim 13, characterized in that, The method for manufacturing the semiconductor device further includes: A first spacer layer is formed on the channel structure, and a first electrode is formed on the first spacer layer.

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