Semiconductor structure and preparation method therefor

Abstract

A semiconductor structure and a preparation method therefor. The semiconductor structure comprises: a substrate; a first memory cell and a second memory cell; a first bit line; and a second bit line. The first memory cell and the second memory cell are arranged in a first direction. The first memory cell comprises a first source / drain region, a first channel region, and a second source / drain region. The second memory cell comprises a third source / drain region, a second channel region, and a fourth source / drain region. The first channel region and the second channel region extend in the first direction, the first source / drain region and the second source / drain region are located on the same side of the first channel region in a second direction, and the third source / drain region and the fourth source / drain region are located on the same side of the second channel region in the second direction. The first bit line and the second bit line extend in a vertical direction, the first bit line is located on one side of the first source / drain region in the first direction and is electrically connected to the first source / drain region, and the second bit line is located on one side of the third source / drain region in the first direction and is electrically connected to the third source / drain region. The semiconductor structure above can improve the integration level of semiconductor structures.

Description

Semiconductor structure and its preparation method

[0001] Cross-references

[0002] This disclosure claims priority to Chinese invention patent application No. 202410797146.7, filed on June 19, 2024, entitled "Semiconductor Structure and Preparation Method Thereof", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0004] The development of Dynamic Random Access Memory (DRAM) pursues performance indicators such as high speed, high integration density, and low power consumption. However, with the miniaturization of semiconductor device structures, the technological barriers encountered by existing structures are becoming increasingly apparent. Therefore, developing more novel structures based on existing ones is a powerful means to overcome these technological barriers.

[0005] The emergence of three-dimensional dynamic random access memory (3D DRAM), especially 3D DRAM that includes multilayer horizontal cell (MHC), typically comprising multiple transistors stacked on a substrate, has met the above requirements.

[0006] However, the integration level of 3D DRAM still needs to be improved.

[0007] Summary of the Invention

[0008] According to a first aspect of the present disclosure, a semiconductor structure is provided, comprising: a substrate; a first memory cell and a second memory cell located on the substrate, the first memory cell and the second memory cell being arranged along a first direction, the first direction being parallel to the plane of the substrate; the first memory cell including a first source / drain region, a first channel region and a second source / drain region, the first channel region extending along the first direction, the first source / drain region and the second source / drain region being located on the same side of the first channel region along a second direction; the second memory cell including a third source / drain region, a second channel region and a fourth source / drain region, the second channel region extending along the first direction, the third source / drain region and the fourth source / drain region being located on the same side of the second channel region along the second direction; a first bit line extending along a vertical direction, the first bit line being located on one side of the first source / drain region along the first direction and electrically connected to the first source / drain region; and a second bit line extending along a vertical direction, the second bit line being located on one side of the third source / drain region along the first direction and electrically connected to the third source / drain region.

[0009] In some embodiments, the first bit line and the second bit line are mirror-symmetric about each other with respect to the center line between the first memory cell and the second memory cell; the first source-drain region, the second source-drain region, the third source-drain region and the fourth source-drain region all extend along the second direction; the first source-drain region and the third source-drain region are mirror-symmetric about each other with respect to the center line; the second source-drain region and the fourth source-drain region are mirror-symmetric about each other with respect to the center line.

[0010] In some embodiments, the first memory cell further includes: a first lightly doped region located between a first source / drain region and a first channel region, and a second lightly doped region located between a second source / drain region and a first channel region; the second memory cell further includes: a third lightly doped region located between a third source / drain region and a second channel region, and a fourth lightly doped region located between a fourth source / drain region and a second channel region; the first lightly doped region and the third lightly doped region are mirror-symmetric about each other about a center line; the second lightly doped region and the fourth lightly doped region are mirror-symmetric about each other about a center line.

[0011] In some embodiments, the first memory cell further includes: a first capacitor structure electrically connected to the second source-drain region, the first capacitor structure including a first lower electrode layer, a first capacitor dielectric layer and a first upper electrode layer; the second memory cell further includes: a second capacitor structure electrically connected to the fourth source-drain region, the second capacitor structure including a second lower electrode layer, a second capacitor dielectric layer and a second upper electrode layer.

[0012] In some embodiments, the first lower electrode layer has a first recess toward the first source / drain region and a first protrusion that contacts and connects with the second source / drain region; the second lower electrode layer has a second recess toward the third source / drain region and a second protrusion that contacts and connects with the fourth source / drain region.

[0013] In some embodiments, the semiconductor structure further includes: an isolation structure located between the first memory cell and the second memory cell, the isolation structure including a first isolation portion and a second isolation portion; the first isolation portion is located between the end of the first source / drain region along the second direction and a first recess of the first capacitor structure; the second isolation portion is located between the end of the third source / drain region along the second direction and a second recess of the second capacitor structure.

[0014] In some embodiments, along the second direction, the thickness of the first channel region decreases as the distance from the first source / drain region and the second source / drain region increases, and the thickness of the second channel region decreases as the distance from the third source / drain region and the fourth source / drain region increases.

[0015] In some embodiments, the semiconductor structure further includes a word line structure extending along a first direction; the word line structure includes a first gate portion and a second gate portion, and a word line connection portion connecting the first gate portion and the second gate portion, the word line connection portion having a first offset from the first gate portion and the second gate portion in a second direction; the first gate portion covers a first channel region, and the projection of the first gate portion on the substrate at least partially covers the projection of the first channel region on the substrate; the second gate portion covers a second channel region, and the projection of the second gate portion on the substrate at least partially covers the projection of the second channel region on the substrate.

[0016] In some embodiments, the semiconductor structure includes a first stacked structure on a substrate, the first stacked structure including multiple memory layers stacked at intervals in a vertical direction, each memory layer including a plurality of memory cell groups, each memory cell group including a first memory cell and a second memory cell, and the plurality of memory cell groups included in each memory layer are arranged along a first direction; a first bit line is electrically connected to a plurality of first source-drain regions stacked in a vertical direction; a second bit line is electrically connected to a plurality of third source-drain regions stacked in a vertical direction.

[0017] In some embodiments, the semiconductor structure further includes a second stacked structure, which is arranged along a second direction with the first stacked structure, and the second stacked structure and the first stacked structure are mirror-symmetrical about each other about the central axis of the second stacked structure and the first stacked structure.

[0018] According to a second aspect of the present disclosure, a method for fabricating a semiconductor structure is provided, comprising: providing a substrate; forming a first active structure and a second active structure on the substrate, the first active structure and the second active structure being arranged along a first direction, the first direction being parallel to the plane of the substrate; the first active structure including a first source / drain region, a first channel region and a second source / drain region, the first channel region extending along the first direction, the first source / drain region and the second source / drain region being located on the same side of the first channel region along a second direction; the second active structure including a third source / drain region, a second channel region and a fourth source / drain region, the second channel region extending along the first direction, the third source / drain region and the fourth source / drain region being located on the same side of the second channel region along the second direction; forming a first bit line and a second bit line extending in a vertical direction between the first active structure and the second active structure, the first bit line being located on one side of the first source / drain region along the first direction and electrically connected to the first source / drain region, the second bit line being located on one side of the third source / drain region along the first direction and electrically connected to the third source / drain region.

[0019] In some embodiments, forming a first active structure and a second active structure on a substrate includes: forming an initial stacked structure on the substrate, the initial stacked structure including an initial active layer and an initial sacrificial layer stacked along a vertical direction; forming a first isolation pillar and a second isolation pillar penetrating the initial stacked structure, the first isolation pillar and the second isolation pillar being arranged along a first direction, the length of the first isolation pillar along a second direction being greater than the length of the second isolation pillar along the second direction; forming a first doped trench in the first isolation pillar; and performing diffusion doping on the initial active layer exposed on both sides of the first doped trench along the first direction to form a first source / drain region, a second source / drain region, a third source / drain region, and a fourth source / drain region all extending along the second direction.

[0020] In some embodiments, both ends of the first isolation pillar extend beyond both ends of the second isolation pillar in a second direction. After forming the first isolation pillar and the second isolation pillar that penetrate the initial stacked structure, the method further includes: forming a word line trench that penetrates the initial stacked structure, the word line trench being located on the same side of the first isolation pillar and the second isolation pillar along the second direction; removing a portion of the initial sacrificial layer laterally along the word line trench to expose a portion of the initial active layer; thinning and doping the exposed portion of the initial active layer to form a first channel region and a second channel region; and forming a word line structure in the word line trench, the word line structure including a word line conductive layer and a word line dielectric layer.

[0021] In some embodiments, forming a first bit line and a second bit line extending in a vertical direction between a first active structure and a second active structure includes: forming a bit line via extending in a vertical direction between the first active structure and the second active structure, the bit line via exposing a first source / drain region and a third source / drain region; forming an initial bit line layer on the sidewall of the bit line via; forming a first opening and removing a first portion of the initial bit line layer along the first opening, the first opening being located on one side of the bit line via along a second direction; forming a second opening and removing a second portion of the initial bit line layer along the second opening, the second opening being located on the other side of the bit line via along the second direction, the retained initial bit line layer serving as the first bit line and the second bit line, the first bit line and the second bit line being mirror-symmetrical about each other with respect to the center line between the first active structure and the second active structure.

[0022] In some embodiments, the first opening is located on the side of the bit line via that is away from the first channel region and the second channel region, and after the first opening is formed and a first portion of the initial bit line layer is removed along the first opening, the method further includes: removing a portion of the initial active layer using a wet etching process to form a first void and a second void; filling the first void and the second void to form a first isolation portion and a second isolation portion, respectively, wherein the first isolation portion is located at the end of the first source / drain region along the second direction, and the second isolation portion is located at the end of the third source / drain region along the second direction; the method for fabricating the semiconductor structure further includes: using the first isolation portion and the second isolation portion as a barrier layer, removing a portion of the initial active layer between the second isolation pillars using a wet etching process to expose the second source / drain region and the fourth source / drain region; forming a first lower electrode layer and a second lower electrode layer, wherein the first lower electrode layer has a first recess that is in contact with the first isolation portion and a first protrusion that is in contact with the second source / drain region, and the second lower electrode layer has a second recess that is in contact with the second isolation portion and a second protrusion that is in contact with the fourth source / drain region.

[0023] In this embodiment, since the first and second source / drain regions are located on the same side of the first channel region, and the third and fourth source / drain regions are located on the same side of the second channel region, a first bit line located on one side of the first source / drain region along the first direction and a second bit line located on one side of the third source / drain region along the first direction can be provided. By adopting this novel memory cell layout, the ends of the first and third source / drain regions away from the channel region have more space for forming a capacitor structure. This space can be used to increase the capacitance of the capacitor structure, and it can also be used to compress the length of the capacitor structure in the second direction, thereby improving the overall integration of the semiconductor structure. Attached Figure Description

[0024] Figure 1 is a partial schematic diagram of a semiconductor structure according to an exemplary embodiment;

[0025] Figures 2A, 2B, and 2C are schematic horizontal cross-sectional views of semiconductor structures according to three exemplary embodiments;

[0026] Figure 3 is a three-dimensional structural schematic diagram of a semiconductor structure according to an exemplary embodiment;

[0027] Figures 4-15 are schematic diagrams illustrating a semiconductor structure fabrication process according to an exemplary embodiment, wherein Figures 4, 5, 6, 7A, 8A and 9A are three-dimensional structural schematic diagrams during the semiconductor structure fabrication process, and Figures 7B, 8B, 9B and 10-15 are horizontal cross-sectional schematic diagrams during the semiconductor structure fabrication process.

[0028] Figure 16 is a flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0029] Figure reference numerals: 10 / 10A / 10B / 10C - Semiconductor structure; 100 - Substrate; 101 - Initial active layer; 101L - Storage layer; 102 - Initial sacrificial layer; 102L - Spacer layer; 103 - First isolation pillar; 104 - Second isolation pillar; 111 - First source / drain region; 112 - Second source / drain region; 121 - Third source / drain region; 122 - Fourth source / drain region; 111a - First lightly doped region; 112a - Second lightly doped region; 121a - Third lightly doped region; 12 2a - Fourth lightly doped region; 113 - First channel region; 123 - Second channel region; 200 - Capacitor trench; 210 - First capacitor structure; 220 - Second capacitor structure; 211 - First lower electrode layer; 221 - Second lower electrode layer; 211a - First recess; 221a - Second recess; 211b - First convex portion; 221b - Second convex portion; 212 - First capacitor dielectric layer; 222 - Second capacitor dielectric layer; 213 - First upper electrode layer; 223 - Second upper electrode layer; 311 g - First gap; 321g - Second gap; 311 - First isolation section; 321 - Second isolation section; STA' - Initial stacked structure; STA1 - First stacked structure; STA2 - Second stacked structure; ISO - Isolation structure; MC1 - First memory cell; MC2 - Second memory cell; MCG - Memory cell group; AA1 - First active structure; AA2 - Second active structure; WT - Word line trench; WL - Word line structure; WLa - First gate section; WLb - Second gate section WLc - Word line connector; BT - Bit line slot; BL1 - First bit line; BL2 - Second bit line; BL' - Initial bit line layer; BLa - First part of the initial bit line layer; BLb - Second part of the initial bit line layer; GND - Grounding plug; OP1 - First opening; OP2 - Second opening; OP3 - Third opening; X - First direction; Y - Second direction; Z - Vertical direction; CL - Center line; CC1 - First unit center line; CC2 - Second unit center line; HL - Center axis. Detailed Implementation

[0030] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of this disclosure and to fully convey the scope of this disclosure to those skilled in the art.

[0031] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.

[0032] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.

[0033] In the embodiments of this disclosure, the terms "first," "second," "third," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0034] In embodiments of this disclosure, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of the continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.

[0035] It should be noted that the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict.

[0036] Figure 1 is a partial schematic diagram of a semiconductor structure 10 according to an exemplary embodiment; Figure 2A is a horizontal cross-sectional schematic diagram of semiconductor structure 10A according to an exemplary embodiment; Figure 2B is a horizontal cross-sectional schematic diagram of semiconductor structure 10B according to an exemplary embodiment; Figure 2C is a horizontal cross-sectional schematic diagram of semiconductor structure 10C according to an exemplary embodiment; Figure 3 is a three-dimensional structural schematic diagram of a semiconductor structure 10 according to an exemplary embodiment; Figures 4-15 are schematic diagrams of a semiconductor structure fabrication process according to an exemplary embodiment, wherein Figures 4, 5, 6, 7A, 8A, and 9A are three-dimensional structural schematic diagrams during the semiconductor structure fabrication process, and Figures 7B, 8B, 9B, and 10-15 are horizontal cross-sectional schematic diagrams during the semiconductor structure fabrication process; Figure 16 is a flowchart of a method for fabricating a semiconductor structure 100 according to an exemplary embodiment. The semiconductor structure 100 and its fabrication process will be described below with reference to Figures 1 to 16.

[0037] Referring to Figures 1 and 3, the semiconductor structure 10 includes: a substrate 100; a first memory cell MC1 and a second memory cell MC2 located on the substrate 100, the first memory cell MC1 and the second memory cell MC2 being arranged along a first direction X, the first direction X being parallel to the plane of the substrate 100; the first memory cell MC1 includes a first source / drain region 111, a first channel region 113 and a second source / drain region 112, the first channel region 113 extending along the first direction X, the first source / drain region 111 and the second source / drain region 112 being located on the same side of the first channel region 113 along a second direction Y; the second memory cell includes... The third source / drain region 121, the second channel region 123, and the fourth source / drain region 122 are located on the same side of the second channel region 123 along the second direction Y; the first bit line BL1 extends along the vertical direction Z and is located on one side of the first source / drain region 111 along the first direction and is electrically connected to the first source / drain region 111; the second bit line BL2 extends along the vertical direction Z and is located on one side of the third source / drain region 121 along the first direction and is electrically connected to the third source / drain region 121.

[0038] It is understood that in this example, the first direction X and the second direction Y are horizontal directions parallel to the plane where the substrate 100 is located, and the first direction X intersects the second direction Y. For example, the first direction X can be perpendicular to the second direction Y. The vertical direction Z is the direction that intersects the plane where the substrate 110 is located. For example, the vertical direction Z is perpendicular to the plane where the substrate 100 is located.

[0039] Taking dynamic random access memory as an example, by setting the channel region on the same side of the source and drain regions, it is beneficial to the channel doping of transistors and the formation of horizontally extended word line structures. By setting the bit lines on one side of the source and drain regions along the first direction, the spacing between the bit lines and the capacitor structure can be increased, the coupling between the bit lines and the capacitor structure can be reduced, and by providing more space for forming the capacitor structure, the capacitance of the capacitor structure can be effectively improved.

[0040] In some embodiments, the substrate 100 may include silicon, such as monocrystalline silicon, polycrystalline silicon, or amorphous silicon. In some embodiments, the material of the substrate 100 may include germanium (Ge), silicon germanide (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and / or indium phosphide (InP). The active structures in the semiconductor structure 10, such as the first source / drain region 111, the first channel region 113, the second source / drain region 112, the third source / drain region 121, the second channel region 123, and the fourth source / drain region 122, may be made of monocrystalline silicon, polycrystalline silicon, germanium, silicon-germanium, or oxide semiconductor materials (e.g., zinc tin oxide (ZnO)). x Sn yO, commonly known as "ZTO"), indium zinc oxide (In x Zn y O, commonly known as "IZO"), zinc oxide (Zn) x O), Indium gallium zinc oxide (In x Ga y Zn z O, commonly known as "IGZO"), indium gallium silicon oxide (In x Ga y Si z O (commonly known as "IGSO") and one or more other similar materials. The active structure can be doped with dopant ions. For example, the first source / drain region 111, the second source / drain region 112, the third source / drain region 121, and the fourth source / drain region 122 can be doped with N-type dopant ions, and the first channel region 113 and the second channel region 123 can be doped with P-type dopant ions. Among them, the P-type dopant ions can include any one of boron ions, aluminum ions, gallium ions, or indium ions, and the N-type dopant ions can include any one of phosphorus ions, bismuth ions, antimony ions, or arsenic ions.

[0041] In some embodiments, the first bit line BL1 and the second bit line BL2 are mirror-symmetric about each other with respect to the center line CL between the first memory cell and the second memory cell; the first source-drain region 111, the second source-drain region 112, the third source-drain region 121 and the fourth source-drain region 122 all extend along the second direction Y; the first source-drain region 111 and the third source-drain region 121 are mirror-symmetric about each other with respect to the center line CL; the second source-drain region 112 and the fourth source-drain region 122 are mirror-symmetric about each other with respect to the center line CL.

[0042] In some embodiments, the first source / drain region 111 and the second source / drain region 112 are mirror-symmetric about each other with respect to the first cell center line CC1 of the first source / drain region 111 and the second source / drain region 112; the third source / drain region 121 and the fourth source / drain region 122 are mirror-symmetric about each other with respect to the second cell center line CC2 of the third source / drain region 121 and the fourth source / drain region 122.

[0043] It is understandable that mirror symmetry can also be called mirror image symmetry or axial symmetry. As used herein, the term "mirror symmetry" with respect to a given parameter, property, or condition means, and is included within, the degree to which a given parameter, property, or condition satisfies variance (e.g., within acceptable manufacturing tolerances) as would be understood by one of ordinary skill in the art. For example, the first line BL1 and the second line BL2 being mirror symmetric about the center line CL means that the first line BL1 and the second line BL2 have similar lengths in the second direction Y, similar widths in the first direction X, and similar distances to the center line CL, and that their projections in the first direction X almost overlap. For example, if the width of the first line BL1 differs from the width of the second line BL2 by less than 1 nm, the first line BL1 and the second line BL2 can also be considered mirror symmetric about the center line CL.

[0044] Bit lines, including a first bit line BL1 and a second bit line BL2, can be made of conductive materials. The conductive materials can include one or more of the following: metals (e.g., tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), cobalt (Co), nickel (Ni)); alloys (e.g., Co-based alloys, Ti-based alloys, Co and Ni-based alloys, Fe and Co-based alloys); materials containing conductive metals (e.g., conductive metal nitrides, conductive metal silicides, conductive metal carbides, conductive metal oxides); and conductive doped semiconductor materials (e.g., conductive doped polysilicon, conductive doped silicon-germanium). The bit lines can be single-layer or multi-layer structures. For example, the bit lines can be a multi-layer structure composed of a conductive metal silicide layer, a titanium nitride layer, and a tungsten layer, wherein the conductive metal silicide layer is configured to directly contact and connect with the source / drain regions to reduce the contact resistance between the bit lines and the source / drain regions.

[0045] The active structure formed by the first source / drain region 111, the first channel region 113, and the second source / drain region 112, and the active structure formed by the third source / drain region 121, the second channel region 123, and the fourth source / drain region 122, are U-shaped when projected onto the substrate 100. The source / drain regions, including the first source / drain region 111, the second source / drain region 112, the third source / drain region 121, and the fourth source / drain region 122, can all be formed in the same process, thus having similar or identical source / drain doping concentrations and concentration distributions.

[0046] Understandably, due to the influence of actual manufacturing processes, the horizontal cross-sections of the first source / drain region 111 and the third source / drain region 121 can be curved in opposite directions, while the horizontal cross-sections of the second source / drain region 112 and the fourth source / drain region 122 can be curved in opposite directions. The first source / drain region 111 and the third source / drain region 121 can be curved in opposite directions, and the third source / drain region 121 and the fourth source / drain region 122 can be curved in opposite directions. A curved shape refers to a shape with arc-shaped sidewalls that taper inwards from both ends towards the center, and the dimensions of the shape can gradually decrease from the center to both ends. A curved shape that tapers in opposite directions means that the inward direction of the sidewalls of one shape is consistent with the direction towards the other shape, while a curved shape that tapers in opposite directions means that the inward direction of the sidewalls of one shape is opposite to the direction towards the other shape.

[0047] In some embodiments, the first memory cell MC1 and the second memory cell MC2 can be mirror-symmetrical about each other with respect to the center line CL between the first memory cell MC1 and the second memory cell MC2. The first memory cell MC1 and the second memory cell MC2 will have the same device characteristics, thereby improving the structural consistency of the semiconductor structure and enhancing the stability of the semiconductor structure performance.

[0048] In some embodiments, the horizontal cross-sections of the first bit line BL1 and the second bit line BL2 may be trapezoidal. Along the direction from the first bit line BL1 to the second bit line BL2, the size of the first bit line BL1 in the second direction Y gradually decreases, and along the direction from the second bit line BL2 to the first bit line BL1, the size of the second bit line BL2 in the second direction Y gradually decreases.

[0049] In some other embodiments, the first bit line BL1 and the second bit line BL2 can be staggered relative to each other in the second direction Y, that is, the projections of the first bit line BL1 and the second bit line BL2 in the first direction X only partially overlap or do not overlap, thereby reducing the parasitic capacitance between adjacent first bit lines BL1 and second bit lines BL2 and reducing the coupling between adjacent memory cells. The first bit line BL1 and the second bit line BL2 can also be axially symmetrical about each other about the center line in the vertical direction.

[0050] In some embodiments, referring to Figures 1 and 3, the first memory cell MC1 further includes: a first lightly doped region 111a located between the first source / drain region 111 and the first channel region 113, and a second lightly doped region 112a located between the second source / drain region 112 and the first channel region 113; the second memory cell MC2 further includes: a third lightly doped region 121a located between the third source / drain region 121 and the second channel region 123, and a fourth lightly doped region 122a located between the fourth source / drain region 122 and the second channel region 123; the first lightly doped region 111a and the third lightly doped region 121a are mirror-symmetric about the center line CL; the second lightly doped region 112a and the fourth lightly doped region 122a are mirror-symmetric about the center line CL.

[0051] The lightly doped regions, including a first lightly doped region 111a, a second lightly doped region 112a, a third lightly doped region 121a, and a fourth lightly doped region 122a, can all be formed in the same process, thus having similar or identical source / drain doping concentrations and distributions. The doping concentrations of the first lightly doped region 111a, the second lightly doped region 112a, the third lightly doped region 121a, and the fourth lightly doped region 122a are all lower than the doping concentrations of the first source / drain region 111, the second source / drain region 112, the third source / drain region 121, and the fourth source / drain region 122, but higher than the doping concentrations of the first channel region 113 and the second channel region 123. For example, the doping concentration range of the channel region can be 1E16cm. -3 Up to 1E18cm -3 The doping concentration range of the source and drain regions can be 1E20cm. -3 ~1E22cm -3 The doping concentration range of the lightly doped region can be 1E18cm. -3 ~1E20cm -3 By placing a lightly doped region between the channel region and the source / drain region, the drain electric field of the transistor can be weakened, thereby improving the hot electron degradation effect.

[0052] In some embodiments, the channel region includes a first channel region 113 and a second channel region 123, having a channel horizontal portion extending along a first direction X and a channel protrusion located on the same side of the channel horizontal portion facing the source / drain region. A first lightly doped region 111a and a second lightly doped region 112a are respectively connected to the two channel protrusions of the first channel region 113, and a third lightly doped region 121a and a fourth lightly doped region 122a are respectively connected to the two channel protrusions of the second channel region 123.

[0053] In some embodiments, the channel region includes a first channel region 113 and a second channel region 123, having only a horizontal channel portion extending along a first direction X. A first lightly doped region 111a and a second lightly doped region 112a are respectively connected to both ends of the first channel region 113, and a third lightly doped region 121a and a fourth lightly doped region 122a are respectively connected to both ends of the second channel region 123.

[0054] In some embodiments, referring to Figures 1 and 3, the first memory cell MC1 further includes: a first capacitor structure 210, which is electrically connected to the second source / drain region 112, and includes a first lower electrode layer 211, a first dielectric layer 212, and a first upper electrode layer 213; the second memory cell MC2 further includes: a second capacitor structure 220, which is electrically connected to the fourth source / drain region 122, and includes a second lower electrode layer 221, a second dielectric layer 222, and a second upper electrode layer 223. The capacitor structure, including the first capacitor structure 210 and the second capacitor structure 220, can be a cylindrical double-sided capacitor structure, and the dielectric layer can cover both sides of the lower electrode layer to increase the capacitance of the capacitor structure.

[0055] Since the first bit line BL1 and the second bit line BL2 extending in the vertical direction Z are located on one side of the first source / drain region 111 and the third source / drain region 121 along the first direction X, rather than at the ends of the first source / drain region 111 and the third source / drain region 121 away from the channel region, the ends of the first source / drain region 111 and the third source / drain region 121 away from the channel region have more space to form a capacitor structure. This space can be used to increase the capacitance of the capacitor structure, or to compress the length of the capacitor structure in the second direction Y, thereby improving the overall integration of the semiconductor structure.

[0056] The first capacitor dielectric layer 212 and the second capacitor dielectric layer 222 can be integrally formed. The first upper electrode layer 213 and the second upper electrode layer 223 can be integrally formed. The electrode layers, including the first lower electrode layer 211, the first upper electrode layer 213, the second lower electrode layer 221, and the second upper electrode layer 223, can be made of conductive materials. The capacitor dielectric layers, including the first capacitor dielectric layer 212 and the second capacitor dielectric layer 222, can be made of high dielectric constant materials. High dielectric constant materials can include one or more of the following: hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, etc. The first upper electrode layer 213 and the second upper electrode layer 223 can be an integral upper electrode layer. The upper electrode layer can be a multilayer structure. For example, it can include a first conductive layer that conformally covers the first capacitor dielectric layer 212 and the second capacitor dielectric layer 222 and a second conductive layer that fills the space between the first conductive layers. The first conductive layer can be a titanium nitride layer, and the second conductive layer can be a tungsten layer, a conductive doped polycrystalline silicon layer, or a conductive doped germanium silicon layer.

[0057] In some embodiments, as shown in FIG1, the first lower electrode layer 211 has a first recess 211a facing the first source / drain region 111 and a first protrusion 211b that is in contact with the second source / drain region 112; the second lower electrode layer 221 has a second recess 221a facing the third source / drain region 121 and a second protrusion 221b that is in contact with the fourth source / drain region 122.

[0058] The first recess 211a is the portion of the first lower electrode layer 211 facing the first source / drain region 111, the first convex portion 211b is the portion of the first lower electrode layer 211 facing the second source / drain region 112, the second recess 221a is the portion of the second lower electrode layer 221 facing the third source / drain region 121, and the second convex portion 221b is the portion of the second lower electrode layer 221 facing the fourth source / drain region 122. Referring to FIG1, the first lower electrode layer 211 also includes a portion connecting the first recess 211a and the first convex portion 211b and a portion extending along the second direction Y, and the second lower electrode layer 221 also includes a portion connecting the second recess 221a and the second convex portion 221b and a portion extending along the second direction Y. The first lower electrode layer 211 and the second lower electrode layer 221 are insulated from each other and can be mirror-symmetrical about the centerline CL.

[0059] In some embodiments, referring to Figures 1 and 3, the semiconductor structure further includes an isolation structure ISO located between the first memory cell MC1 and the second memory cell MC2. The isolation structure includes a first isolation portion 311 and a second isolation portion 321. The first isolation portion 311 is located between the end of the first source / drain region 111 along the second direction Y and the first recess 211a of the first capacitor structure 210. The second isolation portion 321 is located between the end of the third source / drain region 121 along the second direction Y and the second recess 221a of the second capacitor structure 220.

[0060] The isolation structure ISO can be an insulating material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon oxynitride, or other low dielectric constant materials. By providing a first isolation portion 311 between the first lower electrode layer 211 of the first capacitor structure 210 and the first source / drain region 111, and a second isolation portion 321 between the second lower electrode layer 221 of the second capacitor structure 220 and the third source / drain region 121, the coupling between the first capacitor structure 210 and the first source / drain region 111 is reduced, and the coupling between the second capacitor structure 220 and the third source / drain region 121 is also reduced, thereby reducing RC delay and improving the efficiency of the semiconductor structure.

[0061] In some embodiments, referring to FIG3, along the second direction Y, the thickness of the first channel region 113 decreases as the distance from the first source / drain region 111 and the second source / drain region 112 increases, and the thickness of the second channel region 123 decreases as the distance from the third source / drain region 121 and the fourth source / drain region 122 increases. The first channel region 113 and the second channel region 123 are trapezoidal or conical in the cross-section formed by the second direction Y and the vertical direction Z. The first channel region 113 and the second channel region 123 are thinned relative to other parts of the active structure, such that the surfaces of the first channel region 113 and the second channel region 123 intersecting the vertical direction Z are not parallel to the plane containing the substrate 100.

[0062] In some embodiments, referring to Figures 1 and 3, the semiconductor structure 10 further includes a word line structure WL extending along a first direction X; the word line structure WL includes a first gate portion WLa and a second gate portion WLb, and a word line connection portion WLc connecting the first gate portion WLa and the second gate portion WLb; the first gate portion WLa covers the first channel region 113, and the projection of the first gate portion WLa on the substrate at least partially covers the projection of the first channel region 113 on the substrate; the second gate portion WLb covers the second channel region 123, and the projection of the second gate portion WLb on the substrate at least partially covers the projection of the second channel region 123 on the substrate.

[0063] It is understandable that the word line structure WL covers the end face of the channel region parallel to the vertical direction Z and at least part of the top and bottom surfaces intersecting the vertical direction Z, forming a horizontally arranged fin field-effect transistor. By increasing the contact area between the word line structure WL and the channel region, the gate's control over the channel region can be enhanced, effectively mitigating the short-channel effect caused by high integration and reducing leakage current.

[0064] In some embodiments, the gate portion includes a first gate portion WLa and a second gate portion WLb, having a gate horizontal portion extending along a first direction X and a gate protrusion located on the same side of the gate horizontal portion facing the source / drain region, the gate protrusion covering the channel protrusion of the channel region.

[0065] The word line structure WL includes a word line conductive layer 401 and a word line dielectric layer 402. The word line dielectric layer 402 can conformally cover the first channel region 113 and the second channel region 123, as well as a portion of the isolation structure ISO between the first channel region 113 and the second channel region 123. The word line dielectric layer 402 can contact the first lightly doped region 111a, the second lightly doped region 112a, the third lightly doped region 121a, and the fourth lightly doped region 122a.

[0066] In some embodiments, referring to Figures 1 and 3, the word line connection portion WLc is located at the end face of the isolation structure ISO along the second direction Y. The word line connection portion WLc has a first offset d1 with the first gate portion WLa and the second gate portion WLb in the second direction. The first offset d1 can be smaller than the width of the first gate portion WLa and the second gate portion WLb along the second direction Y. The projection of the word line structure WL on the substrate 100 is wavy, and the word line connection portion WLc protrudes away from the active structure, thereby increasing the distance between the word line connection portion WLc and the first bit line BL1 and the second bit line BL2, and reducing the coupling between the word line structure WL and the bit lines.

[0067] In some embodiments, referring to FIG1, the semiconductor structure 10 further includes a ground plug GND, which can extend in the vertical direction Z and is located on one side of the channel region along the second direction Y. For example, it can be located in and through the second isolation pillar 104 between the source and drain regions. With a U-shaped active structure, it is easy to form the ground plug GND located in the third opening OP3, and the ground plug GND does not affect the arrangement of the word line structure WL and bit lines, efficiently utilizing the space in the semiconductor structure 10. The ground plug GND is made of a conductive material, such as polysilicon. The ground plug GND is used to connect to the ground voltage. The ground plug GND can be in direct contact with the first channel region 113 and the second channel region 123, and is used to draw out the charge accumulated in the channel region to improve the floating body effect of the transistor.

[0068] In some embodiments, referring to FIG2A, FIG2B, FIG2C and FIG3, the semiconductor structure 10 includes a first stacked structure STA1 on a substrate 100. The first stacked structure STA1 includes multiple memory layers 101L stacked at intervals in the vertical direction Z. Each memory layer 101L includes a plurality of memory cell groups MCG. Each memory cell group MCG includes a first memory cell MC1 and a second memory cell MC2. The plurality of memory cell groups MCG included in each memory layer 101L are arranged along the first direction X. The first bit line BL1 is electrically connected to a plurality of first source-drain regions 111 stacked in the vertical direction Y. The second bit line BL2 is electrically connected to a plurality of third source-drain regions 121 stacked in the vertical direction Y.

[0069] It is understood that the semiconductor structure 10 is a three-dimensional structure, with memory cells arranged in an array at least in the vertical direction Z and the first direction X. This three-dimensional structure, with cells arranged horizontally and stacked vertically, improves the integration density of the semiconductor structure. Memory cells located in the same layer can form a memory layer 101L. The memory cells in each memory layer 101L can be divided into multiple memory cell groups (MCGs) arranged along the first direction X, and each MCG is connected to the others in the first direction X. The memory layers 101L are stacked at intervals in the vertical direction Z, and spacer layers 102L can be provided between the memory layers 101L. The spacer layers 102L include insulating material to isolate the memory cells stacked in the vertical direction Z.

[0070] In some embodiments, referring to Figures 2A, 2B, 2C, and 3, the semiconductor structure 10 further includes a second stacked structure STA2, which is arranged along the second direction Y with the first stacked structure STA1. An insulating material may be filled between the first stacked structure STA1 and the second stacked structure STA2 to prevent short circuits between the two stacked structures.

[0071] In some embodiments, referring to FIG2A, the second stacked structure STA2 and the first stacked structure STA1 are mirror-symmetrical about each other about their central axes HL. The word line structures in the two stacked structures can be mirror-symmetrical about their central axes HL and can be formed in the same process step.

[0072] In some embodiments, referring to Figures 2B and 2C, the second stacked structure STA2 and the first stacked structure STA1 are mirror images of each other about their central axes HL. Mirror image misalignment means that in a horizontal cross-section formed by the first direction X and the second direction Y, the shape of the second stacked structure STA2 is a mirror image of the shape of the first stacked structure STA1 along the central axis HL, translated by a predetermined distance along the first direction X. In Figure 2B, the shape of the second stacked structure STA2 is a mirror image of the shape of the first stacked structure STA1 along the central axis HL, translated by one cell size along the first direction X. The cell size refers to the width of the first memory cell MC1 or the second memory cell MC2 in the first direction X. The word line structures in the two stacked structures can be mirror images of each other about their central axes HL. In Figure 2C, the shape of the second stacked structure STA2 is a mirror image of the shape of the first stacked structure STA1 along the central axis HL, translated by 0.5 or 1.5 times the cell size along the first direction X. The cell size refers to the width of the first memory cell MC1 or the second memory cell MC2 in the first direction X.

[0073] This disclosure also provides a method for fabricating a semiconductor structure. The method for fabricating the semiconductor structure provided by this disclosure will be described in detail below with reference to Figures 4 to 16. Referring to Figure 16, the fabrication method includes at least the following steps:

[0074] S210: Provides substrate 100;

[0075] S220: A first active structure AA1 and a second active structure AA2 are formed on a substrate. The first active structure AA1 and the second active structure AA2 are arranged along a first direction X, which is parallel to the plane of the substrate 100. The first active structure AA1 includes a first source / drain region 111, a first channel region 113, and a second source / drain region 112. The first channel region 113 extends along the first direction X, and the first source / drain region 111 and the second source / drain region 112 are located on the same side of the first channel region 113 along the second direction Y. The second active structure AA2 includes a third source / drain region 121, a second channel region 123, and a fourth source / drain region 122. The second channel region 123 extends along the first direction X, and the third source / drain region 121 and the fourth source / drain region 122 are located on the same side of the second channel region 123 along the second direction Y.

[0076] S230: A first bit line BL1 and a second bit line BL2 extending in the vertical direction Z are formed between the first active structure and the second active structure. The first bit line BL1 is located on one side of the first source-drain region 111 along the first direction and is electrically connected to the first source-drain region 111.

[0077] In some embodiments, forming a first active structure AA1 and a second active structure AA2 on a substrate 100 includes: forming an initial stacked structure STA' on the substrate 100, as shown in FIG4, the initial stacked structure STA' including an initial active layer 101 and an initial sacrificial layer 102 stacked along the vertical direction Z; forming a first isolation pillar 103 and a second isolation pillar 104 penetrating the initial stacked structure STA', the first isolation pillar 103 and the second isolation pillar 104 being arranged along a first direction X, the length of the first isolation pillar 103 along the second direction Y being greater than the length of the second isolation pillar 104 along the second direction Y; forming a first doped trench DT in the first isolation pillar 103, as shown in FIGS. 9A and 9B, wherein FIG. 9B is a horizontal cross-sectional view of the three-dimensional structure shown in FIG. 9A; and performing diffusion doping on the initial active layer 101 exposed on both sides of the first doped trench DT along the first direction X to form a first source / drain region 111, a second source / drain region 112, a third source / drain region 121 and a fourth source / drain region 122, all extending along the second direction Y.

[0078] The initial active layer 101 and the initial sacrificial layer 102 are made of different materials. The initial active layer 101 can be made of single-crystal silicon, polycrystalline silicon, germanium, silicon-germanium, or oxide semiconductor materials (e.g., zinc tin oxide (ZnO)). x Sn y O, commonly known as "ZTO"), indium zinc oxide (In x Zn y O, commonly known as "IZO"), zinc oxide (Zn) x O), Indium gallium zinc oxide (In x Ga y Zn z O, commonly known as "IGZO"), indium gallium silicon oxide (In x Ga y Si zO (commonly known as "IGSO") and one or more similar materials. For example, the initial active layer 101 is monocrystalline silicon, and the initial sacrificial layer 102 is silicon germanide or silicon oxide, etc. The initial active layer 101 and the initial sacrificial layer 102 can be formed alternately by epitaxial growth or deposition processes. The deposition processes can include chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma-enhanced ALD, physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), or low-pressure chemical vapor deposition (LPCVD), etc.

[0079] The first isolation pillar 103 and the second isolation pillar 104 can be a single-layer structure or a multi-layer structure. For example, they can be a multi-layer structure composed of silicon nitride and silicon oxide, wherein silicon nitride is used to improve the structural stability of the isolation pillar, and silicon oxide is used to reduce the dielectric constant of the isolation pillar.

[0080] The width of the first doped trench DT formed in the first isolation pillar 103 in the first direction X is greater than or equal to the width of the first isolation pillar 103 in the first direction X, and the sidewalls of the first doped trench DT expose the initial active layer 101 on both sides along the first direction X. Diffusion doping along the first doped trench DT can be performed using ALD doping or vapor phase doping. ALD doping involves depositing a doped material layer followed by heat treatment to diffuse dopant ions from the doped material layer into the initial active layer 101, and then removing the remaining doped material layer in the first doped trench DT. By employing diffusion doping for the source and drain regions, good consistency in the doping concentration of the source and drain regions of multiple memory cells stacked in the vertical direction Z can be ensured.

[0081] In some embodiments, a first diffusion doping process can be performed before a second diffusion doping process. The doping concentration of the first diffusion doping process is lower than that of the second diffusion doping process, and the doped region of the first diffusion doping process is larger than that of the second diffusion doping process. The first diffusion doping process forms a first lightly doped region 111a, a second lightly doped region 112a, a third lightly doped region 121a, and a fourth lightly doped region 122a. The second diffusion doping process forms a first source / drain region 111, a second source / drain region 112, a third source / drain region 121, and a fourth source / drain region 122. By forming the source / drain regions and lightly doped regions in each active structure within the same process step, the performance consistency of the active structure can be ensured. The initial lightly doped regions can be located at both ends of the source / drain regions, and the portion of the lightly doped regions located away from the channel region at the ends of the source / drain regions will be removed subsequently using a lateral etching process.

[0082] In other embodiments, a second doped trench can be formed after a first diffusion doping process is performed on the first doped trench DT. The second doped trench can be offset from the first doped trench DT in the second direction Y. A second diffusion process is performed on the second doped trench to form a lightly doped region located only at one end of the source / drain region.

[0083] In some embodiments, both ends of the first isolation post 103 extend beyond both ends of the second isolation post 104 along the second direction Y. The portion of the initial active layer 101 located between the first isolation post 103 and the second isolation post 104 is used for self-alignment to form mutually independent active structures.

[0084] In some embodiments, after forming the first isolation pillar 103 and the second isolation pillar 104 through the initial stacked structure STA', the method further includes: as shown in FIG6, forming a word line trench WT through the initial stacked structure STA', the word line trench WT being located on the same side of the first isolation pillar 103 and the second isolation pillar 104 along the second direction Y; as shown in FIG7A and 7B, removing a portion of the initial sacrificial layer 102 laterally along the word line trench WT to expose a portion of the initial active layer 101; thinning and doping the exposed portion of the initial active layer 101 to form a first channel region 113 and a second channel region 123; as shown in FIG8A and 8B, wherein FIG8B is a horizontal cross-sectional view of the three-dimensional structure schematic diagram shown in FIG8A, a word line structure WL is formed in the word line trench WT, the word line structure WL including a word line conductive layer 401 and a word line dielectric layer 402.

[0085] Referring to Figures 5, 6, and 7B, where Figure 7B is a horizontal cross-sectional view of the three-dimensional structure shown in Figure 7A, the initially formed word line trench WT may not expose the first isolation pillar 104. During the thinning process of the initial active layer 101, the size of the initial active layer 101 in the second direction Y also decreases. The word line trench WT exposes the first isolation pillar 103 and part of the top and bottom surfaces of the initial active layer 101. The word line trench WT may also expose the second isolation pillar 104, thereby forming a discrete initial active structure separated by the first isolation pillar 103. In other embodiments, the word line trench WT may also be initially formed to expose the first isolation pillar 103, ensuring that the subsequently formed active structures are isolated from each other. Doping a portion of the initial active layer 101 along the word line trench WT includes diffusion doping using ALD doping or vapor phase doping. By using diffusion doping for the source and drain regions, it is possible to ensure good consistency in the doping concentration of the channel regions of multiple memory cells stacked in the vertical direction Z.

[0086] In some embodiments, referring to Figures 2A, 2B, and 2C, initial stacking structures STA' can be formed on both sides of the word line groove WT along the second direction Y. The two initial stacking structures STA' form a first stacking structure STA1 and a second stacking structure STA2, respectively. The first stacking structure STA1 and the second stacking structure STA2 can share a single word line groove WT, forming two stacked word line structures WL within the groove WT. This improves the fabrication efficiency of the word line structures WL and reduces the manufacturing difficulty of the horizontal word line structure. The two stacked word line structures WL can be interconnected to form a ring-shaped word line structure for synchronous control, improving the efficiency of stacked structure control; alternatively, the two stacked word line structures WL can be isolated for separate control, increasing the flexibility of stacked structure control.

[0087] In some embodiments, forming a first bit line BL1 and a second bit line BL2 extending in the vertical direction Z between a first active structure and a second active structure includes: forming a bit line via BT extending in the vertical direction Z between the first active structure and the second active structure, as shown in FIG10, the bit line via BT exposing a first source / drain region 111 and a third source / drain region 121; forming an initial bit line layer BL' on the sidewall of the bit line via BT; forming a first opening OP1, as shown in FIGS11 and 12, and removing a first portion BL1 of the initial bit line layer BL' along the first opening OP1, the first opening OP1 being located on one side of the bit line via BT along the second direction Y; forming a second opening OP2, as shown in FIG13, and removing a second portion BL1b of the partial initial bit line layer BL' along the second opening OP2, the second opening OP2 being located on the other side of the bit line via BT along the second direction Y, the retained initial bit line layer serving as the first bit line BL1 and the second bit line BL2, the first bit line BL1 and the second bit line BL2 being mirror-symmetrical about each other about the center line CL between the first memory cell and the second memory cell.

[0088] Bit line vias BT penetrate the first isolation pillar 103 along the vertical direction Z, forming an initial bit line layer BL' in a portion of the bit line vias BT. For example, the initial bit line layer BL' and an isolation material layer are alternately used to penetrate the first isolation pillar 103. The active structures located on both sides of the initial bit line layer BL' are used to form memory cell groups (MCGs). The first opening OP1 and the second opening OP2 are located on opposite sides of the bit line vias BT along the second direction Y, respectively. The first opening OP1 and the second opening OP2 penetrate the first isolation pillar 103 along the vertical direction Z, and the second opening OP2 is closer to the word line structure WL than the first opening OP2. By simultaneously depositing and etching, a first bit line BL2 and a second bit line BL2 that are mirror-symmetrical along the second direction Y can be formed, improving the consistency of device performance in the semiconductor structure.

[0089] In some embodiments, referring to FIG12, the first opening OP1 is located on the side of the bit line via BT away from the first channel region 113 and the second channel region 123, and the first opening OP1 is formed. After removing the first portion BLa of the initial bit line layer BL' along the first opening OP1, the method further includes: removing a portion of the initial active layer 101 using a wet etching process to form a first void 311g and a second void 321g; referring to FIG13, the first void 311g and the second void 321g are respectively filled to form a first isolation portion 311 and a second isolation portion 321, the first isolation portion 311 is located at the end of the first source / drain region 111 along the second direction Y, and the second isolation portion 321 is located at the end of the third source / drain region 121 along the second direction Y. The method for fabricating the semiconductor structure further includes: referring to FIG14, using the first isolation portion 311 and the second isolation portion 321 as a barrier layer, a wet etching process is used to remove a portion of the initial active layer 101 between the second isolation pillars 104 to expose the second source / drain region 112 and the fourth source / drain region 122; referring to FIG15, a first lower electrode layer 211 and a second lower electrode layer 221 are formed, the first lower electrode layer 211 having a first recess 211a that contacts and connects with the first isolation portion 311 and a first protrusion 211b that contacts and connects with the second source / drain region 112, and the second lower electrode layer 221 having a second recess 221a that contacts and connects with the second isolation portion 321 and a second protrusion 221b that contacts and connects with the fourth source / drain region 122.

[0090] During the process of removing part of the initial active layer 101 along the first opening OP1 using a wet etching process, a portion of the lightly doped region is also removed. This lightly doped region is located at the end of the first source / drain region 111 and the third source / drain region 121 away from the channel region, so that the first gap 311g and the second gap 321g can expose the first source / drain region 111 and the third source / drain region 121, thereby increasing the spacing between the subsequently formed capacitor structure and the first source / drain region 111 and the third source / drain region 121.

[0091] Insulating material is filled along the first opening OP1 and the first gap 311g and the second gap 321g, with the portions filled in the first gap 311g and the second gap 321g serving as the first isolation portion 311 and the second isolation portion 321. After removing the second portion BLb of the initial bit line layer BL', insulating material is filled along the second opening OP2. The insulating material filled between the first memory cell MC1 and the second memory cell MC2 together constitutes the isolation structure ISO, which is used to reduce the coupling between adjacent memory cells.

[0092] In some embodiments, referring to FIG1, a third opening OP3 may also be formed through the second isolation pillar 104. The third opening OP3 exposes a plurality of channel regions stacked along the vertical direction Z. A ground plug GND is formed in the third opening OP3, which is in direct contact with the first channel region 113 and the second channel region 123. The ground plug GND is used to draw out the charge accumulated in the channel regions to improve the floating body effect of the transistor.

[0093] Referring to FIG14, lateral etching is performed using the first isolation portion 311 and the second isolation portion 321 as barrier layers. This protects the first source / drain region 111 and the third source / drain region 121 from damage during the lateral etching process, preventing short circuits between the subsequently formed capacitor structure and the first source / drain region 111, the third source / drain region 121, or the bit lines. During the lateral etching process, a portion of the initial active layer 101 and a portion of the lightly doped region are removed. The removed lightly doped region is located at the ends of the second source / drain region 112 and the fourth source / drain region 122 away from the channel region, forming a capacitor trench 200 exposing the second source / drain region 112 and the fourth source / drain region 122. This reduces the contact resistance between the subsequently formed capacitor structure and the second source / drain region 112 and the fourth source / drain region 122.

[0094] Referring to Figures 15 and 1, a capacitor structure is formed in the capacitor trench 200, including a first capacitor structure 210 and a second capacitor structure 220. The first capacitor structure 210 is connected to the second source / drain region 112 via a first protrusion 211b of the first lower electrode layer 211, and the second capacitor structure 220 is connected to the fourth source / drain region 122 via a second protrusion 221b of the second lower electrode layer 221.

[0095] In some embodiments, forming the first lower electrode layer 211 and the second lower electrode layer 221 includes: forming an initial lower electrode layer covering the sidewalls of the capacitor trench 200, the initial lower electrode layer also covering the first isolation pillar 103 and the second isolation pillar 104; filling the capacitor trench 200 with an electrode protection material, the electrode protection material being located only between adjacent second isolation pillars 104 and exposing the initial lower electrode layer located at the end face of the second isolation pillar 104 away from the word line structure; removing the initial lower electrode layer located at the end face of the second isolation pillar 104 away from the word line structure to form the first lower electrode layer 211 and the second lower electrode layer 221 spaced apart along a first direction X; and removing the electrode protection material.

[0096] In some embodiments, after forming the first lower electrode layer 211 and the second lower electrode layer 221, the method further includes: forming a conformally conformally covering the first lower electrode layer 211 and the second lower electrode layer 221 in the capacitor trench 200, the capacitor dielectric layer including the first capacitor dielectric layer 212 and the second capacitor structure 220; and forming an upper electrode layer on the surface of the capacitor dielectric layer, the upper electrode layer including the first upper electrode layer 213 and the second upper electrode layer 223. A first conductive layer conformally covering the first capacitor dielectric layer 212 and the second capacitor dielectric layer 222, and a second conductive layer filling the space between the first conductive layers can be formed. The first conductive layer can be a titanium nitride layer, and the second conductive layer can be a tungsten layer, a conductive doped polysilicon layer, or a conductive doped germanium silicon layer.

[0097] In some embodiments, the semiconductor structure 10 includes a memory, which may be a dynamic random access memory or a memory known in the art, such as a phase change memory or a ferroelectric memory.

[0098] The various semiconductor structures illustrated in this specific embodiment can be used in electronic devices with storage functions. These electronic devices can be terminal devices, such as mobile phones, tablets, and smart bracelets, or personal computers (PCs), servers, workstations, etc. The storage function in these electronic devices can be implemented using the following types of memory: Dynamic Random Access Memory (DRAM), Ferroelectric Random Access Memory (FRAM), Phase Change Memory (PCM), Magnetic Random Access Memory (MRAM), or Resistive Random Access Memory (RRAM).

[0099] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A semiconductor structure, comprising: Substrate (100); A first memory cell (MC1) and a second memory cell (MC2) are located on the substrate (100), the first memory cell (MC1) and the second memory cell (MC2) are arranged along a first direction (X), the first direction (X) is parallel to the plane of the substrate (100); The first memory cell (MC1) includes a first source-drain region (111), a first channel region (113), and a second source-drain region (112). The first channel region (113) extends along the first direction (X), and the first source-drain region (111) and the second source-drain region (112) are located on the same side of the first channel region (113) along the second direction (Y). The second memory cell (MC2) includes a third source-drain region (121), a second channel region (123), and a fourth source-drain region (122). The second channel region (123) extends along the first direction (X), and the third source-drain region (121) and the fourth source-drain region (122) are located on the same side of the second channel region (123) along the second direction (Y). The first bit line (BL1) extends along the vertical direction (Z), and the first bit line (BL1) is located on one side of the first source-drain region (111) along the first direction (X) and is electrically connected to the first source-drain region (111). The second bit line (BL2) extends in the vertical direction (Z) and is located on one side of the third source-drain region (121) along the first direction (X) and is electrically connected to the third source-drain region (121).

2. The semiconductor structure according to claim 1, wherein, The first bit line (BL1) and the second bit line (BL2) are mirror images of each other about the center line between the first memory cell (MC1) and the second memory cell (MC2); The first source / drain region (111), the second source / drain region (112), the third source / drain region (121), and the fourth source / drain region (122) all extend along the second direction (Y); The first source / drain region (111) and the third source / drain region (121) are mirror images of each other about the center line; The second source / drain region (112) and the fourth source / drain region (122) are mirror images of each other about the center line.

3. The semiconductor structure according to claim 1, wherein, The first memory cell (MC1) further includes: a first lightly doped region (111a) located between the first source / drain region (111) and the first channel region (113), and a region located between the second source / drain region (112) and the first channel region (113). The second lightly doped region (112a) between; The second memory cell (MC2) further includes: a third lightly doped region (121a) located between the third source / drain region (121) and the second channel region (123), and a fourth lightly doped region (122a) located between the fourth source / drain region (122) and the second channel region (123); The first lightly doped region (111a) and the third lightly doped region (121a) are mirror-symmetric about the center line; The second lightly doped region (112a) and the fourth lightly doped region (122a) are mirror images of each other about the center line.

4. The semiconductor structure according to claim 1, wherein, The first memory cell (MC1) further includes: a first capacitor structure (210), the first capacitor structure (210) being electrically connected to the second source-drain region (112), the first capacitor structure (210) including a first lower electrode layer (211), a first capacitor dielectric layer (212) and a first upper electrode layer (213); The second memory cell (MC2) further includes a second capacitor structure (220), which is electrically connected to the fourth source-drain region (122). The second capacitor structure (220) includes a second lower electrode layer (221), a second capacitor dielectric layer (222), and a second upper electrode layer (223).

5. The semiconductor structure according to claim 4, wherein, The first lower electrode layer (211) has a first recess (211a) facing the first source / drain region (111) and a first protrusion (211b) that is in contact with the second source / drain region (112); The second lower electrode layer (221) has a second recess (221a) facing the third source / drain region (121) and a second protrusion (221b) in contact with the fourth source / drain region (122).

6. The semiconductor structure according to claim 4, wherein, The semiconductor structure also includes: An isolation structure (ISO) is located between a first storage cell (MC1) and a second storage cell (MC2), the isolation structure (ISO) including a first isolation section (311) and a second isolation section (321); The first isolation portion (311) is located between the end of the first source-drain region (111) along the second direction (Y) and the first recess (211a) of the first capacitor structure (210); The second isolation portion (321) is located between the end of the third source / drain region (121) along the second direction (Y) and the second recess (221a) of the second capacitor structure (220).

7. The semiconductor structure according to claim 1, wherein, Along the second direction (Y), the thickness of the first channel region (113) decreases as the distance from the first source / drain region (111) and the second source / drain region (112) increases, and the thickness of the second channel region (123) decreases as the distance from the third source / drain region (121) and the fourth source / drain region (122) increases.

8. The semiconductor structure according to any one of claims 1-7, wherein, The semiconductor structure further includes a word line structure (WL) extending along the first direction (X); the word line structure (WL) includes a first gate portion (WLa) and a second gate portion (WLb), and a word line connection portion (WLc) connecting the first gate portion (WLa) and the second gate portion (WLb), the word line connection portion (WLc) having a first offset from the first gate portion (WLa) and the second gate portion (WLb) in the second direction (Y); The first gate portion (WLa) covers the first channel region (113), and the projection of the first gate portion (WLa) on the substrate (100) at least partially covers the projection of the first channel region (113) on the substrate (100); The second gate portion (WLb) covers the second channel region (123), and the projection of the second gate portion (WLb) on the substrate (100) at least partially covers the projection of the second channel region (123) on the substrate (100).

9. The semiconductor structure according to any one of claims 1-7, wherein, The semiconductor structure includes a first stacked structure (STA1) on the substrate (100), the first stacked structure (STA1) includes multiple memory layers (101L) stacked at intervals in the vertical direction (Z), each memory layer (101L) includes multiple memory cell groups (MCG), each memory cell group (MCG) includes the first memory cell (MC1) and the second memory cell (MC2), and the multiple memory cell groups (MCG) included in each memory layer (101L) are arranged along a first direction (X); The first bit line (BL1) is electrically connected to a plurality of first source-drain regions (111) stacked along the vertical direction (Z); The second bit line (BL2) is electrically connected to a plurality of third source-drain regions (121) stacked along the vertical direction (Z).

10. The semiconductor structure according to claim 9, wherein, The semiconductor structure further includes a second stacked structure (STA2), which is arranged along a second direction (Y) with the first stacked structure (STA1), and the second stacked structure (STA2) and the first stacked structure (STA1) are mirror-symmetrical about each other about the central axis of the second stacked structure (STA2) and the first stacked structure (STA1).

11. A method for fabricating a semiconductor structure, comprising: Provide substrate (100); A first active structure (AA1) and a second active structure (AA2) are formed on the substrate (100), wherein the first active structure (AA1) and the second active structure (AA2) are formed on the substrate (100). An active structure (AA1) and a second active structure (AA2) are arranged along a first direction (X), which is parallel to the plane of the substrate (100). The first active structure (AA1) includes a first source / drain region (111), a first channel region (113), and a second source / drain region (112). The first channel region (113) extends along the first direction (X), and the first source / drain region (111) and the second source / drain region (112) are located on the same side of the first channel region (113) along a second direction (Y). The second active structure (AA2) includes a third source / drain region (121), a second channel region (123), and a fourth source / drain region (122). The second channel region (123) extends along the first direction (X), and the third source / drain region (121) and the fourth source / drain region (122) are located on the same side of the second channel region (123) along a second direction (Y). A first bit line (BL1) and a second bit line (BL2) extending in the vertical direction (Z) are formed between the first active structure (AA1) and the second active structure (AA2). The first bit line (BL1) is located on one side of the first source-drain region (111) along the first direction (X) and is electrically connected to the first source-drain region (111). The second bit line (BL2) is located on one side of the third source-drain region (121) along the first direction (X) and is electrically connected to the third source-drain region (121).

12. The preparation method according to claim 11, wherein, Forming a first active structure (AA1) and a second active structure (AA2) on the substrate (100) includes: An initial stacked structure (STA') is formed on the substrate (100), the initial stacked structure (STA') including an initial active layer (101) and an initial sacrificial layer (102) stacked along the vertical direction (Z); A first isolation pillar (103) and a second isolation pillar (104) are formed through the initial stacked structure (STA'), the first isolation pillar (103) and the second isolation pillar (104) are arranged along the first direction (X), and the length of the first isolation pillar (103) along the second direction (Y) is greater than the length of the second isolation pillar (104) along the second direction (Y); A first doped trench is formed in the first isolation pillar (103); The initial active layer (101) exposed on both sides of the first doped trench along the first direction (X) is diffused and doped to form the first source / drain region (111), the second source / drain region (112), the third source / drain region (121), and the fourth source / drain region (122) extending along the second direction (Y).

13. The preparation method according to claim 12, wherein, Both ends of the first isolation post (103) extend beyond the ends of the second isolation post (104) in the second direction (Y), forming the first isolation post (103) and the second isolation post (104) penetrating the initial stacked structure (STA'), and further comprising: A word line trench (WT) is formed through the initial stack structure (STA'), the word line trench (WT) being positioned... On the same side of the first isolation post (103) and the second isolation post (104) along the second direction (Y); A portion of the initial sacrificial layer (102) is removed laterally along the word line trench (WT) to expose a portion of the initial active layer (101); The exposed portion of the initial active layer (101) is thinned and doped to form a first channel region (113) and a second channel region (123); A word line structure (WL) is formed in the word line trench (WT), the word line structure (WL) including a word line conductive layer and a word line dielectric layer.

14. The preparation method according to claim 11, wherein, A first active line (BL1) and a second active line (BL2) extending in the vertical direction (Z) are formed between the first active structure (AA1) and the second active structure (AA2), including: A bit line via (BT) extending in the vertical direction (Z) is formed between the first active structure (AA1) and the second active structure (AA2), the bit line via (BT) exposing the first source / drain region (111) and the third source / drain region (121); An initial bit line layer (BL') is formed on the sidewall of the bit line slot (BT); A first opening (OP1) is formed, and a first portion of the initial bit line layer (BL') is removed along the first opening (OP1), the first opening (OP1) being located on one side of the bit line via (BT) along the second direction (Y); A second opening (OP2) is formed, and a second portion of the initial bit line layer (BL') is removed along the second opening (OP2), the second opening (OP2) being located on the other side of the bit line slot (BT) along the second direction (Y). The retained initial bit line layer (BL') serves as the first bit line (BL1) and the second bit line (BL2), the first bit line (BL1) and the second bit line (BL2) being mirror-symmetric to each other about the center line between the first active structure (AA1) and the second active structure (AA2).

15. The preparation method according to claim 14, wherein, The first opening (OP1) is located on the side of the bit line via (BT) away from the first channel region (113) and the second channel region (123), and after removing a first portion of the initial bit line layer (BL') along the first opening (OP1), the following is further included: A wet etching process was used to remove part of the initial active layer (101) to form the first void (311g) and the second void (321g); A first isolation portion (311) and a second isolation portion (321) are respectively filled into the first gap (311g) and the second gap (321g). The first isolation portion (311) is located at the end of the first source / drain region (111) along the second direction (Y), and the second isolation portion (321) is located in the third source / drain region (121) along the second direction (Y). The end; The method for preparing the semiconductor structure further includes: Using the first isolation portion (311) and the second isolation portion (321) as a barrier layer, a wet etching process is used to remove part of the initial active layer (101) between the second isolation pillars (104) to expose the second source / drain region (112) and the fourth source / drain region (122). A first lower electrode layer (211) and a second lower electrode layer (221) are formed. The first lower electrode layer (211) has a first recess (211a) that is in contact with the first isolation portion (311) and a first protrusion (211b) that is in contact with the second source / drain region (112). The second lower electrode layer (221) has a second recess (221a) that is in contact with the second isolation portion (321) and a second protrusion (221b) that is in contact with the fourth source / drain region (122).

Images