Wireless communication system

Abstract

The purpose of the present disclosure is to provide a radio communication system capable of improving error correction capability. This wireless communication system includes a transmission device and a reception device. The transmission device executes a process of generating a concatenated packet in which three or more packets having the same bit string for a portion including a frame check sequence and a payload are concatenated, and a process of transmitting the concatenated packet. The reception device executes: a process of receiving the concatenated packet; a first comparison / correction process of comparing the bit string among the frame check sequences included in the concatenated packet and correcting, by means of majority decision, bits the values of which do not match; and a process of performing forward error correction decoding of the payloads included in the concatenated packet by using the frame check sequences corrected in the first comparison / correction process.

Description

wireless communication system

[0001] The present disclosure relates to wireless communication systems, and more particularly to wireless communication systems suitable for correcting bit errors.

[0002] It is known that radio waves are easily affected by noise, and a typical example is noise interference caused by power transmission lines in the VHF band, UHF band, etc. (see Non-Patent Document 1).

[0003] Conventionally, error control is performed by error correction coding and interleaving to deal with continuous bit errors (also called burst errors) caused by fading or burst interference waves (see Non-Patent Document 2). In some cases, these techniques are combined with packet retransmission control techniques.

[0004] "Noise Interference Caused by Power Lines", Jushin Service Co., Ltd., https: / / www.jushin-s.co.jp / michi / download / 122_k24.pdf "Knowledge Base 4 Group 1 Part 5 Application of Error Correction Technology", Shuji Kubota, Institute of Electronics, Information and Communication Engineers, Ver.1 / 2010.11.9, https: / / www.ieice-hbkb.org / files / 04 / 04gun_01hen_05.pdf

[0005] However, even with the above techniques, bit errors exceeding a certain percentage cannot be corrected completely. Since retransmission of packets means delays, it is desirable to improve error correction capabilities.

[0006] In order to solve the above-mentioned problems, an object of the present disclosure is to provide a wireless communication system capable of improving error correction capabilities.

[0007] An aspect of the present disclosure is preferably a wireless communication system comprising a transmitting device and a receiving device, wherein the transmitting device is configured to perform a process of generating a concatenated packet by concatenating three or more packets whose bit strings including a frame check sequence and a payload are identical, and a process of transmitting the concatenated packet, and the receiving device is configured to perform a process of receiving the concatenated packet, a first comparison and correction process of comparing the bit strings between the frame check sequences included in the concatenated packet and correcting bits whose values ​​do not match by majority vote, and a process of forward error correction decoding the payload included in the concatenated packet using the frame check sequence corrected by the first comparison and correction process.

[0008] In the wireless communication system of the present disclosure, forward error correction decoding is performed using a frame check sequence that has been error corrected by majority vote, which improves error detection accuracy and correction capability.

[0009] FIG. 1 is a configuration example of a wireless communication system according to a first embodiment; FIG. 2 is a diagram illustrating hardware configurations of a transmitting device and a receiving device according to the first embodiment; FIG. 3 is a diagram illustrating processing performed by a replica circuit; FIG. 4 is a diagram illustrating processing performed by a concatenation circuit; FIG. 5 is a diagram illustrating interleaving performed by a concatenation circuit; FIG. 6 is a diagram illustrating bit errors that occur when transmitting concatenated packets; FIG. 7 is a diagram illustrating processing performed by a restoration circuit; FIG. 8 is a diagram illustrating first comparison and correction processing performed by a restoration circuit; FIG. 9 is a diagram illustrating forward error correction decoding performed by a decoding circuit; and FIG. 10 is a diagram illustrating second comparison and correction processing performed by a comparison circuit; and FIG. 11 is a flowchart illustrating processing performed by CPUs of a transmitting device and a receiving device according to the first embodiment.

[0010] Embodiments of the present disclosure will be described with reference to the drawings. The same or corresponding components will be designated by the same reference numerals, and repeated description may be omitted.

[0011] 1 shows an example of the configuration of a wireless communication system 100 according to embodiment 1. The wireless communication system 100 includes a transmitting device 110 and a receiving device 120 that perform wireless communication.

[0012] First, the functions of the transmitting device 110 will be described. The interface circuit 111 receives user signals to be transmitted from an upper layer or another device. The framing circuit 112 functions as a buffer that stores a certain number of user signals from the interface circuit 111. The framing circuit 112 divides the user signals into bits to generate multiple payloads 2. The framing circuit 112 also calculates an FCS (Frame Check Sequence) 3 for each of the multiple payloads 2. The framing circuit 112 generates multiple packets by adding a header 1 based on the communication protocol to the front of each payload 2 and adding the calculated FCS 3 to the end.

[0013] The duplication circuit 113 duplicates the packet 10 received from the framing circuit 112. The duplication circuit 113 generates three or more packets 10, including the duplicated packet 10 and the original packet 10. For the sake of explanation, it is assumed below that three packets 10-1, 10-2, and 10-3 have been generated. The packets 10-1, 10-2, and 10-3 have the same bit strings in the portions including the header 1, payload 2, and FCS 3.

[0014] The concatenation circuit 114 receives the packets 10-1, 10-2, and 10-3 from the duplication circuit 113. The concatenation circuit 114 concatenates the packets 10-1, 10-2, and 10-3 into one concatenated packet 30. Furthermore, the concatenation circuit 114 performs interleaving on the concatenated packet 30 to rearrange the order of bits.

[0015] The modulation circuit 115 modulates the interleaved concatenated packet 30 after adding a code for forward error correction (FEC).

[0016] The RF transmission circuit 116 converts the concatenated packet 30 received from the modulation circuit 115 into a radio signal suitable for transmission. The RF transmission circuit 116 amplifies the radio signal, removes unnecessary frequency components from the radio signal, and then transmits the signal to the antenna 117.

[0017] The antenna 117 transmits the radio signal to the receiving device 120 .

[0018] The control circuit 118 controls each circuit of the transmitting device 110. When the control circuit 118 receives an alarm from the modulation circuit 115 and the RF transmitting circuit 116, it performs necessary control on the source of the alarm. The control circuit 118 also monitors and controls each other with the control circuit 129 of the receiving device 120, and exchanges information necessary for synchronizing the transmission and reception of radio signals.

[0019] Next, a description will be given of the functions of the receiving device 120. The antenna 121 receives a radio signal from the transmitting device 110. The RF receiving circuit 122 amplifies and performs automatic gain control (AGC) on the received signal.

[0020] The demodulation circuit 123 demodulates the concatenated packet 30 contained in the received signal, and also monitors the BER based on the received signal.

[0021] The restoration circuit 124 deinterleaves the concatenated packet 30 received from the demodulation circuit 123, and restores the order of bits that were rearranged by the transmitting device 110. Furthermore, the restoration circuit 124 restores packets 10-1, 10-2, and 10-3 from the deinterleaved concatenated packet 30.

[0022] Furthermore, the restoration circuit 124 performs error correction by majority vote on the headers 1 and FCSs 3 of the packets 10-1, 10-2, and 10-3. Specifically, it performs a first comparison and correction process in which it compares the bit strings between the headers 1 and FCSs 3 of the three packets 10 and corrects any bits that do not match by majority vote. The restoration circuit 124 replaces the headers 1 of the packets 10-1, 10-2, and 10-3 with the corrected headers 51, and replaces the FCSs 3 of the packets 10-1, 10-2, and 10-3 with the corrected FCSs 53.

[0023] The decoding circuit 125 performs forward error correction decoding on the payload 2 of each of the packets 10-1, 10-2, and 10-3 using the corrected FCS 53. By performing forward error correction decoding using the FCS 53 that has been error corrected by majority vote, the correction capability can be improved.

[0024] The comparison circuit 126 performs error correction by majority vote on each payload 2 of packets 10-1, 10-2, and 10-3. Specifically, the comparison circuit 126 compares the bit strings between the payloads 2 that have been forward error correction decoded, and performs a second comparison and correction process to correct bits whose values ​​do not match by majority vote. The comparison circuit 126 sends packet 50 obtained by performing the second comparison and correction process to the deframing circuit 127 as the final error correction result.

[0025] The deframing circuit 127 functions as a buffer that stores a certain number of packets 50 from the comparison circuit 126. The deframing circuit 127 arranges the stored packets 50 in the order in which they were generated by the transmitting device 110, and reassembles the user signal.

[0026] The interface circuit 128 outputs the user signal to a higher layer or other device.

[0027] The control circuit 129 controls each circuit of the receiving device 120. When the control circuit 129 receives an alarm from the demodulation circuit 123 and the RF receiving circuit 122, the control circuit 129 performs necessary control on the source of the alarm.

[0028] 2 is a diagram showing the hardware configuration of the transmitting device 110 and the receiving device 120 according to the first embodiment. The processing performed by the transmitting device 110 and the receiving device 120 may be executed by a program using a computer having a CPU and memory and storing a wireless communication program in the memory. Alternatively, the processing may be executed by a program using an integrated circuit such as an FPGA (Field Programmable Gate Array). The wireless communication program may be provided by being recorded on a storage medium or provided via a network.

[0029] The transmitting device 110 and the receiving device 120 have computer functions, with an input unit 40, an output unit 41, a communication unit 42, a CPU (Central Processing Unit, also called a processor) 43, a memory 44, and an HDD (Hard Disk Drive) 45 connected via a bus 46. The transmitting device 110 and the receiving device 120 are also capable of inputting and outputting data to and from a computer-readable storage medium 47.

[0030] The input unit 40 is, for example, a keyboard and a mouse, etc. The output unit 41 is, for example, a display device such as a display.

[0031] The communication unit 42 is a communication interface that enables the transmitting device 110 and the receiving device 120 to communicate with each other, for example.

[0032] The memory 44 may be, for example, a volatile or non-volatile semiconductor memory such as a RAM, a ROM, or a flash memory, or a magnetic disk, a flexible disk, an optical disk, a DVD, or the like.

[0033] The CPU 43 controls each component of the transmitting device 110 or the receiving device 120 and performs predetermined processing, etc. The memory 44 and the HDD 45 are storage devices that store, for example, data of a wireless communication program, etc.

[0034] The storage medium 47 is capable of storing a wireless communication program or the like that causes the transmitting device 110 and the receiving device 120 to execute the functions of the transmitting device 110 and the receiving device 120. The storage medium 47 is a USB (Universal Serial Bus) memory, a CD-ROM (Compact Disc Read Only Memory), or the like.

[0035] The architecture configuring the transmitting device 110 and the receiving device 120 is not limited to the example shown in the figure.

[0036] 3 to 5 are diagrams illustrating the processing executed by the transmitting device 110. Fig. 3 is a diagram illustrating the processing executed by the duplication circuit 113. The duplication circuit 113 collectively duplicates the header 1, payload 2, and FCS 3 contained in the original packet 10.

[0037] 4 is a diagram illustrating the process executed by the concatenation circuit 114. The concatenation circuit 114 concatenates the packets 10-1, 10-2, and 10-3 into one.

[0038] 5 is a diagram illustrating the interleaving performed by the concatenation circuit 114. Interleaving rearranges the order of bits in the concatenated packet 30. This disperses burst errors that occur during transmission and turns them into random errors, which makes forward error correction decoding easier on the receiving side.

[0039] 6 is a diagram illustrating a bit error 5 that occurs during transmission of a concatenated packet 30. A bit error 5 occurs in the concatenated packet 30 transmitted from the transmitting device 110 due to the influence of an interference wave.

[0040] 7 to 10 are diagrams illustrating the processing executed by the receiving device 120. Fig. 7 is a diagram illustrating the processing executed by the restoration circuit 124. The restoration circuit 124 divides the deinterleaved concatenated packet 30 and restores packets 10-1, 10-2, and 10-3.

[0041] FIG. 8 is a diagram illustrating the first comparison and correction process performed by the restoration circuit 124. The bit strings of the header 1 and FCS3 extracted from packets 10-1, 10-2, and 10-3 are shown here. The restoration circuit 124 compares the bit strings between the three headers 1 and the three FCS3. The restoration circuit 124 determines that bits whose values ​​do not match between the three headers 1 and the three FCS3 are errors, and determines the corrected bit value by majority vote. For example, if the bits in the three headers 1 are 0, 0, and 1, respectively, the restoration circuit 124 will adopt the majority of 0 as the corrected bit. Similarly, if the bits in the three FCS3 are 1, 1, and 0, respectively, the restoration circuit 124 will adopt the majority of 1 as the corrected bit. This is based on the probabilistic grounds that the probability of a bit error 5 occurring simultaneously in the majority of packets is low.

[0042] The recovery circuit 124 generates a corrected header 51 and FCS 53 by performing a first comparison and correction process.

[0043] 9 is a diagram for explaining the forward error correction decoding performed by the decoding circuit 125. The decoding circuit 125 uses the corrected FCS 53 to perform forward error correction decoding on the payload 2 of each of the packets 10-1, 10-2, and 10-3.

[0044] 10 is a diagram illustrating the second comparison and correction process performed by the comparison circuit 126. Here, the bit strings of packets 10-1, 10-2, and 10-3, each of which has been forward error correction decoded, are shown. The comparison circuit 126 compares the bit strings between the three payloads 2. The comparison circuit 126 determines that bits whose values ​​do not match among the three payloads 2 are errors, and determines the corrected bit value by majority vote of the bit values ​​indicated by the three payloads 2.

[0045] The comparison circuit 126 performs the second comparison and correction process to generate a packet 50 that is the final error correction result.

[0046] 11 is a flowchart illustrating processing executed by the CPU 43 of the transmitting device 110 and the receiving device 120 according to the first embodiment. The CPU 43 reads a wireless communication program stored in the memory 44 or the HDD 45 and executes the following processing.

[0047] First, the transmitting device 110 combines the duplicated packet 10 with the original packet 10 to generate three or more packets 10 containing the same bit sequence (step S01). Next, the transmitting device 110 generates a concatenated packet 30 by concatenating packets 10-1, 10-2, and 10-3 (step S02). The transmitting device 110 then interleaves the concatenated packet 30 (step S03). The transmitting device 110 then transmits the concatenated packet 30 to the receiving device 120 (step S04).

[0048] Next, the receiving device 120 receives the concatenated packet 30 (step S05). Next, the receiving device 120 deinterleaves the concatenated packet 30 (step S06). Furthermore, the receiving device 120 restores packets 10-1, 10-2, and 10-3 from the concatenated packet 30 (step S07). Furthermore, the receiving device 120 performs a first comparison and correction process on the headers 1 and FCSs 3 of the three packets 10, and corrects bits whose values ​​do not match among the three headers 1 or the three FCSs 3 by majority vote (step S08).

[0049] The receiving device 120 then performs forward error correction decoding on the payloads 2 of the packets 10-1, 10-2, and 10-3 using the corrected FCS 53 (step S09).The receiving device 120 then performs a second comparison and correction process on the payloads 2 of the packets 10-1, 10-2, and 10-3, and corrects bits whose values ​​do not match among the three payloads 2 by majority vote (step S10).

[0050] In this way, in the wireless communication system 100 of the present disclosure, forward error correction decoding is performed using the FCS 53 that has been error corrected by majority vote, so that the error detection accuracy can be improved, thereby improving the correction capability.

[0051] <Modification 1> In the above description, it has been explained that the transmitting device 110 concatenates three packets 10. It has also been explained that the receiving device 120 executes the first and second comparison and correction processes using the three packets 10. However, the number of packets 10 to be concatenated and the number of packets 10 used for majority voting are not limited to three and may be more than three. In this case, the effects described in the first embodiment can also be obtained.

[0052] <Variation 2> In the above description, it has been explained that the receiving device 120 performs the second comparison and correction process on payload 2 of packets 10-1, 10-2, and 10-3. By performing majority error correction on payload 2 as well, it is possible to correct bit error 5 that could not be completely corrected by forward error correction decoding. However, the second comparison and correction process does not necessarily have to be performed, and in that case, the effects described in embodiment 1 can still be obtained.

[0053] <Modification 3> In the above description, the receiving device 120 performs the second comparison and correction process on the forward error correction decoded packets 10-1, 10-2, and 10-3. However, the second comparison and correction process may be performed before the first comparison and correction process and forward error correction decoding, or may be performed between the first comparison and correction process and forward error correction decoding. In this case, the effects described in embodiment 1 can also be obtained.

[0054] <Modification 4> In the above description, the transmitting device 110 generates three or more packets 10 in which the bit sequences including the header 1, payload 2, and FCS 3 are identical. However, the header 1 does not necessarily have to have the same bit sequence among the packets 10. In the above description, the receiving device 120 performs the first comparison and correction process on the header 1 and FCS 3 of three packets 10. However, the header 1 does not necessarily have to be subjected to the first comparison and correction process, and in this case, the effect described in the first embodiment can still be obtained.

[0055] The present disclosure is not limited to the above-described embodiments, and various modifications can be made in the implementation stage without departing from the spirit of the present disclosure. Furthermore, the embodiments and modifications may be implemented in appropriate combinations, in which case the combined effects can be obtained.

[0056] 1 Header, 2 Payload, 3 Frame Check Sequence (FCS), 10 Packet, 30 Concatenated Packet, 40 Input Unit, 41 Output Unit, 42 Communication Unit, 43 CPU, 44 Memory, 46 Bus, 47 Storage Medium, 50 Packet, 51 Header, 53 FCS, 100 Wireless Communication System, 110 Transmitter, 111 Interface Circuit, 112 Framing Circuit, 113 Replicator Circuit, 114 Concatenator Circuit, 115 Modulator Circuit, 116 RF Transmitter Circuit, 117 Antenna, 118 Control Circuit, 120 Receiver, 121 Antenna, 122 RF Receiver Circuit, 123 Demodulator Circuit, 124 Restoration Circuit, 125 Decoder Circuit, 126 Comparison Circuit, 127 Deframing Circuit, 128 Interface Circuit, 129 Control Circuit

Claims

1. A wireless communication system comprising a transmitting device and a receiving device, wherein the transmitting device is configured to perform a process of generating a concatenated packet by concatenating three or more packets whose bit strings including a frame check sequence and a payload are identical, and a process of transmitting the concatenated packet, and the receiving device is configured to perform a process of receiving the concatenated packet, a first comparison and correction process of comparing the bit strings between the frame check sequences included in the concatenated packets and correcting bits whose values ​​do not match by majority vote, and a process of forward error correction decoding the payload included in the concatenated packet using the frame check sequence corrected by the first comparison and correction process.

2. The wireless communication system according to claim 1, wherein the receiving device further performs a second comparison and correction process of comparing the bit strings between the payloads and correcting bits whose values ​​do not match by majority vote.

3. The wireless communication system according to claim 2, wherein the second comparison and correction process uses the payload that has been forward error corrected and decoded.

4. A wireless communication system according to any one of claims 1 to 3, wherein the portion further includes a header, and the receiving device, in the first comparison and correction process, further performs a process of comparing the bit strings between the headers included in the concatenated packets and correcting bits whose values ​​do not match by majority vote.

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