Model compression via reinterpretable lookup tables

Abstract

Systems, apparatuses and methods may provide for technology that converts a first plurality of source weights from a weight matrix into a first plurality of quantized weights based on a first weight scale factor and a first lookup table, converts a second plurality of source weights from the weight matrix into a second plurality of quantized weights based on a second weight scale factor and a second lookup table, wherein the first plurality of quantized weights and the second plurality of quantized weights are clustered within a quantization range, and generates an output artificial intelligence (AI) model based on the first plurality of quantized weights and the second plurality of quantized weights. A data type format corresponding to the first plurality of quantized weights and the second plurality of quantized weights is interpretable as a floating point data type format and an integer data type format.

Description

[0001] MODEL COMPRESSION VIA REINTERPRETABLE LOOKUP TABLES

[0002] BACKGROUND

[0003] A large language model (LLM) is a type of language model notable for the ability to achieve general-purpose language understanding and generation. LLMs acquire these abilities by using large amounts of data to leam billions of parameters during training and consuming large computational resources during training and operation (e.g., inference). Weight data used by LLMs may originally be in a relatively high precision format such as, for example, the 32-bit floating point (FP32) format. Execution of LLMs on edge / client devices may be limited due to memory pressure during the loading of weights throughout the inference process. Quantizing the weight data used by LLMs to a lower-precision format such as, for example, 4-bit integer (INT4), can reduce the computational and memory demands of these modem architectures. Conventional quantization approaches, however, may encounter accuracy problems that negate the benefits of quantization. Additionally, the weight representation format may not run efficiently on all instruction sets, which limits data type adoption.

[0004] BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The various advantages of the embodiments will become apparent to one skilled in the art by reading the following specification and appended claims, and by referencing the following drawings, in which:

[0006] FIG. 1 A is an illustration of an example of an artificial intelligence (Al) model compression solution according to an embodiment;

[0007] FIG. IB is an illustration of an example of column groups from a weight matrix according to an embodiment;

[0008] FIG. 2 is an illustration of an example of a weight clustering solution according to an embodiment;

[0009] FIG. 3 is an illustration of an example of a model quantization solution according to an embodiment;

[0010] FIG. 4 is an illustration of an example of a 4-bit weight quantization solution according to an embodiment;

[0011] FIG. 5 is an illustration of an example of an Al model decompression solution according to an embodiment; FIG. 6 is a flowchart of an example of a method of compressing a pre-trained Al model according to an embodiment;

[0012] FIG. 7 is a flowchart of an example of a method of decompressing an output Al model according to an embodiment;

[0013] FIG. 8 is a block diagram of an example of a performance-enhanced computing system according to an embodiment;

[0014] FIG. 9 is an illustration of an example of a semiconductor package apparatus according to an embodiment;

[0015] FIG. 10 is a block diagram of an example of a processor according to an embodiment; and

[0016] FIG. 11 is a block diagram of an example of a multi-processor based computing system according to an embodiment.

[0017] DETAILED DESCRIPTION

[0018] Current solutions in the model optimization domain may include methods for large language model (LLM) optimization that are inaccurate or inefficient, as well as post-optimization methods for accuracy improvement that do not focus on LLM optimization or involve relatively long model tuning procedures.

[0019] For example, generative pre-trained transformer quantization (GPTQ) may quantize model weights in a layer-wise fashion into 4-bit integer (INT4) precision by default using zero-point and scale factor. A substantial challenge of GPTQ, however, is that the data type (INT4) that is used does not consider the nature of the weight distribution, which mostly corresponds to a unimodal normal distribution. As a result, the results are less accurate compressed models despite the complicated compression process.

[0020] Another alternative is a 4-bit normal floating point (NF4) data type that may contain sixteen (24) floating point values in the range [-1.0, 1.0] that are based on the quantiles of the normal distribution. Although this type allows a more accurate representation of the model weights and may lead to better accuracy after weight compression, one limitation of the NF4 type is that the data type can be used only with floating-point instructions (e.g., 32-bit floating point / FP32, 16-bit floating point / FP16, 16-bit brain floating point / Bfloatl6) when computing dot product operations during inferences. The NF4 data type does not allow the use of 8-bit integer (INT8) instructions, which are more power-efficient, performant, and available in most contemporary hardware (e.g., central processing units / CPUs, integrated and discrete graphics processing units / GPUs, and specialized accelerators such as network processing units / NPUs).

[0021] Other proposed methods similar to NF4 include palletization, which may cluster and fit weights into a set of floating-point values. Although palletization solutions may improve accuracy, such solutions are typically not efficient during inference for certain platforms.

[0022] As will be discussed in greater detail, the technology described herein conducts accurate weight compression via clustering and runtime decompression via lookup tables of a reinterpretable data type that can be interpreted as the floating-point type or cast to 8-bit integer data type depending on the available instruction set. More particularly, embodiments provide for accurate weight compression via a clustering solution that not only considers weight distribution in a particular layer but also some theoretical aspects of model inference that achieve better accuracy for the entire model while being applied during the clustering process. To address cross-hardware compatibility concerns, embodiments cluster weights into the reinterpretable data type that be represented with the floating-point or integer lookup tables. As a result, efficient decompression and inference on various types of hardware (HW) can be achieved.

[0023] The proposed weight compression and decompression technology described herein enables accurate post-training and training-time optimization of Deep Learning (DL) models and provides cross-hardware compatibility when running inference operations on various types of HW that have different instruction sets. The technology described herein is highly applicable to the optimization of transformer-based models including Large Language Models (LLMs). Moreover, the technology described herein can be used standalone in a data- free setup or stacked with data-driven approaches, providing even better accuracy -performance trade-off after optimization.

[0024] Turning now to FIG. 1 A, a compression solution is shown in which a pre-trained Al model 20 (e.g., source LLM) includes a plurality of weight matrices 22 (e.g., tensors). In the illustrated example, a first plurality of source weights 24 from the weight matrices 22 are contained within a source range and are in a floating point (FP) data type format (e.g., FP32). Additionally, a first set of model parameters 26 including a first lookup table and a first weight scale factor are associated with the first plurality of source weights 24. Similarly, a second plurality of source weights 28 from the weight matrices 22 are contained within a source range and are in the FP data type format, wherein a second set of model parameters 30 (e.g., second lookup table, second weight scale factor) are associated with the second plurality of source weights 28. The weight matrices 22 may also include additional source weights (not shown) with corresponding lookup tables and weight scale factors.

[0025] As will be discussed in greater detail, the technology described herein converts the first plurality of source weights 24 into a first plurality of quantized weights 34 based on the first weight scale factor and the first lookup table. The technology described herein also converts the second plurality of source weights 28 into a second plurality of quantized weights 38 based on the second weight scale factor and the second lookup table. Both the first plurality of quantized weights 34 and the second plurality of quantized weights 38 are clustered within a quantization range.

[0026] Additionally, the first plurality of quantized weights 34 and the second plurality of quantized weights 38 are in a reinterpretable data type format. For example, the first plurality of quantized weights 34 can be interpreted as floating point quantized weights 32 or integer quantized weights 36 during decompression. Similarly, the second plurality of quantized weights 38 can be interpreted as floating point quantized weights 42 or integer quantized weights 46 during decompression. An output (e.g., optimized) Al model 40 is generated based on the first plurality of quantized weights 34, the first set of model parameters 26, the second plurality of quantized weights 38 and the second set of model parameters 30.

[0027] Thus, considering a single linear (e.g., Fully-Connected) layer that is optimized with the reinterpretable data type described herein, the weights of the pre-trained Al model 20 (W9) and the output Al model 40 ( optimized have the following relationship:

[0028] Where scale is the scale factor presented in the output Al model 40 and defined as I max |VIA9'|, and W9- is a part of one of the weight matrices 22 that forms a group (e.g., a set of columns, such as 128 columns). The clusterQ operator converts the scaled floating-point value from the range [-1.0, 1.0] (e.g., quantization range) to the nearest value from the lookup table of the output Al model 40. As will be discussed in greater detail, the borders of each cluster can be computed using the values of the lookup table. FIG. IB shows a weight matrix 50 that may be substituted for one or more of the weight matrices 22 (FIG. 1A), already discussed. The illustrated example demonstrates that per-channel group-wise quantization can be used to conduct weight compression. This approach assumes that the entire weight matrix 50 is evenly split into groups of columns (e.g., 128 columns), wherein each group of weights in each row undergoes a dedicated / independent quantization. For example, in the case of INT4 quantization, the following quantization formula results: where I G [0, rows],

[0029] To reduce quantization error and improve the final accuracy of the model, the following weight clustering approach is used:

[0030] - Each group of weights in the matrix 50 (e.g., tensor) has corresponding quantization parameters including a lookup table to dequantize the weights during inference operations.

[0031] - The number of centroids corresponds to the number of bits allocated to represent one weight value. For example, in case of 4 bits, the number of centroids is 24= 16 centroids.

[0032] - Clustering is performed for normalized (scaled) weights so that E [-1.0, 1.0].

[0033] - A subset of three fixed centroids, namely -1.0, 1.0, and 0.0, are included in the total set of centroids. This choice provides theoretical and experimental advantages. The values -1.0 and 1.0 enables minimum and maximum values of the weights to not be “shrunk” by the quantization process (e.g., the minimum and maximum values are important during the model decision-making process). Additionally, the values -1.0 and 1.0 also help to keep weights symmetrically distributed after quantization. Moreover, the value 0.0 zeros out unimportant weights with small magnitudes that usually produce a noise during inference. Thus, zeroing out weights with small magnitudes helps to exclude the weights from the decision-making process.

[0034] - The remaining 2blts— 3 centroids are estimated by the clustering procedure. For example, a modified k-means clustering may be used for this purpose, wherein the modified k-means clustering follows two constraints: 1) keep fixed centroids -1,0,1, and 2) make centroids reinterpretable by applying the following quantization process to INT8 type to the centroids so that: centroidfp32= centroidint8* 127.0.

[0035] Having a lookup table per each group of weights does not introduce significant overhead because of the low cost per each weight value. Indeed, considering the regular size of the weight matrices in LLMs >= 512x512, and minimal group size as 32, the following results:

[0036] FIG. 2 shows pseudo code 60 to conduct weight clustering, where split() is an auxiliary function that creates slices of a weight matrix and kmeans_int8() is a modified version of k-means clustering that considers fixed pre-defined centroids and searches only for integer centroids, namely from the range [-127, 127]. In the illustrated example, a first portion 62 establishes layer-wise clustering and a second portion 64 uses the k-means approach with clustering inside.

[0037] FIG. 3 shows pseudo code 70 to conduct quantization once the lookup tables and weight scaling parameters have been defined. In the illustrated example, a first portion 72 provides for iteration across all layers of the model and quantized is a value quantization function.

[0038] FIG. 4 shows pseudo code 80 (e.g., decision tree) for the quantization function in the case of 4-bit quantization. In the illustrated example, the borders are effectively the middle of the centroids.

[0039] Other settings may also be used. For example, per-tensor look-up might involve each linear layer having a single lookup tuned for the entire weight tensor. Additionally, per-model look-up may involve the use of a single look-up table that is tuned for the entire model.

[0040] Turning now to FIG. 5, a decompression solution is shown in which a determination is made as to whether a plurality of input activations 90 are in an FP data type format (e.g., FP32) or an INT data type format (e.g., INT8). If the plurality of input activations 90 are in the FP data type format, an FP matrix multiplication is conducted based on first model parameters 92 including a plurality of lookup tables corresponding to a plurality of column groups from a weight matrix. The first model parameters 92 may also include a plurality of weight scale factors corresponding to the plurality of column groups from the weight matrix. If the plurality of input activations 90 are in the INT data type format, an integer matrix multiplication is conducted based on the first model parameters. In one example, the integer matrix multiplication is conducted further based on second model parameters 94 including a fixed scale factor and an activation scale factor associated with the plurality of input activations 90. The floating point matrix multiplication and / or the integer matrix multiplication produce matrix multiplication results 96 during inference operations.

[0041] Thus, the weight dequantization that occurs at inference time immediately before the matrix multiplication (MatMul) operation has two options:

[0042] - Floating-point instructions are used for MatMul (dot product). In this case, quantized weights (< / j) are mapped to the floating-point range using a lookup table and scaled back to the source range using the scaling factor: is a lookup table that maps quantized 4-bit values to the float32 data type format.

[0043] - An 8-bit integer instruction set is available and input activations 90 are quantized to 8-bits (e.g., using dynamic quantization). The quantized weights are converted into the INT8 data type using an integer lookup table so that l4 / int8= = lookup fp32(qi') * 127.0. Then, the dot product operation can be computed in 8-bit precision as follows: okupint8qt) * sa* lookup table that maps quantized 4-bit values to the INT8 data type.

[0044] Compressing and decompressing Al models as described herein reduces perplexity (e.g., complexity) and increases accuracy relative to INT4 matrix multiplications for most workloads. Indeed, compressing and decompressing Al models as described herein also reduces perplexity and increases accuracy relative to FP32 matrix multiplications for some workloads.

[0045] FIG. 6 shows a method 100 of compressing a pre- trained Al model. The method 100 may be implemented in one or more modules as a plurality of logic instructions (e.g., compression instructions) stored in a machine- or computer-readable storage medium such as random access memory (RAM), read only memory (ROM), programmable ROM (PROM), firmware, flash memory, etc., in hardware, or any combination thereof. For example, hardware implementations may include configurable logic, fixed-functionality logic, or any combination thereof. Examples of configurable logic (e.g., configurable hardware) include suitably configured programmable logic arrays (PLAs), field programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), and general purpose microprocessors. Examples of fixed-functionality logic (e.g., fixed-functionality hardware) include suitably configured application specific integrated circuits (ASICs), combinational logic circuits, and sequential logic circuits. The configurable or fixed- functionality logic can be implemented with complementary metal oxide semiconductor (CMOS) logic circuits, transistor- transistor logic (TTL) logic circuits, or other circuits.

[0046] For example, computer program code to carry out operations shown in the method 100 can be written in any combination of one or more programming languages, including an object oriented programming language such as JAVA, SMALLTALK, C++ or the like and conventional procedural programming languages, such as the “C” programming language or similar programming languages. Additionally, logic instructions might include assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, statesetting data, configuration data for integrated circuitry, state information that personalizes electronic circuitry and / or other structural components that are native to hardware (e.g., host processor, central processing unit / CPU, microcontroller, etc.).

[0047] Illustrated block 102 provides for converting a first plurality of source weights from a weight matrix into a first plurality of quantized weights based on a first weight scale factor and a first lookup table. Block 104 converts a second plurality of source weights from the weight matrix into a second plurality of quantized weights based on a second weight scale factor and a second lookup table, wherein the first plurality of quantized weights and the second plurality of quantized weights are clustered within a quantization range (e.g., [-1.0, 1.0]). Block 106 generates an output Al model (e.g., optimized model) based at least in part on the first plurality of quantized weights and the second plurality of quantized weights. In an embodiment, a data type format corresponding to the first plurality of quantized weights and the second plurality of quantized weights is interpretable as an FP data type format and an INT data type format. The first plurality of source weights may correspond to a first plurality of columns (e.g., group) in the weight matrix, whereas the second plurality of source weights may correspond to may correspond to a second plurality of columns (e.g., group) in the weight matrix. In one example, the first plurality of quantized weights are clustered around a first plurality of centroids within the quantization range and the second plurality of quantized weights are clustered around a second plurality of centroids within the quantization range. In such a case, the first plurality of centroids and the second plurality of centroids may include a subset of fixed centroids. For example, the subset of fixed centroids can include an upper bound of the quantization range (e.g., 1.0), a lower bound of the quantization range (e.g., -1.0) and a midpoint between the upper bound and the lower bound (e.g., 0.0). The method 100 therefore enhances performance at least to the extent that using multiple lookup tables enables more effective clustering within the quantization range. The method 100 also enables accurate post-training and training-time optimization of deep learning (DL) models and provides cross-hardware compatibility when running inference on various types of HW that have different instruction sets.

[0048] FIG. 7 shows a method 110 of decompressing an output Al model. The method 110 may be implemented in one or more modules as a plurality of logic instructions (e.g., decompression instructions) stored in a machine- or computer-readable storage medium such as RAM, ROM, PROM, firmware, flash memory, etc., in hardware, or any combination thereof.

[0049] Illustrated processing block 112 provides for determining whether a plurality of input activations are in a floating point data type format. If the input activations are in the floating point data type format, block 114 conducts a floating point matrix multiplication (MatMul) based on a plurality of lookup tables corresponding to a plurality of column groups from a weight matrix. In an embodiment, the floating point matrix multiplication is conducted further based on a plurality of weight scale factors corresponding to the plurality of column groups. If it is determined at block 112 that the input activations are not in the floating point data type format, block 116 determines whether the plurality of input activations are in an integer data type format. If so, block 118 conducts an inter matrix multiplication based on the plurality of lookup tables. In an embodiment, the integer matrix multiplication is conducted further based on a plurality of weight scale factors corresponding to the plurality of column groups, a fixed scale factor, and an activation scale factor associated with the plurality of input activations. The fixed scale factor may be associated with an integer range such as, for example, [-127, 127], Additionally, the floating point matrix multiplication and / or the integer matrix multiplication may be conducted with respect to a first plurality of quantized weights, a second plurality of quantized weights, and the plurality of input activations. In such a case, the first plurality of quantized weights and the second plurality of quantized weights can be independently clustered within a quantization range such as, for example, [-1.0, 1.0].

[0050] The method 110 therefore enhances performance at least to the extent that using multiple lookup tables enables more effective clustering within the quantization range. The method 100 also enables accurate post-training and training-time optimization of DL models and provides cross-hardware compatibility when running inference on various types of HW that have different instruction sets.

[0051] Turning now to FIG. 8, a performance-enhanced computing system 280 is shown. The system 280 may generally be part of an electronic device / platform having computing functionality (e.g., personal digital assistant / PDA, notebook computer, tablet computer, convertible tablet, server), communications functionality (e.g., smart phone), imaging functionality (e.g., camera, camcorder), media playing functionality (e.g., smart television / TV), wearable functionality (e.g., watch, eyewear, headwear, footwear, jewelry), vehicular functionality (e.g., car, truck, motorcycle), robotic functionality (e.g., autonomous robot), Internet of Things (loT) functionality, drone functionality, etc., or any combination thereof.

[0052] In the illustrated example, the system 280 includes a host processor 282 (e.g., central processing unit / CPU) having an integrated memory controller (IMC) 284 that is coupled to a system memory 286 (e.g., dual inline memory module / DIMM). In an embodiment, an IO module 288 is coupled to the host processor 282. The illustrated IO module 288 communicates with, for example, a display 290 (e.g., touch screen, liquid crystal display / LCD, light emitting diode / LED display), and a network controller 292 (e.g., conducting wired and / or wireless communications). The host processor 282 may be combined with the IO module 288, a graphics processor 294, and an Al accelerator 296 into a system on chip (SoC) 298.

[0053] In an embodiment, the Al accelerator 296, the host processor 282 and / or the SoC 298 executes a plurality of executable program instructions 300 (e.g., compression and / or decompression instructions) retrieved from mass storage 302 and / or the system memory 286 to perform one or more aspects of the method 100 (FIG. 6) and / or the method 1 10 (FIG. 7), already discussed. Thus, during compression, execution of the instructions 300 causes the Al accelerator 296, the host processor 282 and / or the SoC 298 to convert a first plurality of source weights from a weight matrix into a first plurality of quantized weights based on a first weight scale factor and a first lookup table, convert a second plurality of source weights from the weight matrix into a second plurality of quantized weights based on a second weight scale factor and a second lookup table, wherein the first plurality of quantized weights and the second plurality of quantized weights are clustered within a quantization range, and generate an output artificial intelligence (Al) model based on the first plurality of quantized weights and the second plurality of quantized weights. As already noted, a data type format corresponding to the first plurality of quantized weights and the second plurality of quantized weights is interpretable as a floating point data type format and an integer data type format.

[0054] During decompression, execution of the instructions 300 causes the Al accelerator 296, the host processor 282 and / or the SoC to determine whether a plurality of input activations are in the floating point data type format or the integer data type format, conduct a floating point matrix multiplication if the plurality of input activations are in the floating point data type format, wherein the floating point matrix multiplication is conducted based on a plurality of lookup tables including the first lookup table and the second lookup table, and conduct an integer matrix multiplication if the plurality of input activations are in the integer data type format, wherein the integer matrix multiplication is conducted based on the plurality of lookup tables.

[0055] The computing system 280 is therefore considered performance-enhanced at least to the extent that using multiple lookup tables enables more effective clustering within the quantization range. The method 100 also enables accurate post- training and training-time optimization of DL models and provides cross-hardware compatibility when running inference on various types of HW that have different instruction sets.

[0056] FIG. 9 shows a semiconductor apparatus 350 (e.g., chip, die, package). The illustrated apparatus 350 includes one or more substrates 352 (e.g., silicon, sapphire, gallium arsenide) and logic 354 (e.g., transistor array and other integrated circuit / IC components) coupled to the substrate(s) 352. In an embodiment, the logic 354 implements one or more aspects of the method 100 (FIG. 6) and / or the method 110 (FIG. 7), already discussed.

[0057] The logic 354 may be implemented at least partly in configurable or fixed- functionality hardware. In one example, the logic 354 includes transistor channel regions that are positioned (e.g., embedded) within the substrate(s) 352. Thus, the interface between the logic 354 and the substrate(s) 352 may not be an abrupt junction. The logic 354 may also be considered to include an epitaxial layer that is grown on an initial wafer of the substrate(s) 352.

[0058] In an embodiment, the method 100 (FIG. 6) and / or the method 110 (FIG. 7) are incorporated into an INTEL OPENVINO toolkit, which streamlines Al model development and integration of deep learning in domains such as computer vision, large language models, and generative AT. In such a case, the use of reinterpretable lookup tables as described herein improves accuracy and / or reduces latency during inference operations.

[0059] FIG. 10 illustrates a processor core 400 according to one embodiment. The processor core 400 may be the core for any type of processor, such as a micro-processor, an embedded processor, a digital signal processor (DSP), a network processor, or other device to execute code. Although only one processor core 400 is illustrated in FIG. 10, a processing element may alternatively include more than one of the processor core 400 illustrated in FIG. 10. The processor core 400 may be a single-threaded core or, for at least one embodiment, the processor core 400 may be multithreaded in that it may include more than one hardware thread context (or “logical processor”) per core.

[0060] FIG. 10 also illustrates a memory 470 coupled to the processor core 400. The memory 470 may be any of a wide variety of memories (including various layers of memory hierarchy) as are known or otherwise available to those of skill in the art. The memory 470 may include one or more code 413 instruction(s) to be executed by the processor core 400, wherein the code 413 may implement the method 100 (FIG. 6) and / or the method 110 (FIG. 7), already discussed. The processor core 400 follows a program sequence of instructions indicated by the code 413. Each instruction may enter a front end portion 410 and be processed by one or more decoders 420. The decoder 420 may generate as its output a micro operation such as a fixed width micro operation in a predefined format, or may generate other instructions, microinstructions, or control signals which reflect the original code instruction. The illustrated front end portion 410 also includes register renaming logic 425 and scheduling logic 430, which generally allocate resources and queue the operation corresponding to the convert instruction for execution.

[0061] The processor core 400 is shown including execution logic 450 having a set of execution units 455-1 through 455-N. Some embodiments may include a number of execution units dedicated to specific functions or sets of functions. Other embodiments may include only one execution unit or one execution unit that can perform a particular function. The illustrated execution logic 450 performs the operations specified by code instructions.

[0062] After completion of execution of the operations specified by the code instructions, back end logic 460 retires the instructions of the code 413. In one embodiment, the processor core 400 allows out of order execution but requires in order retirement of instructions. Retirement logic 465 may take a variety of forms as known to those of skill in the art (e.g., re-order buffers or the like). In this manner, the processor core 400 is transformed during execution of the code 413, at least in terms of the output generated by the decoder, the hardware registers and tables utilized by the register renaming logic 425, and any registers (not shown) modified by the execution logic 450.

[0063] Although not illustrated in FIG. 10, a processing element may include other elements on chip with the processor core 400. For example, a processing element may include memory control logic along with the processor core 400. The processing element may include I / O control logic and / or may include VO control logic integrated with memory control logic. The processing element may also include one or more caches.

[0064] Referring now to FIG. 11 , shown is a block diagram of a computing system 1000 embodiment in accordance with an embodiment. Shown in FIG. 11 is a multiprocessor system 1000 that includes a first processing element 1070 and a second processing element 1080. While two processing elements 1070 and 1080 are shown, it is to be understood that an embodiment of the system 1000 may also include only one such processing element.

[0065] The system 1000 is illustrated as a point-to-point interconnect system, wherein the first processing element 1070 and the second processing element 1080 are coupled via a point-to-point interconnect 1050. It should be understood that any or all of the interconnects illustrated in FIG. 11 may be implemented as a multi-drop bus rather than point-to-point interconnect.

[0066] As shown in FIG. 11, each of processing elements 1070 and 1080 may be multicore processors, including first and second processor cores (i.e., processor cores 1074a and 1074b and processor cores 1084a and 1084b). Such cores 1074a, 1074b, 1084a, 1084b may be configured to execute instruction code in a manner similar to that discussed above in connection with FIG. 10.

[0067] Each processing element 1070, 1080 may include at least one shared cache 1896a, 1896b. The shared cache 1896a, 1896b may store data (e.g., instructions) that are utilized by one or more components of the processor, such as the cores 1074a, 1074b and 1084a, 1084b, respectively. For example, the shared cache 1896a, 1896b may locally cache data stored in a memory 1032, 1034 for faster access by components of the processor. In one or more embodiments, the shared cache 1896a, 1896b may include one or more mid-level caches, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, a last level cache (LLC), and / or combinations thereof.

[0068] While shown with only two processing elements 1070, 1080, it is to be understood that the scope of the embodiments are not so limited. In other embodiments, one or more additional processing elements may be present in a given processor. Alternatively, one or more of processing elements 1070, 1080 may be an element other than a processor, such as an accelerator or a field programmable gate array. For example, additional processing element(s) may include additional processors(s) that are the same as a first processor 1070, additional processor(s) that are heterogeneous or asymmetric to processor a first processor 1070, accelerators (such as, e.g., graphics accelerators or digital signal processing (DSP) units), field programmable gate arrays, or any other processing element. There can be a variety of differences between the processing elements 1070, 1080 in terms of a spectrum of metrics of merit including architectural, micro architectural, thermal, power consumption characteristics, and the like. These differences may effectively manifest themselves as asymmetry and heterogeneity amongst the processing elements 1070, 1080. For at least one embodiment, the various processing elements 1070, 1080 may reside in the same die package.

[0069] The first processing element 1070 may further include memory controller logic (MC) 1072 and point-to-point (P-P) interfaces 1076 and 1078. Similarly, the second processing element 1080 may include a MC 1082 and P-P interfaces 1086 and 1088. As shown in FIG. 11, MC’s 1072 and 1082 couple the processors to respective memories, namely a memory 1032 and a memory 1034, which may be portions of main memory locally attached to the respective processors. While the MC 1072 and 1082 is illustrated as integrated into the processing elements 1070, 1080, for alternative embodiments the MC logic may be discrete logic outside the processing elements 1070, 1080 rather than integrated therein.

[0070] The first processing element 1070 and the second processing element 1080 may be coupled to an I / O subsystem 1090 via P-P interconnects 1076 1086, respectively. As shown in FIG. 11, the VO subsystem 1090 includes P-P interfaces 1094 and 1098. Furthermore, VO subsystem 1090 includes an interface 1092 to couple VO subsystem 1090 with a high performance graphics engine 1038. In one embodiment, bus 1049 may be used to couple the graphics engine 1038 to the I / O subsystem 1090. Alternately, a point-to-point interconnect may couple these components.

[0071] In turn, VO subsystem 1090 may be coupled to a first bus 1016 via an interface 1096. In one embodiment, the first bus 1016 may be a Peripheral Component Interconnect (PCI) bus, or a bus such as a PCI Express bus or another third generation VO interconnect bus, although the scope of the embodiments are not so limited.

[0072] As shown in FIG. 11, various VO devices 1014 (e.g., biometric scanners, speakers, cameras, sensors) may be coupled to the first bus 1016, along with a bus bridge 1018 which may couple the first bus 1016 to a second bus 1020. In one embodiment, the second bus 1020 may be a low pin count (LPC) bus. Various devices may be coupled to the second bus 1020 including, for example, a keyboard / mouse 1012, communication device(s) 1026, and a data storage unit 1019 such as a disk drive or other mass storage device which may include code 1030, in one embodiment. The illustrated code 1030 may implement the method 100 (FIG. 6) and / or the method 110 (FIG. 7), already discussed. Further, an audio VO 1024 may be coupled to second bus 1020 and a battery 1010 may supply power to the computing system 1000.

[0073] Note that other embodiments are contemplated. For example, instead of the point-to-point architecture of FIG. 11 , a system may implement a multi-drop bus or another such communication topology. Also, the elements of FIG. 11 may alternatively be partitioned using more or fewer integrated chips than shown in FIG. 11.

[0074] Additional Notes and Examples:

[0075] Example 1 includes a performance-enhanced computing system comprising a network controller, a processor coupled to the network controller, and a memory coupled to the processor, the memory including a plurality of compression instructions, which when executed by the processor, cause the processor to convert a first plurality of source weights from a weight matrix into a first plurality of quantized weights based on a first weight scale factor and a first lookup table, convert a second plurality of source weights from the weight matrix into a second plurality of quantized weights based on a second weight scale factor and a second lookup table, wherein the first plurality of quantized weights and the second plurality of quantized weights are clustered within a quantization range, and generate an output artificial intelligence (Al) model based on the first plurality of quantized weights and the second plurality of quantized weights.

[0076] Example 2 includes the computing system of Example 1, wherein a data type format corresponding to the first plurality of quantized weights and the second plurality of quantized weights is interpretable as a floating point data type format and an integer data type format.

[0077] Example 3 includes the computing system of Example 2, wherein the memory further includes a plurality of decompression instructions, which when executed by the processor, cause the processor to determine whether a plurality of input activations are in the floating point data type format or the integer data type format, conduct a floating point matrix multiplication if the plurality of input activations are in the floating point data type format, wherein the floating point matrix multiplication is conducted based on a plurality of lookup tables including the first lookup table and the second lookup table, and conduct an integer matrix multiplication if the plurality of input activations are in the integer data type format, wherein the integer matrix multiplication is conducted based on the plurality of lookup tables.

[0078] Example 4 includes the computing system of Example 1, wherein the first plurality of quantized weights are clustered around a first plurality of centroids within the quantization range, and wherein the second plurality of quantized weights are clustered around a second plurality of centroids within the quantization range.

[0079] Example 5 includes the computing system of Example 4, wherein the first plurality of centroids and the second plurality of centroids include a subset of fixed centroids.

[0080] Example 6 includes the computing system of Example 5, wherein the subset of fixed centroids includes an upper bound of the quantization range, a lower bound of the quantization range and a midpoint between the upper bound and the lower bound.

[0081] Example 7 includes at least one computer readable storage medium comprising a plurality of compression instructions, which when executed by a computing system, cause the computing system to convert a first plurality of source weights from a weight matrix into a first plurality of quantized weights based on a first weight scale factor and a first lookup table, convert a second plurality of source weights from the weight matrix into a second plurality of quantized weights based on a second weight scale factor and a second lookup table, wherein the first plurality of quantized weights and the second plurality of quantized weights are clustered within a quantization range, and generate an output artificial intelligence (Al) model based on the first plurality of quantized weights and the second plurality of quantized weights.

[0082] Example 8 includes the at least one computer readable storage medium of Example 7, wherein a data type format corresponding to the first plurality of quantized weights and the second plurality of quantized weights is interpretable as a floating point data type format and an integer data type format.

[0083] Example 9 includes the at least one computer readable storage medium of Example 7, wherein the first plurality of quantized weights are clustered around a first plurality of centroids within the quantization range, and wherein the second plurality of quantized weights are clustered around a second plurality of centroids within the quantization range.

[0084] Example 10 includes the at least one computer readable storage medium of Example 9, wherein the first plurality of centroids and the second plurality of centroids include a subset of fixed centroids.

[0085] Example 11 includes the at least one computer readable storage medium of Example 10, wherein the subset of fixed centroids includes an upper bound of the quantization range, a lower bound of the quantization range and a midpoint between the upper bound and the lower bound.

[0086] Example 12 includes the at least one computer readable storage medium of any one of Examples 7 to 11, wherein the quantization range is [-1.0, 1.0].

[0087] Example 13 includes the at least one computer readable storage medium of Example 7 to 11, wherein the first plurality of source weights corresponds to a first plurality of columns in the weight matrix, and wherein the second plurality of source weights corresponds to a second plurality columns in the weight matrix.

[0088] Example 14 includes at least one computer readable storage medium comprising a plurality of decompression instructions, which when executed by a computing system, cause the computing system to determine whether a plurality of input activations are in a floating point data type format or an integer data type format, conduct a floating point matrix multiplication if the plurality of input activations are in the floating point data type format, wherein the floating point matrix multiplication is conducted based on a plurality of lookup tables corresponding to a plurality of column groups from a weight matrix, and conduct an integer matrix multiplication if the plurality of input activations are in the integer data type format, wherein the integer matrix multiplication is conducted based on the plurality of lookup tables.

[0089] Example 15 includes the least one computer readable storage medium of Example 14, wherein one or more of the floating point matrix multiplication or the integer matrix multiplication are conducted with respect to a first plurality of quantized weights, a second plurality of quantized weights, and the plurality of input activations, and wherein the first plurality of quantized weights and the second plurality of quantized weights are clustered within a quantization range.

[0090] Example 16 includes the least one computer readable storage medium of Example 15, wherein the quantization range is [-1.0, 1.0].

[0091] Example 17 includes the least one computer readable storage medium of any one of Examples 14 to 16, wherein the floating point matrix multiplication is conducted further based on a plurality of weight scale factors corresponding to the plurality of column groups.

[0092] Example 18 includes the least one computer readable storage medium of any one of Examples 14 to 16, wherein the integer matrix multiplication is conducted further based on a plurality of weight scale factors corresponding to the plurality of column groups, a fixed scale factor, and an activation scale factor associated with the plurality of input activations.

[0093] Example 19 includes the least one computer readable storage medium of Example 18, wherein the fixed scale factor is associated with an integer range.

[0094] Example 20 includes the least one computer readable storage medium of Example 19, wherein the integer range is [-127, 127].

[0095] Example 21 includes a method of conducting compression, the method comprising converting a first plurality of source weights from a weight matrix into a first plurality of quantized weights based on a first weight scale factor and a first lookup table, converting a second plurality of source weights from the weight matrix into a second plurality of quantized weights based on a second weight scale factor and a second lookup table, wherein the first plurality of quantized weights and the second plurality of quantized weights are clustered within a quantization range, and generating an output artificial intelligence (Al) model based on the first plurality of quantized weights and the second plurality of quantized weights. Example 22 includes a method of conducting decompression, the method comprising determining whether a plurality of input activations are in a floating point data type format or an integer data type format, conducting a floating point matrix multiplication if the plurality of input activations are in the floating point data type format, wherein the floating point matrix multiplication is conducted based on a plurality of lookup tables corresponding to a plurality of column groups from a weight matrix, and conducting an integer matrix multiplication if the plurality of input activations are in the integer data type format, wherein the integer matrix multiplication is conducted based on the plurality of lookup tables.

[0096] Example 23 includes an apparatus comprising means for performing the method of any one of Examples 21 to 22.

[0097] Embodiments are applicable for use with all types of semiconductor integrated circuit (“IC”) chips. Examples of these IC chips include but are not limited to processors, controllers, chipset components, programmable logic arrays (PLAs), memory chips, network chips, systems on chip (SoCs), SSD / NAND controller ASICs, and the like. In addition, in some of the drawings, signal conductor lines are represented with lines. Some may be different, to indicate more constituent signal paths, have a number label, to indicate a number of constituent signal paths, and / or have arrows at one or more ends, to indicate primary information flow direction. This, however, should not be construed in a limiting manner. Rather, such added detail may be used in connection with one or more exemplary embodiments to facilitate easier understanding of a circuit. Any represented signal lines, whether or not having additional information, may actually comprise one or more signals that may travel in multiple directions and may be implemented with any suitable type of signal scheme, e.g., digital or analog lines implemented with differential pairs, optical fiber lines, and / or single-ended lines.

[0098] Example sizes / models / values / ranges may have been given, although embodiments are not limited to the same. As manufacturing techniques (e.g., photolithography) mature over time, it is expected that devices of smaller size could be manufactured. In addition, well known power / ground connections to IC chips and other components may or may not be shown within the figures, for simplicity of illustration and discussion, and so as not to obscure certain aspects of the embodiments. Further, arrangements may be shown in block diagram form in order to avoid obscuring embodiments, and also in view of the fact that specifics with respect to implementation of such block diagram arrangements are highly dependent upon the computing system within which the embodiment is to be implemented, i.e., such specifics should be well within purview of one skilled in the art. Where specific details (e.g., circuits) are set forth in order to describe example embodiments, it should be apparent to one skilled in the art that embodiments can be practiced without, or with variation of, these specific details. The description is thus to be regarded as illustrative instead of limiting.

[0099] The term “coupled” may be used herein to refer to any type of relationship, direct or indirect, between the components in question, and may apply to electrical, mechanical, fluid, optical, electromagnetic, electromechanical or other connections. In addition, the terms “first”, “second”, etc. may be used herein only to facilitate discussion, and carry no particular temporal or chronological significance unless otherwise indicated.

[0100] As used in this application and in the claims, a list of items joined by the term “one or more of’ may mean any combination of the listed terms. For example, the phrases “one or more of A, B or C” may mean A; B; C; A and B; A and C; B and C; or A, B and C.

[0101] Those skilled in the art will appreciate from the foregoing description that the broad techniques of the embodiments can be implemented in a variety of forms. Therefore, while the embodiments have been described in connection with particular examples thereof, the true scope of the embodiments should not be so limited since other modifications will become apparent to the skilled practitioner upon a study of the drawings, specification, and following claims.

Claims

CLAIMSWe claim:

1. A performance-enhanced computing system comprising: a network controller; a processor coupled to the network controller; and a memory coupled to the processor, the memory including a plurality of compression instructions, which when executed by the processor, cause the processor to: convert a first plurality of source weights from a weight matrix into a first plurality of quantized weights based on a first weight scale factor and a first lookup table, convert a second plurality of source weights from the weight matrix into a second plurality of quantized weights based on a second weight scale factor and a second lookup table, wherein the first plurality of quantized weights and the second plurality of quantized weights are clustered within a quantization range, and generate an output artificial intelligence (Al) model based on the first plurality of quantized weights and the second plurality of quantized weights.

2. The computing system of claim 1 , wherein a data type format corresponding to the first plurality of quantized weights and the second plurality of quantized weights is interpretable as a floating point data type format and an integer data type format.

3. The computing system of claim 2, wherein the memory further includes a plurality of decompression instructions, which when executed by the processor, cause the processor to: determine whether a plurality of input activations are in the floating point data type format or the integer data type format, conduct a floating point matrix multiplication if the plurality of input activations are in the floating point data type format, wherein the floatingpoint matrix multiplication is conducted based on a plurality of lookup tables including the first lookup table and the second lookup table, and conduct an integer matrix multiplication if the plurality of input activations are in the integer data type format, wherein the integer matrix multiplication is conducted based on the plurality of lookup tables.

4. The computing system of claim 1 , wherein the first plurality of quantized weights are clustered around a first plurality of centroids within the quantization range, and wherein the second plurality of quantized weights are clustered around a second plurality of centroids within the quantization range.

5. The computing system of claim 4, wherein the first plurality of centroids and the second plurality of centroids include a subset of fixed centroids.

6. The computing system of claim 5, wherein the subset of fixed centroids includes an upper bound of the quantization range, a lower bound of the quantization range and a midpoint between the upper bound and the lower bound.

7. At least one computer readable storage medium comprising a plurality of compression instructions, which when executed by a computing system, cause the computing system to: convert a first plurality of source weights from a weight matrix into a first plurality of quantized weights based on a first weight scale factor and a first lookup table; convert a second plurality of source weights from the weight matrix into a second plurality of quantized weights based on a second weight scale factor and a second lookup table, wherein the first plurality of quantized weights and the second plurality of quantized weights are clustered within a quantization range; and generate an output artificial intelligence (Al) model based on the first plurality of quantized weights and the second plurality of quantized weights.

8. The at least one computer readable storage medium of claim 7, wherein a data type format corresponding to the first plurality of quantized weightsand the second plurality of quantized weights is interpretable as a floating point data type format and an integer data type format.

9. The at least one computer readable storage medium of claim 7, wherein the first plurality of quantized weights are clustered around a first plurality of centroids within the quantization range, and wherein the second plurality of quantized weights are clustered around a second plurality of centroids within the quantization range.

10. The at least one computer readable storage medium of claim 9, wherein the first plurality of centroids and the second plurality of centroids include a subset of fixed centroids.

11. The at least one computer readable storage medium of claim 10, wherein the subset of fixed centroids includes an upper bound of the quantization range, a lower bound of the quantization range and a midpoint between the upper bound and the lower bound.

12. The at least one computer readable storage medium of any one of claims 7 to 11, wherein the quantization range is [-1.0, 1.0].

13. The at least one computer readable storage medium of claim 7 to 11, wherein the first plurality of source weights corresponds to a first plurality of columns in the weight matrix, and wherein the second plurality of source weights corresponds to a second plurality columns in the weight matrix.

14. At least one computer readable storage medium comprising a plurality of decompression instructions, which when executed by a computing system, cause the computing system to: determine whether a plurality of input activations are in a floating point data type format or an integer data type format; conduct a floating point matrix multiplication if the plurality of input activations are in the floating point data type format, wherein the floating point matrixmultiplication is conducted based on a plurality of lookup tables corresponding to a plurality of column groups from a weight matrix; and conduct an integer matrix multiplication if the plurality of input activations are in the integer data type format, wherein the integer matrix multiplication is conducted based on the plurality of lookup tables.

15. The least one computer readable storage medium of claim 14, wherein one or more of the floating point matrix multiplication or the integer matrix multiplication are conducted with respect to a first plurality of quantized weights, a second plurality of quantized weights, and the plurality of input activations, and wherein the first plurality of quantized weights and the second plurality of quantized weights are clustered within a quantization range.

16. The least one computer readable storage medium of claim 15, wherein the quantization range is [-1.0, 1.0].

17. The least one computer readable storage medium of any one of claims 14 to 16, wherein the floating point matrix multiplication is conducted further based on a plurality of weight scale factors corresponding to the plurality of column groups.

18. The least one computer readable storage medium of any one of claims 14 to 16, wherein the integer matrix multiplication is conducted further based on a plurality of weight scale factors corresponding to the plurality of column groups, a fixed scale factor, and an activation scale factor associated with the plurality of input activations.

19. The least one computer readable storage medium of claim 18, wherein the fixed scale factor is associated with an integer range.

20. The least one computer readable storage medium of claim 19, wherein the integer range is [-127, 127].

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