Shift register, driving circuit, driving method, and display device

Abstract

The present disclosure relates to the technical field of display, and provides a shift register, a driving circuit, a driving method, and a display device. The shift register comprises: a gating circuit configured to provide a gating signal to a first node under the control of a first input signal from a first input end and a second input signal from a second input end; a control circuit configured to, under the control of the potential of the first node, use a first power supply voltage of a first power supply, a second power supply voltage of a second power supply, a third input signal from a third input end, a first clock signal from a first clock end, a second clock signal from a second clock end and a third clock signal from a third clock end to control the potential of a second node and the potential of a third node; and an output circuit configured to, under the control of the potential of the second node and the potential of the third node, provide the second power supply voltage or the third clock signal to a first output end to serve as a first output signal, wherein the gating signal controls the output of the first output signal.

Description

Shift register, driving circuit, driving method and display device TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to a shift register, a driving circuit, a driving method and a display device. BACKGROUND

[0002] In order to achieve good compatibility in power consumption and high refresh rate, a display product usually adopts a region refresh technology, which requires the driving circuit of the display product to have the ability of flexible opening. When the scanning signal required by the pixel circuit of the display product includes multiple pulses, the region refresh technology is difficult to implement.

[0003] SUMMARY

[0004] To solve the above problems, the present disclosure provides a shift register, a driving circuit, a driving method and a display device.

[0005] According to a first aspect, the present disclosure provides a shift register, comprising: a gating circuit configured to provide a gate signal from a gating terminal to a first node under the control of a first input signal from a first input terminal and a second input signal from a second input terminal; a control circuit configured to control the potential of a second node and a third node by using a first power supply voltage of a first power supply, a second power supply voltage of a second power supply, a third input signal from a third input terminal, a first clock signal from a first clock terminal, a second clock signal from a second clock terminal and a third clock signal from a third clock terminal under the control of the potential of the first node; and an output circuit configured to provide the second power supply voltage or the third clock signal to a first output terminal as a first output signal under the control of the potential of the second node and the potential of the third node, wherein the gate signal controls the output of the first output signal.

[0006] According to a second aspect, the present disclosure provides a driving circuit, comprising M shift registers provided by the embodiments of the present disclosure connected in cascade, M being an integer greater than 1.

[0007] According to a third aspect, the present disclosure provides a display device comprising the driving circuit provided by the embodiments of the present disclosure.

[0008] According to a fourth aspect, the present disclosure provides a driving method applied to any one of the shift registers provided by the embodiments of the present disclosure, comprising: controlling the gate signal to be a first level in a gating phase; and controlling the gate signal to be a second level in a non-gating phase. BRIEF DESCRIPTION OF DRAWINGS

[0009] FIG. 1 is a structural schematic diagram of a shift register according to an embodiment of the present disclosure;

[0010] FIG. 2 is a structural schematic diagram of a shift register according to another embodiment of the present disclosure;

[0011] FIG. 3 is a structural schematic diagram of a shift register according to another embodiment of the present disclosure;

[0012] FIG. 4 is a structural schematic diagram of a shift register according to another embodiment of the present disclosure;

[0013] FIG. 5A is a signal timing diagram of a shift register according to an embodiment of the present disclosure;

[0014] FIG. 5B is a simulation schematic diagram of a voltage in a shift register according to an embodiment of the present disclosure;

[0015] FIG. 6A is a signal timing diagram of a shift register according to an embodiment of the present disclosure;

[0016] FIG. 6B is a simulation schematic diagram of a voltage in a shift register according to an embodiment of the present disclosure;

[0017] FIG. 7 is a structural schematic diagram of a shift register according to another embodiment of the present disclosure;

[0018] FIG. 8 is a structural schematic diagram of a shift register according to another embodiment of the present disclosure;

[0019] FIG. 9 is a structural schematic diagram of a shift register according to another embodiment of the present disclosure;

[0020] FIG. 10 is a structural schematic diagram of a shift register according to another embodiment of the present disclosure;

[0021] FIG. 11 is a structural schematic diagram of a shift register according to another embodiment of the present disclosure;

[0022] FIG. 12 is a structural schematic diagram of a driving circuit according to an embodiment of the present disclosure;

[0023] FIG. 13A is a structural schematic diagram of a driving circuit according to another embodiment of the present disclosure;

[0024] FIG. 13B is a structural schematic diagram of a driving circuit according to another embodiment of the present disclosure;

[0025] FIG. 13C is a structural schematic diagram of a driving circuit according to another embodiment of the present disclosure;

[0026] FIG. 13D is a structural schematic diagram of a driving circuit according to another embodiment of the present disclosure;

[0027] FIG. 14A is a signal timing diagram of a driving circuit according to an embodiment of the present disclosure;

[0028] FIG. 14B is a signal timing diagram of a driving circuit according to another embodiment of the present disclosure;

[0029] FIG. 15 is a structural schematic diagram of a display device according to an embodiment of the present disclosure; and

[0030] FIG. 16 is a flowchart of a driving method according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0031] For the purpose of making the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all. Based on the described embodiments of the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative effort belong to the scope of protection of the present disclosure. It should be noted that throughout the drawings, the same elements are denoted by the same or similar reference numerals. In the following description, some specific embodiments are used only for the purpose of description, and should not be understood as any limitation on the present disclosure, but only as examples of the embodiments of the present disclosure. When it is possible to cause confusion to the understanding of the present disclosure, the conventional structures or configurations will be omitted. It should be noted that the shapes and sizes of the components in the drawings do not reflect the true size and ratio, but only illustrate the content of the embodiments of the present disclosure.

[0032] Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should be understood as the general meaning understood by a person of ordinary skill in the art. The terms “first”, “second” and the like used in the embodiments of the present disclosure do not represent any order, number or importance, but are only used to distinguish different components.

[0033] In addition, in the description of the embodiments of the present disclosure, the term “connected” or “connected to” can mean that two components are directly connected, or can mean that two components are connected via one or more other components. In addition, the two components can be connected or coupled by wired or wireless means.

[0034] The source and drain of the switching transistor used in the embodiments of the present disclosure are symmetrical, so the source and drain thereof can be interchangeable. In the embodiments of the present disclosure, according to its function, the gate can be called a control electrode, one of the source and drain can be called a first electrode, and the other of the source and drain can be called a second electrode.

[0035] In addition, in the description of the embodiments of the present disclosure, the terms “first power supply voltage” and “second power supply voltage” are only used to distinguish the amplitudes of the two power supply voltages. For example, the following description is described by taking “first power supply voltage” as a relatively high voltage, and “second power supply voltage” and “third power supply voltage” as relatively low voltages. A person of ordinary skill in the art can understand that the present disclosure is not limited thereto.

[0036] It should be noted that in the description of the embodiments of the present disclosure, INPUT1 can represent both a first input signal terminal and a first input signal provided by a first input terminal. Similarly, CK1 can represent both a first clock terminal and a first clock signal provided by the first clock terminal, OUT1 can represent both a first output terminal and a first output signal output by the first output terminal, and VGH and VGL can represent both a power terminal and a power voltage provided by the power terminal. For example, the power VGH can provide a high-level voltage, and the power VGL can provide a low-level voltage. The following embodiments are the same as this, and will not be described again.

[0037] FIG. 1 is a structural schematic diagram of a shift register according to an embodiment of the present disclosure.

[0038] As shown in FIG. 1, the shift register 100 includes a gating circuit 110, a control circuit 120, and an output circuit 130.

[0039] In the embodiment of the present disclosure, the gating circuit 110 is electrically connected with a first input terminal INPUT1, a second input terminal INPUT2, and a gating terminal MS. Under the control of a first input signal INPUT1 from the first input terminal INPUT1 and a second input signal INPUT2 from the second input terminal INPUT2, the gating circuit 110 provides a gate signal MS from the gating terminal MS to a first node N1.

[0040] For example, the first input signal INPUT1 and the second input signal INPUT2 jointly control the gating circuit 110 to switch between a conductive state and a non-conductive state. When the first input signal INPUT1 and the second input signal INPUT2 jointly control the gating circuit 110 to be in the conductive state, the gate signal MS is written to the first node N1. When the first input signal INPUT1 and the second input signal INPUT2 jointly control the gating circuit 110 to be in the non-conductive state, the potential of the first node N1 can maintain the state of the previous stage.

[0041] In the embodiment of the present disclosure, the control circuit 120 is electrically connected with a first power VGL, a second power VGH, a third input terminal INPUT3, a first clock terminal CK1, a second clock terminal CK2, and a third clock terminal CK3. Under the control of the potential of the first node N1, the control circuit 120 controls the potentials of a second node N2 and a third node N3 by using a first power voltage VGL of the first power VGL, a second power voltage VGH of the second power VGH, a third input signal INPUT3 from the third input terminal INPUT3, a first clock signal CK1 from the first clock terminal CK1, a second clock signal CK2 from the second clock terminal CK2, and a third clock signal CK3 from the third clock terminal CK3.

[0042] For example, the potential of the first node N1, the first power voltage VGL, and the first clock signal CK1 can control the second clock signal CK2 and the second node N2 to be in a communication state or a cutoff state. When the second clock signal CK2 and the second node N2 are in the communication state, the control circuit 120 provides the second clock signal CK2 to the second node N2 to control the potential of the second node N2.

[0043] For example, the potential of the first node N1, the first power voltage VGL, the third clock signal CK3, and the second clock signal CK2 can control the second power VGH and the third node N3 to be in a communication state or a cutoff state. When the second power VGH and the third node N3 are in the communication state, the control circuit 120 provides the second power voltage VGH to the third node N3 to control the potential of the third node N3.

[0044] For example, the potential of the first node N1 and the second clock signal CK2 can control the first power VGL and the second node N2 to be in a communication state or a cutoff state. When the first power VGL and the second node N2 are in the communication state, the control circuit 120 provides the first power voltage VGL to the second node N2 to control the potential of the second node N2.

[0045] For example, the potential of the first node N1, the third input terminal INPUT3, and the first clock signal CK1 can control the second clock signal CK2 and the second node N2 to be in a communication state or a cutoff state. When the second clock signal CK2 and the second node N2 are in the communication state, the control circuit 120 provides the second clock signal CK2 to the second node N2 to control the potential of the second node N2.

[0046] In the embodiment of the present disclosure, the output circuit 130 is electrically connected with the second power VGH and the third clock terminal CK3. Under the control of the potential of the second node N2 and the potential of the third node N3, the output circuit 130 provides the second power voltage VGH or the third clock signal CK3 to the first output terminal OUT1 as the first output signal OUT1.

[0047] For example, the potential of the second node N2 can control the second power VGH and the first output terminal OUT1 to be in a communication state or a cutoff state. When the second power VGH and the first output terminal OUT1 are in the communication state, the output circuit 130 provides the second power voltage VGH to the first output terminal OUT1, and the first output terminal OUT1 outputs a high-level signal.

[0048] For example, the potential of the third node N3 can control the third clock terminal CK3 and the first output terminal OUT1 to be in a communication state or a cutoff state. When the third clock terminal CK3 and the first output terminal OUT1 are in the communication state, the output circuit 130 provides the third clock signal CK3 to the first output terminal OUT1, and the first output terminal OUT1 outputs a low high-level signal.

[0049] In the embodiment of the present disclosure, the first input signal OUT1 can be a scanning signal for driving the P-type transistor in the pixel circuit. For example, when the level of the first input signal OUT is low, the P-type transistor is turned on, and the data signal can be written, so as to realize picture refresh. When the level of the first input signal OUT is high, the P-type transistor is cut off, and the data signal cannot be written, so as to realize picture non-refresh and keep unchanged.

[0050] In the embodiment of the present disclosure, the gate signal MS controls the potential of the first node N1, thereby realizing the control of the potentials of the second node N2 and the third node N3. Based on the potential of the second node N2 and the potential of the third node N3, the first output terminal OUT1 can be controlled to output a high-level signal or a low-level signal, thereby controlling whether the transistor in the pixel circuit is turned on or not, realizing picture refresh or picture keeping.

[0051] For example, the level of the gate signal MS indicates whether the transistor in the pixel circuit electrically connected to the shift register 100 is turned on or not. For example, when the gate signal MS is high, the first output signal OUT1 output by the first output terminal OUT1 always keeps high. At this time, the P-type transistor in the pixel circuit always keeps in the cutoff state, and the corresponding display picture is not refreshed. When the gate signal MS is low, the level of the first output signal OUT1 output by the first output terminal OUT1 is switched between high and low. At this time, the P-type transistor in the pixel circuit is switched to the communication state based on the low-level first output signal OUT, and the corresponding display picture is refreshed.

[0052] In the embodiment of the present disclosure, the first input signal INPUT1 and the third input signal INPUT3 are multi-pulse signals. The multi-pulse signal can be understood as a signal including multiple pulses, for example, in the process of refreshing a frame of display picture, the scanning signal with multiple pulses can turn on the transistor in a row of pixel circuits multiple times.

[0053] Therefore, when the display picture is refreshed by using the first input signal OUT1, the first input signal OUT1 is also a multi-pulse signal. When the display picture is not refreshed by using the first input signal OUT1, the first input signal OUT1 has no pulse, and the level can be kept constant as high.

[0054] In the embodiments of the present disclosure, the plurality of cascaded shift registers 100 can drive a plurality of pixel rows in a pixel array. For example, the plurality of first output signals output by the plurality of cascaded shift registers 100 are sequentially shifted in low level.

[0055] When the plurality of cascaded shift registers 100 perform line-by-line scanning on the plurality of pixel rows, the level of the gate signal MS can jump. For example, the plurality of cascaded shift registers 100 can include 1000 shift registers. When the first 500 shift registers sequentially output the first output signals, the gate signal MS is in low level, and at this time, the first 500 shift registers sequentially output the first output signals to refresh the first 500 pixel rows in the pixel circuit. When the last 500 shift registers sequentially output the first output signals, the level of the gate signal MS jumps from high level to low level, and at this time, the level of the first output signals output by the last 500 shift registers is always high, and the last 500 pixel rows in the pixel circuit are not refreshed.

[0056] For example, when the 1000 first output signals output by the 1000 shift registers are all double-pulse signals, the time of the level jump of the gate signal MS can be after the first pulse is output by the 501st shift register. At this time, the 501st shift register has output the first pulse, but cannot output the second pulse. In this case, the 501st pixel row in the pixel circuit will have a display abnormality problem.

[0057] The double-pulse of the first output signals output by the plurality of shift registers is sequentially shifted. For example, after the first pulse is output by the mth shift register, the first pulse is output by the m+1th shift register. After the first pulse is output by the m+1th shift register, the second pulse is output by the mth shift register. Therefore, the time of the level jump of the gate signal MS is always after the first pulse is output by a certain shift register, which causes the corresponding pixel row of the shift register to have a display abnormality.

[0058] Based on the above problems, in the shift register provided by the present disclosure, the gate circuit 110 controls the potential of the first node N1 by using the first input signal INPUT1 and the second input signal INPUT2. In this case, after the level of the gate signal MS jumps, the level of the gate signal MS after the jump is not immediately written to the first node N1 to change the level of the first output signal OUT1 output by the first output terminal OUT1. This ensures that for the first output signal with multiple pulses, after the level of the gate signal MS jumps, none of the shift registers will output the first output signal with only the first pulse, thereby ensuring the normal display of the display picture.

[0059] FIG. 2 is a structural schematic diagram of a shift register according to another embodiment of the present disclosure.

[0060] As shown in FIG. 2, the shift register 200 includes a gating circuit 210, a control circuit 220, and an output circuit 230. The gating circuit 210 includes a gating unit 211 and a reset unit 212, the control circuit 220 includes a first control unit 221 and a second control unit 222, and the output circuit 230 includes a first output unit 231 and a second output unit 232.

[0061] In the embodiment of the present disclosure, the reset unit 212 of the gating circuit 210 is electrically connected with the fourth input terminal INPUT4, the first node N1, and the first power supply VGL. The gating unit 211 is electrically connected with the gate terminal MS, the first input terminal INPUT1, and the second input terminal INPUT2.

[0062] Under the control of the first input signal INPUT1 and the second input signal INPUT2, the gating unit 211 provides the gate signal MS to the first node N1. Under the control of the fourth input signal INPUT4 from the fourth input terminal INPUT4, the reset unit 212 controls the potential of the first node N1 by using the first power supply voltage VGL.

[0063] In the embodiment of the present disclosure, under the control of the fourth input signal INPUT4, the reset unit 212 resets the potential of the first node N1 by using the first power supply voltage VGL, and pulls down the potential of the first node N1.

[0064] For example, based on the fourth input terminal INPUT4, the reset unit 212 can control the first power supply VGL to be in a connected state or a cut-off state with the first node N1. When the first power supply VGL is in the connected state with the first node N1, the reset unit 212 provides the first power supply voltage VGL to the fourth node N4.

[0065] For example, when the potential of the first node N1 is high, the first output signal OUT1 output by the output circuit 230 does not refresh the corresponding pixel row. After the display picture refreshes a frame of picture, the reset unit 212 pulls down the potential of the first node N1 again, so that the gate signal MS controls the potential of the first node N1 again during the refresh process of the next frame of picture. When the potential of the first node N1 is low after the display picture refreshes a frame of picture, the reset unit 212 also writes the first power supply voltage VGL to the first node N1, so as to ensure that the potential of the first node N1 is stably kept at a low potential. Based on the reset unit 212 resetting the potential of the first node N1, the working stability of the circuit can be improved.

[0066] In the embodiment of the present disclosure, the first control unit 221 is electrically connected with the first node N1, the first clock terminal CK1, the second clock terminal CK2, the third input terminal INPUT3, the first power supply VGL and the second node N2. Under the control of the potential of the first node N1, the second clock signal CK2, the third input signal INPUT3 and the first clock signal CK1, the first control unit 221 provides at least one of the first power supply voltage and the second clock signal to the second node N2.

[0067] For example, based on the potential of the first node N1 and the second clock signal CK2, the first control unit 221 can control the first power supply VGL and the second node N2 to be in a communication state or a cutoff state. Based on the potential of the first node N1, the third input signal INPUT3 and the first clock signal CK1, the first control unit 221 can control the second clock terminal CK2 and the second node N2 to be in a communication state or a cutoff state.

[0068] When the first power supply VGL and the second node N2 are in a communication state, the first control unit 221 provides the first power supply voltage VGL to the second node N2. Or when the second clock terminal CK2 and the second node N2 are in a communication state, the first control unit 221 provides the second clock signal CK2 to the second node N2. Or when the first power supply VGL and the second node N2 are in a communication state and the second clock terminal CK2 and the second node N2 are in a communication state, the first control unit 221 provides the first power supply voltage VGL and the second clock signal CK2 to the second node N2.

[0069] In the embodiment of the present disclosure, the second control unit 222 is electrically connected with the first node N1, the first clock terminal CK1, the second clock terminal CK2, the third input terminal INPUT3, the first power supply VGL, the second node N2 and the second power supply VGH. Under the control of the potential of the first node N1, the first power supply voltage VGL, the first clock signal CK1, the second clock signal CK2 and the third clock signal CK3, the second control unit 222 provides at least one of the second power supply voltage VGH and the third input terminal INPUT3 to the third node N3.

[0070] For example, based on the potential of the first node N1, the second clock signal CK2, the third clock signal CK3 and the first power supply voltage VGL, the second control unit 222 can control the third input terminal INPUT3 and the third node N3 to be in a communication state or a cutoff state. Based on the potential of the first node N1, the first power supply voltage VGL, the third input signal INPUT3 and the first clock signal CK1, the second control unit 222 can control the second power supply VGH and the third node N3 to be in a communication state or a cutoff state.

[0071] When the third input terminal INPUT3 is in a conductive state with the third node N3, the second control unit 222 supplies the third input terminal INPUT3 to the third node N3. Or when the second power supply VGH is in a conductive state with the third node N3, the second control unit 222 supplies the second power supply VGH to the third node N3. Or when the third input terminal INPUT3 is in a conductive state with the third node N3 and the second power supply VGH is in a conductive state with the third node N3, the second control unit 222 supplies the third input terminal INPUT3 and the second power supply VGH to the third node N3.

[0072] In the embodiment of the present disclosure, the control circuit 220 is electrically connected with the first power supply VGL and the third node N3. Under the control of the potential of the third node N3 or the first power supply voltage VGL, the control circuit 220 can also control the potential of the first node N1.

[0073] For example, under the control of the potential of the third node N3 or the first power supply voltage VGL, the control circuit 220 can store the level of the strobe signal MS to stabilize the potential of the first node N1, and can stably control the first control unit 221 and the second control unit 222 based on the potential of the first node N1, so that the first control unit 221 and the second control unit 222 can stably control the potentials of the second node N2 and the third node N3, thereby ensuring that the first output terminal OUT1 stably outputs the first output signal OUT1.

[0074] In the embodiment of the present disclosure, the first output unit 231 is electrically connected with the second node N2, the second power supply VGH and the first output terminal OUT1. The second output unit 232 is electrically connected with the third node N3, the third clock terminal CK3 and the first output terminal OUT1.

[0075] The first control unit 221 can pull down the potential of the second node N2, so that under the control of the low potential of the second node N2, the first output unit 231 controls the second power supply VGH to be in a conductive state with the first output terminal OUT1, and the output terminal OUT outputs a high-level signal. The first control unit 221 can pull up the potential of the second node N2, so that under the control of the high potential of the second node N2, the first output unit 231 controls the second power supply VGH to be in an off state with the first output terminal OUT1.

[0076] The second control unit 222 can pull down the potential of the third node N3, so that under the control of the low potential of the third node N3, the second output unit 232 controls the third clock terminal CK3 to be in communication with the first output terminal OUT1, and the output terminal OUT outputs a high level signal. The second control unit 222 can pull up the potential of the third node N3, so that under the control of the high potential of the third node N3, the second output unit 232 controls the third clock terminal CK3 to be cut off from the first output terminal OUT1.

[0077] In the embodiment of the present disclosure, the gating unit 211 controls the potential of the first node N1 by using the first output signal INPUT1 and the second output signal INPUT2 jointly, which can avoid the first output signal OUT1 output by the first output terminal OUT1 only having part of pulse, thereby affecting the display picture. The potential of the first node N1 is pulled down and reset by the reset unit 212, which can improve the working stability of the circuit. In addition, the control circuit 220 stabilizes the potential of the first node N1, which can improve the working stability of the gating circuit 210.

[0078] FIG. 3 is a structural schematic diagram of a shift register according to another embodiment of the present disclosure.

[0079] As shown in FIG. 3, the shift register 300 includes a gating circuit 310, a control circuit 320, an output circuit 330, and a shift circuit 340.

[0080] In the embodiment of the present disclosure, the gating circuit 310, the control circuit 320, and the output circuit 330 are similar to the gating circuit 110, the control circuit 120, and the output circuit 130 described above, respectively, and will not be described again for simplicity.

[0081] In the embodiment of the present disclosure, the shift circuit 340 is connected to the first clock terminal CK1, the second clock terminal CK2, the third clock terminal CK3, the first power supply VGL, the second power supply VGH, and the third input terminal INPUT3.

[0082] Under the control of the second clock signal CK2, the third input signal INPUT3, and the first clock signal CK1, the shift circuit 340 provides at least one of the first power supply voltage VGL and the second clock signal CK2 to the fourth node N4. Under the control of the first clock signal CK1, the first power supply voltage VGL, the third clock signal CK3, and the potential of the fourth node N4, the shift circuit 340 provides at least one of the third input signal INPUT3 and the second power supply voltage VGH to the fifth node N5. Under the control of the potential of the fourth node N4 and the potential of the fifth node N5, the shift circuit 340 provides the second power supply voltage VGH or the third clock signal CK3 to the second output terminal OUT2 as the second output signal OUT2.

[0083] In the embodiment of the present disclosure, the shift circuit 340 can control the first power supply VGL and the fourth node N4 to be in a communication state or a cutoff state based on the second clock signal CK2. The shift circuit 340 can control the second clock terminal CK2 and the fourth node N4 to be in a communication state or a cutoff state based on the potential of the fifth node N5.

[0084] When the first power supply VGL and the fourth node N4 are in a communication state, the shift circuit 340 provides the first power supply voltage VGL to the fourth node N4. Or when the second clock terminal CK2 and the fourth node N4 are in a communication state, the shift circuit 340 provides the second clock signal CK2 to the fourth node N4. Or when the first power supply VGL and the fourth node N4 are in a communication state and the second clock terminal CK2 and the fourth node N4 are in a communication state, the shift circuit 340 provides the first power supply voltage VGL and the second clock signal CK2 to the fourth node N4.

[0085] In the embodiment of the present disclosure, the shift circuit 340 can control the third input terminal INPUT3 and the fifth node N5 to be in a communication state or a cutoff state based on the first clock signal CK1 and the first power supply VGL. The shift circuit 340 can control the second power supply VGH and the fifth node N5 to be in a communication state or a cutoff state based on the potential of the fourth node N4 and the third clock signal CK3.

[0086] When the third input terminal INPUT3 and the fifth node N5 are in a communication state, the shift circuit 340 provides the third input signal INPUT3 to the fifth node N5. Or when the second power supply VGH and the fifth node N5 are in a communication state, the shift circuit 340 provides the second power supply voltage VGH to the fifth node N5. Or when the third input terminal INPUT3 and the fifth node N5 are in a communication state and the second power supply VGH and the fifth node N5 are in a communication state, the shift circuit 340 provides the third input signal INPUT3 and the second power supply voltage VGH to the fifth node N5.

[0087] Under the control of the potential of the first node N1, the control circuit 320 provides the potential of the fourth node N4 to the second node N2 and provides the potential of the fifth node N5 to the third node N3.

[0088] In the embodiment of the present disclosure, the second output signal OUT2 output by the second input terminal OUT2 is provided to other shift registers cascaded with the shift register 300, for realizing shift driving of the cascaded plurality of shift registers.

[0089] For example, the shift register 300 can be an mth stage shift register, the second output signal OUT2 can be provided to at least one of the first input and the second input of an (m+1)th stage shift register, and the second output signal OUT2 can be provided to at least one of the first input and the second input of an (m+2)th stage shift register.

[0090] FIG. 4 is a structural schematic diagram of a shift register according to another embodiment of the present disclosure.

[0091] In the embodiment of the present disclosure, the shift register 400 includes a gating circuit 410, a control circuit 420, an output circuit 430, and a shift circuit 440.

[0092] In the embodiment of the present disclosure, the control circuit 420 includes a first transistor T1, a second transistor T2, and a first capacitor C1, the gating circuit 410 includes a third transistor T3 to a fifth transistor T5, the output circuit 430 includes a sixth transistor T6, a seventh transistor T7, a second capacitor C2, and a third capacitor C3, and the shift circuit 440 includes an eighth transistor T8 to a fifteenth transistor T15, a fourth capacitor C4, and a fifth capacitor C5.

[0093] The control electrode of the first transistor T1 is electrically connected to the first node N1, the first electrode of the first transistor T1 is electrically connected to the fifth node N5, and the second electrode of the first transistor T1 is electrically connected to the third node N3.

[0094] The control electrode of the second transistor T2 is electrically connected to the first node N1, the first electrode of the second transistor T2 is electrically connected to the first power supply VGL, and the second electrode of the second transistor T2 is electrically connected to the second node N2.

[0095] The first end of the first capacitor C1 is electrically connected to the third node N3, and the second end of the first capacitor C1 is electrically connected to the first node N1.

[0096] The control electrode of the third transistor T3 is electrically connected to the second input end INPUT2, the first electrode of the third transistor T3 is electrically connected to the first node N1, and the second electrode of the third transistor T3 is electrically connected to the sixth node N6.

[0097] The control electrode of the fourth transistor T4 is electrically connected to the first input end INPUT1, the first electrode of the fourth transistor T4 is electrically connected to the sixth node N6, and the second electrode of the fourth transistor T4 is electrically connected to the gating end MS.

[0098] The control electrode of the fifth transistor T5 is electrically connected to the fourth input end INPUT4, the first electrode of the fifth transistor T5 is electrically connected to the first node N1, and the second electrode of the fifth transistor T5 is electrically connected to the first power supply VGL.

[0099] The control electrode of the sixth transistor T6 is electrically connected to the second node N2, the first electrode of the sixth transistor T6 is electrically connected to the second power supply VGH, and the second electrode of the sixth transistor T6 is electrically connected to the first output terminal INPUT1.

[0100] The control electrode of the seventh transistor T7 is electrically connected to the third node N3, the first electrode of the seventh transistor T7 is electrically connected to the first output terminal INPUT1, and the second electrode of the seventh transistor T7 is electrically connected to the third clock terminal CK3.

[0101] The first terminal of the second capacitor C2 is electrically connected to the second power supply VGH, and the second terminal of the second capacitor C2 is electrically connected to the second node N2.

[0102] The first terminal of the third capacitor C2 is electrically connected to the first output terminal INPUT1, and the second terminal of the third capacitor C2 is electrically connected to the third node N3.

[0103] The control electrode of the eighth transistor T8 is electrically connected to the first power supply VGL, the first electrode of the eighth transistor T8 is electrically connected to the seventh node N7, and the second electrode of the eighth transistor T8 is electrically connected to the fifth node N5.

[0104] The control electrode of the ninth transistor T9 is electrically connected to the fourth node N4, the first electrode of the ninth transistor T9 is electrically connected to the second power supply VGH, and the second electrode of the ninth transistor T9 is electrically connected to the eighth node N8.

[0105] The control electrode of the tenth transistor T10 is electrically connected to the third clock terminal CK3, the first electrode of the tenth transistor T10 is electrically connected to the eighth node N8, and the second electrode of the tenth transistor T10 is electrically connected to the seventh node N7.

[0106] The control electrode of the eleventh transistor T11 is electrically connected to the third clock terminal CK3, the first electrode of the eleventh transistor T11 is electrically connected to the third output terminal INPUT3, and the second electrode of the eleventh transistor T11 is electrically connected to the seventh node N7.

[0107] The control electrode of the twelfth transistor T12 is electrically connected to the seventh node N7, the first electrode of the twelfth transistor T12 is electrically connected to the fourth node N4, and the second electrode of the twelfth transistor T12 is electrically connected to the second clock terminal CK2.

[0108] The control electrode of the thirteenth transistor T13 is electrically connected to the first power supply VGL, the first electrode of the thirteenth transistor T13 is electrically connected to the third output terminal INPUT3, and the second electrode of the thirteenth transistor T13 is electrically connected to the fourth node N4.

[0109] The control electrode of the fourteenth transistor T14 is electrically connected to the fourth node N4, the first electrode of the fourteenth transistor T14 is electrically connected to the second power supply VGH, and the second electrode of the fourteenth transistor T14 is electrically connected to the second output terminal OUT2.

[0110] The control electrode of the fifteenth transistor T15 is electrically connected to the fifth node N5, the first electrode of the fifteenth transistor T15 is electrically connected to the second output terminal OUT2, and the second electrode of the fifteenth transistor T15 is electrically connected to the third clock terminal CK3.

[0111] The first terminal of the fourth capacitor C4 is electrically connected to the second power supply VGH, and the second terminal of the fourth capacitor C4 is electrically connected to the fourth node N4.

[0112] The first terminal of the fifth capacitor C5 is electrically connected to the second output terminal OUT2, and the second terminal of the fifth capacitor C5 is electrically connected to the fifth node N5.

[0113] In the embodiments of the present disclosure, the first transistor T1 to the fifteenth transistor T15 are P-type TFT transistors. For example, the active layer is a low-temperature doped polysilicon (LTPS) thin film transistor. Those skilled in the art can understand that the first transistor T1 to the fifteenth transistor T15 in the present disclosure can also be N-type TFT transistors, for example, the active layer is an indium gallium zinc oxide (IGZO) thin film transistor, and the corresponding gate drive signal level of each transistor can be changed. It should be noted that.

[0114] In addition, those skilled in the art can understand that the storage capacitor can be realized as a single capacitor or a plurality of parallel or series capacitor units, as long as it can realize its corresponding function.

[0115] In the description of the embodiments of the present disclosure, the first node N1 to the eighth node N8 do not represent actual components, but represent the convergence points of the relevant circuit connections in the circuit diagram.

[0116] FIG. 5A is a signal timing diagram of a shift register according to an embodiment of the present disclosure, and FIG. 5B is a simulation diagram of voltages in the shift register according to an embodiment of the present disclosure. FIG. 6A is a signal timing diagram of a shift register according to an embodiment of the present disclosure, and FIG. 6B is a simulation diagram of voltages in the shift register according to an embodiment of the present disclosure.

[0117] FIG. 5A and FIG. 5B show that the first output signal OUT1 output by the shift register 400 can control the corresponding pixel row to be refreshed, and FIG. 6A and FIG. 6B show that the first output signal OUT1 output by the shift register 400 can control the corresponding pixel row not to be refreshed.

[0118] The working process of the shift register provided in the embodiments of the present disclosure is described below with the structure of the shift register 400 shown in FIG. 4 as an example, in combination with the signal timing diagrams shown in FIG. 5A, FIG. 5B, FIG. 6A and FIG. 6B. The working process of the shift register 400 is divided into six time periods.

[0119] As shown in FIG. 5A, the strobe signal MS is at a low level, and at this time, the first output signal OUT1 output by the shift register 400 can control the refresh of the corresponding pixel row.

[0120] In the first time period P1, the first clock signal CK1 is at a low level, the second clock signal CK2 is at a high level, the third clock signal CK3 is at a high level, the first input signal INPUT1 is at a low level, the second input signal INPUT2 is at a low level, the third input signal INPUT3 is at a low level, and the fourth input signal INPUT4 is at a high level.

[0121] The eleventh transistor T11 and the eighth transistor T8 are turned on, and the thirteenth transistor T13 is turned off. The third input signal INPUT3 is written into the seventh node N7 and the fifth node N5 through the eleventh transistor T11 and the eighth transistor T8, and the potential of the seventh node N7 and the fifth node N5 is pulled low, at this time, the twelfth transistor T12 and the fifteenth transistor T15 are turned on. The second clock signal CK2 is written into the fourth node N4, and the potential of the fourth node N4 is pulled high, at this time, the fourteenth transistor T14 is turned off. The third clock signal CK3 is written into the second output end OUT2 through the fifteenth transistor T15, and the second output end OUT2 outputs a high level signal.

[0122] The third transistor T3 and the fourth transistor T4 are turned on, the strobe signal MS is written into the first node N1, and the potential of the first node N1 is pulled low, at this time, the second transistor T2 and the first transistor T11 are turned on, and the first capacitor C1 stores a low level. The potential of the fourth node N4 is written into the second node N2, and the potential of the fifth node N5 is written into the third node N3. The sixth transistor T6 is turned off, and the seventh transistor T7 is turned on. At this time, the third clock signal CK3 is written into the first output end OUT1 through the seventh transistor T7, and the first output end OUT1 outputs a high level signal.

[0123] In the second time period P2, the first clock signal CK1 is at a high level, the second clock signal CK2 is at a low level, the third clock signal CK3 is at a high level, the first input signal INPUT1 is at a high level, the second input signal INPUT2 is at a low level, the third input signal INPUT3 is at a high level, and the fourth input signal INPUT4 is at a high level.

[0124] The eleventh transistor T11 is turned off, and the thirteenth transistor T13 is turned on. The first power supply voltage VGL is written into the fourth node N4 through the thirteenth transistor T13, and the potential of the fourth node N4 is pulled low. At this time, the ninth transistor T9 and the fourteenth transistor T14 are turned on. The second power supply voltage VGH is written into the eighth node N8 through the ninth transistor T9, and the potential of the eighth node N8 is high. The second power supply voltage VGH is written into the second output terminal OUT2 through the fourteenth transistor T14, and the second output terminal OUT2 outputs a high level signal.

[0125] The third transistor T3 is turned off, and the fourth transistor T4 is turned on. Under the control of the low level stored in the first capacitor C1, the first node N1 remains low, and the second transistor T2 and the first transistor T11 are turned on. The potential of the fourth node N4 is written into the second node N2, and the potential of the fifth node N5 is written into the third node N3. The sixth transistor T6 is turned on, and the seventh transistor T7 is turned off. At this time, the second power supply voltage VGH is written into the first output terminal OUT1 through the sixth transistor T6, and the first output terminal OUT1 outputs a high level signal.

[0126] In the third period P3, the first clock signal CK1 is high, the second clock signal CK2 is high, the third clock signal CK3 is low, the first input signal INPUT1 is high, the second input signal INPUT2 is low, the third input signal INPUT3 is high, and the fourth input signal INPUT4 is high.

[0127] The eleventh transistor T11 and the thirteenth transistor T13 are turned off, and the potential of the seventh node N7 remains low as in the previous stage. The twelfth transistor T12 is turned on, and the second clock signal CK2 is written into the fourth node N4 through the twelfth transistor T12. At this time, the fourteenth transistor T14 is turned off, and the fifteenth transistor T15 is turned on. The tenth transistor T10 is turned on, and the potential of the seventh node N7 is written into the eighth node N8 through the tenth transistor T10, and the potential of the eighth node N8 is pulled low. The third clock signal CK3 is written into the second output terminal OUT2 through the fifteenth transistor T15, and the second output terminal OUT2 outputs a low level signal.

[0128] The third transistor T3 is turned off, and the fourth transistor T4 is turned on. Under the control of the low level stored in the first capacitor C1, the first node N1 remains low, and the second transistor T2 and the first transistor T11 are turned on. The potential of the fourth node N4 is written into the second node N2, and the potential of the fifth node N5 is written into the third node N3. The sixth transistor T6 is turned off, and the seventh transistor T7 is turned on. At this time, the third clock signal CK3 is written into the first output terminal OUT1 through the seventh transistor T7, and the first output terminal OUT1 outputs a low level signal.

[0129] In the fourth period P4, the first clock signal CK1 is at high level, the second clock signal CK2 is at high level, the third clock signal CK3 is at high level, the first input signal INPUT1 is at high level, the second input signal INPUT2 is at high level, the third input signal INPUT3 is at high level, and the fourth input signal INPUT4 is at high level.

[0130] Under the control of the fifth capacitor C5, the potential of the fifth node N5 is maintained at low level, the fifteenth transistor T15 is turned on, the third clock signal CK3 is written into the second output terminal OUT2 through the fifteenth transistor T15, and the second output terminal OUT2 outputs a high level signal. Correspondingly, under the control of the third capacitor C3, the potential of the third node N3 is maintained at low level, the seventh transistor T7 is turned on, the third clock signal CK3 is written into the second output terminal OUT2 through the seventh transistor T7, and the second output terminal OUT2 outputs a high level signal.

[0131] In the fifth period P5, the first clock signal CK1 is at low level, the second clock signal CK2 is at high level, the third clock signal CK3 is at high level, the first input signal INPUT1 is at low level, the second input signal INPUT2 is at high level, the third input signal INPUT3 is at low level, and the fourth input signal INPUT4 is at high level.

[0132] The eleventh transistor T11 and the eighth transistor T8 are turned on, and the thirteenth transistor T13 is turned off. The third input signal INPUT3 is written into the seventh node N7 and the fifth node N5 through the eleventh transistor T11 and the eighth transistor T8, and the potentials of the seventh node N7 and the fifth node N5 are low. At this time, the twelfth transistor T12 and the fifteenth transistor T15 are turned on. The second clock signal CK2 is written into the fourth node N4, the potential of the fourth node N4 is pulled high, and at this time the fourteenth transistor T14 is turned off. The third clock signal CK3 is written into the second output terminal OUT2 through the fifteenth transistor T15, and the second output terminal OUT2 outputs a high level signal.

[0133] Under the control of the third capacitor C3, the potential of the third node N3 is maintained at low level, the seventh transistor T7 is turned on, the third clock signal CK3 is written into the second output terminal OUT2 through the seventh transistor T7, and the second output terminal OUT2 outputs a high level signal.

[0134] In the sixth period P6, the first clock signal CK1 is at high level, the second clock signal CK2 is at low level, the third clock signal CK3 is at high level, the first input signal INPUT1 is at high level, the second input signal INPUT2 is at high level, the third input signal INPUT3 is at high level, and the fourth input signal INPUT4 is at high level.

[0135] The potential change of the sixth period P6 is similar to that of the second period P2, the second power voltage VGH is written into the second output terminal OUT2 through the fourteenth transistor T14, and the second output terminal OUT2 outputs a high level signal. The second power voltage VGH is written into the first output terminal OUT1 through the sixth transistor T6, and the first output terminal OUT1 outputs a high level signal.

[0136] In the embodiment of the present disclosure, when the potential of the first node N1 remains low, the potential of the second node N2 is consistent with that of the fourth node N4, and the potential of the third node N3 is consistent with that of the fifth node N5. Therefore, the output of the first output terminal OUT1 is consistent with that of the second output terminal OUT2.

[0137] In the embodiment of the present disclosure, when the fourth input signal INPUT4 is low, the fifth transistor T5 is turned on, and the first power voltage VGL is written into the first node N1 through the fifth transistor T5 to reset the potential of the first node N1.

[0138] As shown in FIG. 5B, the simulation waveforms of each signal potential of the shift register in the embodiment of the present disclosure are similar to the timing waveforms described in FIG. 5A. For the sake of simplicity, the description is not repeated.

[0139] For example, the clock signal CK1, the clock signal CK2 and the clock signal CK3 are provided to the shift register 400, and the clock signal CK4 is provided to the next stage shift register which is cascaded with the shift register 400.

[0140] In the embodiment of the present disclosure, when the fourth input signal INPUT4 is low, the fifth transistor T5 is turned on, and the first power voltage VGL is written into the first node N1 through the fifth transistor T5. At this time, the voltage of the strobe signal MS can be maintained as VGL-Vth, Vth is the threshold voltage of the fifth transistor T5. Due to the coupling effect of the first capacitor C1, the potential of the first node N1 is affected by the potential of the third node N3, so that the potential of the third node N3 is pulled down to the potential of the first node N1, and the potential of the first node N1 is lower than the first power voltage VGL.

[0141] As shown in FIG. 6A, the strobe signal MS is high, and at this time, the first output signal OUT1 output by the shift register 400 can control the corresponding pixel row not to be refreshed.

[0142] The potential changes of the fourth node N4, the fifth node N5, the seventh node N7 and the eighth node N8 shown in FIG. 6A can refer to the potential changes of the fourth node N4, the fifth node N5, the seventh node N7 and the eighth node N8 shown in FIG. 5A, and for the sake of simplicity, the description is not repeated.

[0143] In the embodiment of the present disclosure, the high level of the selection signal MS is written to the first node N1, so that the potential of the first node N1 is pulled high. Under the control of the high level of the first node N1, the first transistor T1 and the second transistor T2 are always kept in the off state, and the potentials of the second node N2 and the third node N3 are always kept at the high level of the previous period. Therefore, the first output terminal OUT1 always keeps outputting the high level of the previous period, and the pixel row to which the first output terminal OUT1 is electrically connected is not refreshed at this time.

[0144] As shown in FIG. 6B, the simulation waveforms of the potentials of the signals of each stage of the shift register provided in the embodiment of the present disclosure are similar to the timing waveforms described in FIG. 6A. For the sake of simplicity, the description is not repeated.

[0145] For example, the clock signal CK1, the clock signal CK2 and the clock signal CK3 are provided for the shift register 400, and the clock signal CK4 is provided for the next stage shift register which is cascaded with the shift register 400.

[0146] In the embodiment of the present disclosure, when the first input signal INPUT1 and the second input signal INPUT2 are low, the high level of the selection signal MS is written to the first node N1, and the potential of the first node N1 is high. After the second input signal INPUT2 jumps to high, the potential of the first node N1 is always kept high.

[0147] In the embodiment of the present disclosure, the input signals provided by the first input terminal INPUT1 and the third input terminal INPUT3 can be the same. For example, the shift register 400 is the mth stage shift register, and the first input terminal INPUT1 and the third input terminal INPUT3 can be electrically connected to the second output terminal of the m-1th shift register. For another example, the first input terminal INPUT1 and the third input terminal INPUT3 can be electrically connected to the second output terminal of the m-2th shift register.

[0148] The input signals provided by the first input terminal INPUT1 and the third input terminal INPUT3 can also be different. For example, the shift register 400 is the mth stage shift register, and the first input terminal INPUT1 can be electrically connected to the second output terminal of the m-1th shift register, and the third input terminal INPUT3 can be electrically connected to the second output terminal of the m-2th shift register. For another example, the shift register 400 is the mth stage shift register, and the first input terminal INPUT1 can be electrically connected to the second output terminal of the m-2th shift register, and the third input terminal INPUT3 can be electrically connected to the second output terminal of the m-1th shift register.

[0149] In the embodiments of the present disclosure, the first clock signal CK1 can be the same as the timing change of the second clock signal CK2. For example, in the first period P1 and the second period P2 shown in FIG. 5A, the first clock signal CK1 and the second clock signal CK2 can both be low. In the third period P3 and the fourth period P4 shown in FIG. 5A, the first clock signal CK1 and the second clock signal CK2 can both be high. In the fifth period P5 and the sixth period P6 shown in FIG. 5A, the first clock signal CK1 and the second clock signal CK2 can both be low. Accordingly, in the first period P1 and the second period P2 shown in FIG. 5A, the third clock signal CK3 can be high. In the third period P3 and the fourth period P4 shown in FIG. 5A, the third clock signal CK3 can be low. In the fifth period P5 and the sixth period P6 shown in FIG. 5A, the third clock signal CK3 can be high.

[0150] FIG. 7 is a structural schematic diagram of a shift register according to another embodiment of the present disclosure.

[0151] As shown in FIG. 7, the shift register 700 includes the first transistor T1 to the fourth transistor T4, the sixth transistor T6 to the sixteenth transistor T16, and the first capacitor C1 to the fifth capacitor C5.

[0152] The shift register 700 includes the first transistor T1 to the fourth transistor T4, the sixth transistor T6 to the eleventh transistor T11, the thirteenth transistor T13 to the fifteenth transistor T15, and the first capacitor C1 to the fifth capacitor C5 can refer to the shift register 400 described in the foregoing, and are not described herein for the sake of brevity.

[0153] In the embodiments of the present disclosure, the control electrode of the sixteenth transistor T16 is electrically connected to the second clock terminal CK2, the first electrode of the sixteenth transistor T16 is electrically connected to the second electrode of the twelfth transistor T12, and the second electrode of the sixteenth transistor T16 is electrically connected to the second power supply VGH.

[0154] In the embodiments of the present disclosure, the second power supply voltage VGH can be used to maintain the high potential of the fourth node N4, to ensure that the potential of the fourth node N4 does not drop, thereby ensuring that the fourteenth transistor T14 is completely in the off state.

[0155] FIG. 8 is a structural schematic diagram of a shift register according to another embodiment of the present disclosure.

[0156] As shown in FIG. 8, the shift register 800 includes the first transistor T1, the second transistor T2, the fourth transistor T4 to the sixteenth transistor T16, and the first capacitor C1 to the fifth capacitor C5.

[0157] The fifth transistor T5 included in the shift register 800 can refer to the shift register 400 described above, the first transistor T1, the second transistor T2, the sixth transistor T6 to the sixteenth transistor T16 and the first capacitor C1 to the fifth capacitor C5 included in the shift register 800 can refer to the shift register 700 described above, and details are not repeated for simplicity.

[0158] In the embodiment of the present disclosure, the control electrode of the fourth transistor T4 is electrically connected with the first input terminal INPUT1, the first electrode of the fourth transistor T4 is electrically connected with the first node N1, and the second electrode of the fourth transistor T4 is electrically connected with the gate terminal MS.

[0159] In the embodiment of the present disclosure, the first input signal INPUT1 provided by the first input terminal INPUT1 is a single pulse signal. The writing of the gate signal MS is controlled based on the single pulse signal, and the fourth transistor T4 is only turned on once in the output process of the first output signal OUT1. Therefore, for the first output signal of multiple pulses, any stage of the shift register will not output the first output signal with only the first pulse after the level of the gate signal MS jumps, thereby ensuring the normal display of the display picture.

[0160] FIG. 9 is a structural schematic diagram of a shift register according to another embodiment of the present disclosure.

[0161] As shown in FIG. 9, the shift register 900 includes the first transistor T1 to the fifteenth transistor T15 and the first capacitor C1 to the fifth capacitor C5.

[0162] The first transistor T1 to the fifteenth transistor T15 and the first capacitor C2 to the fifth capacitor C5 included in the shift register 900 can refer to the shift register 400 described above, and details are not repeated for simplicity.

[0163] In the embodiment of the present disclosure, the first end of the first capacitor C1 is electrically connected to the first power supply VGL, and the second end of the first capacitor C1 is electrically connected to the first node N1. The first capacitor C1 is provided with low voltage by the first power supply VGL, so that the gate signal MS charges the first capacitor C1. The first capacitor C1 maintains the potential of the first node N1 through bootstrap action.

[0164] In the embodiment of the present disclosure, the first end of the first capacitor C1 can also be electrically connected to any signal terminal providing a direct current signal. For example, the first end of the first capacitor C1 can also be electrically connected to the second power supply VGH.

[0165] FIG. 10 is a structural schematic diagram of a shift register according to another embodiment of the present disclosure.

[0166] As shown in FIG. 10, the shift register 1000 includes first to sixteenth transistors T1-T16 and first to fifth capacitors C1-C5.

[0167] In the embodiments of the present disclosure, the first to eleventh transistors T1-T11, the thirteenth to fifteenth transistors T13-T15 and the first to fifth capacitors C2-C5 included in the shift register 900 can refer to the shift register 400 described above, the twelfth transistor T12 and the sixteenth transistor T16 included in the shift register 900 can refer to the shift register 700 described above, and are not described herein again for simplicity.

[0168] FIG. 11 is a structural schematic diagram of a shift register according to another embodiment of the present disclosure.

[0169] As shown in FIG. 11, the shift register 1100 includes second to fifteenth transistors T2-T15 and first to fifth capacitors C1-C5.

[0170] In the embodiments of the present disclosure, the first transistor T1, the third to fifteenth transistors T3-T15 and the first to fifth capacitors C2-C5 included in the shift register 1100 can refer to the shift register 400 described above, and are not described herein again for simplicity.

[0171] In the embodiments of the present disclosure, the potential of the second node N2 is always consistent with the potential of the fourth node N4. The potential of the first node N1 only controls the potential of the third node N3, so that whether the first output end OUT1 outputs the low level of the third clock signal CK3 can be controlled by controlling the on or off state of the seventh transistor T7.

[0172] FIG. 12 is a structural schematic diagram of a driving circuit according to an embodiment of the present disclosure.

[0173] As shown in FIG. 12, the driving circuit 1200 includes M shift registers in cascade, where M is a positive integer greater than 1. The M shift registers include a first-stage shift register ST1, an m-th stage shift register STm, and an M-th stage shift register STM.

[0174] In the embodiments of the present disclosure, the shift register ST1 can be any one of the shift register 100, the shift register 200, the shift register 300, the shift register 400, the shift register 700, the shift register 800, the shift register 900, the shift register 1000 and the shift register 1100 described above. For example, the M shift registers are all the shift register 300. For example, the M shift registers are all the shift register 700. Details are not described herein again.

[0175] In the embodiment of the present disclosure, in the M cascaded shift registers, the input signal INPUT1 of the first input terminal INPUT1 of the first shift register ST1 is the start signal GSTV.

[0176] FIG. 13A is a structural schematic diagram of a driving circuit according to another embodiment of the present disclosure.

[0177] In the embodiment of the present disclosure, the driving circuit 1300a includes M cascaded shift registers.

[0178] In the embodiment of the present disclosure, the first input terminal INPUT1 of the mth shift register STm is electrically connected with the second output terminal OUT2 of the (m-1)th shift register, the third input terminal INPUT3 of the mth shift register STm is electrically connected with the second output terminal OUT2 of the (m-2)th shift register, 2

[0179] In the embodiment of the present disclosure, the driving circuit 1300a further includes a first clock signal line ck1, a second clock signal line ck2, a third clock signal line ck3 and a fourth clock signal line ck4.

[0180] The first clock terminal CK1 of the mth shift register is electrically connected with the first clock signal line ck1, the second clock terminal CK2 of the mth shift register is electrically connected with the second clock signal line, and the third clock terminal CK3 of the mth shift register is electrically connected with the third clock signal line ck3.

[0181] The first clock terminal CK1 of the (m+1)th shift register is electrically connected with the second clock signal line, the second clock terminal CK2 of the (m+1)th shift register is electrically connected with the third clock signal line ck3, and the third clock terminal CK3 of the mth shift register is electrically connected with the fourth clock signal line ck4.

[0182] The first clock terminal CK1 of the (m+2)th shift register is electrically connected with the third clock signal line ck3, the second clock terminal CK2 of the (m+2)th shift register is electrically connected with the fourth clock signal line ck4, and the third clock terminal CK3 of the mth shift register is electrically connected with the first clock signal line ck1.

[0183] The first clock terminal CK1 of the (m+3)th shift register is electrically connected with the fourth clock signal line ck4, the second clock terminal CK2 of the (m+3)th shift register is electrically connected with the first clock signal line ck1, and the third clock terminal CK3 of the mth shift register is electrically connected with the second clock signal line ck2.

[0184] In the embodiment of the present disclosure, the driving circuit 1300a uses four clock signal lines to provide clock signals, which can reduce the power consumption of the driving circuit.

[0185] For example, the power consumption of clock signal generation can be calculated according to the following formula:

[0186] where f is the signal frequency, C is the total capacitance in the driving circuit, and V is the transition voltage of the clock signal.

[0187] For 2 clock signal lines, the power consumption of clock signal generation is For 4 clock signal lines, C 4CK ≈0.7C 2CK , V 4CK =V 2CK In an ideal case, C 4CK =0.5C 2CK , the actual complexity is affected by the layout environment, and is approximately between 0.6 and 0.8, calculated as C 4CK =0.7C 2CK

[0188] The power consumption of 4 clock signals is

[0189] Therefore, compared with providing clock signals through 2 clock signal lines, the driving circuit can save about 30% to 50% of GOA power consumption by providing clock signals through 4 clock signal lines.

[0190] In the embodiment of the present disclosure, the second input signal INPUT2 can be provided by each stage of the shift register of the gate driving circuit GOA. For example, the gate driving circuit is used to provide a driving signal for the N-type tube in the pixel circuit, and the Nout signal output by the mth stage of the shift register of the gate driving circuit is provided to the second input end INPUT2 of the mth stage of the shift register in the driving circuit 1300a.

[0191] In the embodiment of the present disclosure, the fourth input signal INPUT4 can be provided by each stage of the shift register of the light-emitting control driving circuit EOA. For example, the light-emitting control driving circuit is used to provide a light-emitting control signal for the pixel circuit, and the Nout signal output by the mth stage of the shift register of the light-emitting control driving circuit is provided to the fourth input end INPUT4 of the mth stage of the shift register in the driving circuit 1300a.

[0192] FIG. 13B is a structural schematic diagram of a driving circuit according to another embodiment of the present disclosure.

[0193] In the embodiment of the present disclosure, the driving circuit 1300b includes M cascaded shift registers.

[0194] ​In the embodiment of the present disclosure, the first input end of the mth shift register STm is electrically connected with the second output end of the (m-1)th shift register STm-1, the third input end of the mth shift register STm is electrically connected with the second output end of the (m-1)th shift register STm-1, 1 < m ≤ M, and m is an integer.

[0195] In the embodiment of the present disclosure, the first clock end CK1 and the second clock end CK2 of the mth shift register are electrically connected with the first clock signal line, the third clock end CK3 of the mth shift register is electrically connected with the second clock signal line. The first clock end CK1 and the second clock end CK2 of the (m+1)th shift register are electrically connected with the second clock signal line, and the third clock end CK3 of the mth shift register is electrically connected with the first clock signal line.

[0196] FIG. 13C is a structural schematic diagram of a driving circuit according to another embodiment of the present disclosure.

[0197] In the embodiment of the present disclosure, the driving circuit 1300c includes M shift registers in cascade.

[0198] In the embodiment of the present disclosure, the first input end INPUT1 of the mth shift register STm is electrically connected with the second output end OUT2 of the (m-2)th shift register STm-2, the third input end of the mth shift register STm is electrically connected with the second output end OUT1 of the (m-1)th shift register STm-1, 1 < m ≤ M, and m is an integer.

[0199] In the embodiment of the present disclosure, the connection mode of the M shift registers and the clock line can refer to the driving circuit 1300a.

[0200] FIG. 13D is a structural schematic diagram of a driving circuit according to another embodiment of the present disclosure.

[0201] In the embodiment of the present disclosure, the driving circuit 1300d includes M shift registers in cascade.

[0202] In the embodiment of the present disclosure, the cascade mode of the M shift registers can refer to the driving circuit 1300a.

[0203] In the embodiment of the present disclosure, the driving circuit 1300d further includes a first clock signal line ck1, a second clock signal line ck2, and a third clock signal line ck3.

[0204] The first clock end CK1 of the mth shift register is electrically connected with the first clock signal line ck1, the second clock end CK2 of the mth shift register is electrically connected with the second clock signal line ck2, and the third clock end CK3 of the mth shift register is electrically connected with the third clock signal line ck3.

[0205] The first clock end CK1 of the m+1th shift register is electrically connected with the third clock signal line ck3, the second clock end CK2 of the m+1th shift register is electrically connected with the first clock signal line ck1, and the third clock end of the mth shift register is electrically connected with the second clock signal line ck2.

[0206] The first clock end CK1 of the m+1th shift register is electrically connected with the third clock signal line ck3, the second clock end CK2 of the m+1th shift register is electrically connected with the first clock signal line ck1, and the third clock end of the mth shift register is electrically connected with the second clock signal line ck2.

[0207] In the embodiment of the present disclosure, the first input end INPUT1 of the mth shift register can also be electrically connected with the second output end of the m-yth shift register, and the third input end of the mth shift register can also be electrically connected with the second output end of the m-xth shift register, 1 < m ≤ M, y-x=k*n, k and m are positive integers, and n is the number of clock lines in the driving circuit.

[0208] For example, the driving circuit includes 4 clock lines, n=4, the first input end INPUT1 of the mth shift register can be electrically connected with the second output end of the m-10th shift register, and the third input end of the mth shift register can also be electrically connected with the second output end of the m-2th shift register, wherein 10-2=2*4.

[0209] For example, the driving circuit includes 3 clock lines, n=3, the first input end INPUT1 of the mth shift register can be electrically connected with the second output end of the m-8th shift register, and the third input end of the mth shift register can also be electrically connected with the second output end of the m-2th shift register, wherein 8-2=2*3.

[0210] FIG. 14A is a signal timing diagram of the driving circuit according to an embodiment of the present disclosure.

[0211] FIG. 14A shows the timing changes of the clock signals output by the first clock signal line ck1, the second clock signal line ck2, the third clock signal line ck3 and the fourth clock signal line ck4 in the driving circuit 1300a.

[0212] FIG. 14A shows the timing changes of the trigger signal provided to the first input end of the 1st shift register, the second output signal output by the second output end of the 1st shift register, the 2nd shift register, the m-2th shift register and the m-1th shift register.

[0213] As shown in FIG. 14A, the double pulses in the second output signals of the m-2th shift register and the m-1th shift register are sequentially shifted and output.

[0214] For example, the timing changes of the first output signal OUT1(m) and the second output signal OUT2(m) of the mth stage shift register can refer to the change process described in FIG. 5A, which will not be repeated here for the sake of brevity.

[0215] FIG. 14B is a signal timing diagram of a driving circuit according to another embodiment of the present disclosure.

[0216] FIG. 14B shows the first output signals output by the first output terminals of the first stage shift register to the sixteenth stage shift register and the strobe signal MS. For example, FIG. 14B shows the first output signals output by the first output terminals of the first stage shift register to the sixteenth stage shift register in the driving circuit 1300a and the strobe signal MS applied to the driving circuit 1300a.

[0217] In the embodiments of the present disclosure, when the strobe signal MS is at a low level, the first output terminals of the first stage shift register to the third stage shift register output first output signals with double pulses. When the strobe signal MS jumps from a low level to a high level, the first output signals output by the first output terminals of the fourth stage shift register to the eleventh stage shift register are always at a high level. When the strobe signal MS jumps from a high level to a low level, the first output terminals of the twelfth stage shift register to the sixteenth stage shift register output first output signals with double pulses.

[0218] In the embodiments of the present disclosure, by controlling the changes of the strobe signal, the driving circuit outputs the first output signals, and local refresh of the pixel circuit is achieved.

[0219] FIG. 15 is a structural schematic diagram of a display device according to an embodiment of the present disclosure.

[0220] As shown in FIG. 15, the display device 1500 can include a driving circuit 1510.

[0221] In the embodiments of the present disclosure, the driving circuit 1310 can be any one of the driving circuits 1100, 1200a, 1200b, 1200c, and 1200d described above, which will not be repeated here.

[0222] FIG. 16 is a flowchart of a driving method according to an embodiment of the present disclosure.

[0223] As shown in FIG. 16, the driving method can include operations S1610 to S1620.

[0224] In operation S1610, in a strobe phase, the strobe signal is controlled to be at a first level.

[0225] In operation S1620, the control signal is at the second level in the non-gating phase.

[0226] In the embodiments of the present disclosure, operations S1610 to S1620 are similar to the operations performed by the shift register 400 described above, and thus are not described again here.

[0227] In the embodiments of the present disclosure, the first level is a low level and the second level is a high level. Alternatively, the first level can be a high level and the second level can be a low level according to the type of the transistor in the shift register.

[0228] In the embodiments of the present disclosure, in the first time period, the first input signal is at the first level and the second input signal is at the first level. In the second time period, the first input signal is at the second level and the second input signal is at the first level. In the third time period, the first input signal is at the second level and the second input signal is at the first level. In the fourth time period, the first input signal is at the second level and the second input signal is at the second level. In the fifth time period, the first input signal is at the first level and the second input signal is at the second level. In the sixth time period, the first input signal is at the second level and the second input signal is at the second level.

[0229] In the embodiments of the present disclosure, the first time period is similar to the operation of the first time period P1 shown in FIG. 5A, the second time period includes the operation of the second time period P2 shown in FIG. 5A, the third time period is similar to the operation of the third time period P3 shown in FIG. 5A, the fourth time period is similar to the operation of the fourth time period P4 shown in FIG. 5A, the fifth time period is similar to the operation of the fifth time period P5 shown in FIG. 5A, and the sixth time period is similar to the operation of the sixth time period P6 shown in FIG. 5A. For the sake of simplicity, the same parts are not described again here.

[0230] The flowcharts and block diagrams in the drawings illustrate the possible architectures, functionality, and operations of systems, methods, and computer program products in accordance with various embodiments of the present disclosure. In this regard, each block in the flowcharts or block diagrams can represent a module, a segment, or a portion of code, which comprises one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions noted in the blocks can occur in a different order than that noted in the drawings. For example, two blocks noted in succession can in fact be executed substantially concurrently or in reverse order, depending on the functionality involved. It should also be noted that each block in the flowcharts or block diagrams, and combinations of blocks in the flowcharts or block diagrams, can be implemented by dedicated hardware-based systems that perform the specified functions or operations, or can be implemented by a combination of dedicated hardware and computer instructions.

[0231] Those skilled in the art can understand that the features recited in various embodiments and / or claims of the present disclosure can be combined and / or integrated in various combinations, even if such combinations or integrations are not expressly recited in the present disclosure. In particular, the features recited in various embodiments and / or claims of the present disclosure can be combined and / or integrated in various combinations without departing from the spirit and teachings of the present disclosure. All such combinations and / or integrations fall within the scope of the present disclosure.

[0232] The above describes embodiments of the present disclosure. However, these embodiments are merely for illustrative purposes, and are not intended to limit the scope of the present disclosure. Although each embodiment is described above separately, this does not mean that the measures in each embodiment cannot be advantageously used in combination. The scope of the present disclosure is defined by the appended claims and their equivalents. Those skilled in the art can make various substitutions and modifications without departing from the scope of the present disclosure, and all such substitutions and modifications shall fall within the scope of the present disclosure.

Claims

1. A shift register, comprising: The gating circuit is configured to provide a gating signal from the gating terminal to the first node under the control of a first input signal from a first input terminal and a second input signal from a second input terminal; The control circuit is configured to control the potentials of the second node and the third node under the control of the potential of the first node by using the first power supply voltage of the first power supply, the second power supply voltage of the second power supply, the third input signal from the third input terminal, the first clock signal from the first clock terminal, the second clock signal from the second clock terminal, and the third clock signal from the third clock terminal. as well as The output circuit is configured to provide the second power supply voltage or the third clock signal to the first output terminal as a first output signal under the control of the potential of the second node and the potential of the third node, wherein the strobe signal controls the output of the first output signal.

2. The shift register according to claim 1, wherein, The gating circuit is electrically connected to the fourth input terminal and the first power supply. The gating circuit is further configured to control the potential of the first node using the first power supply voltage under the control of a fourth input signal from the fourth input terminal.

3. The shift register according to claim 1, wherein, The control circuit is electrically connected to the third node and the first power source; The control circuit is also configured to control the potential of the first node under the control of the potential of the third node or the first power supply voltage.

4. The shift register according to claim 2, wherein, The control circuit includes: A first control unit is configured to provide at least one of the first power supply voltage and the second clock signal to the second node under the control of the potential of the first node, the second clock signal, the third input signal, and the first clock signal; and The second control unit is configured to provide at least one of the third input signal and the second power supply voltage to the third node under the control of the potential of the first node, the first power supply voltage, the first clock signal, the second clock signal and the third clock signal.

5. The shift register according to claim 1, further comprising a shift circuit configured as follows: Under the control of the second clock signal, the third input signal and the first clock signal, at least one of the first power supply voltage and the second clock signal is provided to the fourth node; Under the control of the first clock signal, the first power supply voltage, the third clock signal and the potential of the fourth node, at least one of the third input signal and the second power supply voltage is provided to the fifth node; as well as Under the control of the potential of the fourth node and the potential of the fifth node, the second power supply voltage or the third clock signal is provided to the second output terminal as the second output signal; The control circuit is configured to provide the potential of the fourth node to the second node and the potential of the fifth node to the third node under the control of the potential of the first node.

6. The shift register according to claim 1, wherein, The control circuit includes a first transistor and a first capacitor; Wherein, the control electrode of the first transistor is electrically connected to the first node, the first pole of the first transistor is electrically connected to the third output terminal, and the second pole of the first transistor is electrically connected to the third node; and The first end of the first capacitor is electrically connected to the third node or the first power supply, and the second end of the first capacitor is electrically connected to the first node.

7. The shift register according to claim 6, wherein, The control circuit further includes a second transistor; Wherein, the control electrode of the second transistor is electrically connected to the first node, the first pole of the second transistor is electrically connected to the first power supply, and the second pole of the second transistor is electrically connected to the second node.

8. The shift register according to claim 1, wherein, The strobe circuit includes a third transistor and a fourth transistor; Wherein, the control electrode of the third transistor is electrically connected to the second input terminal, the first pole of the third transistor is electrically connected to the first node, and the second pole of the third transistor is electrically connected to the sixth node; and The control electrode of the fourth transistor is electrically connected to the first input terminal, the first pole of the fourth transistor is electrically connected to the sixth node, and the second pole of the fourth transistor is electrically connected to the strobe terminal.

9. The shift register according to claim 8, wherein, The strobe circuit further includes a fifth transistor; Wherein, the control electrode of the fifth transistor is electrically connected to the fourth input terminal, the first pole of the fifth transistor is electrically connected to the first node, and the second pole of the fifth transistor is electrically connected to the first power supply.

10. The shift register according to claim 1, wherein, The output circuit includes a sixth transistor, a seventh transistor, a second capacitor and a third capacitor; Wherein, the control electrode of the sixth transistor is electrically connected to the second node, the first pole of the sixth transistor is electrically connected to the second power supply, and the second pole of the sixth transistor is electrically connected to the first output terminal; The control electrode of the seventh transistor is electrically connected to the third node, the first pole of the seventh transistor is electrically connected to the first output terminal, and the second pole of the seventh transistor is electrically connected to the third clock terminal; The first end point of the second capacitor is connected to the second power supply, and the second end point of the second capacitor is connected to the second node; and [[ID= 11. The shift register according to any one of claims 1-10, wherein, ​ ​ ​ ​ ​ ​ 15. The driving circuit according to claim 12, wherein the first input end of the m-th stage shift register is electrically connected to the second output end of the (m - 1)-th stage shift register, and the third input end of the m-th stage shift register is electrically connected to the second output end of the (m - 2)-th stage shift register, where 2 < m ≤ M and m is an integer.

16. The driving circuit according to claim 12, wherein the first input end of the m-th stage shift register is electrically connected to the second output end of the (m - y)-th stage shift register, and the third input end of the m-th stage shift register is electrically connected to the second output end of the (m - x)-th stage shift register, where 1 < m ≤ M, y - x = k * n, k and m are positive integers, and n is the number of clock lines in the driving circuit.

17. The driving circuit according to claim 12, further comprising: A first clock signal line and a second clock signal line; wherein the first clock terminal and the second clock terminal of the m-th stage shift register are electrically connected to the first clock signal line, and the third clock terminal of the m-th stage shift register is electrically connected to the second clock signal line; the first clock terminal and the second clock terminal of the (m + 1)-th stage shift register are electrically connected to the second clock signal line, and the third clock terminal of the m-th stage shift register is electrically connected to the first clock signal line.

18. The driving circuit according to claim 12, wherein, Further comprising: a first clock signal line, a second clock signal line, and a third clock signal line; wherein the first clock terminal of the m-th stage shift register is electrically connected to the first clock signal line, the second clock terminal of the m-th stage shift register is electrically connected to the second clock signal line, and the third clock terminal of the m-th stage shift register is electrically connected to the third clock signal line; the first clock terminal of the (m + 1)-th stage shift register is electrically connected to the second clock signal line, the second clock terminal of the (m + 1)-th stage shift register is electrically connected to the third clock signal line, and the third clock terminal of the m-th stage shift register is electrically connected to the first clock signal line; and the first clock terminal of the (m + 2)-th stage shift register is electrically connected to the third clock signal line, the second clock terminal of the (m + 2)-th stage shift register is electrically connected to the first clock signal line, and the third clock terminal of the m-th stage shift register is electrically connected to the second clock signal line.

19. The driving circuit according to claim 12, wherein, Further comprising: a first clock signal line, a second clock signal line, a third clock signal line, and a fourth clock signal line; wherein the first clock terminal of the m-th stage shift register is electrically connected to the first clock signal line, the second clock terminal of the m-th stage shift register is electrically connected to the second clock signal line, and the third clock terminal of the m-th stage shift register is electrically connected to the third clock signal line; the first clock terminal of the (m + 1)-th stage shift register is electrically connected to the second clock signal line, the second clock terminal of the (m + 1)-th stage shift register is electrically connected to the third clock signal line, and the third clock terminal of the m-th stage shift register is electrically connected to the fourth clock signal line; the first clock terminal of the (m + 2)-th stage shift register is electrically connected to the third clock signal line, the second clock terminal of the (m + 2)-th stage shift register is electrically connected to the fourth clock signal line, and the third clock terminal of the m-th stage shift register is electrically connected to the first clock signal line; and The first clock terminal of the (m+3)th stage shift register is electrically connected to the fourth clock signal line, the second clock terminal of the (m+3)th stage shift register is electrically connected to the first clock signal line, and the third clock terminal of the m-th stage shift register is electrically connected to the second clock signal line.

20. A display device, comprising: The driving circuit as described in any one of claims 12 to 19.

21. A driving method applied to a shift register as described in any one of claims 1-11, comprising: During the gating phase, the gating signal is controlled to be at the first level; as well as During the non-gating phase, the gating signal is controlled to be at the second level.

22. The driving method according to claim 21, wherein, During the first time period, both the first input signal and the second input signal are at a first level. During the second time period, the first input signal is at a second level, and the second input signal is at a first level. During the third time period, the first input signal is at the second level, and the second input signal is at the first level; During the fourth time period, the first input signal is at the second level, and the second input signal is at the second level; During the fifth time period, the first input signal is at a first level, and the second input signal is at a second level; as well as During the sixth time period, the first input signal is at the second level, and the second input signal is at the second level.

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