Memory address randomization method and apparatus

Abstract

Embodiments of the present application disclose a memory address randomization method and apparatus, which are used for improving memory access performance. The method in the embodiments of the present application comprises: a compiler compiling a program source code to generate a bytecode, the bytecode comprising an extended semantic parameter, the extended semantic parameter being used for indicating segment information corresponding to one or more memory addresses with which the bytecode is involved, and the segment information comprising an intra-segment offset of the one or more memory addresses in a memory segment to which the one or more memory addresses belong; on the basis of a randomization algorithm, performing address randomization on a memory segment corresponding to the bytecode, and determining a randomized memory segment base address; and, on the basis of the randomized memory segment base address and the extended semantic parameter, computing a randomized memory address.

Description

Randomization method and device of memory address

[0001] The present application claims priority to the Chinese Patent Application No. 202410874391.3, filed on June 29, 2024, and entitled "Randomization method and device of memory address", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] Embodiments of the present application relate to the field of storage, and in particular, to a randomization method and device of memory address. BACKGROUND

[0003] Address space layout randomization (ASLR) is a computer security technique used to prevent malicious attackers from exploiting known memory addresses. The principle of ASLR is to randomly allocate the memory address space of a program when the operating system starts, making it difficult for malicious attackers to accurately predict the storage location of program code and data, thereby increasing the difficulty of attackers.

[0004] In the current address space layout randomization scheme, in order to correctly address the randomized memory address, the computing device needs to modify the original memory address reference in the program. Specifically, the computing device generates metadata information of the memory address during program compilation. The data metadata records information related to the memory address that needs to be modified. After the randomization of the memory address space, the computing device can modify the memory address based on these data metadata, so that the computing device can correctly address based on the modified memory address.

[0005] However, the program of the computing device often involves a large number of memory address accesses. In the current scheme, for a large number of memory address accesses, the computing device generates metadata information of the memory address during program compilation, which occupies a large amount of space, making the file overhead of the compiled bytecode larger, thereby causing poor memory access performance of the computing device. SUMMARY

[0006] Embodiments of the present application provide a memory address modification method. In the method, an extended semantic parameter is carried in the program source code, so that the compiler can directly identify the segment offset of the memory address reference involved in the program source code during the compilation of the program source code. Therefore, a large amount of metadata information does not need to be generated for memory address modification, thereby reducing the program source code compilation and running overhead and improving the memory access performance. Embodiments of the present application also provide a memory address modification method, a memory address modification device, a computing device, a computing device cluster, a computer readable storage medium, and a computer program product corresponding to the memory address modification method.

[0007] In a first aspect, an embodiment of the present application provides a memory address correction method. The method can be executed by a WebAssembly system, or a component of the WebAssembly system, such as a processor, a chip, or a chip system of a computing device, or a logic module or software that can implement all or part of the functions of the WebAssembly system. The method provided in the first aspect includes: obtaining program source code and compiling the program source code to obtain bytecode by the WebAssembly system, the bytecode including an extended semantic parameter, the extended semantic parameter being used to indicate segment information corresponding to one or more memory addresses involved in the program source code, the segment information including an intra-segment offset of the one or more memory addresses in a memory segment to which the one or more memory addresses belong, and the segment information further including a segment type of the memory segment to which the one or more memory addresses belong. The WebAssembly system performs address randomization on a memory segment corresponding to the bytecode based on a randomization algorithm, and determines a base address of the memory segment after randomization. The address randomization changes the base address of the one or more memory segments corresponding to the bytecode. The WebAssembly system determines a corrected memory address based on the base address of the memory segment after randomization and the extended semantic parameter.

[0008] In the embodiment of the present application, the bytecode compiled by the WebAssembly system carries the extended semantic parameter. The WebAssembly system can directly identify the intra-segment offset referenced by the one or more memory addresses involved in the program source code based on the extended semantic parameter, so that the virtual machine can calculate the memory address after randomization according to the intra-segment offset in the process of executing the bytecode. Compared with the existing scheme in which the compiler generates a large amount of metadata information when compiling the program source code and relies on the metadata information to correct the address reference, the scheme provided in the embodiment of the present application can reduce the generated metadata information, thereby reducing the file size overhead in the process of compiling and executing the program source code, and further improving the memory access performance.

[0009] In a possible implementation, the extended semantic parameter includes an immediate number parameter and an extended flag parameter. The immediate number parameter is used to indicate the intra-segment offset referenced by the memory address. The extended flag parameter is used to indicate the memory segment type to which the one or more memory addresses belong. The memory segment type includes a heap segment, a stack segment, and a data segment. The heap segment is used to store the memory that needs to be dynamically applied and released during the running of the program. The stack segment is used to store the region of the local variables, the function parameter values, and the return address of the function call in the process of function call, and the like. The data segment is used to store the initialized global variables, static variables, and some constants in the program.

[0010] In the embodiments of the present application, an extended flag parameter can be added in the bytecode, and the segment type of the memory segment where the address reference is located can be indicated based on the extended flag parameter. Meanwhile, the semantics of the immediate number parameter in the original bytecode is changed, and the semantics of the address reference is changed from memory offset to intra-segment offset. Compared with the current bytecode, the number of instructions in the bytecode is reduced by extending the semantic parameter, thereby reducing the file size of the bytecode and the running overhead.

[0011] In a possible implementation, the WebAssembly system includes a compiler and a virtual machine. The compiler is configured to compile program source code to obtain bytecode. The virtual machine is configured to execute the bytecode, including performing address randomization on a memory segment corresponding to the bytecode based on a randomization algorithm, determining a randomized memory segment base address, and determining a corrected memory address based on the randomized memory segment base address and an extended semantic parameter.

[0012] The WebAssembly system in the embodiments of the present application includes a compiler and a virtual machine. The virtual machine can directly identify the intra-segment offset of one or more memory address references in the program source code based on the extended semantic parameter, so that the virtual machine can calculate the randomized memory address according to the intra-segment offset during the execution of the bytecode, thereby improving the memory access performance.

[0013] In a possible implementation, the bytecode can have multiple immediate number parameters. When the multiple immediate number parameters in the bytecode involve address references, the immediate number parameters that involve address references all correspond to an extended flag parameter.

[0014] In the embodiments of the present application, the bytecode can include multiple immediate number parameters. When the compiler identifies that multiple immediate number parameters involve address references, the immediate number parameters that involve address references all correspond to an extended flag parameter indicating the segment type to which the address reference belongs, thereby reducing the code running overhead when the bytecode involves multiple memory address references.

[0015] In a possible implementation, the bytecode includes instruction bytecode. The address reference in the instruction bytecode, for example, the immediate number parameter of the instruction, is a memory address. The intra-segment offset and the memory segment type are identified based on the extended semantic parameter in the instruction bytecode, and the randomized memory address is calculated based on the intra-segment offset and the segment type.

[0016] In the embodiments of the present application, the bytecode can be divided into instruction bytecode and data bytecode. In the address reference in the instruction bytecode, the immediate number parameter can be a memory address. The compiler can directly identify the intra-segment offset and the memory segment type based on the extended semantic parameter in the instruction bytecode, and compile to obtain the bytecode, thereby reducing the generated metadata information and reducing the running overhead in the program source code compilation and execution process.

[0017] In a possible implementation, the bytecode further includes data bytecode, the compiler generates metadata information based on the compilation information of the data bytecode, the metadata information includes a segment number and a segment offset, the segment number is used to indicate a memory segment to which the data bytecode belongs, and the segment offset is used to indicate an offset of the data bytecode in the segment of the memory segment. The virtual machine corrects the memory address of the data bytecode based on the metadata information, and the memory address involved in the data bytecode is a memory address after address randomization.

[0018] In the embodiment of the application, for the data bytecode in the bytecode, in the address reference in the data bytecode, the immediate number parameter can be a pointer to another memory address. The compiler needs to generate metadata information based on the compilation information of the data bytecode, and then the virtual machine corrects the memory address reference of the data bytecode according to the metadata information. Since the proportion of the data bytecode in the bytecode is low, the file overhead of the compiler generating the metadata information is also small, thereby reducing the running overhead in the bytecode compilation and execution process.

[0019] In a possible implementation, in the format of the metadata information, the metadata information contains one or more relocation structures, each relocation structure includes a segment number, a segment offset, and a memory address position, and the like, wherein the segment type indicates a segment to which the address reference belongs, and the segment offset indicates a position of the address reference in the segment in the linear memory.

[0020] In the embodiment of the application, the compiler can identify the address reference in the data code, generate a relocation structure for each address reference or pointer reference, and save the obtained metadata information, thereby improving the realizability of the memory address correction of the memory address corresponding to the data code.

[0021] In a possible implementation, when there is a redundant bit in the bytecode, an extended flag parameter is stored based on the redundant bit. For example, the redundant bit of the original instruction in the bytecode in the memory can be defined as the extended flag parameter. When the original instruction has a 2-bit redundant bit, the extended flag parameter can use the 2-bit redundant bit to represent 4 segment types. When the 2 bits are “00”, it indicates a non-address constant, when the 2 bits are “11”, it indicates that the segment type is a heap segment, when the 2 bits are “01”, it indicates that the segment type is a stack segment, and when the 2 bits are “10”, it indicates that the segment type is a data segment.

[0022] In the embodiment of the application, the extended flag parameter can be carried by the redundant bit in the bytecode, so that the extended flag parameter in the embodiment of the application does not need to occupy additional instruction code, thereby not increasing the file overhead of the bytecode, and the memory access performance is improved.

[0023] In a possible implementation, a new instruction code is added in the bytecode, and the new instruction code is used to carry the extended flag parameter. For example, a 1-byte new instruction code is inserted in the bytecode in the embodiment of the present application as the extended flag parameter. At this time, the extended flag parameter is 8 bits, and 256 different segment types can be supported at most.

[0024] In the embodiment of the present application, a 1-byte instruction code can also be added in the bytecode to carry the extended flag parameter, so that only one byte of instruction code needs to be added in the bytecode to reduce a large amount of metadata information, thereby reducing the running overhead in the bytecode compilation and execution process.

[0025] In a possible implementation, after the virtual machine performs address randomization on the memory segment corresponding to the bytecode based on the randomization algorithm, the virtual machine stores the randomized memory segment base address in an object of the virtual machine, and the object is used to record context environment information of the virtual machine. For example, the virtual machine records the randomized stack segment base address "Stack-offset" in "VM context.stack", records the randomized data segment base address "Data-offset" in "VM context.Data", and records the randomized heap segment base address "Heap-offset" in "VM context.Heap".

[0026] In the embodiment of the present application, after the virtual machine performs randomization on the memory address space, the virtual machine can save the randomized segment base address in the object recording the context environment information of the virtual machine, so as to perform address correction by using the object recording the context environment information of the virtual machine, and the realizability of the scheme is improved.

[0027] In a possible implementation, the bytecode includes WebAssembly binary format bytecode. The WebAssembly binary format bytecode is executed in an environment supporting a WebAssembly virtual machine, such as a browser, a terminal, a server, and the like. The WebAssembly binary format bytecode has an execution performance close to that of a native binary when executed.

[0028] In the embodiment of the present application, program source code can be compiled into WebAssembly bytecode, distributed through a network, and executed in an environment supporting a WebAssembly virtual machine. The WebAssembly binary format bytecode obtained based on the extended semantic parameter in the embodiment of the present application can meet the characteristics of high performance and easy distribution of the WebAssembly binary format bytecode in a web application scenario.

[0029] In a possible implementation, the address space distribution randomization in the implementation of the application includes two modes, namely a JIT mode and an AOT mode. In the JIT mode, the randomization of the segment base address in the memory is implemented by the virtual machine. In the AOT mode, the virtual machine generates the random segment base address by adding an initialization function.

[0030] In the implementation of the application, the virtual machine can perform address space distribution randomization in multiple ways, thereby improving the richness of the memory address correction method.

[0031] In a possible implementation, in the process in which the virtual machine calculates the random memory address based on the random memory segment base address and the extended semantic parameter, the virtual machine calculates the random memory address based on the random memory segment base address and the segment offset indicated by the extended semantic parameter, and then the virtual machine continues to execute the bytecode according to the random memory address.

[0032] In the implementation of the application, the virtual machine can calculate the random memory address according to the segment offset indicated by the extended semantic parameter in the process of executing the bytecode, and execute the bytecode according to the random memory address, thereby improving the security of the network assembly system in memory access.

[0033] In a second aspect, the implementation of the application provides a memory address correction device. The device includes a compiling unit and a processing unit. The compiling unit is configured to compile program source code to generate bytecode, and the bytecode includes an extended semantic parameter. The extended semantic parameter is used to indicate segment information corresponding to one or more memory addresses involved in the bytecode. The segment information includes a segment offset of the one or more memory addresses in a memory segment. The processing unit is configured to perform address randomization on a memory segment corresponding to the bytecode based on a randomization algorithm, and determine a random memory segment base address. The processing unit is configured to calculate a random memory address based on the random memory segment base address and the extended semantic parameter.

[0034] In a possible implementation, the extended semantic parameter includes an immediate number parameter and an extended flag parameter. The immediate number parameter is used to indicate the segment offset, and the extended flag parameter is used to indicate a segment type of the memory segment to which the one or more memory addresses belong. The segment type includes a heap segment, a stack segment, and a data segment.

[0035] In a possible implementation, the bytecode includes instruction bytecode. The processing unit is further configured to identify the segment offset and the segment type based on the extended semantic parameter in the instruction bytecode, and the segment offset and the segment type are used to calculate the random memory address.

[0036] In a possible implementation, the bytecode includes data bytecode, and the processing unit is further configured to generate metadata information based on the compilation information of the data bytecode, the metadata information including a segment number and a segment offset, the segment number being used to indicate a memory segment to which the data bytecode belongs, and the segment offset being used to indicate an offset of the data bytecode in a segment of the memory segment. The memory address involved by the data bytecode is corrected based on the metadata information, the memory address involved by the data bytecode being a memory address after address randomization.

[0037] In a possible implementation, the processing unit is further configured to store the extension flag parameter based on the redundant bit when the redundant bit exists in the bytecode.

[0038] In a possible implementation, the processing unit is further configured to add, in the bytecode, new instruction bytecode used to carry the extension flag parameter.

[0039] In a possible implementation, the processing unit is further configured to store the memory segment base address after randomization to an object of the virtual machine, the object being used to record context environment information of the virtual machine.

[0040] In a possible implementation, the bytecode includes WebAssembly (WASM) bytecode.

[0041] In a possible implementation, the processing unit is further configured to continue to execute the bytecode according to the memory address after randomization.

[0042] In a third aspect, an embodiment of the present application provides a computing device, the computing device including a processor and a memory coupled to the processor, the memory being configured to store instructions, when the instructions are executed by the processor, to cause the computing device to perform the method in the first aspect or any possible implementation of the first aspect.

[0043] In a fourth aspect, an embodiment of the present application provides a computing device cluster, the computing device cluster including one or more computing devices, each computing device including a processor and a memory coupled to the processor, the memory being configured to store instructions, when the instructions are executed by the processor, to cause the computing device cluster to perform the method in the first aspect or any possible implementation of the first aspect.

[0044] In a fifth aspect, an embodiment of the present application provides a computer-readable storage medium, the computer-readable storage medium storing instructions, when the instructions are executed, to cause a computer to perform the method in the first aspect or any possible implementation of the first aspect.

[0045] In a sixth aspect, an embodiment of the present application provides a computer program product, the computer program product including instructions, when the instructions are executed, to cause a computer to implement the method in the first aspect or any possible implementation of the first aspect.

[0046] It can be understood that the beneficial effects achieved by any one of the above-provided memory address randomization apparatus, computing device, computing device cluster, computer readable medium or computer program product, etc. can refer to the beneficial effects in the corresponding method, which will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0047] FIG. 1 is a schematic diagram of a system architecture of a network assembly system according to an embodiment of the present application;

[0048] FIG. 2 is a schematic diagram of a memory address correction method according to an embodiment of the present application;

[0049] FIG. 3 is a schematic diagram of a program source code compilation and execution process according to an embodiment of the present application;

[0050] FIG. 4 is a schematic diagram of metadata information according to an embodiment of the present application;

[0051] FIG. 5 is a schematic diagram of memory address randomization according to an embodiment of the present application;

[0052] FIG. 6 is a schematic diagram of another memory address randomization according to an embodiment of the present application;

[0053] FIG. 7 is a schematic diagram of a memory address correction apparatus according to an embodiment of the present application;

[0054] FIG. 8 is a schematic diagram of a computing device according to an embodiment of the present application;

[0055] FIG. 9 is a schematic diagram of a computing device cluster according to an embodiment of the present application;

[0056] FIG. 10 is a schematic diagram of another computing device cluster according to an embodiment of the present application. DETAILED DESCRIPTION

[0057] The embodiments of the present application provide a memory address randomization method and apparatus, which are used to improve the memory access performance of a computing device.

[0058] The terms "first", "second", "third", "fourth" and the like in the description and in the claims of the present application, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the use of these terms herein is to be construed to cover a generalised use of these terms to refer to similar elements independently of use of the terms in this form in every instance herein. It is to be understood that the terms "comprises", "comprising", "includes", "including", "has", "having" and any variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, system, product, or apparatus that comprises, has or includes a list of elements is not necessarily limited to those elements but can include other elements not expressly listed or inherent to such process, method, system, product, or apparatus.

[0059] In the embodiments of the present application, the words "exemplary" and "for example" are used to mean serving as an example, instance, or illustration, at 5 2 least. Any implementation described herein as "exemplary" or "for example" is not necessarily to be construed as preferred or advantageous over other implementations. The

[0060] First, some terms involved in the embodiments of the present application are introduced to facilitate understanding of the technical solutions by those skilled in the art.

[0061] Address space layout randomization (ASLR) is a computer security technique used to prevent malicious attackers from exploiting known memory addresses. The principle of ASLR is to randomly allocate the memory address space of a program when the operating system starts, that is, to randomize the memory segment address of the program after each start, including the data (Data) segment, the stack (Stack) segment and the heap (Heap) segment, so that it is difficult for a malicious attacker to accurately predict the storage location of the program code and data, thereby increasing the difficulty for the attacker.

[0062] WebAssembly (WASM) is an operating system-independent and architecture-independent binary format compilation target, which can compile code written in programming languages such as C / C++, Rust, Golang, Python, etc. into a Web Assembly bytecode file, and distribute it through the network, and execute in an environment supporting Web Assembly virtual machine, such as a browser, terminal, server, etc. When executing, it has an execution performance close to that of a native binary.

[0063] In order to make the technical solutions of the present application clearer and easier to understand, the system architecture of the present application will be introduced below in conjunction with the drawings.

[0064] Please refer to FIG. 1, which is a schematic diagram of a system architecture of a memory address randomization system according to an embodiment of the present application. In the example shown in FIG. 1, a network assembly system 10 includes a compiler 101 and a virtual machine 102, which can be deployed in various types of clients such as browsers, cloud devices, and Internet of Things (IoT) devices, without limitation. The specific functions of each part of the network assembly system 10 are described below.

[0065] The compiler 101 can also be referred to as a WASM compiler in the embodiments of the present application. The compiler 101 is used to compile program source code into a WebAssembly program and distribute the generated WebAssembly program to the virtual machine 102 of the client. The compiler 101 can be an independent compilation tool or a functional module integrated in the system, without limitation.

[0066] The compiler 101 can compile program source code of various types and programming languages into a WebAssembly program. The program source code includes system programs, application programs, and script programs, etc. The program source code can be a program written in various programming languages such as C / C++, Golang, and JS.

[0067] The WebAssembly program compiled by the compiler 101 is a binary bytecode that runs across platforms and can be executed in different clients, with characteristics of high security, high performance, and easy distribution, etc. The WebAssembly program can be applied to Web applications, cloud-native, edge computing, IoT, and blockchain, etc.

[0068] The virtual machine 102 can also be referred to as a WASM stack-based virtual machine in the embodiments of the present application. The virtual machine 102 is used to run the WebAssembly program compiled by the compiler 101. The virtual machine 102 can be deployed in various types of clients such as browsers, terminal devices, cloud devices, and IoT devices, etc. The virtual machine 102 can also provide a sandbox-based isolated execution environment so that the WebAssembly program cannot read or write data other than the program itself, which can prevent virtual machine escape.

[0069] Specifically, the virtual machine 102 divides the memory involved in the Web Assembly program into managed memory and unmanaged memory. The managed memory is usually used to store safe type data such as integer and character, and the access to the managed memory is completed by the virtual machine 102 to ensure the safety of data access. The unmanaged memory, also known as linear memory, is used to store non-safe type data such as array or string, and the WebAssembly program can access any data on the linear memory, and the virtual machine 102 will perform a boundary check when accessing to prevent the WebAssembly program from accessing data outside the linear memory, and to ensure that the Web Assembly program will not produce a virtual machine escape behavior.

[0070] Although the virtual machine 102 achieves strong isolation at the linear memory boundary, the memory vulnerability of the WebAssembly program still causes the linear memory to be tampered with by attacks, for example, an attacker may tamper with sensitive data by exploiting vulnerabilities when the virtual machine 102 executes the WebAssembly program, thereby hijacking program execution to perform malicious behavior, including privacy theft, denial of service attacks, and lateral movement.

[0071] Therefore, the virtual machine 102 protects multiple different types of memory vulnerabilities through the address space distribution randomization (ASLR) technology. The principle of ASLR is to randomize the distribution of the base addresses of each segment of the program memory at each program startup, to achieve random arrangement of process data, hide the actual addresses of key data, and make it difficult for attackers to predict the actual addresses of key data in the process, and only through brute force or other means to obtain the randomized addresses, it is difficult to perform effective attacks at a reasonable cost.

[0072] However, in order to correctly address the randomized memory addresses, the computing device needs to correct the original memory address references in the program. The following continues to introduce the memory address correction method provided by the embodiments of the present application. Based on the memory address randomization system 10 shown in FIG. 1, the present application also provides a memory address randomization method. The following introduces the memory address correction method provided by the embodiments of the present application in combination with the embodiments.

[0073] Please refer to FIG. 2, which is a flowchart of a memory address correction method provided by an embodiment of the present application. In the example shown in FIG. 2, the method includes the following steps:

[0074] 201. The compiler compiles the program source code to generate bytecode, and the bytecode includes an extended semantic parameter, which is used to indicate the segment information corresponding to one or more memory addresses involved in the bytecode. The segment information includes the segment offset of one or more memory addresses in the corresponding memory segment.

[0075] The compiler 101 first acquires program source code, which can be program code written in one or more programming languages. Specifically, after the developer writes the program source code, the compiler 101 compiles the program source code to generate an executable bytecode file. The programming languages of the program source code include one or more of the following: C / C++, Golang, and JS.

[0076] Referring to FIG. 3, FIG. 3 is a flowchart of a program source code compilation and execution process according to an embodiment of the present application. In step a of the example shown in FIG. 3, the Web Assembly compiler acquires program source code, compiles the program source code, and outputs the compiled Web Assembly program, which is bytecode.

[0077] The bytecode in the embodiment of the present application carries an extended semantic parameter, which is used to indicate segment information corresponding to one or more memory addresses involved in the bytecode. The segment information includes the in-segment offset of the one or more memory addresses in the memory segment to which the one or more memory addresses belong. The segment information also includes the segment type of the memory segment to which the one or more memory addresses belong.

[0078] The bytecode in the embodiment of the present application is an instruction file written based on an extended semantic instruction set. The extended semantic instruction set is a new instruction set in which the segment information of a memory address is encoded into an instruction. The instruction in the extended semantic instruction set contains the above-mentioned extended semantic parameter. The extended semantic parameter can change the meaning of the original instruction and the meaning of the parameter in the original instruction.

[0079] For example, the original bytecode includes an operation code and an immediate number parameter. When the immediate number parameter is an instruction code involving an address reference, the immediate number parameter represents a global offset in memory. In the bytecode compiled based on the extended semantic instruction set in the embodiment of the present application, an extended flag parameter is added. That is, the bytecode compiled based on the extended semantic instruction set in the embodiment of the present application includes an operation code, an immediate number parameter, and an extended flag parameter. After the addition of the extended flag parameter, the value and semantics of the immediate number parameter change, indicating the in-segment offset of the address reference in memory. Because the semantics of the immediate number parameter change, both the immediate number parameter and the extended flag parameter can be called an extended semantic parameter.

[0080] The extended semantic parameters in the embodiments of the present application include an immediate number parameter and an extended flag parameter. The immediate number parameter is used to indicate an offset within a segment, and the extended flag parameter is used to indicate a memory segment type to which one or more memory addresses belong. The memory segment type includes a heap segment, a stack segment, and a data segment. The heap segment is a region used for dynamically allocating memory, and is usually used to store memory that needs to be dynamically applied and released at runtime of a program. The stack segment is a region used to store local variables, function parameter values, and return addresses of function calls, and the like, in a function call process. The data segment is used to store initialized global variables, static variables, and some constants in a program.

[0081] For example, in an example of bytecode compiled based on the extended semantic instruction set in the embodiments of the present application, the bytecode includes an operation code, an immediate number parameter, and an extended flag parameter. An example of a format of the bytecode is as follows:

[0082] <opcode> <arg1> , <arg2> ,…, <argisec> , <argi> ,…, <argn>;

[0083] wherein, <opcode>For the opcode, <arg1> , <arg2> ,…, <argn>For immediate number parameters, used to represent an offset within a segment referenced by an address, <argisec>To extend the flag parameter, which is used to indicate the segment type of the memory segment to which the address reference belongs, the extended flag parameter is greater than or equal to 2 bits. For example, the 2-bit extended flag parameter can represent 4 segment types. When the 2 bits are "00", it indicates that the address is not a constant. When the 2 bits are "11", it indicates that the segment type is a heap segment. When the 2 bits are "01", it indicates that the segment type is a stack segment. When the 2 bits are "10", it indicates that the segment type is a data segment.

[0084] It can be understood that since the bytecode can contain multiple immediate number parameters, when there are multiple immediate number parameters in the bytecode, each immediate number parameter corresponds to an extended flag parameter. That is, the extended flag parameter identifies the memory segment to which the address belongs, and the immediate number parameter identifies the offset of the address reference in the segment of the memory segment.

[0085] In a possible implementation, a new instruction bytecode is added in the bytecode, and the extended flag parameter is carried by the new instruction bytecode. For example, in an embodiment of the present application, a 1-byte new instruction bytecode is inserted in the bytecode as an extended flag parameter. At this time, the 8-bit extended flag parameter can support up to 256 different segment types.

[0086] In an example in which the new instruction bytecode carries the extended flag parameter, the bytecode is, for example, "i32.sec.const". The bytecode includes 1 byte of opcode, 1 byte of extended flag parameter, and 4 bytes of immediate number parameter. The 1-byte extended flag parameter is the new instruction bytecode.

[0087] In a possible implementation, when there are redundant bits in the bytecode, the extended flag parameter is stored based on the redundant bits. For example, the original instruction in the bytecode has redundant bits in the memory, and the redundant bits can be defined as the extended flag parameter.

[0088] In an example in which the extended flag parameter is stored based on the redundant bits, the bytecode is, for example, "i32.sec.load alignment offset". The bytecode includes 1 byte of alignment parameter and 4 bytes of immediate number parameter. In the 1-byte alignment parameter, 4 bits are redundant bits. Therefore, the bytecode does not need to add new instruction code, and 2 bits of the 4 redundant bits are used as the extended flag parameter. When the redundant bits in the bytecode carry the extended flag parameter, the extended flag parameter in the embodiment of the present application does not need to occupy additional instruction bytecodes, so that the file overhead of the bytecode is not increased, and the memory access performance is improved.

[0089] After the compiler 101 compiles the generated bytecode, the compiler 101 sends the bytecode to the virtual machine 102. In the embodiments of the present application, the bytecode includes instruction bytecode and data bytecode, where the instruction bytecode and the data bytecode can both involve memory address references. For example, an immediate number parameter in the instruction bytecode can be a memory address, and the data bytecode includes a pointer to another address.

[0090] In the embodiments of the present application, for the instruction bytecode in the bytecode, the compiler 101 can translate the instruction bytecode based on the extended instruction semantic parameter in the instruction bytecode to generate the machine code corresponding to the instruction bytecode. The compiler 101 can identify the in-segment offset and the memory segment type based on the extended semantic parameter in the instruction bytecode, and calculate the randomized memory address based on the in-segment offset and the segment type.

[0091] In a possible implementation, for the data bytecode in the bytecode, the compiler 101 generates metadata information based on the compilation information of the data bytecode, where the metadata information includes a segment number and a segment offset. The segment number is used to indicate the memory segment to which the data bytecode belongs and the segment type, and the segment offset is used to indicate the in-segment offset of the data bytecode in the memory segment. The compiler 101 can merge these metadata information into a separate program section and attach the compiled bytecode.

[0092] Please continue to refer to FIG. 3. In steps b and c of the example shown in FIG. 3, after the Web Assembly compiler obtains the program source code, the Web Assembly compiler compiles the code in the program source code. Since the bytecode compiled by the Web Assembly compiler is bytecode containing an extended semantic parameter, the bytecode can also be referred to as an extended semantic instruction. For the instruction bytecode in the bytecode, the Web Assembly virtual machine directly translates the instruction bytecode into machine code based on the extended instruction semantic parameter in the instruction bytecode.

[0093] In the example shown in FIG. 3, for the data bytecode in the bytecode, the Web Assembly compiler can identify the address reference involved in the data bytecode according to the compilation information during the compilation of the program source code, and generate metadata information corresponding to the data bytecode. The metadata information includes a segment number and a segment offset. The segment number is used to indicate the memory segment to which the data bytecode belongs, and the segment offset is used to indicate the in-segment offset of the data bytecode in the memory segment. The Web Assembly compiler can merge these metadata information into a separate program section and attach the Web Assembly program.

[0094] In the format of the metadata information in the embodiments of the present application, the metadata information comprises one or more Reloc structures, each of the Reloc structures comprises a segment type, a segment offset and a memory address position, wherein the segment number indicates a segment to which a pointer refers, the segment offset indicates a position of the pointer in the segment in the linear memory, and the memory address position indicates a storage position of the pointer. An example code of the Reloc structure is as follows:

[0095] Referring to FIG. 4, FIG. 4 is a schematic diagram of metadata information provided by the embodiments of the present application. In the example shown in FIG. 4, the compiler 101 can identify address references in the data bytecode during the compilation of the data bytecode, and generate a Reloc structure for each address reference, and save the obtained metadata information.

[0096] For example, in the example shown in FIG. 4, the compiler 101 identifies that there are two address references in the data bytecode, and the compiler 101 generates two Reloc structures for the two address references, in which the segment numbers both indicate a data segment in the memory, and the segment offsets respectively point to two different offset positions in the data segment.

[0097] 202. The virtual machine determines a randomized memory segment base address based on a randomization algorithm.

[0098] After the virtual machine 102 receives the bytecode sent by the compiler 101, before the virtual machine 102 executes the bytecode, in order to ensure the security of the memory data, the virtual machine 102 needs to determine a randomized memory address based on a randomization algorithm. Specifically, the virtual machine 102 performs address randomization on the memory segments corresponding to the bytecode based on the randomization algorithm, that is, the virtual machine 102 changes the base addresses of the memory segments in the memory based on the randomization algorithm, and when the base addresses of the memory segments are changed by randomization, one or more memory address references corresponding to the bytecode are also changed.

[0099] During the execution of the bytecode by the virtual machine 102, the virtual machine 102 first performs an initialization operation. During the initialization operation, the virtual machine 102 re-arranges the segments in the memory using the randomization algorithm, changes the segment base addresses of the memory segments, and ensures that there is no overlap between the randomized segments. The virtual machine 102 stores the randomized memory segment base addresses to an object of the virtual machine 102, and the object is used to record the context environment information of the virtual machine 102.

[0100] Please refer to FIG. 3, in steps d to e of the example shown in FIG. 3, after the Web Assembly compiler compiles the program source code to obtain the Web Assembly program, the Web Assembly compiler sends the Web Assembly program to the Web Assembly virtual machine, and in the process of executing the Web Assembly program, the Web Assembly virtual machine first randomizes the layout of the memory address space, and the Web Assembly virtual machine randomly modifies the segment base address of each memory segment in the memory.

[0101] Please refer to FIG. 5, which is a memory address randomization diagram provided by an embodiment of the present application. In the example shown in FIG. 5, in order to prevent malicious attackers from attacking by using known memory addresses, the virtual machine 102 can randomly allocate the memory address space of the program at startup, so that it is difficult for malicious attackers to accurately predict the storage location of the critical data.

[0102] For example, in the example shown in FIG. 5, the critical data address of the virtual machine 102 before the address space distribution randomization is "0x601050". After the address space distribution randomization, the critical data address is changed from "0x601050" to "0x83bb50" due to the change of the segment base address of the memory segment, and the data stored in the original memory address "0x601050" after the address space distribution randomization becomes invalid memory data. Therefore, the attacker cannot predict the critical data address and can only obtain the address of the critical data through brute force cracking or other means, thereby increasing the difficulty of the attacker's attack and ensuring the security of the memory data.

[0103] Please refer to FIG. 6, which is a memory address space distribution randomization diagram provided by an embodiment of the present application. In the example shown in FIG. 6, before the address space distribution randomization, the plurality of memory segments in the memory have continuous address spaces, for example, the stack segment, the data segment and the heap segment in the target memory segment have continuous address spaces, and after the address space distribution randomization, the segment base addresses of the plurality of memory segments in the memory change, for example, the stack segment, the data segment and the heap segment after the memory address space randomization have random segment base addresses.

[0104] In the example shown in FIG. 6, after randomizing the memory address space, the virtual machine 102 saves the randomized segment base addresses in an object (VM context) that records context environment information in the virtual machine, for example, the virtual machine records the randomized stack segment base address "Stack-offset" in "VM context.stack", the randomized data segment base address "Data-offset" in "VM context.Data", and the randomized heap segment base address "Heap-offset" in "VM context.Heap".

[0105] The address space distribution randomization in the implementation of the present application includes two modes, namely JIT mode and AOT mode. In the JIT mode, the virtual machine implements randomization of the segment base addresses in the memory. In the AOT mode, the virtual machine 102 generates randomized segment base addresses through a newly added initialization function.

[0106] 203. The virtual machine calculates the randomized memory address based on the randomized memory segment base address and the extended semantic parameter.

[0107] The virtual machine 102 calculates the randomized memory address based on the randomized memory segment base address and the segment information indicated by the extended semantic parameter. Specifically, the virtual machine 102 determines the intra-segment offset based on the immediate number parameter of the extended semantic parameter, and determines the memory segment type based on the segment type identification parameter of the extended semantic parameter. The virtual machine 102 reads the randomized memory segment base address from an object that records context environment information in the virtual machine, and the randomized memory segment base address is the base address of the memory segment corresponding to the extended semantic parameter. The virtual machine 102 calculates the randomized memory address based on the randomized memory segment base address and the intra-segment offset.

[0108] After the virtual machine 102 calculates the randomized memory address, the virtual machine 102 calculates the randomized memory address based on the randomized memory segment base address and the intra-segment offset.

[0109] Please refer to FIG. 3, in steps f to g of the example shown in FIG. 3, after the Web Assembly virtual machine completes the randomization operation on the memory address space, the re-computed address reference after randomization is performed on the Web Assembly program. For example, assuming that the immediate number parameter argi in the bytecode is an address reference, and argi sec represents the segment type to which argi belongs, before using the address reference, the Web Assembly virtual machine will take the segment start address corresponding to the segment type from the context of the virtual machine (VM Context) according to argi sec, that is, the segment base, add argi to obtain the correct absolute address, that is, the memory address after randomization, and then use the absolute address as the correct address reference, including memory access and address calculation, etc.

[0110] In a possible implementation, for the data bytecode, after the virtual machine 102 generates the metadata information based on the compilation information of the data bytecode, the virtual machine 102 corrects the memory address reference of the data bytecode according to the metadata information, and the memory address involved in the data bytecode is the memory address after address randomization.

[0111] Please refer to FIG. 3, in steps f to g of the example shown in FIG. 3, for the data bytecode, after the Web Assembly virtual machine randomizes the memory address space, the Web Assembly virtual machine generates the metadata information corresponding to the data bytecode in the Web Assembly program according to the compilation information of the data bytecode, the Web Assembly virtual machine corrects the data address reference based on the metadata information, determines the memory address corresponding to the corrected data bytecode, and the Web Assembly virtual machine continues to execute the Web Assembly program based on the corrected memory address.

[0112] As can be seen from the above embodiments, the bytecode provided in the embodiments of the present application carries an extended semantic parameter, and the compiler can directly identify the intra-segment offset of one or more memory addresses involved in the bytecode based on the extended semantic parameter, so that the virtual machine can correct the address reference of the memory during the execution of the bytecode according to the intra-segment offset. Since the scheme in the embodiments of the present application can reduce the generated metadata information, the size overhead of the bytecode file is reduced, and the memory access performance is further improved.

[0113] Based on the above method embodiments, the embodiments of the present application further provide a memory address correction device, and the memory address correction device provided in the embodiments of the present application is specifically introduced as follows.

[0114] Please refer to FIG. 7, which is a structural diagram of a memory address randomization apparatus provided by an embodiment of the present application. In the example shown in FIG. 7, the memory address randomization apparatus 700 is used to implement the steps performed by the compiler and the virtual machine in the above embodiments, and the memory address randomization apparatus 700 includes a compiling unit 701 and a processing unit 702.

[0115] The compiling unit 701 is configured to compile program source code to generate bytecode, the bytecode including an extended semantic parameter, the extended semantic parameter being used to indicate segment information corresponding to one or more memory addresses involved by the bytecode, the segment information including an intra-segment offset of the one or more memory addresses in a memory segment to which the one or more memory addresses belong.

[0116] In a possible implementation, the extended semantic parameter includes an immediate number parameter and an extended flag parameter, the immediate number parameter being used to indicate the intra-segment offset, and the extended flag parameter being used to indicate a segment type of the memory segment to which the one or more memory addresses belong, the segment type including a heap segment, a stack segment, and a data segment.

[0117] In a possible implementation, the bytecode includes instruction bytecode, and the processing unit 702 is further configured to identify the intra-segment offset and the segment type based on the extended semantic parameter in the instruction bytecode, the intra-segment offset and the segment type being used to calculate the randomized memory address.

[0118] In a possible implementation, the bytecode includes data bytecode, and the processing unit 702 is further configured to generate metadata information based on compiling information of the data bytecode, the metadata information including a segment number and a segment offset, the segment number being used to indicate a memory segment to which the data bytecode belongs, and the segment offset being used to indicate the intra-segment offset of the data bytecode in the memory segment. The memory address involved by the data bytecode is corrected based on the metadata information, the memory address involved by the data bytecode being the randomized memory address.

[0119] In a possible implementation, the processing unit 702 is further configured to store the extended flag parameter based on a redundant bit in the bytecode when the redundant bit exists in the bytecode.

[0120] In a possible implementation, the processing unit 702 is further configured to add new instruction bytecode in the bytecode, the new instruction bytecode being used to carry the extended flag parameter.

[0121] In a possible implementation, the processing unit 702 is further configured to store the randomized memory segment base address to an object of the virtual machine, the object being used to record context environment information of the virtual machine.

[0122] In a possible implementation, the bytecode includes Web Assembly (WASM) bytecode.

[0123] In a possible implementation, the processing unit 702 is further configured to continue executing the bytecode according to the randomized memory address.

[0124] It can be understood that the compiling unit 701 and the processing unit 702 in the memory address randomization apparatus 700 can be mapped to the modules in the Web Assembly system 10 in FIG. 1 as functional modules, so as to realize the functions of the modules in the Web Assembly system 10.

[0125] It should be understood that the division of the units in the above apparatus is only a logical functional division, and in actual implementation, all or part of the units can be integrated into one physical entity or can be physically separated. The units in the apparatus can all be implemented in the form of software invoked by a processing element; or all be implemented in the form of hardware; or part of the units are implemented in the form of software invoked by a processing element and part of the units are implemented in the form of hardware. For example, each unit can be a separately arranged processing element, or can be integrated in a chip of the apparatus, in addition, the unit can also be stored in the form of a program in a memory and invoked and executed by a processing element of the apparatus. In addition, all or part of the units can be integrated together or can be independently implemented. The processing element described herein can be a processor, which can be an integrated circuit with a signal processing capability. In the implementation process, each step of the above method or each unit can be implemented by an integrated logic circuit of a hardware in a processing element or in the form of software invoked by a processing element.

[0126] It should be noted that, for the above method embodiments, in order to simply describe, they are all expressed as a series of action combinations, but those skilled in the art should know that the present application is not limited by the action order described, and those skilled in the art should also know that the embodiments described in the specification all belong to preferred embodiments, and the actions involved are not necessarily required by the present application.

[0127] Other reasonable step combinations that can be thought of by those skilled in the art according to the above description also belong to the protection scope of the present application. In addition, those skilled in the art should also be familiar with the fact that the embodiments described in the specification all belong to preferred embodiments, and the actions involved are not necessarily required by the present application.

[0128] Referring to FIG. 8, FIG. 8 is a structural schematic diagram of a computing device provided in an embodiment of the present application. As shown in FIG. 8, the computing device 800 includes a processor 801, a memory 802, a communication interface 803, and a bus 804, wherein the processor 801, the memory 802, and the communication interface 803 are coupled through the bus (not shown in the figure). The memory 802 stores instructions, and when the instructions stored in the memory 802 are executed, the computing device 800 executes the method performed by the network assembly system in the above method embodiments.

[0129] The computing device 800 can be one or more integrated circuits configured to implement the above method, for example, one or more application specific integrated circuits (ASICs), or one or more digital signal processors (DSPs), or one or more field programmable gate arrays (FPGAs), or a combination of at least two of these integrated circuit forms. For another example, when the units in the apparatus can be implemented in the form of a processing element scheduler, the processing element can be a general-purpose processor, such as a central processing unit (CPU) or other processor that can invoke programs. For another example, these units can be integrated together to be implemented in the form of a system-on-a-chip (SOC).

[0130] The processor 801 can be a central processing unit (CPU), and can also be other general-purpose processors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs) or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. The general-purpose processor can be a microprocessor, or any conventional processor.

[0131] The memory 802 can be a volatile memory or a nonvolatile memory, or can include both volatile and nonvolatile memory. Among them, the nonvolatile memory can be a read-only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrically EPROM (EEPROM), or a flash memory. The volatile memory can be a random access memory (RAM) used as an external cache. By way of example, and not limitation, many forms of RAM can be used, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchlink DRAM (SLDRAM), and direct rambus RAM (DR RAM).

[0132] The executable program code stored in the memory 802 is executed by the processor 801 to respectively implement the functions of the aforementioned units or modules, thereby implementing the aforementioned memory address correction method. That is, the memory 802 has instructions for executing the aforementioned memory address correction method.

[0133] The communication interface 803 uses a transceiving module such as, but not limited to, a network interface card, a transceiver, to implement communication between the computing device 800 and other devices or communication networks.

[0134] The bus 804 can include, in addition to a data bus, a power bus, a control bus, and a state signal bus, etc. The bus can be a peripheral component interconnect express (PCIe) bus, or an extended industry standard architecture (EISA) bus, a unified bus (Ubus or UB), a compute express link (CXL), a cache coherent interconnect for accelerators (CCIX), etc. The bus can be divided into an address bus, a data bus, a control bus, etc.

[0135] Referring to FIG. 9, FIG. 9 is a schematic diagram of a computing device cluster according to an embodiment of the present application. As shown in FIG. 9, the computing device cluster 900 includes at least one computing device 800.

[0136] As shown in FIG. 9, the computing device cluster 900 includes at least one computing device 800. The memory 802 in one or more computing devices 800 in the computing device cluster 900 can store the same instructions for performing the routing method described above.

[0137] In some possible implementations, the memory 802 in one or more computing devices 800 in the computing device cluster 900 can also respectively store partial instructions for performing the memory address correction method described above. In other words, the combination of one or more computing devices 800 can collectively execute the instructions for performing the memory address correction method described above.

[0138] It should be noted that the memory 802 in different computing devices 800 in the computing device cluster 900 can store different instructions, respectively, for performing part of the functions of the routing apparatus described above. That is, the instructions stored in the memory 802 in different computing devices 800 can implement the functions of one or more modules in the processing unit and the compiling unit.

[0139] In some possible implementations, one or more computing devices 800 in the computing device cluster 900 can be connected through a network. The network can be a wide area network or a local area network, etc.

[0140] Referring to FIG. 10, FIG. 10 is a schematic diagram of the connection of the computer devices in a computer cluster through a network according to an embodiment of the present application. As shown in FIG. 10, two computer devices 800A and 800B are connected through a network. Specifically, the communication interface in each computer device is connected to the network.

[0141] In a possible implementation, the memory in the computer device 800A stores instructions for executing the function of the compiling unit. Meanwhile, the memory in the computer device 800B stores instructions for executing the function of the processing unit.

[0142] It should be understood that the function of the computer device 800A shown in FIG. 10 can also be completed by multiple computer devices. Similarly, the function of the computer device 800B can also be completed by multiple computer devices.

[0143] In another embodiment of the present application, a computer readable storage medium is also provided, which stores computer execution instructions. When the processor of a device executes the computer execution instructions, the device executes the method performed by the network assembly system in the above method embodiments.

[0144] In another embodiment of the present application, a computer program product is also provided, which includes computer execution instructions stored in a computer readable storage medium. When the processor of a device executes the computer execution instructions, the device executes the method performed by the network assembly system in the above method embodiments.

[0145] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the above-described system, device and unit can refer to the corresponding process in the above method embodiments, which will not be described here.

[0146] In the several embodiments of the present application, it should be understood that the disclosed system, device and method can be implemented in other ways. For example, the above-described device embodiments are merely schematic, for example, the division of the units is only a logical function division, and actual implementation can have another division manner, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units or components shown or discussed can be indirect coupling or communication connection through some interfaces, devices or units, and can be electrical, mechanical or other forms.

[0147] The units described as separate components may or may not be physically separate, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment scheme.

[0148] In addition, each functional unit in each embodiment of the present application can be integrated in one processing unit, or each unit can exist physically, or two or more units can be integrated in one unit. The integrated unit can be realized in the form of hardware or in the form of a software functional unit.

[0149] The integrated unit, if realized in the form of a software functional unit and sold or used as an independent product, can be stored in a computer readable storage medium. Based on such understanding, the technical scheme of the present application essentially or the part that contributes to the prior art or the whole or part of the technical scheme can be embodied in the form of a software product. The computer software product is stored in a storage medium, including a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM, read-only memory), a random access memory (RAM, random access memory), a magnetic disk or an optical disk, and various program code storage media.< / argisec> < / argn> < / arg2> < / arg1> < / opcode> < / argn> < / argi> < / argisec> < / arg2> < / arg1> < / opcode>

Claims

1. A method of randomizing memory addresses, comprising: The method is applied to a WebAssembly system for network compilation, and the method comprises: compiling program source code to generate bytecode, the bytecode comprising an extended semantic parameter, the extended semantic parameter being used to indicate segment information corresponding to one or more memory addresses involved in the bytecode, the segment information comprising a segment offset of the one or more memory addresses in a memory segment to which the one or more memory addresses belong; randomizing the memory segment involved in the bytecode based on a randomization algorithm to determine a randomized memory segment base address; calculating a randomized memory address based on the randomized memory segment base address and the extended semantic parameter.

2. The method of claim 1, wherein, The extended semantic parameter comprises an immediate number parameter and an extended flag parameter, the immediate number parameter being used to indicate the segment offset, and the extended flag parameter being used to indicate a segment type of the memory segment to which the one or more memory addresses belong, the segment type comprising a heap segment, a stack segment and a data segment.

3. The method of claim 2, wherein, The bytecode comprises instruction bytecode, and the method further comprises: identifying the segment offset and the segment type based on the extended semantic parameter in the instruction bytecode, the segment offset and the segment type being used to calculate the randomized memory address.

4. The method according to claim 1 or 2, characterized in that, The bytecode comprises data bytecode, and the method further comprises: generating metadata information based on compilation information of the data bytecode, the metadata information comprising a segment number and a segment offset, the segment number being used to indicate the memory segment to which the data bytecode belongs, and the segment offset being used to indicate the segment offset of the data bytecode in the memory segment to which the data bytecode belongs; modifying a memory address involved in the data bytecode based on the metadata information, the memory address involved in the data bytecode being the randomized memory address.

5. The method according to any one of claims 2 to 4, characterized in that, The method further comprises: storing the extended flag parameter based on a redundant bit in the bytecode when the redundant bit exists in the bytecode.

6. The method according to any one of claims 2 to 4, characterized in that, The method further comprises: adding new instruction bytecode in the bytecode, the new instruction bytecode being used to carry the extended flag parameter.

7. The method according to any one of claims 1 to 6, characterized in that, The WebAssembly system comprises a compiler and a virtual machine, the compiler being used to compile program source code to obtain bytecode, and the virtual machine being used to execute the bytecode, and after the determination of the randomized memory segment base address, the method further comprises: storing the randomized memory segment base address to an object of the virtual machine, the object being used to record context environment information of the virtual machine.

8. The method according to any one of claims 1 to 7, characterized in that, The bytecode comprises WebAssembly (WASM) bytecode.

9. The method according to any one of claims 1 to 8, characterized in that, After the calculation of the randomized memory address based on the randomized memory segment base address and the extended semantic parameter, the method further comprises: continuing to execute the bytecode according to the randomized memory address.

10. An apparatus for randomizing memory addresses, comprising: The method comprises: a compiling unit configured to compile program source code to generate bytecode, the bytecode comprising an extended semantic parameter, the extended semantic parameter being used to indicate segment information corresponding to one or more memory addresses involved in the bytecode, the segment information comprising a segment offset of the one or more memory addresses in a memory segment to which the one or more memory addresses belong; a processing unit configured to randomize the memory segment involved in the bytecode based on a randomization algorithm to determine a randomized memory segment base address; and The processing unit is further configured to calculate the randomized memory address based on the randomized memory segment base address and the extended semantic parameter.

11. The apparatus of claim 10, wherein, The extended semantic parameter comprises an immediate number parameter and an extended flag parameter, the immediate number parameter is used to indicate the intra-segment offset, and the extended flag parameter is used to indicate a segment type of a memory segment to which the one or more memory addresses belong, the segment type comprises a heap segment, a stack segment, and a data segment.

12. The apparatus of claim 10 or 11, wherein, The bytecode comprises an instruction bytecode, and the processing unit is further configured to: identify the intra-segment offset and the segment type based on an extended semantic parameter in the instruction bytecode, the intra-segment offset and the segment type being used to calculate the randomized memory address.

13. The apparatus of claim 10 or 11, wherein, The bytecode comprises a data bytecode, and the processing unit is further configured to: generate metadata information based on compilation information of the data bytecode, the metadata information comprising a segment number and a segment offset, the segment number being used to indicate a memory segment to which the data bytecode belongs, and the segment offset being used to indicate an intra-segment offset of the data bytecode in the memory segment; correct a memory address involved in the data bytecode based on the metadata information, the memory address being a randomized memory address.

14. The apparatus of any one of claims 11 to 13, wherein, The processing unit is further configured to: store the extended flag parameter based on a redundant bit in the bytecode when the redundant bit exists in the bytecode.

15. The apparatus of any one of claims 11-13, wherein, The processing unit is further configured to: add a new instruction bytecode in the bytecode, the new instruction bytecode being used to carry the extended flag parameter.

16. The apparatus of any one of claims 10 to 15, wherein, The processing unit is further configured to: store the randomized memory segment base address to an object of a virtual machine, the object being used to record context environment information of the virtual machine, the virtual machine being a virtual machine in a WebAssembly (WASM) system.

17. The apparatus of any one of claims 10-16, wherein, The bytecode comprises a WebAssembly (WASM) bytecode.

18. The apparatus of any one of claims 10-17, wherein, The processing unit is further configured to: continue to execute the bytecode according to the randomized memory address.

19. A computing device, comprising: A computing device comprising a processor coupled to a memory, the memory storing instructions that, when executed by the processor, cause the computing device to perform any one of the methods of claims 1-9.

20. A cluster of computing devices, characterized in that, A computing device cluster comprising at least one computing device, the computing device comprising a processor coupled to a memory, the processor configured to store instructions that, when executed by the processor, cause the computing device cluster to perform any one of the methods of claims 1-9.

21. A computer-readable storage medium having stored thereon instructions, The instructions, when executed, cause a computer to perform any one of the methods of claims 1-9.

22. A computer program product comprising instructions therein, characterised in that, The instructions, when executed, cause a computer to implement any one of the methods of claims 1-9.

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