Shift register, driving circuit, driving method, and display device

Abstract

A shift register, a driving circuit, a driving method, and a display device. The shift register (100, 200a, 200b, 300, 500, 600) comprises: a first control circuit (110, 210, 310, 510, 610) configured to, under the control of a first clock signal from a first clock terminal, provide the first clock signal to a first node, or under the control of a first power supply voltage of a first power supply, provide the first power supply voltage to the first node; a second control circuit (120, 220, 320, 520, 620) configured to, under the control of a potential of the first node, use a second power supply voltage of a second power supply to control a potential of a second node; a gating circuit (130, 230, 330, 530, 630) configured to, under the control of a plurality of gating signals from a plurality of gating terminals, use the first power supply voltage of the first power supply to control the potential of the second node; and an output circuit (140, 240, 340, 540, 640) configured to, under the control of the potentials of the first node and the second node, provide the second power supply voltage or a second clock signal from a second clock terminal to an output terminal as an output signal.

Description

Shift register, driving circuit, driving method and display device

[0001] The present application claims priority to Chinese Patent Application No. 202410832055.2, filed on June 25, 2024, the contents of which are incorporated herein by reference in their entirety. TECHNICAL FIELD

[0002] The present disclosure relates to the technical field of display, and in particular to a shift register, a driving circuit, a driving method and a display device. BACKGROUND

[0003] In order to achieve good compatibility between power consumption and high refresh rate, a display usually adopts a regional high refresh rate technology, which requires a driving circuit to have the ability of flexible opening. Common shift register driving circuits have single driving ability for a display, and cannot be adjusted in real time according to a picture, so as to fail to meet more flexible high refresh rate requirements for the display. SUMMARY

[0004] The present disclosure provides a shift register, a driving circuit, a driving method and a display device.

[0005] According to a first aspect, the present disclosure provides a shift register, comprising a first control circuit configured to provide a first clock signal from a first clock terminal to a first node under control of the first clock signal or provide a first power supply voltage to the first node under control of the first power supply voltage; a second control circuit configured to control a potential of a second node by a second power supply voltage of a second power supply under control of a potential of the first node; a gate circuit configured to control the potential of the second node by a first power supply voltage of a first power supply under control of a plurality of gate signals from a plurality of gate terminals; and an output circuit configured to provide the second power supply voltage or a second clock signal from a second clock terminal to an output terminal as an output signal under control of the potentials of the first node and the second node, wherein the plurality of gate signals control output of the output signal.

[0006] According to a second aspect, the present disclosure provides a driving circuit, comprising M shift registers according to any one of the embodiments of the present disclosure; wherein an mth shift register is electrically connected with a first gate terminal, an m+1th shift register is electrically connected with a second gate terminal, a first gate signal output by the first gate terminal and a second gate signal output by the second gate terminal are not simultaneously at an effective level when the first gate signal and the second gate signal are not the same, 1≤m

[0007] According to a third aspect, the present disclosure provides a display device, comprising a display panel; and a driving circuit as provided in the embodiments of the present disclosure; wherein the display panel comprises M pixel rows arranged in an array, and the driving circuit comprises M shift registers for driving the M pixel rows in the display panel respectively.

[0008] According to a fourth aspect, the present disclosure provides a driving method applied to the shift register as provided in the embodiments of the present disclosure, comprising: in a gate-on phase, controlling a specified one of a plurality of gate signals to be at a second level, and controlling the other gate signals of the plurality of gate signals to be at a first level; and in a gate-off phase, controlling at least one of the other gate signals of the plurality of gate signals to be at the second level. BRIEF DESCRIPTION OF DRAWINGS

[0009] FIG. 1 is a structural schematic diagram of a shift register according to an embodiment of the present disclosure;

[0010] FIG. 2A is a structural schematic diagram of a shift register according to another embodiment of the present disclosure;

[0011] FIG. 2B is a structural schematic diagram of a shift register according to another embodiment of the present disclosure;

[0012] FIG. 3 is a structural schematic diagram of a shift register according to another embodiment of the present disclosure;

[0013] FIG. 4 is a signal timing diagram of a shift register according to an embodiment of the present disclosure;

[0014] FIG. 5 is a structural schematic diagram of a shift register according to another embodiment of the present disclosure;

[0015] FIG. 6 is a structural schematic diagram of a shift register according to another embodiment of the present disclosure;

[0016] FIG. 7 is a structural schematic diagram of a driving circuit according to an embodiment of the present disclosure;

[0017] FIG. 8 is a structural schematic diagram of a display device according to an embodiment of the present disclosure; and

[0018] FIG. 9 is a flowchart of a driving method according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0019] In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the following will be combined with the accompanying drawings to make a clear and complete description of the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all. Based on the described embodiments of the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without any inventive effort fall within the protection scope of the present disclosure. It should be noted that throughout the drawings, the same elements are denoted by the same or similar reference numerals. In the following description, some specific embodiments are only for the purpose of description, and should not be understood as any limitation on the present disclosure, but only as examples of the embodiments of the present disclosure. When it is possible to cause confusion to the understanding of the present disclosure, the conventional structure or configuration will be omitted. It should be noted that the shape and size of each component in the drawings do not reflect the actual size and ratio, but only illustrate the content of the embodiments of the present disclosure.

[0020] Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should be understood as the general meaning understood by a person of ordinary skill in the art. The "first", "second" and similar words used in the embodiments of the present disclosure do not represent any order, number or importance, but are only used to distinguish different components.

[0021] In addition, in the description of the embodiments of the present disclosure, the term "connected" or "connected to" can mean that two components are directly connected, or that two components are connected via one or more other components. In addition, the two components can be connected or coupled by wired or wireless means.

[0022] The source and drain of the switching transistor used in the embodiments of the present disclosure are symmetrical, so the source and drain can be interchangeable. In the embodiments of the present disclosure, according to its function, the control pole can be called the control pole, one of the source and drain can be called the first pole, and the other of the source and drain can be called the second pole.

[0023] It should be noted that in the description of the embodiments of the present disclosure, the symbol OUT can represent both the output signal and the output terminal. Similarly, the symbol CKLE1 can represent both the first clock terminal and the first clock signal provided by the first clock terminal, the symbol VGH can represent both the first power supply and the first power supply voltage provided by the first power supply, and the symbol VGL can represent both the second power supply and the second power supply voltage provided by the second power supply. For example, the power supply VGL and the power supply LVGL can provide a low voltage, and the power supply VGH and the power supply GVDD can provide a high level. The following embodiments are the same as this, and similar parts will not be described again.

[0024] FIG. 1 is a structural schematic diagram of a shift register according to an embodiment of the present disclosure.

[0025] As shown in FIG. 1, the shift register 100 includes a first control circuit 110, a second control circuit 120, a gating circuit 130, and an output circuit 140.

[0026] In the embodiment of the present disclosure, the first control circuit 110 is electrically connected with the first clock terminal CLKE1 and the second power supply VGL, or the first control circuit 110 is electrically connected with the first power supply VGH and the second power supply VGL. Under the control of the first clock signal CLKE1 from the first clock terminal CLKE1, the first control circuit 110 provides the first clock signal CLKE1 to the first node QB. Or under the control of the first power supply voltage VGH of the first power supply VGH, the first control circuit 110 provides the first power supply voltage VGH to the first node QB.

[0027] For example, the first clock signal CLKE1 or the first power supply voltage VGH can control the first control circuit 110 to switch between the on and off states. For example, when the first clock signal CLKE1 controls the first control circuit 110 to be in the on state, the first clock signal CLKE1 is in the on state between the first clock terminal CLKE1 and the first node QB, and the first clock terminal CLKE1 is written to the first node QB. When the first power supply voltage VGH controls the first control circuit 110 to be in the on state, the first power supply VGH is in the on state between the first power supply VGH and the first node QB, and the first power supply voltage VGH is written to the first node QB.

[0028] In the embodiment of the present disclosure, the second control circuit 120 is electrically connected with the second power supply VGL, the first node QB, and the second node Q. Under the control of the potential of the first node QB, the second control circuit 120 controls the potential of the second node Q by using the second power supply voltage VGL of the second power supply VGL.

[0029] For example, the potential of the first node QB can control the second power supply VGL and the second node Q to be in the on state or the off state. When the second power supply VGL and the second node Q are in the on state, the second control circuit 120 can write the second power supply voltage VGL to the second node Q to control the potential of the second node Q.

[0030] In the embodiment of the present disclosure, the gating circuit 130 is electrically connected with the plurality of gating terminals D0, D0’, D1’, …, Dn’, the first power supply VGH, and the second node Q. Under the control of the plurality of gating signals D0, D0’, D1’, …, Dn’ from the plurality of gating terminals D0, D0’, D1’, …, Dn’, the gating circuit 130 controls the potential of the second node Q by using the first power supply voltage VGH of the first power supply VGH.

[0031] For example, the plurality of gate signals D0, D0', D1',..., Dn' can control the first power supply VGH and the second node Q to be in a conductive state or a non-conductive state. When the first power supply VGH and the second node Q are in the conductive state, the gate circuit 130 can write the first power supply voltage VGH to the second node Q to control the potential of the second node Q.

[0032] In the embodiment of the present disclosure, the second control circuit 120 can pull down the potential of the second node Q based on the second power supply voltage VGL. The gate circuit 130 can pull up the potential of the second node Q based on the first power supply voltage VGH.

[0033] In the embodiment of the present disclosure, the output circuit 140 is electrically connected with the output terminal OUT, the first node QB, the second node Q, the second power supply VGL and the second clock terminal CLKE2. Under the control of the potentials of the first node QB and the second node Q, the second power supply voltage VGL or the second clock signal CLKE2 from the second clock terminal CLKE2 is provided to the output terminal OUT as an output signal OUT.

[0034] For example, the potential of the first node QB can control the second power supply VGL and the output terminal OUT to be in a conductive state or a non-conductive state. When the second power supply VGL and the output terminal OUT are in the conductive state, the output circuit 140 provides the second power supply voltage VGL to the output terminal OUT, and the output terminal OUT outputs a low-level signal.

[0035] For example, the potential of the second node Q can control the second clock terminal CLKE2 and the output terminal OUT to be in a conductive state or a non-conductive state. When the second clock terminal CLKE2 and the output terminal OUT are in the conductive state, the output circuit 140 provides the second clock signal CLKE2 to the output terminal OUT, and the output terminal OUT outputs the second clock signal CLKE2.

[0036] In the embodiment of the present disclosure, the output signal OUT can be used to drive an N-type transistor in a pixel circuit. For example, when the level of the input signal OUT is high, the N-type transistor is turned on, and a data signal can be written, so as to realize picture refreshing. When the level of the input signal OUT is low, the N-type transistor is turned off, and the data signal cannot be written, so as to realize picture non-refreshing, keeping unchanged.

[0037] For example, the level of the selection signal D0, D1',..., Dn' can represent whether the transistor in the pixel circuit electrically connected with the shift register 100 is turned on. For example, when the selection signal D0, D1',..., Dn' are all high level, the first power voltage VGH is written into the second node Q, the voltage of the first node Q is pulled high, and the output terminal OUT outputs the second clock signal CLKE2 as the output signal OUT. At this time, the N-type transistor in the pixel circuit can be switched to the on state, and the corresponding display image is refreshed. When any one of the selection signals D0, D1',..., Dn' is low level, the first power VGH is in the off state between the second node Q, and the second power voltage VGH cannot be written into the second node Q. The level of the output signal OUT output by the output terminal OUT remains low. At this time, the N-type transistor in the pixel circuit remains in the off state based on the low-level output signal OUT, and the corresponding display image is not refreshed.

[0038] According to the embodiments of the present disclosure, the potentials of the first node QB and the second node Q are controlled according to the selection signals, whether the shift register 100 is in the gating stage can be determined, and whether one pixel row electrically connected with the shift register 100 is refreshed can be controlled. In the driving circuit including a plurality of shift registers, any shift register can be selected for gating through the selection signals, so that each pixel row in the pixel circuit has the ability of flexible opening, and the control of whether a single pixel row is refreshed is realized.

[0039] In some embodiments, under the control of the first level of the specified selection signal D0 from the specified gating terminal D0 among the plurality of gating terminals D0, D0', D1',..., Dn', the gating circuit 130 provides the second power voltage VGL to the second node Q. Under the control of the first level of the plurality of selection signals from the plurality of gating terminals except the specified gating terminal, the gating circuit 130 provides the first power voltage VGH to the second node Q.

[0040] In the embodiments of the present disclosure, the selection signal D0' among the plurality of selection signals D0, D0', D1',..., Dn' is the specified selection signal. The first level is high level, and the second level is low level.

[0041] When the selection signals D0', D1',..., Dn' are all high level, and the selection signal D0' is low level, the shift register 100 is in the gating stage. Under the control of the high level of the selection signals D0'', D1',..., Dn' and the low level of the selection signal D0, the gating circuit 130 controls the first power voltage VGH to be written into the second node Q, and the potential of the second node Q is high potential at this time. Under the control of the second node Q, the first control circuit 110 controls the first node QB to be low level.

[0042] In this case, the output terminal OUT and the second clock terminal CLKE2 are in a conducting state, and the output terminal OUT outputs the second clock signal CLKE2 as the output signal OUT.

[0043] In the embodiments of the present disclosure, when any one of the gate signals D0', D1',..., Dn' is at a low level, the shift register 100 is in a non-gating stage.

[0044] For example, when any one of the gate signals D0', D1',..., Dn' is at a low level, the first power voltage VGH and the second node Q are in an off state, and the first power voltage VGH cannot pull up the potential of the second node Q. In this case, the output terminal OUT and the second clock terminal CLKE2 are in an off state, and the output terminal OUT cannot output the second clock signal CLKE2 as the output signal OUT.

[0045] When the first clock signal CLKE1 or the first power voltage VGH is written to the first node QB, the output terminal OUT and the second power VGL are in a conducting state, and the output terminal OUT outputs the second power voltage VGL as the output signal OUT.

[0046] FIG. 2A is a structural schematic diagram of a shift register according to another embodiment of the present disclosure.

[0047] As shown in FIG. 2A, the shift register 200a includes a first control circuit 210, a second control circuit 220, a gating circuit 230, and an output circuit 240.

[0048] In the embodiments of the present disclosure, the second control circuit 220 is electrically connected with the first node QB, the output terminal OUT, and the second power VGL. Under the control of the output signal OUT, the second control circuit 220 provides the second power voltage VGL to the first node QB.

[0049] For example, the output signal OUT can control the first node QB and the second power VGL to be in a conducting state and an off state. When the output signal OUT controls the first node QB and the second power VGL to be in a conducting state, the second power voltage VGL is written to the first node QB to pull down the potential of the first node QB.

[0050] In some embodiments, the first control circuit 210 is also electrically connected with the first node QB, the second node Q, and the second power VGL. Under the control of the potential of the second node Q, the first control circuit 210 provides the second power voltage VGL to the first node.

[0051] For example, the potential of the second node Q can control the first node QB and the second power supply VGL to be in the conductive state and the non-conductive state. When the potential of the second node Q controls the first node QB and the second power supply VGL to be in the conductive state, the second power supply voltage VGL is written into the first node QB to pull down the potential of the first node QB.

[0052] In the embodiment of the present disclosure, in the non-gating phase, when the first control circuit 210 controls the potential of the first node QB to be high, under the control of the high potential of the first node QB, the second power supply voltage VGL pulls down the potential of the second node Q through the second control circuit 220. In the gating phase, when the gating circuit 230 controls the potential of the second node Q to be high, under the control of the high potential of the second node Q, the second power supply voltage VGL pulls down the potential of the first node QB through the first control circuit 210.

[0053] In the embodiment of the present disclosure, the first control circuit 210 and the second control circuit 220 can control the potentials of the first node QB and the second node Q to be reversed, which makes the output circuit 240 of the shift register 100 normally output the output signal OUT.

[0054] FIG. 2B is a structural schematic diagram of a shift register according to another embodiment of the present disclosure.

[0055] As shown in FIG. 2B, the shift register 200b includes a first control circuit 210, a second control circuit 220, a gating circuit 230, an output circuit 240, and a third control circuit 250.

[0056] In the embodiment of the present disclosure, the first control circuit 210, the second control circuit 220, the gating circuit 230, and the output circuit 240 are similar in structure to the first control circuit 110, the second control circuit 120, the gating circuit 130, and the output circuit 140 described above, respectively, and will not be described again for simplicity.

[0057] In the embodiment of the present disclosure, the third control circuit 250 is electrically connected with the first node QB, the first power supply VGH, and a third node P. The gating circuit 230 is electrically connected with the third node P. Under the control of a plurality of gate signals D0’, D1’, …, Dn’, the potential of the third node P is controlled by the first power supply voltage VGH. Under the control of the potential of the third node P, the third control circuit 250 provides the first power supply voltage VGH to the potential of the first node QB.

[0058] For example, the plurality of gate signals D0’, D1’, …, Dn’ can control the third node P and the first power supply VGH to be in the conductive state and the non-conductive state. When the third node P and the first power supply VGH are in the conductive state, the first power supply voltage VGH is written into the third node P to pull up the potential of the third node P.

[0059] The third node P can control the second node Q and the first power supply VGH to be in the on state and the off state. When the second node Q and the first power supply VGH are in the on state, the first power supply voltage VGH is written into the second node Q to pull up the potential of the second node Q.

[0060] In the embodiment of the present disclosure, since the ability of the gating circuit 230 to write the first power supply voltage VGH into the second node Q is weak, in order to ensure that the potential of the second node Q can be stably kept at a high level in the gating phase. The third control unit 250 writes the first power supply voltage VGH into the second node Q to enhance the ability to pull up the potential of the second node Q.

[0061] In some embodiments, the third control circuit 250 is also electrically connected with the designated gating terminal D0 and the second power supply VGL.

[0062] In the embodiment of the present disclosure, under the control of the high level of the designated gating signal D0, the third control circuit 250 provides the second power supply voltage VGL to the third node P to pull down the potential of the third node P, realizing the reset of the potential of the third node P.

[0063] For example, the high level of the designated gating signal D0 controls the second power supply VGL and the third node P to be in the on state. The third control circuit 250 writes the second power supply voltage VGL into the third node P.

[0064] In the embodiment of the present disclosure, the first control circuit 210 is electrically connected with the third node P, the first node QB, the second node Q and the second power supply VGL. Under the control of the potential of the third node P, the first control circuit 210 provides the second power supply voltage VGL to the first node QB.

[0065] For example, the potential of the third node P controls the second power supply VGL and the first node QB to be in the on state. The third control circuit 250 writes the second power supply voltage VGL into the first node QB to pull down the potential of the first node QB.

[0066] For example, in the gating phase, when the potential of the third node P is at a high level, the first power supply VGH and the second node Q are in the on state, and the potential of the second node Q is also at a high level. Under the control of the high level of the second node Q, the second control circuit 220 pulls down the potential of the first node QB, thereby avoiding the coupling of the second node QB to the high potential. The low potential of the first node QB can ensure that the second power supply VGL and the output terminal OUT are in the off state, thereby avoiding the second power supply voltage VGL to pull down the output signal OUT, causing the output signal OUT output by the output terminal OUT to have noise.

[0067] FIG. 3 is a structural schematic diagram of a shift register according to another embodiment of the present disclosure.

[0068] As shown in FIG. 3, the shift register 300 includes a first control circuit 310, a second control circuit 320, a gating circuit 330, and an output circuit 340.

[0069] In the embodiment of the present disclosure, the gating circuit 330 includes a first transistor T1 to a ninth transistor T9. The first transistor T1 to the ninth transistor T9 are gating transistors. The control electrodes of the first transistor T1 to the ninth transistor T9 are electrically connected to a plurality of gating terminals D0, D1’, …, D7’, D0’ respectively. The control electrode of the ninth transistor T9 is electrically connected to the designated gating terminal D0’.

[0070] The first electrode of the first transistor T1 is electrically connected to a first power supply VGH, the second electrode of the first transistor T1 is electrically connected to the first electrode of the second transistor T2, the second electrode of the second transistor T2 is electrically connected to the first electrode of the third transistor T3, the second electrode of the third transistor T3 is electrically connected to the first electrode of the fourth transistor T4, the second electrode of the fourth transistor T4 is electrically connected to the first electrode of the fifth transistor T5, the second electrode of the fifth transistor T5 is electrically connected to the first electrode of the sixth transistor T6, the second electrode of the sixth transistor T6 is electrically connected to the first electrode of the seventh transistor T7, the second electrode of the seventh transistor T7 is electrically connected to the first electrode of the eighth transistor T8, and the second electrode of the eighth transistor T8 is electrically connected to a second node Q.

[0071] The first electrode of the ninth transistor T9 is electrically connected to the second node Q, and the second electrode of the ninth transistor T9 is electrically connected to a second power supply VGL.

[0072] In the embodiment of the present disclosure, the first control circuit 310 includes a tenth transistor T10 and an eleventh transistor T11.

[0073] The control electrode and the first electrode of the tenth transistor T10 are electrically connected to a first clock terminal CLKE1, and the second electrode of the tenth transistor T10 is electrically connected to a first node QB.

[0074] The control electrode of the eleventh transistor T11 is electrically connected to the second node Q, the first electrode of the eleventh transistor T11 is electrically connected to the first node QB, and the second electrode of the eleventh transistor T11 is electrically connected to the second power supply VGL.

[0075] In the embodiment of the present disclosure, the second control circuit 320 includes a twelfth transistor T12 and a thirteenth transistor T13.

[0076] The control electrode of the twelfth transistor T12 is electrically connected to the first node QB, the first electrode of the twelfth transistor T12 is electrically connected to the second node Q, and the second electrode of the twelfth transistor T12 is electrically connected to the second power supply VGL.

[0077] The control electrode of the thirteenth transistor T13 is electrically connected to the output terminal OUT, the first electrode of the thirteenth transistor T13 is electrically connected to the first node QB, and the second electrode of the thirteenth transistor T13 is electrically connected to the second power supply VGL.

[0078] In the embodiments of the present disclosure, the output circuit 340 includes a fourteenth transistor T14, a fifteenth transistor T15, and a first capacitor C1.

[0079] The control electrode of the fourteenth transistor T14 is electrically connected to the second node Q, the first electrode of the fourteenth transistor T14 is electrically connected to the second clock terminal CLKE2, and the second electrode of the fourteenth transistor T14 is electrically connected to the output terminal OUT.

[0080] The control electrode of the fifteenth transistor T15 is electrically connected to the first node QB, the first electrode of the fifteenth transistor T15 is electrically connected to the output terminal OUT, and the second electrode of the fifteenth transistor T15 is electrically connected to the second power supply VGL.

[0081] The first end of the first capacitor C1 is electrically connected to the second node Q, and the second end of the first capacitor C1 is electrically connected to the output terminal OUT.

[0082] In the embodiments of the present disclosure, the first transistor T1 to the fifteenth transistor T15 are N-type TFT transistors, for example, thin film transistors with an active layer of indium gallium zinc oxide (IGZO). Those skilled in the art can understand that the first transistor T1 to the fifteenth transistor T15 in the present disclosure can also be P-type TFT transistors, for example, thin film transistors with an active layer of low-temperature polysilicon (LTPS). The level of the gate drive signal of each transistor can be changed accordingly.

[0083] In addition, those skilled in the art can understand that the capacitor can be implemented as a single capacitor or a plurality of parallel or series capacitor units, as long as it can realize its corresponding function.

[0084] In the description of the embodiments of the present disclosure, the first node QB and the second node Q do not represent actual components, but represent the convergence point of the relevant circuit connection in the circuit diagram.

[0085] FIG. 4 is a signal timing diagram of the shift register in FIG. 3. The working process of the shift register provided by the embodiments of the present disclosure will be described below by taking the structure of the shift register 300 shown in FIG. 3 as an example in combination with the signal timing diagram shown in FIG. 4. FIG. 4 shows the signal timing of the shift register 300 in five stages S1-S5 in the process.

[0086] In the embodiments of the present disclosure, the strobe signals received by the strobe terminals D0', D1',..., D7' are strobe signals D0, D1',..., D7' respectively, and the strobe signal received by the strobe terminal D0 is designated as the strobe signal D0'.

[0087] In the first stage S1, the levels of the strobe signals D0, D0', D1',..., D7' are high, high, low, low, low, low, low, low and low respectively. The first clock signal CLKE1 and the second clock signal CLKE2 are both toggled from low level to high level.

[0088] The first transistor T1, the tenth transistor T10 and the ninth transistor T9 are turned on, and the second transistor T2 to the eighth transistor T8 are turned off.

[0089] The first clock signal CLKE1 is written into the first node QB through the tenth transistor T10. When the first clock signal CLKE1 is toggled from low level to high level, the potential of the first node QB is also toggled from low level to high level.

[0090] Under the control of the high level of the first node QB, the twelfth transistor T12 is turned on. The second power voltage VGL is written into the second node Q through the twelfth transistor T12, and the potential of the second node Q is low.

[0091] Under the control of the high level of the first node QB, the fifteenth transistor T15 is turned on. Under the control of the low level of the second node Q, the fourteenth transistor T14 is turned off. At this time, the first power voltage VGH is output to the output terminal OUT through the fifteenth transistor T15, and the output terminal OUT outputs a low level signal.

[0092] In the second stage S2, the levels of the strobe signals D0, D0', D1',..., D7' are high, low, high, high, high, high, high, high and high respectively. The first clock signal CLKE1 and the second clock signal CLKE2 are both low.

[0093] The tenth transistor T10 and the ninth transistor T9 are turned off, and the first transistor T1 to the eighth transistor T8 are turned on.

[0094] The first power voltage VGH is written into the second node Q through the first transistor T1 to the eighth transistor T8, and the potential of the second node Q is pulled up and the first end of the first capacitor C1 is charged. Under the control of the high level of the second node Q, the eleventh transistor T11 is turned on. The second power voltage VGL is written into the first node QB through the eleventh transistor T11, and the potential of the first node QB is pulled down.

[0095] Under the control of the low level of the first node QB, the fifteenth transistor T15 is off. Under the control of the high level of the second node Q, the fourteenth transistor T14 is on. At this time, the low level of the second clock signal CLKE2 is output to the output terminal OUT through the fourteenth transistor T14, and the output terminal OUT outputs a low level signal.

[0096] In the third stage S3, the levels of the selection signals D0, D0', D1',..., D7' are high, low, high, high, high, high, high, high and high respectively. The first clock signal CLKE1 is low level, and the second clock signal CLKE2 is high level.

[0097] The states of the first transistor T1 to the fifteenth transistor T15 are the same as those in the second stage S2. The first power voltage VGH continues to charge the second node Q. Under the bootstrap action of the first capacitor C1, the potential of the second node Q is pulled high again.

[0098] Under the control of the low level of the first node QB, the fifteenth transistor T15 is off. Under the control of the high level of the second node Q, the fourteenth transistor T14 is on. At this time, the low level of the second clock signal CLKE2 is output to the output terminal OUT through the fourteenth transistor T14, and the output terminal OUT outputs a low level signal.

[0099] Under the control of the high level of the output signal OUT, the thirteenth transistor T13 is on. The second power voltage VGL is written into the first node QB through the thirteenth transistor T13, and the potential of the first node QB remains low level. At this time, the fifteenth transistor T15 is completely off, which can avoid the noise of the fifteenth transistor T15 to the high level signal output by the output terminal OUT.

[0100] In the fourth stage S4, the levels of the selection signals D0, D0', D1',..., D7' are low, high, low, high, high, high, high, high and high respectively. The first clock signal CLKE1 and the second clock signal CLKE2 are both low level.

[0101] The third transistor T3 to the ninth transistor T9 are on, and the first transistor T1 and the second transistor T2 are off. The second power voltage VGL is written into the second node Q through the ninth transistor T9, and the potential of the second node Q jumps from high level to low level. Under the action of the first capacitor C1, the potential of the output terminal OUT is also low level. The potential of the first node QB remains low level of the previous stage.

[0102] In the fifth stage S5, the levels of the selection signals D0, D0', D1',..., D7' are low, high, low, high, high, high, high, high and high respectively. The first clock signal CLKE1 is high level, and the second clock signal CLKE2 is low level.

[0103] The first transistor T1, the third transistor T3 to the ninth transistor T9 are turned on, and the second transistor T2 is turned off.

[0104] The high level of the first clock signal CLKE1 is written into the first node QB through the tenth transistor T10, and the potential of the first node QB is pulled high. Under the control of the high level of the first node QB, the potential of the second node Q is pulled low by the second power supply voltage VGL.

[0105] Under the control of the high level of the first node QB, the fifteenth transistor T15 is turned on. Under the control of the low level of the second node Q, the fourteenth transistor T14 is turned off. At this time, the first power supply voltage VGH is output to the output terminal OUT through the fifteenth transistor T15, and the output terminal OUT outputs a low level signal.

[0106] In the embodiment of the present disclosure, a plurality of selection signals can support the selection display of a plurality of pixel rows. For example, the number of selection signals is 2n, the number of decoding bits realized by the selection signals is n, and the maximum supported row number is 2n. For example, the number of decoding bits is 14 bits, and the maximum supported row number reaches 16384 rows. For example, the number of decoding bits realized by the selection signals D0-D7, D0'-D7' is 8, and 256 rows can be selected. If the number of rows needs to be increased, each increase of 1 selection signal can support the selection of double the number of rows. FIG. 5 is a structural schematic diagram of a shift register according to another embodiment of the present disclosure.

[0107] As shown in FIG. 5, the shift register 500 includes a first control circuit 510, a second control circuit 520, a selection circuit 530, an output circuit 540, and a third control circuit 550.

[0108] In the embodiment of the present disclosure, the first control circuit 510, the second control circuit 520, the selection circuit 530, and the output circuit 540 are similar in structure to the first control circuit 410, the second control circuit 420, the selection circuit 430, and the output circuit 440 described above, and will not be described again for the sake of simplicity.

[0109] In the embodiment of the present disclosure, the third control circuit 550 includes a sixteenth transistor T16, a seventeenth transistor T17, and a second capacitor C2.

[0110] The control electrode of the sixteenth transistor T16 is electrically connected to the third node P, the first electrode of the sixteenth transistor T16 is electrically connected to the first power supply VGH, and the second electrode of the sixteenth transistor T16 is electrically connected to the second node Q.

[0111] The control electrode of the seventeenth transistor T17 is electrically connected to the designated selection terminal D0', the first electrode of the seventeenth transistor T17 is electrically connected to the third node P, and the second electrode of the seventeenth transistor T17 is electrically connected to the second power supply VGL.

[0112] The first end of the second capacitor C2 is electrically connected to the third node P, and the second end of the second capacitor C2 is electrically connected to the second node Q.

[0113] In the embodiment of the present disclosure, since the gating circuit 530 includes more transistors, the ability of the first power supply voltage VGH to be written into the second node Q through the first transistor T1 to the eighth transistor T8 is weak, and the third control circuit 550 charges the potential of the first node Q.

[0114] Under the control of the high level of the third node P, the sixteenth transistor T16 is turned on, and the first power supply voltage VGH is written into the second node Q through the sixteenth transistor T16. The first power supply voltage VGH also charges the second capacitor C2 when writing into the third node P. The high level of the third node P is maintained through the second capacitor C2.

[0115] The third control circuit 530 can improve the writing ability of the first power supply voltage VGH to the second node QB.

[0116] In the embodiment of the present disclosure, when the strobe signal D0' is at a high level, the seventeenth transistor T17 and the ninth transistor T9 are turned on at the same time. The seventeenth transistor T17 discharges the third node P and pulls down the potential of the third node P. The ninth transistor T9 discharges the second node Q and pulls down the potential of the second node Q, thereby realizing the reset of the second node Q and the third node P.

[0117] FIG. 6 is a structural schematic diagram of a shift register according to another embodiment of the present disclosure.

[0118] As shown in FIG. 6, the shift register 600 includes a first control circuit 610, a second control circuit 620, a gating circuit 630, an output circuit 640, and a third control circuit 650.

[0119] In the embodiment of the present disclosure, the second control circuit 620, the gating circuit 630, the output circuit 640, and the third control circuit 650 are similar in structure to the first control circuit 510, the gating circuit 530, the output circuit 540, and the third control circuit 550 described above, and are not described again for simplicity.

[0120] In the embodiment of the present disclosure, the first control circuit 610 includes a tenth transistor T10, an eleventh transistor T11, an eighteenth transistor T18, a nineteenth transistor T19, and a twentieth transistor T20.

[0121] The control electrode and the first electrode of the tenth transistor T10 are electrically connected to the first power supply VGH, and the second electrode of the tenth transistor T10 is electrically connected to the fifth node H.

[0122] The control electrode of the eleventh transistor T11 is electrically connected to the second node Q, the first electrode of the eleventh transistor T11 is electrically connected to the fifth node H, and the second electrode of the eleventh transistor T11 is electrically connected to the second power supply Q.

[0123] The control electrode of the eighteenth transistor T18 is electrically connected to the third node P, the first electrode of the eighteenth transistor T18 is electrically connected to the first node QB, and the second electrode of the eighteenth transistor T18 is electrically connected to the second power supply Q.

[0124] The control electrode of the nineteenth transistor T19 is electrically connected to the fifth node H, the first electrode of the nineteenth transistor T19 is electrically connected to the first power supply VGH, and the second electrode of the nineteenth transistor T19 is electrically connected to the first node QB.

[0125] The control electrode of the twentieth transistor T20 is electrically connected to the second node Q, the first electrode of the twentieth transistor T20 is electrically connected to the first node QB, and the second electrode of the twentieth transistor T20 is electrically connected to the second power supply VGLQ.

[0126] In the embodiments of the present disclosure, when the second node Q is at a low level, the first power supply voltage VGH continuously pulls up the potential of the first node QB under the actions of the tenth transistor T10, the eleventh transistor T11, the nineteenth transistor T19, and the twentieth transistor T20, thereby having a continuous noise reduction effect on the shift register 600.

[0127] When the second node Q is at a high level, the third node P is also at a high level. Under the action of the high level of the third node P, the eighteenth transistor T18 is turned on. The eighteenth transistor T18 can pull down the potential of the first node QB in advance, thereby cutting off the twelfth transistor T12 in advance, guaranteeing the charging capability of the second node Q, and making the potential of the second node Q stably maintain at a high level.

[0128] FIG. 7 is a structural schematic diagram of a driving circuit according to an embodiment of the present disclosure.

[0129] As shown in FIG. 7, the driving circuit 700 includes M shift registers. For example, M = 254. The shift registers GOA1, GOA2, GOA3, …, GOA254 can be any one of the shift registers 100, 200, 300, 500, and 600 described above.

[0130] In the embodiments of the present disclosure, the mth shift register is electrically connected to the first gate signal line, the m+1th shift register is electrically connected to the second gate signal line, the first gate signal output by the first gate signal line is at an effective level when the second gate signal output by the second gate signal line is not at an effective level, 1≤m<M, and M is a positive integer greater than 1.

[0131] For example, the first selection signal line can be selection signal line d0', and the second selection signal line can be selection signal line d0. The designated gating terminal D0 of the first shift register is electrically connected with selection signal line d0', and the designated gating terminal D0 of the second shift register is electrically connected with selection signal line d0. The selection signals provided by selection signal line d0' and selection signal line d0 are not simultaneously at the effective level.

[0132] For example, the timing change of the selection signals provided by selection signal line d0' and selection signal line d0 can refer to the selection signal D0' and selection signal D0 shown in FIG. 4. When selection signal d0' is at a high level, selection signal d0 is at a low level. When selection signal d0 is at a high level, selection signal d0' is at a low level.

[0133] In the embodiments of the present disclosure, the driving circuit 700 further includes a first clock line clke1 and a second clock line clke2.

[0134] The first clock terminal CLKE1 of the mth shift register is connected with the first clock line clke1, and the second clock terminal CLKE2 of the mth shift register is connected with the second clock line clke2. The first clock terminal CLKE1 of the m+1th shift register is connected with the second clock line clke2, and the second clock terminal CLKE2 of the m+1th shift register is connected with the first clock line clke1.

[0135] For example, the first clock terminal CLKE1 of the first shift register is connected with the first clock line clke1, and the second clock terminal CLKE2 of the first shift register is connected with the second clock line clke2. The first clock terminal CLKE1 of the second shift register is connected with the second clock line clke2, and the second clock terminal CLKE2 of the second shift register is connected with the first clock line clke1. c lke1.

[0136] The timing change of the clock signals provided by the first clock line clke1 and the second clock line clke2 can refer to the first clock signal CLKE1 and the second clock signal CLKE12 shown in FIG. 4.

[0137] In the embodiments of the present disclosure, the driving circuit 700 includes 16 selection signal lines d0-D7, d0'-d7' and 2 clock signal lines. The 16 selection signals provided by the 16 selection signal lines d0-d7, d0'-d7' can be divided into two groups of selection signals, and each group includes 8 selection signals. For example, selection signals d0-d7 are a positive gating group, and selection signals d0'-d7' are a negative gating group. The timing change of the selection signals d0-d7, d0'-d7' can refer to the selection signals d0-d7, d0'-d7' shown in FIG. 4.

[0138] The selection signal in the positive selection group is active when it is at a different level than the corresponding selection signal in the negative selection group. For example, selection signal d1 and selection signal d1' are not active at the same time, and selection signal d7 and selection signal d7' are not active at the same time.

[0139] The first transistor T1 to the eighth transistor T8 in the shift register included in the driving circuit 700 are electrically connected to eight selection signal lines d0-d7, d0'-d7' respectively. The first transistor T1 is electrically connected to one of the selection signal line d0 and the selection signal line d0', the second transistor T2 is electrically connected to one of the selection signal line d1 and the selection signal line d1', the third transistor T3 is electrically connected to one of the selection signal line d3 and the selection signal line d3', and so on, and the eighth transistor T8 is electrically connected to one of the selection signal line d7 and the selection signal line d7'.

[0140] For example, the shift register can record the selection signal as 1 when it receives the selection signal in the positive selection group, and record the selection signal as 0 when it receives the selection signal in the negative selection group. The selection signals received by D7' to D0' of the shift register GOA1 are 00000001, the selection signals received by D7' to D0' of the shift register GOA2 are 00000010, the selection signals received by D7' to D0' of the shift register GOA3 are 00000011, and so on, and the selection signals received by D7' to D0' of the shift register GOA254 are 11111110.

[0141] Based on the 8 selection signals of each group, the 2 8 = 256 rows of pixel rows can be selected. However, the selection signals 00000000 and 11111111 are used to reset all the second nodes Q in the driving circuit 700, so the driving circuit 700 only outputs 254 output signals for selecting (256-2) rows of pixel rows. For example, the average of the selection signals d0'-d7' is high, and all the second nodes Q in the driving circuit 700 are reset based on the selection signals d0'-d7'.

[0142] In the embodiments of the present disclosure, the first control circuit of the shift register in the driving circuit 700 can be arranged in the backplane of the display device to reduce the number of signal lines in the display device.

[0143] FIG. 8 is a structural schematic diagram of a display device according to an embodiment of the present disclosure.

[0144] [Corrections according to Rule 91, 15.07.2025] As shown in FIG. 8, the display device 800 includes a display panel 810 and a driving circuit 820.

[0145] In the embodiments of the present disclosure, the display panel 810 includes a plurality of sub-pixel units Pixel arranged in an array, and the driving circuit is configured to drive the sub-pixel units Pixel. Each row of pixel units Piexl in the display panel 810 forms a pixel row 811.

[0146] In the embodiments of the present disclosure, the driving circuit 820 can be the driving circuit 700 described above, and details are not repeated here. One shift register 821 in the driving circuit 820 can drive one pixel row 811, thereby controlling whether a single pixel row is gated on.

[0147] It should be noted that the number of sub-pixel units included in the display panel 810 is only illustrative, and the present disclosure does not limit the number of sub-pixel units.

[0148] The driving circuit 820 includes a plurality of shift registers supporting gating, each of which is connected to sub-pixel units of different rows. When it is necessary to refresh sub-pixel units of a certain row, the corresponding shift register can be gated on by the driving circuit, thereby achieving the refresh of the specified row of sub-pixel units.

[0149] FIG. 9 is a flowchart of a driving method according to an embodiment of the present disclosure.

[0150] As shown in FIG. 9, the driving method can include operations S910-S920.

[0151] In the embodiments of the present disclosure, the driving method can be applied to the shift register 100, the shift register 200, the shift register 300, the shift register 500, and the shift register 600 described above.

[0152] In operation S910, in the gating phase, a specified one of a plurality of gate signals is controlled to be at a second level, and the gate signals other than the specified one are all at a first level.

[0153] In operation S920, in the non-gating phase, at least one of the gate signals other than the specified one is controlled to be at the second level.

[0154] In the embodiments of the present disclosure, operations S910-S920 are similar to the operations performed by the shift register 300, the shift register 500, and the shift register 600 described above, and details are not repeated here.

[0155] The computer program product of the first aspect can include one or more non-transitory computer-readable media storing instructions that, when executed, cause one or more processors to perform the operations of the first aspect. The one or more non-transitory computer-readable media can include, for example, magnetic media such as one or more magnetic disks, magnetic tapes or cassettes; optical media such as one or more compact discs (CD), optical discs or discs (for example, DVD, Blu-ray Disc®, digital video disc, ultra density disc, ultra-compact disc, any optical media, etc.); semiconductor media such as solid state hard drives (for example, flash memory, solid state USB drives, etc.); any other suitable medium; or any suitable combination of media.

[0156] Those skilled in the art will understand that features of the various embodiments and / or claims of the present disclosure can be combined and / or sub-combined, even if such combinations or sub-combinations are not expressly noted in the present disclosure. In particular, features of the various embodiments and / or claims of the present disclosure can be combined and / or sub-combined in any number of ways, without departing from the spirit and scope of the present disclosure. All such combinations and / or sub-combinations are within the scope of the present disclosure.

[0157] The above describes embodiments of the present disclosure. However, these embodiments are merely for illustrative purposes, and are not intended to limit the scope of the present disclosure. Although the above describes each embodiment separately, this does not mean that the measures in each embodiment cannot be used advantageously in combination. The scope of the present disclosure is defined by the appended claims and their equivalents. Those skilled in the art can make various substitutions and modifications without departing from the scope of the present disclosure, and all such substitutions and modifications shall fall within the scope of the present disclosure.

Claims

1. A shift register, comprising: A first control circuit is configured to provide the first clock signal to control a first node under the control of a first clock signal from a first clock terminal, or to provide the first power supply voltage to the first node under the control of a first power supply voltage from a first power supply. The second control circuit is configured to control the potential of the second node using the second power supply voltage of the second power supply under the control of the potential of the first node. The gating circuit is configured to control the potential of the second node using a first power supply voltage from a first power supply, under the control of multiple gating signals from multiple gating terminals. The output circuit is configured to provide the second power supply voltage or a second clock signal from the second clock terminal to the output terminal as an output signal under the control of the potentials of the first node and the second node, wherein the plurality of strobe signals control the output of the output signal.

2. The shift register according to claim 1, wherein, The gating circuit is electrically connected to the second node, the plurality of gating terminals, the first power supply, and the second power supply, and the gating circuit is configured to: Under the control of a first level of a designated gating signal from a designated gating terminal among the plurality of gating terminals, the second power supply voltage is provided to the second node; as well as Under the control of a first level of multiple gating signals from multiple gating terminals other than the designated gating terminal, the first power supply voltage is provided to the second node.

3. The shift register according to claim 1 or 2, further comprising: The third control circuit is electrically connected to the first node, the first power supply, and the third node. The third control circuit is configured to provide the first power supply voltage to the potential of the first node under the control of the potential of the third node; The gating circuit, under the control of the multiple gating signals, uses the first power supply voltage to control the potential of the third node.

4. The shift register according to claim 3, wherein, The third control circuit is also electrically connected to the designated gating terminal and the second power supply. The third control circuit is further configured to provide the second power supply voltage to the third node under the control of the first level of the designated strobe signal.

5. The shift register according to claim 1, wherein, The second control circuit is electrically connected to the first node, the output terminal, and the second power supply: The second control circuit is configured to provide a second power supply voltage to the first node under the control of the output signal.

6. The shift register according to claim 1, wherein, The first control circuit is electrically connected to the first node, the second node, and the second power supply. The first control circuit is also configured to provide the second power supply voltage to the first node under the control of the second node.

7. The shift register according to claim 3, wherein, The first control circuit is electrically connected to the third node, the first node, and the second power supply; The first control circuit is also configured to provide the second power supply voltage to the first node under the control of the potential of the third node.

8. The shift register according to claim 1, wherein, The gating circuit includes a first transistor through a ninth transistor; Wherein, the control electrodes of the first transistor to the ninth transistor are respectively electrically connected to the plurality of gating terminals, and the control electrode of the ninth transistor is electrically connected to a designated gating terminal. The first terminal of the first transistor is electrically connected to the first power supply; the second terminal of the first transistor is electrically connected to the first terminal of the second transistor; the second terminal of the second transistor is electrically connected to the first terminal of the third transistor; the second terminal of the third transistor is electrically connected to the first terminal of the fourth transistor; the second terminal of the fourth transistor is electrically connected to the first terminal of the fifth transistor; the second terminal of the fifth transistor is electrically connected to the first terminal of the sixth transistor; the second terminal of the sixth transistor is electrically connected to the first terminal of the seventh transistor; the second terminal of the seventh transistor is electrically connected to the first terminal of the eighth transistor; and the second terminal of the eighth transistor is electrically connected to the second node. The first electrode of the ninth transistor is electrically connected to the second node, and the second electrode of the ninth transistor is electrically connected to the second power supply.

9. The shift register according to claim 1, wherein, The first control circuit includes a tenth transistor and an eleventh transistor; The control electrode and the first electrode of the tenth transistor are electrically connected to the first clock terminal, and the second electrode of the tenth transistor is electrically connected to the first node. The control electrode of the eleventh transistor is electrically connected to the second node, the first electrode of the eleventh transistor is electrically connected to the first node, and the second electrode of the eleventh transistor is electrically connected to the second power supply.

10. The shift register according to claim 1, wherein, The second control circuit includes a twelfth transistor and a thirteenth transistor; The control electrode of the twelfth transistor is electrically connected to the first node, the first electrode of the twelfth transistor is electrically connected to the second node, and the second electrode of the twelfth transistor is electrically connected to the second power supply. The control electrode of the thirteenth transistor is electrically connected to the output terminal, the first electrode of the thirteenth transistor is electrically connected to the first node, and the second electrode of the thirteenth transistor is electrically connected to the second power supply.

11. The shift register according to claim 1, wherein, The output circuit includes a fourteenth transistor, a fifteenth transistor, and a first capacitor; The control electrode of the fourteenth transistor is electrically connected to the second node, the first electrode of the fourteenth transistor is electrically connected to the second clock terminal, and the second electrode of the fourteenth transistor is electrically connected to the output terminal. The control electrode of the fifteenth transistor is electrically connected to the first node, the first electrode of the fifteenth transistor is electrically connected to the output terminal, and the second electrode of the fifteenth transistor is electrically connected to the second power supply. The first terminal of the first capacitor is electrically connected to the second node, and the second terminal of the first capacitor is electrically connected to the output terminal.

12. The shift register according to claim 3, wherein, The third control circuit includes a sixteenth transistor, a seventeenth transistor, and a second capacitor; The control electrode of the sixteenth transistor is electrically connected to the third node, the first electrode of the sixteenth transistor is electrically connected to the first power supply, and the second electrode of the sixteenth transistor is electrically connected to the second node. The control electrode of the seventeenth transistor is electrically connected to a designated gating terminal, the first electrode of the seventeenth transistor is electrically connected to the third node, and the second electrode of the seventeenth transistor is electrically connected to the second power supply. The first terminal of the second capacitor is electrically connected to the third node, and the second terminal of the second capacitor is electrically connected to the second node.

13. The shift register according to claim 1, wherein, The first control circuit includes a tenth transistor, an eleventh transistor, an eighteenth transistor, a nineteenth transistor, and a twentieth transistor; Among them, the control electrode and the first electrode of the tenth transistor are electrically connected to the first power supply, and the second electrode of the tenth transistor is electrically connected to the fifth node; The control electrode of the eleventh transistor is electrically connected to the second node, the first electrode of the eleventh transistor is electrically connected to the fifth node, and the second electrode of the eleventh transistor is electrically connected to the second power supply; The control electrode of the eighteenth transistor is electrically connected to the third node, the first electrode of the eighteenth transistor is electrically connected to the first node, and the second electrode of the eighteenth transistor is electrically connected to the second power supply; The control electrode of the nineteenth transistor is electrically connected to the fifth node, the first electrode of the nineteenth transistor is electrically connected to the first power supply, and the second electrode of the nineteenth transistor is electrically connected to the first node; The control electrode of the twentieth transistor is electrically connected to the second node, the first electrode of the twentieth transistor is electrically connected to the first node, and the second electrode of the twentieth transistor is electrically connected to the second power supply.

14. A driving circuit, comprising M shift registers as described in any one of claims 1-13; in, The m-th shift register is electrically connected to the first strobe signal line, the (m + 1)-th shift register is electrically connected to the second strobe signal line, and the first strobe signal output by the first strobe signal line and the second strobe signal output by the second strobe signal line are not both valid levels at the same time, where 1 ≤ m < M and M is a positive integer greater than 1.

15. The driving circuit according to claim 14, further comprising a first clock line and a second clock line; in, The first clock terminal of the m-th shift register is connected to the first clock line, and the second clock terminal of the m-th shift register is connected to the second clock line; The first clock terminal of the (m + 1)-th shift register is connected to the second clock line, and the second clock terminal of the (m + 1)-th shift register is connected to the first clock line.

16. A display device, comprising: A display panel; And The driving circuit as described in claim 14 or 15; Among them, the display panel includes M pixel rows arranged in an array, and the M shift registers included in the driving circuit are used to drive the M pixel rows in the display panel respectively.

17. A driving method, applied to the shift register as described in any one of claims 1-13, comprising: In the strobe stage, controlling a specified strobe signal among the multiple strobe signals to be a second level, and the strobe signals other than the specified strobe signal among the multiple strobe signals are all at a first level; In the non-strobe stage, controlling at least one of the strobe signals other than the specified strobe signal among the multiple strobe signals to be a second level.

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