Display substrate and display device

Abstract

A display substrate and a display device. The display substrate comprises a display area and a first bezel area. The display area comprises a plurality of sub-pixels and data lines in a plurality of data signal lines. The first bezel area comprises a bending area. In the bending area, data connection lines of the plurality of data signal lines and a plurality of first power supply connection structures are arranged at intervals in a first direction, and at least one data connection line is arranged between two adjacent first power supply connection structures.

Description

Display substrate and display device

[0001] The present application claims priority to the Chinese patent application No. 202410834081.9, filed on June 25, 2024, and entitled "Display substrate and display device", the content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] Embodiments of the present disclosure relate to, but are not limited to, the technical field of display, in particular to a display substrate and a display device. BACKGROUND

[0003] Organic light emitting diode (OLED) and quantum dot light emitting diode (QLED) are active light emitting display devices, which have the advantages of self-emission, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, low cost, etc. With the continuous development of display technology, flexible display devices using OLED or QLED as light emitting devices and controlled by thin film transistors (TFT) have become the mainstream products in the current display field. SUMMARY

[0004] The following is a summary of the subject matter of the detailed description herein. This summary is not intended to limit the scope of the claims.

[0005] In a first aspect, the embodiments of the present disclosure provide a display substrate, comprising a display area and a first frame area located at one side of the display area, the first frame area being provided with a bending area;

[0006] a plurality of sub-pixels located in the display area;

[0007] a plurality of data signal lines located in the display area and the first frame area and electrically connected with the plurality of sub-pixels, the plurality of data signal lines being configured to provide data signals to the plurality of sub-pixels; the data signal lines comprise data lines and data connection lines, the data lines being located in the display area, the data connection lines being located in the first frame area and electrically connected with corresponding data lines, at least part of the line segments of the data connection lines being located in the bending area in the same data signal line;

[0008] a plurality of first power supply connection structures located in the bending area, the plurality of first power supply connection structures are arranged at intervals along a first direction and extend along a second direction, and are configured to provide a first power supply signal to the plurality of sub-pixels, the first direction intersects the second direction;

[0009] In the bending area, along the first direction, the data connection lines of the plurality of data signal lines are arranged at intervals with the plurality of first power supply connection structures, and at least one data connection line is arranged between any two adjacent first power supply connection structures.

[0010] In an example embodiment, in the bending area, along the first direction, the plurality of first power supply connection structures are arranged at equal intervals.

[0011] In an example embodiment, in the bending area, along the first direction, a plurality of first distances between the plurality of data connection lines are consistent, the first distance being a distance between any two adjacent data connection lines.

[0012] In an example embodiment, in the bending area, along the first direction, the plurality of data connection lines are arranged at equal intervals between any two adjacent first power supply connection structures.

[0013] In an example embodiment, in the bending area, along the first direction, the first distance is greater than or equal to a second distance, the second distance being a distance between the first power supply connection structure and an adjacent data connection line.

[0014] In an example embodiment, in the bending area, along the first direction, a ratio of the first distance to the second distance is greater than or equal to 1.5.

[0015] In an example embodiment, in the bending area, along the first direction, a size of the first power supply connection structure is consistent with a size of the data connection line.

[0016] In an example embodiment, in a direction perpendicular to a plane on which the display substrate is located, the display substrate includes a base and a driving circuit layer disposed on the base, the driving circuit layer includes a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer disposed on the base in sequence, and at least part of a line segment of the data connection line and the plurality of first power supply connection structures are located in the fourth conductive layer.

[0017] In an example embodiment, the first frame area further comprises a first fan-out area in a plane parallel to the plane on which the display substrate is located, the first fan-out area is located between the display area and the bending area in the second direction; the display substrate further comprises a first power supply connection line, the data connection line comprises a first data connection line and a second data connection line, the data line is electrically connected to the second data connection line through the first data connection line in the same data signal line, wherein:

[0018] The first power supply connection line is located in the first fan-out area, the first power supply connection line extends along the first direction and is electrically connected to the plurality of first power supply connection structures, the plurality of first power supply connection structures provide the plurality of sub-pixels with first power supply signals through the first power supply connection line;

[0019] The first data connection line is located in the first fan-out area, at least part of the plurality of first data connection lines is located in the first conductive layer and at least part of the plurality of first data connection lines is located in the second conductive layer, the first data connection line located in the first conductive layer and the first data connection line located in the second conductive layer are arranged alternately;

[0020] The second data connection line is located in the bending area, the second data connection line is located in the fourth conductive layer in a direction perpendicular to the plane on which the display substrate is located, at least part of the data connection line comprises the second data connection line.

[0021] In an example embodiment, the first power supply connection line is located in the fourth conductive layer in a direction perpendicular to the plane on which the display substrate is located, the first power supply connection line is directly connected to the plurality of first power supply connection structures; in the same data signal line, the first data connection line and the second data connection line are electrically connected through a via, and the first data connection line and the data line are electrically connected through a via.

[0022] In an example embodiment, the first frame area further comprises a second fan-out area in a plane parallel to the plane on which the display substrate is located, the second fan-out area is located on a side of the bending area away from the display area in the second direction, the display substrate further comprises a first power supply line, and the data connection line further comprises a third data connection line, the first data connection line is electrically connected to the third data connection line through the second data connection line in the same data connection line; wherein:

[0023] The first power supply line is located in the second fan-out area, and the first power supply line is connected to the plurality of first power supply connection structures.

[0024] The third data connection lines are located in the second fan-out area, and in the plurality of third data connection lines, at least part of the third data connection lines are located in the first conductive layer and at least part of the third data connection lines are located in the second conductive layer, and the third data connection lines located in the first conductive layer and the third data connection lines located in the second conductive layer are arranged alternately.

[0025] In the exemplary embodiments, in a direction perpendicular to a plane in which the display substrate is located, the first power supply line is located in the fourth conductive layer, and the first power supply line is directly connected with the plurality of first power supply connection structures; in the same data signal line, the second data connection line and the third data connection line are electrically connected through a via.

[0026] In the exemplary embodiments, in a direction parallel to a plane in which the display substrate is located, the first frame area further comprises a binding area, and in the second direction, the binding area is located on a side of the second fan-out area away from the display area, and the binding area is provided with a first power supply pad and a driving circuit; the third data connection line is electrically connected with the driving circuit; and the first power supply line extends to the binding area and is electrically connected with the first power supply pad.

[0027] In a second aspect, the present disclosure further provides a display device comprising the display substrate as described in any of the above embodiments.

[0028] Other aspects can become apparent from a review of the drawings and detailed description. BRIEF DESCRIPTION OF DRAWINGS

[0029] The accompanying drawings are included to provide a further understanding of the technical solutions of the present disclosure, and constitute a part of the specification, and are used to explain the technical solutions of the present disclosure together with the embodiments of the present disclosure, and do not constitute a limitation on the technical solutions of the present disclosure. The shapes and sizes of the components in the drawings do not reflect the true proportions, and the purpose is only to schematically illustrate the present disclosure.

[0030] FIG. 1 shows a structural schematic diagram of a display device;

[0031] FIG. 2 shows a structural schematic diagram of a display substrate;

[0032] FIG. 3 shows an enlarged structural schematic diagram of a first frame area;

[0033] FIG. 4 shows a structural schematic diagram of a display substrate;

[0034] FIG. 5 shows a structural schematic diagram of a display substrate;

[0035] FIG. 6 shows a resistance curve schematic diagram of a data signal line;

[0036] FIG. 7 shows a structural schematic diagram of a display substrate provided by the embodiments of the present disclosure;

[0037] Fig. 8a is an enlarged structural view of the position M1 in Fig. 7;

[0038] Fig. 8b is an enlarged structural view of the position M2 in Fig. 7;

[0039] Fig. 8c is an enlarged structural view of the position M1 in Fig. 7;

[0040] Fig. 9 is a schematic view of a display device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0041] Embodiments of the present disclosure will be described below in detail with reference to the accompanying drawings. Embodiments of the present disclosure can be implemented in various forms. It will be readily apparent to those skilled in the art that the embodiments and contents can be changed into various forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be construed as being limited to the contents described in the following embodiments. Embodiments of the present disclosure and features in the embodiments can be arbitrarily combined with each other without conflict unless otherwise specified, and the embodiments of the present disclosure can be implemented by combining the features of the embodiments.

[0042] In the drawings, the size, the thickness, or the region of each constituent element shown in the drawings can be exaggerated for clarity in some cases. Therefore, the size, the thickness or the region of one embodiment of the present disclosure is not limited to the actual one. The same applies to the same constituent elements in different drawings. Moreover, the present disclosure is not limited to the shapes, the values, and the like illustrated in the drawings, and includes appropriate modifications thereof.

[0043] In the present disclosure, ordinal numbers such as "first", "second", and "third" are used to avoid confusion among constituent elements, and are not used to describe the number of the constituent elements.

[0044] In the present disclosure, words of a positional relation or a positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like are used to describe the positional relationship of constituent elements with reference to the drawings, and are used only for convenience in describing the embodiments and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore should not be construed as limiting the present disclosure. The positional relationship of the constituent elements can be appropriately changed according to the direction of the constituent elements described. Therefore, it is not limited to the words described in the text, and can be appropriately changed according to the situation.

[0045] In the present disclosure, unless clearly specified and limited otherwise, the terms "mounting", "connection", and "linking" should be interpreted in a broad sense. For example, it can be fixed connection, or detachable connection, or integral connection; it can be mechanical connection, or electrical connection; it can be direct connection, or indirect connection through intermediate components, or internal connection of two elements. For those skilled in the art, the meaning of the above terms in the present disclosure can be understood according to the circumstances.

[0046] In the present disclosure, a transistor refers to an element including at least three terminals of gate electrode, drain electrode, and source electrode. The transistor has a channel region between the drain electrode (or drain terminal, drain connection region, or drain electrode) and the source electrode (or source terminal, source connection region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In the present disclosure, the channel region refers to a region through which current mainly flows.

[0047] In the present disclosure, the first electrode can be a drain electrode, and the second electrode can be a source electrode, or the first electrode can be a source electrode, and the second electrode can be a drain electrode. In the case of using a transistor with opposite polarity or in the case of changing the direction of current in the circuit operation, the functions of "source electrode" and "drain electrode" can sometimes be exchanged with each other. Therefore, in the present disclosure, "source electrode" and "drain electrode" can be exchanged with each other. In the present disclosure, the control electrode can be a gate electrode.

[0048] In the present disclosure, "electrically connected" includes the case where the constituent elements are connected together through an element having some electrical action. The element having some electrical action is not particularly limited as long as it can perform the transmission and reception of electrical signals between the connected constituent elements. The element having some electrical action can be, for example, an electrode or a wiring, or a switching element such as a transistor, or another functional element such as a resistor, an inductor, or a capacitor, and the like.

[0049] FIG. 1 shows a structural schematic diagram of a display device, a display substrate can include a timing controller, a data signal driving circuit, a scan signal driving circuit, a light emission signal driving circuit, and a pixel array, the timing controller is connected with the data signal driving circuit, the scan signal driving circuit, and the light emission signal driving circuit respectively, the data signal driving circuit is connected with a plurality of data signal lines (D1 to Dn) respectively, the scan signal driving circuit is connected with a plurality of scan signal lines (G1 to Gm) respectively, and the light emission signal driving circuit is connected with a plurality of light emission signal lines (E1 to Eo) respectively. The pixel array can include a plurality of sub-pixels Pxij, i and j can be natural numbers, at least one sub-pixel Pxij can include a circuit unit and a light emitting device connected with the circuit unit, the circuit unit can include a pixel driving circuit, and the pixel driving circuit can be connected with a scan signal line, a light emission signal line, and a data signal line (which can be referred to as a data line) respectively. In an exemplary embodiment, the timing controller can provide a gray value and a control signal suitable for the specification of the data signal driving circuit to the data signal driving circuit, can provide a clock signal, a scan start signal, and the like suitable for the specification of the scan signal driving circuit to the scan signal driving circuit, and can provide a clock signal, an emission stop signal, and the like suitable for the specification of the light emission signal driving circuit to the light emission signal driving circuit. The data signal driving circuit can generate a data voltage to be provided to the data signal lines D1, D2, D3, …, and Dn using the gray value and the control signal received from the timing controller. For example, the data signal driving circuit can sample the gray value using the clock signal, and apply a data voltage corresponding to the gray value to the data signal lines D1 to Dn in units of a pixel row. n can be a natural number. The scan signal driving circuit can generate a scan signal to be provided to the scan signal lines G1, G2, G3, …, and Gm by receiving the clock signal, the scan start signal, and the like from the timing controller. For example, the scan signal driving circuit can sequentially provide the scan signal having an on-level pulse to the scan signal lines G1 to Gm. For example, the scan signal driving circuit can be configured in the form of a shift register, and can generate the scan signal in such a manner that the scan start signal provided in the form of an on-level pulse is sequentially transferred to a next stage circuit under the control of the clock signal. m can be a natural number. The light emission signal driving circuit can generate an emission signal to be provided to the light emission signal lines E1, E2, E3, …, and Eo by receiving the clock signal, the emission stop signal, and the like from the timing controller. For example, the light emission signal driving circuit can sequentially provide the emission signal having an off-level pulse to the light emission signal lines E1 to Eo. For example, the light emission driver can be configured in the form of a shift register, and can generate the emission signal in such a manner that the emission stop signal provided in the form of an off-level pulse is sequentially transferred to a next stage circuit under the control of the clock signal. o can be a natural number.

[0050] FIG. 2 shows a structural schematic diagram of a display panel. As shown in FIG. 2, the display panel can include a display area AA and a frame area BB located at the periphery of the display area AA. In some examples, the periphery area BB can include a first frame area (lower frame) B1 and a second frame area (upper frame) B2 oppositely arranged in the second direction Y, and a third frame area (left frame) B3 and a fourth frame area (right frame) B4 oppositely arranged in the first direction X. The first frame area B1 is in communication with the third frame area B3 and the fourth frame area B4, and the second frame area B2 is in communication with the third frame area B3 and the fourth frame area B4. In some examples, the display area AA can include a first edge (lower edge) and a second edge (upper edge) oppositely arranged in the second direction Y, and a third edge (left edge) and a fourth edge (right edge) oppositely arranged in the first direction X. The display area AA can include a plurality of sub-pixels Pxij arranged in a regular pattern, the sub-pixels can include a pixel driving circuit and a light emitting device, the first frame area B1 can include a bonding circuit connecting a signal line to an external driving device, and the third frame area B3 and the fourth frame area B4 can include a gate driving circuit and a second power supply line VSS transmitting a voltage signal to the plurality of sub-pixels.

[0051] FIG. 3 shows a schematic diagram of a first bezel area B1 in a plane parallel to the display substrate. The first bezel area B1 can include, in order from a direction away from the display area AA, a first fan-out area 11, a bending area 12, a second fan-out area 13, and a binding area 14. The binding area 14 can include, in order from a direction away from the bending area 12 of the second fan-out area 13, a driving chip area 141, a third fan-out area 142, and a binding electrode area 143. The first fan-out area 11 can include data fan-out lines, a first power line, and a second power line VSS. The data fan-out lines are located in a middle portion of the first fan-out area 11 and include a plurality of data connection lines configured to connect data lines of the display area AA in a fan-out manner. The first power line is configured to connect a high-voltage power line (VDD) of the display area AA. The second power line is a low-voltage power line (VSS) located in the third bezel area B3 and the fourth bezel area B4. The bending area 12 can include a composite insulating layer provided with a groove and configured to bend the binding area 14 to a back surface of the display area AA (as shown in FIG. 4). The second fan-out area 13 includes a plurality of data connection lines led out in a fan-out manner. The driving chip area 141 can be provided with an integrated circuit (IC) 20 configured to be connected to the plurality of data connection lines. The binding electrode area 143 includes a plurality of bonding pads configured to be connected to a flexible printed circuit (FPC) 30. In an example embodiment, the integrated circuit (IC) 20 can be connected to the driving chip area 141, and the flexible printed circuit (FPC) 30 can be connected to the binding electrode area 142. In an example embodiment, the integrated circuit 20 (which can be referred to as a data driving circuit or a driving circuit) can generate a driving signal required for driving a sub-pixel and can provide the driving signal to the sub-pixel Pxij located in the display area AA. For example, the driving signal can be a data signal for controlling the luminance of the sub-pixel. In an example embodiment, the binding electrode area 143 can be provided with a pad (PAD) including a plurality of pins (PIN), and the flexible printed circuit 30 can be connected to the pad.

[0052] In an example embodiment, as shown in FIG. 4, the bending area 12 can invert the surface of the binding area 14, i.e., the surface of the binding area 14 facing upward can be converted to face downward through the bending of the bending area 12. In an example embodiment, when the bending area 12 is bent, the binding area 14 can overlap the display area AA in a display panel thickness direction.

[0053] In an example embodiment, for a large size display substrate, a plurality of data driving ICs (may be referred to as driving IC, i.e. driving integrated circuit) and a plurality of FPCs can be provided, the plurality of FPCs are respectively bound to the plurality of data driving ICs, for example, four data driving ICs can be provided and bound to four FPCs, the embodiments of the present disclosure are not limited to four ICs and four FPCs, for example, two data driving ICs and two FPCs can be provided; for a small size display substrate, one data driving IC or two data driving ICs can be provided. In the embodiments of the present disclosure, the number of data driving ICs and FPCs can be set according to the size of the display substrate and the need of function, which is not limited herein.

[0054] In an example embodiment, as shown in FIG. 5, a structural schematic diagram of a display substrate, the display area AA can be provided with a plurality of scan signal lines SL and data lines DL0 in a plurality of data signal lines D (the same data signal line D can include the data line DL0 located in the display area AA and the data connection line DL located in the first frame area B1), the plurality of scan signal lines SL can extend along the first direction X and be arranged at intervals along the second direction Y, the plurality of data lines DL0 can extend along the second direction Y and be arranged at intervals along the first direction X, each scan signal line SL can be electrically connected with a plurality of sub-pixels Pxij in a row of sub-pixels, each data line DL0 can be electrically connected with a plurality of sub-pixels in a column of sub-pixels, the second frame area B2 and the third frame area B3 can be provided with a plurality of gate drive circuits GOA (GOA is a short form of array substrate row drive, and the full English name is Gate Driver on Array) and gate drive circuit signal lines (GOA signal lines), the GOA signal lines can include clock signal lines (for example, can include CK signal lines, CB signal lines, STV signal lines, etc.), the gate drive circuit GOA is arranged to be electrically connected with the corresponding scan signal line SL and provide a scan signal to the corresponding scan signal line SL.The data connection lines DL in the data signal line D can include first data connection lines DL1, second data connection lines DL2, and third data connection lines DL3, the first fan-out area 11 can include a plurality of first data connection lines DL1, a first power connection line PL11, the plurality of first data connection lines DL1 can be arranged at intervals along the first direction X, and the first power connection line PL11 is located in a different conductive layer from the plurality of first data connection lines DL1; the bending area 12 can include a plurality of second data connection lines DL2, a first power connection structure PL12, and a second power connection structure PL22, the plurality of second data connection lines DL2, the first power connection structure PL12, and the second power connection structure PL22 are arranged at intervals along the first direction X, the second data connection lines DL2, the first power connection structure PL12, and the second power connection structure PL22 in the bending area 12 are generally located in the same conductive layer, and different signal lines need to be arranged at intervals to avoid signal short circuit; the second fan-out area 13 can include a plurality of third data connection lines DL3, a first power line VDD, and a second power line VSS, the first power line VDD and the second power line VSS can be located in the same conductive layer, and the third data connection lines DL3 and the first power line VDD are located in different conductive layers; the driving chip area 141 can be provided with a driving circuit 20, the third fan-out area 142 can be provided with a plurality of binding leads 201, the binding electrode area 143 can be provided with a plurality of pads, the plurality of pads can include a first power pad 51, a second power pad 52, a driving pad 53, a first gate driving circuit pad 541, and a second gate driving pad 542, the driving circuit 20 can be electrically connected to the driving pad 53 in the binding electrode area 143 through the binding lead 201, the plurality of pads can be connected to the flexible circuit board 30, the first power line VDD can be connected to the first power pad 51, the second power line VSS can be connected to the second power pad 52, and the driving pad 53 can be electrically connected to the corresponding binding lead 201. In the exemplary embodiment, the data line DL0, the first data connection line DL1, the second data connection line DL2, and the third data connection line DL3 can be connected one by one, and the first power line VDD can be electrically connected to the first power connection line PL11 through the first power connection structure PL12.

[0055] In an example embodiment, as shown in FIG. 5, the gate driving circuit signal lines can include a first gate driving circuit signal line 41 and a second gate driving circuit signal line 42, the first gate driving circuit signal line 41 extending from the third bezel area B3 to the first bezel area B1 and connected with the first gate driving pad 541 and the gate driving circuit GOA located at the third bezel area B3; the second gate driving circuit signal line 42 extending from the fourth bezel area B4 to the first bezel area B1 and connected with the second gate driving pad 542 and the gate driving circuit GOA located at the fourth bezel area B4. The gate driving circuit GOA can include a first gate driving circuit GOA1 disposed at the third bezel area B3 and a second gate driving circuit GOA2 disposed at the fourth bezel area B4, the first gate driving circuit GOA1 configured to be electrically connected with the first gate driving pad 541 through the first gate driving circuit signal line 41, and the second gate driving circuit GOA2 configured to be electrically connected with the second gate driving pad 542 through the second gate driving circuit signal line 42.

[0056] In an example embodiment, as shown in FIG. 5, the second data connection line DL2 in the bending area 12 and the first power connection structure PL12 are located in the same conductive layer, and the size of the second data connection line DL2 is much smaller than that of the first power connection structure PL12 in the bending area 12. The first power connection structure PL12 is in a block structure, resulting in different lengths of the two first data connection lines DL1 on both sides of the first power connection structure PL12 in the first direction X. For example, the first data connection line DL12 changes the wiring path to avoid the first power connection structure PL12 in the bending area 12, resulting in a length of the first data connection line DL12 greater than that of the first data connection line DL11, and thus the resistance of the first data connection line DL12 is greater than that of the first data connection line DL11. As shown in FIG. 6, which is a resistance change curve diagram of the data signal line D, it can be seen from FIG. 6 that there are two larger resistance mutations (a large difference in resistance) in the plurality of data signal lines D, and the mutation positions are the data lines corresponding to the first data connection lines DL1 on both sides of the first power connection structure PL12 (the adjacent two data signal lines D at positions Z1 and Z2 in FIG. 6 produce resistance mutations, and Z1 and Z2 correspond to the positions of the two first power connection structures PL12 in the bending area 12). The size of the resistance mutation is about 200 ohms (Ω), which is easy to cause the problem of screen splitting. In FIG. 6, the abscissa is the position of the data line DL0 along the first direction X, and the ordinate is the resistance of the corresponding data line DL0.

[0057] The display substrate provided by the embodiments of the present disclosure can include a display area and a first bezel area located on one side of the display area, and the first bezel area is provided with a bending area.

[0058] a plurality of sub-pixels located in the display region;

[0059] a plurality of data signal lines located in the display region and the first frame region and electrically connected to the plurality of sub-pixels, the plurality of data signal lines being configured to provide data signals to the plurality of sub-pixels; the data signal lines include data lines and data connection lines, the data lines being located in the display region, and the data connection lines being located in the first frame region and electrically connected to corresponding data lines, at least part of the data connection lines being located in the bending area in the same data signal line;

[0060] a plurality of first power supply connection structures located in the bending area, the plurality of first power supply connection structures being arranged at intervals along a first direction and extending along a second direction, and being configured to provide first power supply signals to the plurality of sub-pixels, the first direction intersecting the second direction;

[0061] In the bending area, along the first direction, the data connection lines of the plurality of data signal lines are arranged at intervals with the plurality of first power supply connection structures, and at least one data connection line is provided between two adjacent first power supply connection structures.

[0062] In the display substrate provided by the embodiments of the present disclosure, the display substrate includes a display region and a first frame region located on one side of the display region, the display region includes a plurality of sub-pixels and data lines in a plurality of data signal lines, and the first frame region includes a bending area, in which, along a first direction, data connection lines of the plurality of data signal lines are arranged at intervals with a plurality of first power supply connection structures, and at least one data connection line is provided between two adjacent first power supply connection structures. The display substrate provided by the embodiments of the present disclosure can avoid the technical problem of display split screen caused by sudden change (large resistance difference) of signal line resistance in the bending area of the display substrate.

[0063] As shown in FIGS. 7-8c, FIG. 7 is a structural schematic diagram of a display substrate provided by an embodiment of the present disclosure, FIG. 8a is an enlarged structural schematic diagram of M1 position in FIG. 7, FIG. 8b is an enlarged structural schematic diagram of M2 position in FIG. 7, and FIG. 8c is another enlarged structural schematic diagram of M1 position in FIG. 7. The display substrate can include a display region AA and a first frame region B1 located on one side of the display region AA, and the first frame region B1 is provided with a bending area 12.

[0064] a plurality of sub-pixels Pxij located in the display region AA;

[0065] A plurality of data signal lines D are located in the display area AA and the first frame area B1 and are electrically connected to the plurality of sub-pixels Pxij. The plurality of data signal lines D are configured to provide data signals to the plurality of sub-pixels Pxij. The data signal lines D can include data lines DL0 and data connection lines DL. The data lines DL0 can be located in the display area AA, and the data connection lines DL can be located in the first frame area B1 and are electrically connected to the corresponding data lines DL0. In the same data signal line D, at least part of the line segments of the data connection lines DL are located in the bending area 12.

[0066] A plurality of first power connection structures PL12 are located in the bending area 12. The plurality of first power connection structures PL12 are arranged at intervals along the first direction X and extend along the second direction Y. The plurality of first power connection structures PL12 are configured to provide first power signals to the plurality of sub-pixels Pxij. The first direction X intersects the second direction Y.

[0067] In the bending area 12, along the first direction X, the data connection lines DL of the plurality of data signal lines D are arranged at intervals with the plurality of first power connection structures PL12. At least one data connection line DL is provided between any two adjacent first power connection structures PL12.

[0068] In an example embodiment, as shown in FIGS. 8a and 8b, two data connection lines DL can be provided between any two adjacent first power connection structures PL12, or as shown in FIG. 8c, four data connection lines DL can be provided between any two adjacent first power connection structures PL12. The number of data connection lines DL between any two adjacent first power connection structures PL12 can be one, three, or more than three, which is not limited in the embodiments of the disclosure.

[0069] In an example embodiment, in the bending area 12, the first power provided by the first power connection structure PL12 can be a VDD signal, a VSS signal, or an initialization signal, which is used to provide an initialization signal to a transistor in a driving circuit or to provide a voltage signal such as VGH or VGL to drive the GOA. In an example embodiment, the first power provided by the first power connection structure PL12 can be two constant voltage signals from among the VDD signal, the VSS signal, and the initialization signal. In the bending area 12, along the first direction X, the lines providing the initialization signal, VGL, and VGH can be located on both sides of the data connection lines DL, and the line providing the VDD signal can be located in the middle.

[0070] In an example embodiment, in the bending area 12, along the first direction X, a plurality of first distances R1 between the plurality of data connection lines DL are uniform. The first distance R1 is the distance between any two adjacent data connection lines DL.

[0071] In an exemplary embodiment, the plurality of first distances R1 between the plurality of data connection lines DL are consistent, which can be substantially the same, or have a certain difference within an allowable error range, for example, 0-5 microns.

[0072] In an exemplary embodiment, in the bending area 12, the data connection lines DL of the plurality of data signal lines D are arranged at intervals with the plurality of first power connection structures PL12, and at least one data connection line DL is arranged between any two adjacent first power connection structures PL12. On the one hand, this can improve the consistency of the signal provided by the first power connection structure PL12. On the other hand, the first power connection structure PL12 and the data connection line DL are arranged alternately, the first power connection structure PL2 is not a whole piece, but is divided into a plurality of pieces and arranged between the adjacent two data connection lines DL, which can avoid the problem of resistance jump of the adjacent two data signal lines D.

[0073] In an exemplary embodiment, in the bending area 12, the plurality of first distances R1 between the plurality of data connection lines DL are consistent along the first direction X, which can avoid the problem of large resistance difference caused by large length difference between the adjacent two data signal lines DL.

[0074] In an exemplary embodiment, in the bending area 12, the plurality of first power connection structures PL12 are arranged at equal intervals along the first direction X, so that the first power signals obtained by the plurality of sub-pixels Pxij are consistent as much as possible, which can improve the display uniformity of the display area.

[0075] In an exemplary embodiment, in the bending area 12, the plurality of data connection lines DL between any two adjacent first power connection structures PL12 are arranged at equal intervals along the first direction X, which can avoid the problem of resistance jump of the adjacent two data signal lines D and effectively reduce the risk of display split screen.

[0076] In an exemplary embodiment, in the bending area 12, the first distance R1 is greater than or equal to the second distance R2 along the first direction X, and the second distance R2 is the distance between the first power connection structure PL12 and the adjacent data connection line. The distance between the two data connection lines DL on both sides of the first power connection structure PL12 is consistent with the distance between the two adjacent data connection lines DL as much as possible, so that the resistance difference of the data signal lines D corresponding to the two data connection lines DL on both sides of the first power connection structure PL12 is reduced as much as possible, and the resistance jump is avoided.

[0077] In an exemplary embodiment, in the bending area 12, the ratio of the first distance R1 to the second distance R2 along the first direction X is greater than or equal to 1.5.

[0078] In the exemplary embodiments, in the bending area 12, along the first direction X, the size L1 of the first power supply connection structure PL12 is consistent with the size L2 of the data connection line DL. So that the size of one first power supply connection structure PL12 along the first direction X is not too large, and the resistance mutation of the data signal lines D corresponding to the two data connection lines DL located on both sides of the first power supply connection structure PL12 can be avoided.

[0079] In the exemplary embodiments, in the direction perpendicular to the plane where the display substrate is located, the display substrate can include a substrate and a driving circuit layer arranged on the substrate, the driving circuit layer can include a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer arranged on the substrate in sequence, at least part of the line segments of the plurality of data connection lines and the plurality of first power supply connection structures PL12 are located on the fourth conductive layer; in the exemplary embodiments, the fourth conductive layer can be referred to as the second source-drain metal layer SD2.

[0080] In the exemplary embodiments, in the plane parallel to the plane where the display substrate is located, the first frame area B1 can further include a first fan-out area 11, in the second direction Y, the first fan-out area 11 is located between the display area AA and the bending area 12; the display substrate can further include a first power supply connection line PL11, the data connection line includes a first data connection line DL1 and a second data connection line DL2, in the same data signal line, the data line DL0 is electrically connected to the first data connection line DL1 and the second data connection line DL2 through the first data connection line DL1 and the second data connection line DL2, wherein:

[0081] The first power supply connection line PL11 is located in the first fan-out area 11, the first power supply connection line PL11 extends along the first direction X and is electrically connected to the plurality of first power supply connection structures PL12, the plurality of first power supply connection structures PL12 provide the first power supply signal to the plurality of sub-pixels Pxij through the first power supply connection line PL11;

[0082] The first data connection line DL1 is located in the first fan-out area 11, among the plurality of first data connection lines DL1, at least part of them is located in the first conductive layer, at least part of them is located in the second conductive layer, the first data connection lines DL1 located in the first conductive layer and the first data connection lines DL1 located in the second conductive layer are arranged alternately;

[0083] The second data connection line DL2 is located in the bending area 12, in the direction perpendicular to the plane where the display substrate is located, the second data connection line DL2 can be located in the fourth conductive layer, and at least part of the line segments of the data connection line can include the second data connection line DL2.

[0084] In the example embodiment, the orthogonal projection of the first power connection line PL11 on the substrate at least partially overlaps the orthogonal projection of the plurality of first data connection lines DL1 on the substrate, which can save the space of the first bezel area B1. For example, the orthogonal projection of the first power connection line PL11 on the substrate can cover the orthogonal projection of the plurality of first data connection lines DL1 on the substrate.

[0085] In the example embodiment, in the direction perpendicular to the plane where the display substrate is located, the first power connection line PL11 is located in the fourth conductive layer, and the first power connection line PL11 is directly connected to the plurality of first power connection structures PL12. In the same data signal line, the first data connection line DL1 is electrically connected to the second data connection line DL2 through a via, and the first data connection line DL1 is electrically connected to the data line DL0 through a via.

[0086] In the example embodiment, in the direction parallel to the plane where the display substrate is located, the first bezel area B1 further includes a second fan-out area 13, and the second fan-out area 13 is located on the side of the bending area 12 away from the display area AA in the second direction Y. The display substrate further includes a first power line VDD, and the data connection line further includes a third data connection line DL3. In the same data connection line, the first data connection line DL1 is electrically connected to the third data connection line DL3 through the second data connection line DL2. Wherein:

[0087] The first power line VDD is located in the second fan-out area 13, and the first power line VDD is connected to the plurality of first power connection structures PL12.

[0088] The third data connection line DL3 is located in the second fan-out area 13, and among the plurality of third data connection lines DL3, at least part of them is located in the first conductive layer, and at least part of them is located in the second conductive layer. The third data connection lines DL3 located in the first conductive layer are arranged alternately with the third data connection lines DL3 located in the second conductive layer.

[0089] In the example embodiment, in the direction perpendicular to the plane where the display substrate is located, the first power line VDD is located in the fourth conductive layer, and the first power line VDD is directly connected to the plurality of first power connection structures PL12. In the same data signal line, the second data connection line DL2 is electrically connected to the third data connection line DL3 through a via.

[0090] In the example embodiment, the orthogonal projection of the first power line VDD on the substrate at least partially overlaps the orthogonal projection of the plurality of third data connection lines DL3 on the substrate, which can save the space of the first bezel area B1.

[0091] In the example embodiment, the first bezel area B1 can further include a binding area 14 in a plane parallel to the display substrate, the binding area 14 is located on a side of the second fan-out area 13 away from the display area AA in the second direction Y, the binding area 14 can include the first power pad 51 and the driving circuit 20; the third data connection line DL3 is electrically connected with the driving circuit 20; and the first power line VDD extends to the binding area 14 and is electrically connected with the first power pad 51.

[0092] In the example embodiment, the display area AA can further be provided with a plurality of scan signal lines SL, the plurality of scan signal lines SL can extend along the first direction X and be arranged at intervals along the second direction Y, and each scan signal line SL can be electrically connected with a plurality of sub-pixels Pxij in a row of sub-pixels.

[0093] In the example embodiment, the second bezel area B2 and the third bezel area B3 can be provided with a plurality of gate drive circuits GOA (GOA is a short form of array substrate row drive, and the full English name is Gate Driver on Array) and gate drive circuit signal lines (GOA signal lines), the GOA signal lines can include clock signal lines (for example, can include CK signal lines, CB signal lines, STV signal lines, etc.), and the gate drive circuit GOA can be arranged to be electrically connected with the corresponding scan signal line SL and provide the scan signal to the corresponding scan signal line SL.

[0094] In the example embodiment, as shown in FIG. 7, the first bezel area B1 is further provided with a second power line VSS and a second power connection structure PL22, the second power connection structure PL22 is located in the bending area 12, and in the first direction X, the second power connection structure PL22 is located on both sides of the plurality of first power connection structures PL12 and the plurality of second data connection lines DL2; the second power line VSS is located in the second fan-out area 13 and the binding area 14, and in the first direction X, the second power line VSS is located on both sides of the first power line VDD.

[0095] In the example embodiment, the binding area 14 can include, in sequence along the direction away from the bending area 12 of the second fan-out area 13, a driving chip area 141, a third fan-out area 142, and a binding electrode area 143, the driving chip area 141 can be provided with the driving circuit 20, the third fan-out area 142 can be provided with a plurality of binding leads 201, the binding electrode area 143 can be provided with a plurality of pads, the plurality of pads can include a first power pad 51, a second power pad 52, a driving pad 53, a first gate driving circuit pad 541, and a second gate driving pad 542, the driving circuit 20 can be electrically connected to the driving pad 53 in the binding electrode area 143 through the binding lead 201, the plurality of pads can be bound and connected to the flexible circuit board 30, the first power line VDD can be connected to the first power pad 51, the second power line VSS can be connected to the second power pad 52, and the driving pad 53 can be electrically connected to the corresponding binding lead 201.

[0096] In the example embodiment, the gate driving circuit signal line can include a first gate driving circuit signal line 41 and a second gate driving circuit signal line 42, the first gate driving circuit signal line 41 extends from the third frame area B3 to the first frame area B1 and is connected to the first gate driving pad 541 and the gate driving circuit GOA located in the third frame area B3; the second gate driving circuit signal line 42 extends from the fourth frame area B4 to the first frame area B1 and is connected to the second gate driving pad 542 and the gate driving circuit GOA located in the fourth frame area B4. The gate driving circuit GOA can include a first gate driving circuit GOA1 provided in the third frame area B3 and a second gate driving circuit GOA2 provided in the fourth frame area B4, the first gate driving circuit GOA1 is configured to be electrically connected to the first gate driving pad 541 through the first gate driving circuit signal line 41, and the second gate driving circuit GOA2 is configured to be electrically connected to the second gate driving pad 542 through the second gate driving circuit signal line 42.

[0097] The display device provided by the embodiment of the present disclosure can include a display substrate as shown in FIG. 9.

[0098] The display substrate is the display substrate provided by any one of the foregoing embodiments, and has similar implementation principles and implementation effects, which will not be described here.

[0099] In an example embodiment, the display device can be a liquid crystal display (LCD) or an organic light emitting diode (OLED) or a light emitting diode (LED) display device. The display device can be a liquid crystal panel, electronic paper, an OLED panel, an active-matrix organic light emitting diode (AMOLED) panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, or any product or component with a display function.

[0100] The display substrate and the display device provided by the embodiments of the present disclosure include a display area and a first frame area located at one side of the display area. The display area includes a plurality of sub-pixels and a plurality of data lines in a data signal line. The first frame area includes a bending area. In the bending area, data connection lines of the plurality of data signal lines are arranged at intervals with a plurality of first power connection structures along a first direction. At least one data connection line is arranged between two adjacent first power connection structures. The display substrate provided by the embodiments of the present disclosure can avoid the technical problem of display split screen caused by the sudden change (large resistance difference) of signal wire resistance in the bending area of the display substrate.

[0101] The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures can be referred to the general design.

[0102] In the case of no conflict, the features in the embodiments of the present disclosure, i.e., the embodiments, can be combined to obtain new embodiments.

[0103] Although the embodiments disclosed by the embodiments of the present disclosure are as above, the content described is only the embodiments adopted for the purpose of facilitating the understanding of the embodiments of the present disclosure, and is not intended to limit the embodiments of the present disclosure. Any person skilled in the art of the embodiments of the present disclosure can make any modification and change in the implementation form and details without departing from the spirit and scope of the embodiments of the present disclosure. The patent protection scope of the embodiments of the present disclosure shall be subject to the scope defined by the appended claims.

Claims

1. A display substrate, comprising a display area and a first bezel area located at one side of the display area, the first bezel area being provided with a bending area; a plurality of sub-pixels located in the display area; a plurality of data signal lines located in the display area and the first bezel area and electrically connected to the plurality of sub-pixels, the plurality of data signal lines being configured to provide data signals to the plurality of sub-pixels; the data signal lines comprising data lines and data connection lines, the data lines being located in the display area, the data connection lines being located in the first bezel area and electrically connected to corresponding data lines, at least part of the data connection lines being located in the bending area in the same data signal line; a plurality of first power supply connection structures located in the bending area, the plurality of first power supply connection structures being arranged at intervals along a first direction and extending along a second direction, and configured to provide first power supply signals to the plurality of sub-pixels, the first direction intersecting the second direction; in the bending area, along the first direction, the data connection lines of the plurality of data signal lines are arranged at intervals with the plurality of first power supply connection structures, and at least one data connection line is provided between any two adjacent first power supply connection structures. 2.The display substrate of claim 1, wherein, in the bending area, along the first direction, the plurality of first power supply connection structures are arranged at equal intervals. 3.The display substrate of claim 1, wherein, in the bending area, along the first direction, a plurality of first distances between the plurality of data connection lines are consistent, the first distance being a distance between any two adjacent data connection lines. 4.The display substrate of claim 1, wherein, in the bending area, along the first direction, the plurality of data connection lines are arranged at equal intervals between any two adjacent first power supply connection structures. 5.The display substrate of claim 3, wherein, in the bending area, along the first direction, the first distance is greater than or equal to a second distance, the second distance being a distance between the first power supply connection structure and the adjacent data connection line. 6.The display substrate of claim 5, wherein, in the bending area, along the first direction, a ratio of the first distance to the second distance is greater than or equal to 1.

5. 7.The display substrate according to any one of claims 1 to 6, wherein in the bending area, along the first direction, a size of the first power supply connection structure is consistent with a size of the data connection line. 8.The display substrate according to any one of claims 1 to 6, wherein in a direction perpendicular to a plane in which the display substrate is located, the display substrate comprises a substrate and a driving circuit layer provided on the substrate, the driving circuit layer comprising a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer provided on the substrate in sequence, at least part of the data connection lines and the plurality of first power supply connection structures being located in the fourth conductive layer. 9.The display substrate of claim 8, wherein, in a plane parallel to the plane in which the display substrate is located, the first bezel area further comprises a first fan-out area, the first fan-out area being located between the display area and the bending area in the second direction; the display substrate further comprises a first power supply connection line, the data connection lines comprising first data connection lines and second data connection lines, in the same data signal line, the data line being electrically connected to the second data connection line through the first data connection line, and wherein: The first power connection line is located in the first fan-out area, extends along the first direction, and is electrically connected with the plurality of first power connection structures, which provide first power signals to the plurality of sub-pixels through the first power connection line. The first data connection line is located in the first fan-out area, at least part of the plurality of first data connection lines is located in the first conductive layer, and at least part of the plurality of first data connection lines is located in the second conductive layer, the first data connection lines located in the first conductive layer and the first data connection lines located in the second conductive layer are arranged alternately. The second data connection line is located in the bending area, and in a direction perpendicular to a plane in which the display substrate is located, the second data connection line is located in the fourth conductive layer, and at least part of a line segment of the data connection line includes the second data connection line. 10.The display substrate of claim 9, wherein, In a direction perpendicular to a plane in which the display substrate is located, the first power connection line is located in the fourth conductive layer, and the first power connection line is directly connected with the plurality of first power connection structures; in the same data signal line, the first data connection line and the second data connection line are electrically connected through a via, and the first data connection line and the data line are electrically connected through a via. 11.The display substrate of claim 9, wherein, In parallel to the plane in which the display substrate is located, the first frame area further includes a second fan-out area, the second fan-out area is located on a side of the bending area away from the display area in the second direction, the display substrate further includes a first power line, and the data connection line further includes a third data connection line, in the same data connection line, the first data connection line is electrically connected with the third data connection line through the second data connection line; wherein: The first power line is located in the second fan-out area, and the first power line is connected with the plurality of first power connection structures. The third data connection line is located in the second fan-out area, at least part of the plurality of third data connection lines is located in the first conductive layer, and at least part of the plurality of third data connection lines is located in the second conductive layer, the third data connection lines located in the first conductive layer and the third data connection lines located in the second conductive layer are arranged alternately. 12.The display substrate of claim 11, wherein, In a direction perpendicular to a plane in which the display substrate is located, the first power line is located in the fourth conductive layer, and the first power line is directly connected with the plurality of first power connection structures; in the same data signal line, the second data connection line and the third data connection line are electrically connected through a via. 13.The display substrate of claim 11, wherein, In parallel to the plane in which the display substrate is located, the first frame area further includes a binding area, the binding area is located on a side of the second fan-out area away from the display area in the second direction, the binding area is provided with a first power pad and a driving circuit, the third data connection line is electrically connected with the driving circuit, and the first power line extends to the binding area and is electrically connected with the first power pad.

14. A display device comprising the display substrate according to any one of claims 1 to 13.

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