Integrated chip integrating magnetic core and horizontal hall element, and preparation method for integrated chip

Abstract

An integrated chip integrating a magnetic core and a horizontal Hall element, and a preparation method for an integrated chip. Two magnetic flux concentrators are both aligned with a Hall ASIC chip by means of wafer bonding, and then are respectively wafer-bonded to an upper surface and a lower surface of the Hall ASIC chip, so as to form an integrated chip, wherein a magnetic flux concentrating thin film is provided in each of the magnetic flux concentrators, and the horizontal Hall ASIC chip is provided with a horizontal Hall element. In the present invention, the integrated chip is formed by means of magnetic flux concentrators and a Hall ASIC chip, wherein a magnetic flux concentrating thin film can concentrate magnetic induction lines and amplify the strength of a detected magnetic field, thus realizing the same function as a ferromagnetic core. The integrated chip can realize the miniaturization of a Hall current detection chip without the need to use a large ferromagnetic core, and realizes micron-level precise alignment between the magnetic flux concentrating thin film and the horizontal Hall element, which is significantly better than the precision of alignment of existing magnet core assemblies.

Description

Integrated chip integrating magnetic core and horizontal Hall element and preparation method thereof TECHNICAL FIELD

[0001] The present application relates to the technical field of Hall devices, in particular to an integrated chip integrating a magnetic core and a horizontal Hall element and a preparation method thereof. BACKGROUND

[0002] A Hall chip is a magnetic field sensor based on the Hall effect, which converts a changing magnetic field into a change in output voltage, thereby realizing the measurement and monitoring of the magnetic field. The working principle of the Hall chip is based on the Hall effect. When a semiconductor wafer is placed in a magnetic field, if there is current flowing through, an electromotive force will be generated in the direction perpendicular to the current and the magnetic field, which is the Hall effect. The Hall chip utilizes this effect to convert the change in the magnetic field into a voltage signal output.

[0003] Whether it is an open-loop Hall chip or a closed-loop Hall chip, the magnetic field strength detected by the single Hall chip is relatively weak. At present, it is common to place a ferrite or other ferromagnetic core structure in the upper and lower magnetic field detection areas of the Hall chip in a packaging structure or module structure, thereby playing the role of converging magnetic induction lines and amplifying the detected magnetic field strength. Generally, the ferromagnetic core is much larger than the Hall chip itself, and the size of the ferromagnetic core ranges from 3mm to 8mm, which limits the application scenarios and fields of the Hall chip and increases the actual use volume. At the same time, the assembly precision and consistency of the large block ferromagnetic core structure are poor, which can easily affect the accuracy of the magnetic field detection signal.

[0004] Therefore, in view of the deficiencies of the prior art, it is necessary to provide an integrated chip integrating a magnetic core and a horizontal Hall element and a preparation method thereof to solve the deficiencies of the prior art. SUMMARY

[0005] One of the purposes of the present application is to provide an integrated chip integrating a magnetic core and a horizontal Hall element and a preparation method thereof to avoid the deficiencies of the prior art. The integrated chip prepared by the integrated chip integrating a magnetic core and a horizontal Hall element and a preparation method thereof avoids using a large-size ferromagnetic core in the prior art, which can greatly reduce the size of the integrated chip and has high assembly precision.

[0006] The above purposes of the present application are achieved by the following technical measures:

[0007] Provided is an integrated chip integrating a magnetic core and a horizontal Hall element and a preparation method thereof. Two pieces of magnetic flux concentrators are respectively aligned with a Hall ASIC chip, and then respectively wafer-bonded to the upper surface and the lower surface of the Hall ASIC chip to form an integrated chip.

[0008] A magnetic flux gathering film is arranged in each magnetic flux concentrator, and a horizontal Hall element is arranged on the horizontal Hall ASIC chip, and the magnetic flux gathering film is located directly above or below the horizontal Hall element.

[0009] The two magnetic flux concentrators are defined as a first magnetic flux concentrator and a second magnetic flux concentrator.

[0010] Preferably, the first magnetic flux concentrator wafer is bonded to the upper surface of the Hall ASIC chip, and the magnetic flux gathering film of the first magnetic flux concentrator is located directly above the horizontal Hall element.

[0011] Preferably, the second magnetic flux concentrator wafer is bonded to the lower surface of the Hall ASIC chip, and the magnetic flux gathering film of the second magnetic flux concentrator is located directly below the horizontal Hall element.

[0012] Preferably, each magnetic flux concentrator is further provided with a plurality of first alignment mark points, a first oxide layer and a first wafer substrate, the first alignment mark points and the magnetic flux gathering film are arranged on the upper surface of the first wafer substrate, and the first oxide layer is arranged on the upper surface of the first wafer substrate, the upper surface of the first alignment mark points and the upper surface of the magnetic flux gathering film.

[0013] Preferably, the Hall ASIC chip is provided with a plurality of second alignment mark points, a second wafer substrate, a second oxide layer, a structure layer and a debugging circuit, the second alignment mark points, the horizontal Hall element and the debugging circuit are arranged on the upper surface of the second wafer substrate, the structure layer is arranged on the upper surface of the second wafer substrate, the upper surface of the second alignment mark points and the upper surface of the horizontal Hall element, and the second oxide layer is arranged on the upper surface of the structure layer.

[0014] The integrated chip of the integrated magnetic core and the horizontal Hall element is prepared by the following steps:

[0015] S1, align the first alignment mark points of the first magnetic flux concentrator with the second alignment mark points of the Hall ASIC chip, and then bond the first oxide layer of the first magnetic flux concentrator with the second oxide layer, so that the first magnetic flux concentrator and the Hall ASIC chip form an integrated structure, and the integrated structure is defined as a first wafer structure;

[0016] S2, thin the second wafer substrate in the first wafer structure obtained in S1 to obtain a thinned wafer structure;

[0017] S3, arrange a third oxide layer on the surface of the thinned wafer substrate in the thinned wafer structure obtained in S2;

[0018] S4, aligning the first pair of mark points of the second magnetic flux concentrator with the second pair of mark points in the thinned wafer structure, and bonding the third oxide layer with the first oxide layer of the second magnetic flux concentrator, so that the second magnetic flux concentrator and the thinned wafer structure form an integrated structure, and defining the integrated structure as a second wafer structure;

[0019] S5, thinning the first wafer substrate and the second wafer substrate in the second wafer structure obtained in S4 respectively to obtain a third wafer structure;

[0020] S6, forming a through hole in one of the surfaces of the third wafer structure obtained in S5 by a through silicon via process, and then setting a lead wire in the through hole, and the through hole being connected to the surface of the debugging circuit, and the lead wire being electrically connected with the debugging circuit, to obtain the integrated chip.

[0021] In the S2, the second wafer substrate is thinned to a thickness of 230 Å-280 Å.

[0022] Preferably, the S3 is specifically growing silicon on the surface of the thinned second wafer substrate in the thinned wafer structure obtained in S2 at a temperature of 1180-1250 °C in an oxygen atmosphere in a furnace tube to form a silicon oxide film, the silicon oxide film being the third oxide layer, and the thickness of the third oxide layer being about 2800-3200 Å.

[0023] Preferably, the integrated magnetic core is packaged with an external Hall package lead frame before use, the maximum width of the groove in the external Hall package lead frame is defined as A, the maximum width of the magnetic flux concentrating film is defined as B, and the maximum width of the horizontal Hall element is defined as C, and there is 30 μm≤C≤B≤A≤100 μm.

[0024] Preferably, the magnetic flux concentrating film is a FeNi-based magnetic flux concentrating film, a FeZn-based magnetic flux concentrating film, a FeCo-based magnetic flux concentrating film, or a FeNiMo-based magnetic flux concentrating film.

[0025] Preferably, the thickness of the first oxide layer and the second oxide layer is between 1000 Å and 1 μm.

[0026] Preferably, the material of the first oxide layer and the material of the second oxide layer are silicon dioxide or tetraethyl orthosilicate.

[0027] Preferably, the first wafer substrate is a silicon-based substrate.

[0028] Preferably, the structure layer is at least one of a metal trace layer, a dielectric layer, or a passivation layer.

[0029] Preferably, the first wafer substrate is a silicon substrate, a gallium arsenide substrate or an indium antimonide substrate.

[0030] Preferably, the second wafer substrate is a silicon substrate, a gallium arsenide substrate or an indium antimonide substrate.

[0031] Another object of the present application is to provide an integrated chip to avoid the shortcomings of the prior art. The integrated chip avoids using a large-sized ferromagnetic core in the prior art, can greatly reduce the size of the integrated chip, and has high assembly and alignment precision.

[0032] The above object of the present application is achieved by the following technical measures:

[0033] An integrated magnetic core is provided, which is prepared by the above integrated chip preparation method.

[0034] The integrated magnetic core and the integrated chip of the horizontal type Hall element and the preparation method thereof of the present application form an integrated chip by aligning two magnetic flux concentrators with a Hall ASIC chip respectively, and then wafer bonding each magnetic flux concentrator to the upper surface and the lower surface of the Hall ASIC chip respectively. A magnetic flux concentrating film is arranged in each magnetic flux concentrator, and a horizontal type Hall element is arranged on the horizontal type Hall ASIC chip. The magnetic flux concentrating film is located directly above or below the horizontal type Hall element. The integrated chip of the present application forms an integrated chip by aligning the magnetic flux concentrator with the Hall ASIC chip, and the magnetic flux concentrating film can converge magnetic induction lines and amplify the detected magnetic field strength, achieving the same function as the ferromagnetic core. Compared with the prior art, the integrated chip does not need to use a large ferromagnetic core, and can realize the miniaturization of the Hall current detection chip. The micron-level precision alignment of the magnetic flux concentrating film and the horizontal type Hall element is obviously superior to the alignment precision of the current magnetic core assembly. The bonding thickness between the magnetic flux concentrating film layer and the Hall element can also be controlled, and the thickness precision is obviously superior to the assembly control level of the large magnetic core module. BRIEF DESCRIPTION OF DRAWINGS

[0035] The present application is further described with reference to the accompanying drawings, but the content of the drawings does not constitute any limitation on the present application.

[0036] FIG. 1 is a schematic view of an integrated magnetic core prepared by the integrated chip preparation method of the integrated magnetic core and the horizontal type Hall element of the present application.

[0037] FIG. 2 is a schematic view of a magnetic flux concentrator.

[0038] FIG. 3 is a schematic view of a Hall ASIC chip.

[0039] FIG. 4 is a schematic view of the maximum width of the groove in the lead frame for external Hall packaging, the magnetic flux concentrating film and the horizontal type Hall element.

[0040] Fig. 5 is a schematic diagram of the alignment of the first magnetic flux concentrator and the Hall ASIC chip in S1 of the present application.

[0041] Fig. 6 is a schematic diagram of the first wafer structure obtained in S1.

[0042] Fig. 7 is a schematic diagram of the thinned wafer structure obtained in S2.

[0043] Fig. 8 is a schematic diagram of the thinned wafer structure provided with a third oxide layer in S3.

[0044] Fig. 9 is a schematic diagram of the alignment of the second magnetic flux concentrator and the thinned wafer structure in S4.

[0045] Fig. 10 is a schematic diagram of the second wafer structure obtained in S4.

[0046] Fig. 11 is a schematic diagram of the third wafer structure obtained in S5.

[0047] Fig. 12 is a schematic diagram of the integrated chip obtained in S6.

[0048] In Figs. 1-12, there are included:

[0049] a magnetic flux concentrator 100, a first alignment mark 110, a magnetic flux concentrating film 120, a first oxide layer 130, a first wafer substrate 140,

[0050] a Hall ASIC chip 200, a horizontal Hall element 210, a second wafer substrate 220, a second oxide layer 230, a structure layer 240, a debugging circuit 250, a second alignment mark 260,

[0051] a third oxide layer 300, a via 400, an external Hall package lead frame 500, a recess 510.

[0052] DETAILED DESCRIPTION

[0053] The technical solutions of the present application are further described in connection with the following examples. EXAMPLE

[0054] A method for preparing an integrated chip integrating a magnetic core and a horizontal Hall element, two pieces of magnetic flux concentrator 100 are respectively aligned with a Hall ASIC chip 200, and then wafer bonded to the upper surface and the lower surface of the Hall ASIC chip 200 respectively to form an integrated chip, as shown in Fig. 1. Each piece of magnetic flux concentrator 100 is provided with a magnetic flux concentrating film 120, and the horizontal Hall ASIC chip 200 is provided with a horizontal Hall element 210, and the magnetic flux concentrating film 120 is located directly above or directly below the horizontal Hall element 210.

[0055] Two pieces of magnetic flux concentrators 100 are defined as a first magnetic flux concentrator 100 and a second magnetic flux concentrator 100 respectively; the first magnetic flux concentrator 100 is wafer bonded to the upper surface of the Hall ASIC chip 200, and the magnetic flux concentrating film 120 of the first magnetic flux concentrator 100 is located directly above the horizontal Hall element 210; the second magnetic flux concentrator 100 is wafer bonded to the lower surface of the Hall ASIC chip 200, and the magnetic flux concentrating film 120 of the second magnetic flux concentrator 100 is located directly below the horizontal Hall element 210, as shown in FIG. 2.

[0056] Each piece of magnetic flux concentrator 100 is also provided with a plurality of first alignment mark points 110, a first oxide layer 130 and a first wafer substrate 140, the first alignment mark points 110 and the magnetic flux concentrating film 120 are respectively arranged on the upper surface of the first wafer substrate 140, and the first oxide layer 130 is arranged on the upper surface of the first wafer substrate 140, the upper surface of the first alignment mark points 110 and the upper surface of the magnetic flux concentrating film 120.

[0057] The Hall ASIC chip 200 is provided with a plurality of second alignment mark points 260, a second wafer substrate 220, a second oxide layer 230, a structure layer 240 and a debugging circuit 250, the second alignment mark points 260, the horizontal Hall element 210 and the debugging circuit 250 are all arranged on the upper surface of the second wafer substrate 220, the structure layer 240 is arranged on the upper surface of the second wafer substrate 220, the upper surface of the second alignment mark points 260 and the upper surface of the horizontal Hall element 210, and the second oxide layer 230 is arranged on the upper surface of the structure layer 240, as shown in FIG. 3.

[0058] It should be noted that the plurality of first alignment mark points 110 are cross-distributed on the upper surface of the first wafer substrate 140, and the plurality of second alignment mark points 260 are cross-distributed on the upper surface of the second wafer substrate 220, and the number and position of the first alignment mark points 110 and the second alignment mark points 260 are one-to-one corresponding, so that the magnetic flux concentrator 100 and the Hall ASIC chip 200 can be accurately aligned before wafer bonding. In the art, the technical solution of accurately aligning wafer bonding through alignment mark points is a conventional technical operation, which should be known by those skilled in the art, and will not be described here.

[0059] The integrated magnetic core is packaged with the external Hall package lead frame 500 before use, the maximum width of the groove 510 in the external Hall package lead frame 500 is defined as A, the maximum width of the magnetic flux concentrating film 120 is defined as B, and the maximum width of the horizontal Hall element 210 is defined as C, and there is 30 μm≤C≤B≤A≤100 μm, as shown in FIG. 4.

[0060] It should be noted that the integrated magnetic core of the present application can be directly used in current detection scene after a conventional packaging process, that is, packaging with an external Hall packaging lead frame 500, and when packaged with the external Hall packaging lead frame 500, the magnetic flux concentrator 100 in the integrated chip is located in the groove 510 area. The maximum width of the magnetic flux concentrating film 120 of the present application needs to be less than or equal to the maximum width of the groove 510, and greater than or equal to the maximum width of the horizontal Hall element 210. The groove 510 opened in the external Hall packaging lead frame 500 serves to avoid eddy current effect.

[0061] Compared with the prior art, the magnetic flux concentrating film 120 of the present application can converge magnetic induction lines, amplify the detected magnetic field strength, and realize the same function as the ferromagnetic core, and the size is much smaller than that of the ferromagnetic core, so the present application can greatly reduce the size of the integrated magnetic core and realize miniaturization.

[0062] The present application realizes micron-level precision alignment of the magnetic flux concentrating film 120 and the horizontal Hall element 210 through the second alignment mark point 260 and the first alignment mark point 110. Compared with the alignment of the prior art bulk magnet core module assembly, the precision of the present application is greatly improved.

[0063] It should also be noted that the preparation method of the magnetic flux concentrator 100 and the Hall ASIC chip 200 is a common knowledge in the technical field, and the preparation method of the magnetic flux concentrator 100 and the Hall ASIC chip 200 does not belong to the invention of the present application. Therefore, it will not be described one by one. Moreover, the arrangement of the debugging circuit 250 in the second wafer substrate 220 is related to the specific design layout of the Hall ASIC chip 200. The present application only needs to align and position the magnetic flux concentrator 100 and the Hall ASIC chip 200 so that the magnetic flux concentrating film 120 is located on the upper surface and the lower surface of the horizontal Hall element 210. The arrangement of the debugging circuit 250 is not the focus of the present application, and will not be described one by one.

[0064] The integrated magnetic core and the integrated chip preparation method of the horizontal Hall element of the present application are prepared by the following steps:

[0065] S1, align the first alignment mark point 110 of the first magnetic flux concentrator 100 with the second alignment mark point 260 of the Hall ASIC chip 200, as shown in FIG. 5, then bond the first oxide layer 130 of the first magnetic flux concentrator 100 with the second oxide layer 230, so that the first magnetic flux concentrator 100 and the Hall ASIC chip 200 form an integrated structure, as shown in FIG. 6, and define the integrated structure as a first wafer structure;

[0066] S2, thinning the second wafer substrate 220 in the first wafer structure obtained in S1 to a thickness of 230-280 angstroms to obtain a thinned wafer structure, as shown in Fig. 7;

[0067] S3, disposing a third oxide layer 300 on the surface of the thinned wafer substrate in the thinned wafer structure obtained in S2; specifically, growing silicon on the surface of the thinned second wafer substrate 220 in the thinned wafer structure obtained in S2 at a temperature of 1180-1250 degrees Celsius in an oxygen atmosphere to form a thin silicon oxide film, which is the third oxide layer 300, as shown in Fig. 8, and the thickness of the third oxide layer 300 is about 2800-3200 angstroms;

[0068] S4, aligning the first alignment mark 110 of the second magnetic flux concentrator 100 with the second alignment mark 260 in the thinned wafer structure, as shown in Fig. 9, and bonding the third oxide layer 300 with the first oxide layer 130 of the second magnetic flux concentrator 100, so that the second magnetic flux concentrator 100 and the thinned wafer structure form an integrated structure, as shown in Fig. 10, and the integrated structure is defined as a second wafer structure;

[0069] S5, thinning the first wafer substrate 140 and the second wafer substrate 220 in the second wafer structure obtained in S4 to obtain a third wafer structure, as shown in Fig. 11;

[0070] S6, forming a through hole 400 in one of the surfaces of the third wafer structure obtained in S5 by a through silicon via 400 process, and then disposing a lead wire on the through hole 400, and the through hole 400 is connected to the surface of the debugging circuit 250, and the lead wire is electrically connected to the debugging circuit 250, to obtain an integrated chip, as shown in Fig. 12.

[0071] The material of the first oxide layer 130 and the material of the second oxide layer 230 are silicon dioxide or tetraethyl orthosilicate; the first wafer substrate 140 is a silicon substrate; the first wafer substrate 140 is a silicon substrate, a gallium arsenide substrate or an indium antimonide substrate; the second wafer substrate 220 is a silicon substrate, a gallium arsenide substrate or an indium antimonide substrate. The magnetic flux concentrating film 120 is a FeNi-based magnetic flux concentrating film 120, a FeZn-based magnetic flux concentrating film 120, a FeCo-based magnetic flux concentrating film 120 or a FeNiMo-based magnetic flux concentrating film 120.

[0072] The structure layer 240 is at least one of a metal wiring layer, a dielectric layer or a passivation layer; when the structure layer 240 is a metal wiring layer, the through hole 400 will avoid the metal wiring position to avoid cutting off the metal wiring circuit. The through silicon via 400 process of the present application is a conventional semiconductor process, which is known to those skilled in the art and will not be described here.

[0073] The debugging circuit 250 of the present application refers to a signal circuit for realizing signal amplification, filtering, chopping, clocking, storage, etc. of the horizontal Hall element 210. The shape and size of the horizontal Hall element 210 of the present application include all possible shapes of Hall discs that can implement Hall effect, including but not limited to square, cross, diagonal, polygon, etc. The magnetic flux concentrating film 120 can be a single-layer film or a multi-layer film, or a composite film layer structure formed by alternately arranging magnetic and non-magnetic layers.

[0074] It should be noted that the preparation method of the present application can realize the thickness adjustment of the insulating layer between the magnetic flux concentrating film 120 and the Hall element through the bonding between the oxide layers, and the thickness accuracy and consistency of multiple batches are obviously better than the assembly control level of the magnetic core module.

[0075] The integrated chip of the present application can not only ensure the increase of the magnetic field intensity sensed by the Hall element, but also can avoid the eddy current effect of the strong magnetic field in the metal frame when cooperating with the lead frame for Hall packaging with the groove 510. Moreover, the integrated chip of the present application integrates the magnetic flux concentrator 100, which can realize the magnetic concentration and detection of the three-axis magnetic field, and the structure itself can realize the detection of the magnetic field in the vertical direction. For the horizontal magnetic field, the magnetic core magnetic concentration effect can make the parallel magnetic field converge and change into the vertical magnetic field, thereby realizing the detection of the three-dimensional magnetic field.

[0076] The integrated chip preparation method of the integrated magnetic core and horizontal Hall element integrates the magnetic flux concentrator 100 and the Hall ASIC chip 200, wherein the magnetic flux concentrating film 120 can converge the magnetic induction lines and amplify the detected magnetic field intensity, and realize the same function as the ferromagnetic core. Compared with the prior art, the integrated chip does not need to use a large ferromagnetic core, can realize the miniaturization of the Hall current detection chip, can realize the micron-level precise alignment of the magnetic flux concentrating film 120 and the horizontal Hall element 210, is obviously better than the alignment accuracy of the current magnetic core assembly, can realize the thickness control of the bonding between the magnetic flux concentrating film layer and the Hall element, and the thickness accuracy is obviously better than the assembly control level of the large magnetic core module. Moreover, the present application can realize the thickness adjustment of the insulating layer between the magnetic flux concentrating film 120 and the Hall element.

[0077] Embodiment

[0078] An integrated chip preparation method of an integrated magnetic core and horizontal Hall element, other features are the same as those in Embodiment 1, and the difference lies in that the thickness of the first oxide layer 130 and the second oxide layer 230 is 5000 Å, the magnetic flux concentrating film 120 is a FeNi-based magnetic flux concentrating film 120; the material of the first oxide layer 130 and the material of the second oxide layer 230 are both silicon dioxide, the structure layer 240 is a passivation layer, and the first wafer substrate 140 and the second wafer substrate 220 are both silicon-based substrates.

[0079] The preparation method of the integrated chip is prepared by the following steps:

[0080] S1, align the first alignment mark point 110 of the first magnetic flux concentrator 100 with the second alignment mark point 260 of the Hall ASIC chip 200, then bond the first oxide layer 130 of the first magnetic flux concentrator 100 with the second oxide layer 230, so that the first magnetic flux concentrator 100 and the Hall ASIC chip 200 form an integrated whole structure, and define the whole structure as a first wafer structure;

[0081] S2, thin the second wafer substrate 220 in the first wafer structure obtained in S1 to a thickness of 250 Å to obtain a thinned wafer structure;

[0082] S3, grow silicon on the surface of the thinned second wafer substrate 220 in the thinned wafer structure obtained in S2 at a furnace tube internal temperature of 1200℃ and in an oxygen condition to form a silicon oxide film, the silicon oxide film being a third oxide layer 300, and the thickness of the third oxide layer 300 being about 3000 Å;

[0083] S4, align the first alignment mark point 110 of the second magnetic flux concentrator 100 with the second alignment mark point 260 in the thinned wafer structure, and bond the third oxide layer 300 with the first oxide layer 130 of the second magnetic flux concentrator 100, so that the second magnetic flux concentrator 100 and the thinned wafer structure form an integrated whole structure, and define the whole structure as a second wafer structure;

[0084] S5, thin the first wafer substrate 140 and the second wafer substrate 220 in the second wafer structure obtained in S4 respectively to obtain a third wafer structure;

[0085] S6, form a through hole 400 in one of the third wafer structure obtained in S5 by a through silicon via 400 process, then set a lead wire in the through hole 400, and the through hole 400 is connected to the surface of the debugging circuit 250, the lead wire is electrically connected with the debugging circuit 250, to obtain an integrated chip.

[0086] Through experiments, it is verified that the integrated chip obtained by the preparation method of the embodiment can be directly used in current detection scenes after a conventional packaging process with an external Hall package lead frame 500, and can also be used for three-axis magnetic field detection.

[0087] Embodiment

[0088] An integrated chip is prepared by the integrated magnetic core and the integrated chip preparation method of the horizontal type Hall element of embodiment 1 or 2.

[0089] The integrated magnetic core is formed by integrating the magnetic flux concentrator 100 and the Hall ASIC chip 200, wherein the magnetic flux concentrator film 120 can converge the magnetic induction lines and amplify the detected magnetic field strength, and the same function as the ferromagnetic core is realized. Compared with the prior art, the integrated chip does not need to use a large ferromagnetic core, and the miniaturization of the Hall current detection chip can be realized; the micron-level fine alignment of the magnetic flux concentrator film 120 and the horizontal Hall element 210 is realized, which is obviously superior to the alignment accuracy of the current magnetic core assembly; the bonding thickness control between the magnetic flux concentrator film and the Hall element can also be realized, and the thickness accuracy is obviously superior to the assembly control level of the large ferromagnetic core module.

[0090] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, and are not intended to limit the scope of protection of the present application. Although the present application has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present application can be modified or replaced by equivalents without departing from the essence and scope of the technical solutions of the present application.

Claims

1. A method for fabricating an integrated chip comprising an integrated magnetic core and a horizontal Hall element, characterized in that: Two flux gatherers are aligned with the Hall ASIC chip, and then wafer-bonded to the upper and lower surfaces of the Hall ASIC chip respectively to form an integrated chip. Each flux concentrator is provided with a flux concentrating film, and a horizontal Hall element is provided on the horizontal Hall ASIC chip. The flux concentrating film is located directly above or directly below the horizontal Hall element. Define the two flux gatherers as the first flux gatherer and the second flux gatherer, respectively. Each flux concentrator also includes multiple first alignment markers, a first oxide layer, and a first wafer substrate. The Hall ASIC chip is provided with multiple second alignment markers, a second wafer substrate, a second oxide layer, a structural layer, and debugging circuitry. The thickness of the first oxide layer and the second oxide layer is between 1000 Å and 1 μm; the integrated magnetic core is packaged with the external Hall package lead frame before use, and the maximum width of the groove in the external Hall package lead frame is defined as A, the maximum width of the magnetic flux focusing film is defined as B, and the maximum width of the horizontal Hall element is defined as C, and there exists 30 μm ≤ C ≤ B ≤ A ≤ 100 μm; Prepared by the following steps: S1. Align the first alignment mark of the first magnetic flux aggregator with the second alignment mark of the Hall ASIC chip, and then bond the first oxide layer of the first magnetic flux aggregator to the second oxide layer, so that the first magnetic flux aggregator and the Hall ASIC chip form an integral structure, and define the integral structure as the first wafer structure. S2. Thinning the second wafer substrate in the first wafer structure obtained in S1 to obtain a thinned wafer structure; S3. A third oxide layer is formed on the surface of the thinned wafer substrate in the thinned wafer structure obtained in S2; S4. Align the first alignment mark point of the second magnetic flux aggregator with the second alignment mark point in the thinned wafer structure, and bond the third oxide layer to the first oxide layer of the second magnetic flux aggregator, so that the second magnetic flux aggregator and the thinned wafer structure form an integrally connected structure, and define the integral structure as the second wafer structure. S5. Thin the first wafer substrate and the second wafer substrate in the second wafer structure obtained in S4 respectively to obtain the third wafer structure; S6. A through-silicon via (TSV) process is used to form a through-silicon via on one side of the third wafer structure obtained in S5. Then, a lead is placed in the through-silicon via, and the through-silicon via is connected to the surface of the debugging circuit. The lead is electrically connected to the debugging circuit to obtain the integrated chip.

2. The method for fabricating an integrated chip with an integrated magnetic core and a horizontal Hall element according to claim 1, characterized in that: The first flux aggregator wafer is bonded to the upper surface of the Hall ASIC chip, and the flux-concentrating thin film of the first flux aggregator is located directly above the horizontal Hall element; The second flux aggregator wafer is bonded to the lower surface of the Hall ASIC chip, and the flux-concentrating thin film of the second flux aggregator is located directly below the horizontal Hall element.

3. The method for fabricating an integrated chip with an integrated magnetic core and a horizontal Hall element according to claim 2, characterized in that: The first alignment mark and the magnetic flux focusing film are respectively disposed on the upper surface of the first wafer substrate, and the first oxide layer is disposed on the upper surface of the first wafer substrate, the upper surface of the first alignment mark, and the upper surface of the magnetic flux focusing film.

4. The method for fabricating an integrated chip with an integrated magnetic core and a horizontal Hall element according to claim 3, characterized in that: The second alignment mark, the horizontal Hall element, and the debugging circuit are all disposed on the second wafer substrate. The structural layer is disposed on the upper surface of the second wafer substrate, the upper surface of the second alignment mark, and the upper surface of the horizontal Hall element. The second oxide layer is disposed on the upper surface of the structural layer.

5. The method for fabricating an integrated chip with an integrated magnetic core and a horizontal Hall element according to claim 4, characterized in that: In S2, the second wafer substrate is thinned to a thickness of 230 Å to 280 Å.

6. The method for fabricating an integrated chip with an integrated magnetic core and a horizontal Hall element according to claim 5, characterized in that, Specifically, S3 involves growing silicon on the surface of the thinned second wafer substrate in the thinned wafer structure obtained in S2 at an internal temperature of 1180℃~1250℃ under oxygen conditions, forming a silicon oxide film. The silicon oxide film is the third oxide layer, and the thickness of the third oxide layer is 2800Å~3200Å.

7. The method for fabricating an integrated chip of an integrated magnetic core and a horizontal Hall element according to any one of claims 1 to 6, characterized in that: The magnetic flux focusing thin film is FeNi-based magnetic flux focusing thin film, FeZn-based magnetic flux focusing thin film, FeCo-based magnetic flux focusing thin film, or FeNiMo-based magnetic flux focusing thin film; The materials of the first oxide layer and the second oxide layer are silicon dioxide or tetraethyl silicate; The first wafer substrate is a silicon-based substrate; The structural layer is at least one of a metal trace layer, a dielectric layer, or a passivation layer; The first wafer substrate is a silicon-based substrate, a gallium arsenide substrate, or an indium antimonide substrate; The second wafer substrate is a silicon-based substrate, a gallium arsenide substrate, or an indium antimonide substrate.

8. An integrated magnetic core, characterized in that: It is prepared by the integrated chip fabrication method according to any one of claims 1 to 7.

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