Data processing method and data processing device

Abstract

The present disclosure provides a data processing method and a data processing device. The method is applied to the data processing device, the data processing device comprises a first processor, a second processor, and a memory, and the second processor comprises a first core and a second core. The method comprises: a first core acquires first data from a memory, generates a first processing result on the basis of the first data, and stores the first processing result into the memory, wherein the first data is determined by a first processor on the basis of a first data packet sent by an external device; a second core acquires second data from the memory, generates a second processing result on the basis of the second data, and stores the second processing result into the memory; and the first processor acquires third data from the memory, generates a second data packet on the basis of the third data, and sends the second data packet to the external device.

Description

Data processing method and data processing device

[0001] Cross-reference to related applications

[0002] The present disclosure is based on and claims priority to Chinese Patent Application No. 202410836154.8, filed on June 25, 2024, entitled “Data processing method and data processing device”, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0003] The present disclosure relates to, but is not limited to, the technical field of power equipment, and in particular to a data processing method and a data processing device. BACKGROUND

[0004] In related technologies, most power equipment (for example, energy storage equipment, valve control equipment, control protection equipment, etc.) generally achieves complex functions, high real-time requirements, etc. by improving the performance of the processor, carrying a real-time operating system, etc. However, there are problems such as long development cycle, high cost, poor real-time performance, etc. SUMMARY

[0005] Therefore, the embodiments of the present disclosure provide a data processing method and a data processing device. The first processor, the first core and the second core cooperate with each other to complete the processing of data, fully utilize the characteristics of different processors and different cores, not only realize multi-level control of data, meet the requirements of complex functions and high real-time performance, but also shorten the development cycle and reduce the cost. Meanwhile, each hardware accesses the memory in a ring manner to realize data sharing between different hardware, which not only improves the efficiency and real-time performance of data sharing, but also reduces the possibility of access exception of the memory.

[0006] The technical solutions of the embodiments of the present disclosure are implemented as follows:

[0007] The embodiments of the present disclosure provide a data processing method applied to a data processing device. The data processing device includes a first processor, a second processor and a memory. The type of the second processor is different from the type of the first processor. The second processor includes a first core and a second core. The method includes the following steps:

[0008] The first core obtains first data from the memory, generates a first processing result based on the first data, and stores the first processing result in the memory. The first data is determined by the first processor based on a first data packet sent by an external device.

[0009] The second core obtains second data from the memory, generates a second processing result based on the second data, and stores the second processing result into the memory; wherein the second data comprises at least one of the first data and the first processing result.

[0010] The first processor obtains third data from the memory, generates a second data packet based on the third data, and sends the second data packet to the external device; wherein the third data comprises at least one of the first processing result and the second processing result.

[0011] In the embodiments of the present disclosure, first, the data processing is completed by the cooperation among the first processor, the first core and the second core, which makes full use of the characteristics of different processors and different cores, not only realizes multi-level control of data, meets the requirements of complex functions and high real-time, but also shortens the development cycle and reduces the cost; second, the first processor, the first core and the second core access the memory in a ring mode to realize data sharing among the first processor, the first core and the second core, which improves the efficiency and real-time of data sharing, reduces the possibility of access exception of the memory, and simplifies the data communication inside the device and reduces the complexity of communication, since the first processor does not need to communicate with the second processor to share data; finally, the first core and the second core in the second processor only need to write the corresponding processing result into the memory, without paying attention to the subsequent data transmission, update, etc., which reduces the development complexity of the second processor and improves the real-time of data.

[0012] In some embodiments, the first core obtains the first data from the memory, including: the first core obtains the first data from the memory in response to detecting a first trigger event generated by the first processor; and the second core obtains the second data from the memory, including: the second core obtains the second data from the memory in response to detecting a second trigger event generated by the first core.

[0013] In the embodiments of the present disclosure, on the one hand, the first core obtains the first data shared by the first processor from the memory through the trigger event generated by the first processor, which improves the frequency and accuracy of data sharing between the first core and the first processor, and reduces the possibility of access exception of the memory; on the other hand, the second core obtains the second data shared by the first core and the first processor from the memory through the trigger event generated by the first core, which improves the frequency and accuracy of data sharing among the second core, the first core and the first processor, and further reduces the possibility of access exception of the memory.

[0014] In some embodiments, the memory comprises a receiving storage space and a sending storage space, and the data processing method further comprises: initializing the memory based on the configuration file corresponding to the data processing device to obtain the receiving storage space and the sending storage space; wherein the receiving storage space is used to store the to-be-processed data, and the sending storage space is used to store the to-be-sent data; the to-be-processed data comprises at least one of the first data and the first processing result; and the to-be-sent data comprises at least one of the first processing result and the second processing result.

[0015] In the embodiments of the present disclosure, the memory is allocated in real time based on the configuration file corresponding to the data processing device to obtain various storage spaces for storing shared data, which not only improves the accuracy of the storage space, but also stores different types of data through different storage spaces, thereby reducing the possibility of data interference and the possibility of access exception of the memory.

[0016] In some embodiments, the receiving storage space comprises a first receiving storage space corresponding to the first core and a second receiving storage space corresponding to the second core, and the sending storage space comprises a first sending storage space corresponding to the first core and a second sending storage space corresponding to the second core; the first core obtains the first data from the memory, comprising: the first core obtains the first data from the first receiving storage space; the first core stores the first processing result in the memory, comprising: the first core stores the first processing result in the second receiving storage space, and / or the first core stores the first processing result in the first sending storage space; the second core obtains the second data from the memory, comprising: the second core obtains the first data from the first receiving storage space, and / or the second core obtains the first processing result from the second receiving storage space; and the second core stores the second processing result in the memory, comprising: the second core stores the second processing result in the second sending storage space.

[0017] In the embodiments of the present disclosure, on the one hand, by allocating the corresponding receiving storage space to the first core and the second core to store the corresponding to-be-processed data, the possibility of crosstalk between different to-be-processed data is reduced, thereby improving the accuracy of the to-be-processed data; on the other hand, by allocating the corresponding sending storage space to the first core and the second core to store the corresponding to-be-sent data, the possibility of crosstalk between different to-be-sent data is reduced, thereby improving the accuracy of the to-be-sent data.

[0018] In some embodiments, the first processor comprises at least one communication interface of at least one type, and the data processing method further comprises: the first processor receiving a first data packet sent by an external device through a target communication interface; the target communication interface is one of the at least one communication interface of the at least one type; the first processor parses the first data packet according to a communication protocol corresponding to the target communication interface to obtain initial data, determines first data based on the initial data, and stores the first data into the memory.

[0019] In the embodiments of the present disclosure, firstly, the performance of the first processor is fully utilized through the communication between the different types of communication interfaces of the first processor and the external device, the compatibility of the data processing device is improved, and the use scenarios of the data processing device are widened; secondly, the first processor parses the data packet in real time through the communication protocol corresponding to the target communication interface, and the accuracy of the shared data is improved; finally, the first processor stores the first data into the memory in time, so as to realize the sharing of data between the first core and the second core.

[0020] In some embodiments, the first processor generates a second data packet based on the third data, comprising: the first processor generates the second data packet based on the third data and the communication protocol corresponding to the target communication interface; and the first processor sends the second data packet to the external device, comprising: the first processor sends the second data packet to the external device through the target communication interface.

[0021] In the embodiments of the present disclosure, on the one hand, the first processor generates the data packet in real time through the communication protocol corresponding to the target communication interface, and the accuracy of the data packet is improved; on the other hand, the first processor sends the data packet through the target communication interface, and the accuracy of the data sending is improved.

[0022] The embodiments of the present disclosure provide a data processing device, comprising a first processor, a second processor and a memory, the type of the second processor is different from the type of the first processor, and the second processor comprises a first core and a second core, wherein:

[0023] The first processor is configured to receive a first data packet sent by an external device, determine first data based on the first data packet, and store the first data into the memory;

[0024] The first core is configured to obtain the first data from the memory, generate a first processing result based on the first data, and store the first processing result into the memory;

[0025] The second core is configured to obtain second data from the memory, generate a second processing result based on the second data, and store the second processing result into the memory; the second data comprises at least one of the following: the first data and the first processing result.

[0026] The first processor is further configured to obtain third data from the memory, generate a second data packet based on the third data, and send the second data packet to the external device, wherein the third data comprises at least one of the first processing result and the second processing result.

[0027] In the embodiments of the present disclosure, first, the first processor, the first core and the second core jointly complete the processing of data, fully utilize the characteristics of different processors and different cores, not only realize multi-level control of data, meet the requirements of complex functions and high real-time, but also shorten the development cycle and reduce the cost; second, the first processor, the first core and the second core access the memory in a ring manner to realize data sharing among the first processor, the first core and the second core, which improves the efficiency and real-time of data sharing, reduces the possibility of access exception of the memory, and simplifies the internal data communication of the device and reduces the complexity of communication; finally, the first core and the second core in the second processor only need to write the corresponding processing result into the memory, and do not need to pay attention to the transmission, update and the like of subsequent data, which reduces the development complexity of the second processor and improves the real-time of data.

[0028] In some embodiments, the first processor comprises at least one communication interface of at least one type; the first processor is further configured to receive a first data packet sent by an external device through a target communication interface; the target communication interface is one of the at least one communication interface of at least one type; the first data packet is parsed according to a communication protocol corresponding to the target communication interface to obtain initial data, and the first data is determined based on the initial data.

[0029] In the embodiments of the present disclosure, first, the different types of communication interfaces of the first processor communicate with the external device, fully utilize the performance of the first processor, improve the compatibility of the data processing device, and broaden the use scenarios of the data processing device; second, the first processor parses the data packet in real time according to the communication protocol corresponding to the target communication interface, which improves the accuracy of shared data; finally, the first processor stores the first data in the memory in a timely manner to realize data sharing with the first core and the second core.

[0030] In some embodiments, the first processor is further configured to generate a second data packet based on the third data and the communication protocol corresponding to the target communication interface, and send the second data packet to the external device through the target communication interface.

[0031] In the embodiments of the present disclosure, on the one hand, the first processor generates the data packet in real time through the communication protocol corresponding to the target communication interface, thereby improving the accuracy of the data packet; on the other hand, the first processor sends the data packet through the target communication interface, thereby improving the accuracy of data sending.

[0032] In some embodiments, the first core is further configured to acquire the first data from the memory in response to detecting a first trigger event generated by the first processor; and the second core is further configured to acquire the second data from the memory in response to detecting a second trigger event generated by the first core.

[0033] In the embodiments of the present disclosure, on the one hand, the first core acquires the first data shared by the first processor from the memory through a trigger event generated by the first processor, thereby improving the frequency and accuracy of data sharing between the first core and the first processor and reducing the possibility of access exception of the memory; on the other hand, the second core acquires the second data shared by the first core from the memory through a trigger event generated by the first core, thereby improving the frequency and accuracy of data sharing between the second core, the first core and the first processor and further reducing the possibility of access exception of the memory.

[0034] In some embodiments, the first processor comprises a first processing module, the first core comprises a second processing module, and the second core comprises a third processing module; the first processing module is configured to determine the first data based on the first data packet; the second processing module is configured to generate the first processing result based on the first data; and the third processing module is configured to generate the second processing result based on the second data; wherein the first processing time length is less than the third processing time length and the third processing time length is less than the second processing time length, the first processing time length is a time length for the first processing module to determine the first data, the second processing time length is a time length for the second processing module to generate the first processing result, and the third processing time length is a time length for the third processing module to generate the second processing result.

[0035] In the embodiments of the present disclosure, different processing modules with different processing time lengths are deployed in different processors and different cores to process data, thereby fully utilizing the characteristics of different processors and different cores, meeting the complex functions of the device and improving the real-time performance of data processing.

[0036] In some embodiments, the first core is loaded with an operating system or a bare machine program, and the second core is loaded with a bare machine program.

[0037] In the embodiments of the present disclosure, the operating system or the bare machine program is loaded on different cores, thereby fully utilizing the characteristics of the dual core to achieve accurate processing of data by deploying different real-time requirements of software on different cores, thereby improving the overall control performance while meeting the requirements of speed and accuracy.

[0038] In some embodiments, the data processing device integrates a system on chip, the first processor, the second processor and the memory are located in the system on chip, and the first processor, the second processor and the memory communicate through a bus of the system on chip.

[0039] In the embodiments of the present disclosure, by integrating the SoC in the data processing device, the characteristics of different processors and different cores in the SoC are fully utilized, not only the requirements of high real-time performance, high precision and high complexity are met, but also the development cost is reduced and the development efficiency is improved, thereby improving the safety and stability of the power equipment.

[0040] In some embodiments, the first processor includes a first interrupt module, and the first interrupt module is configured to generate a first trigger event, so that the first core acquires the first data from the memory based on the first trigger event.

[0041] In the embodiments of the present disclosure, the first core acquires the first data shared by the first processor by the trigger event generated by the first interrupt module integrated in the first processor, the frequency and accuracy of data sharing between the first core and the first processor are improved, and the possibility of access exception of the memory is reduced.

[0042] In some embodiments, the first core includes a second interrupt module, and the second interrupt module is configured to generate a second trigger event, so that the second core acquires the second data from the memory based on the second trigger event.

[0043] In the embodiments of the present disclosure, the second core acquires the second data shared by the first core and the first processor by the trigger event generated by the second interrupt module integrated in the first core, the frequency and accuracy of data sharing between the second core, the first core and the first processor are improved, and the possibility of access exception of the memory is reduced.

[0044] In some embodiments, the memory includes a receiving storage space and a sending storage space, the receiving storage space is configured to store to-be-processed data, and the sending storage space is configured to store to-be-sent data, the to-be-processed data includes at least one of the first data and the first processing result, the to-be-sent data includes at least one of the first processing result and the second processing result, and the receiving storage space and the sending storage space are generated by the first core based on a configuration file corresponding to the data processing device.

[0045] In the embodiment of the present disclosure, the memory is allocated in real time by the corresponding configuration file of the data processing device to obtain various storage spaces for storing shared data, which not only improves the accuracy of the storage space, but also stores different types of data in different storage spaces, thereby reducing the possibility of data interference and the possibility of access exception of the memory.

[0046] In some embodiments, the receiving storage space includes a first receiving storage space corresponding to the first core and a second receiving storage space corresponding to the second core, and the sending storage space includes a first sending storage space corresponding to the first core and a second sending storage space corresponding to the second core; the first core is further configured to obtain the first data from the first receiving storage space; store the first processing result in the second receiving storage space, and / or store the first processing result in the first sending storage space; and the second core is further configured to obtain the first data from the first receiving storage space, and / or obtain the first processing result from the second receiving storage space; and store the second processing result in the second sending storage space.

[0047] In the embodiment of the present disclosure, on the one hand, by allocating the corresponding receiving storage space to the first core and the second core to store the corresponding to-be-processed data, the possibility of crosstalk between different to-be-processed data is reduced, thereby improving the accuracy of the to-be-processed data; on the other hand, by allocating the corresponding sending storage space to the first core and the second core to store the corresponding to-be-sent data, the possibility of crosstalk between different to-be-sent data is reduced, thereby improving the accuracy of the to-be-sent data.

[0048] It should be understood that the foregoing general description and the following detailed description are only exemplary and explanatory, rather than limiting the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0049] The accompanying drawings, which are incorporated into and form part of the specification, illustrate embodiments consistent with the present disclosure and, together with the specification, serve to explain the technical solutions of the present disclosure.

[0050] FIG. 1 is a schematic diagram of an implementation flow of a data processing method according to an embodiment of the present disclosure;

[0051] FIG. 2 is a schematic diagram of a component structure of a data processing device according to an embodiment of the present disclosure;

[0052] FIG. 3 is a schematic diagram of an implementation flow of a memory initialization method according to an embodiment of the present disclosure;

[0053] FIG. 4 is a schematic diagram of a component structure of a data processing device according to an embodiment of the present disclosure;

[0054] Fig. 5 is a second implementation flowchart of a data processing method according to an embodiment of the present disclosure;

[0055] Fig. 6 is a third implementation flowchart of a data processing method according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0056] In order to make the objects, technical solutions and advantages of the present disclosure clearer, the present disclosure will be further described in detail below with reference to the drawings, and the described embodiments should not be regarded as limiting the present disclosure, and all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present disclosure.

[0057] In the following description, "some embodiments" are described, which describe a subset of all possible embodiments, but it can be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict.

[0058] In the following description, the terms "first\second\third" are only to distinguish similar objects, and do not represent a specific order of the objects, and it can be understood that "first\second\third" can be interchanged in a specific order or sequence as allowed, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0059] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0060] In the related art, most power equipment (for example, energy storage equipment, valve control equipment, control and protection equipment, etc.) in order to meet the requirements of complex functions, high real-time, etc., is generally realized by improving the performance of the processor, carrying a real-time operating system, etc., which has the following problems:

[0061] (1) If a real-time operating system with good real-time performance is used, although the tasks can be ensured to be real-time, such operating systems generally cannot implement very complex functions, and if ported, the development workload will be increased, the development cycle will be lengthened, and the real-time performance of the real-time operating system will also be affected.

[0062] (2) If a non-real-time operating system is used while improving the computing performance of the processor, although the real-time performance can be improved to some extent, it not only cannot meet the requirements of some microsecond-level, nanosecond-level, etc. tasks, but also increases the cost.

[0063] The embodiment of the disclosure provides a data processing method, first, the processing of data is completed by mutual cooperation between the first processor, the first core and the second core, the characteristics of different processors and different cores are fully utilized, not only the multi-level control of data is realized, the requirements of complex functions and high real-time are met, but also the development cycle is shortened and the cost is reduced; secondly, the first processor, the first core and the second core access the memory in a ring mode to realize data sharing between the first processor, the first core and the second core, not only the efficiency and real-time of data sharing are improved, but also the possibility of access exception of the memory is reduced, and since the first processor does not need to communicate with the second processor to share data, the data communication inside the device is simplified and the complexity of communication is reduced; finally, the first core and the second core in the second processor only need to write the corresponding processing result into the memory, and do not need to pay attention to the transmission, update and the like of subsequent data, thereby reducing the development complexity of the second processor and improving the real-time of data. The method provided by the embodiment of the disclosure can be executed by an electronic device, and the electronic device can be a notebook computer, a tablet computer, a desktop computer, a set top box, a mobile device (for example, a mobile phone, a portable music player, a personal digital assistant, a dedicated message device, a portable game device) and various types of terminals, and can also be implemented as a server. The server can be a physical server, a server cluster composed of multiple physical servers or a distributed system, and can also be a cloud server providing cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, content distribution networks (CDN), and basic cloud computing services such as big data and artificial intelligence platforms.

[0064] In the following, the technical solutions in the embodiments of the disclosure will be described clearly and completely in combination with the drawings in the embodiments of the disclosure.

[0065] FIG. 1 is a flowchart of a data processing method provided by an embodiment of the disclosure, which is applied to a data processing device including a first processor, a second processor and a memory, the type of the second processor is different from the type of the first processor, the second processor includes a first core and a second core, as shown in FIG. 1, the method includes steps S11 to S13, wherein:

[0066] In step S11, the first core obtains first data from the memory, generates a first processing result based on the first data, and stores the first processing result into the memory; wherein the first data is determined by the first processor based on a first data packet sent by an external device.

[0067] Here, the data processing device can be any suitable device capable of achieving the function. In some embodiments, the data processing device is mainly used for processing data of an external device.

[0068] The external device can be any suitable device, for example, an energy storage device, etc. The energy storage device can be any suitable device capable of achieving energy storage of electric energy, light energy, etc. For example, an electric energy storage device, which refers to a device that converts electric energy into other forms for storage and releases it for power use when needed, such as a battery. In implementation, the external device is in communication connection with the data processing device.

[0069] The first processor can be any suitable processor, for example, an FPGA (Field Programmable Gate Array), etc.

[0070] The second processor can be any suitable processor, for example, an ARM (Advanced RISC Machines) processor, a CPU (Central Processing Unit), a DSP (Digital Signal Processing), etc. The second processor at least includes a first core and a second core. In some embodiments, the second processor can further include other cores. The core (Core) is also called the kernel, which is the most important component of the second processor. The performance of different cores can be the same or different.

[0071] The memory can be any suitable unit capable of achieving data storage function, for example, a RAM (Random Access Memory), an OCM (On-Chip Memory), etc. In some embodiments, the data processing device can be integrated with an SoC (System on Chip), and the first processor, the second processor and the memory are all located in the SoC.

[0072] The first data packet includes at least first data. The first data can refer to payload data in the first data packet. The first data can be any suitable power data, such as voltage, current, etc. In some embodiments, the first data corresponding to different power devices can be different. For example, in the case that the external device is a power storage device, the first data can be a parameter related to the power storage device. The parameter related to the power storage device can include, but is not limited to, a parameter of a battery product (e.g., a single battery, a battery module, a battery pack, etc.), a parameter of a switch, etc. The parameter of the battery product can include, but is not limited to, current, voltage, power, temperature, state of charge, capacity, etc. The parameter of the switch can include, but is not limited to, voltage, current, resistance, etc.

[0073] In some embodiments, the first data can include at least one of, but is not limited to, payload data in the first data packet, rated data of the data processing device, etc. For example, the first data includes actual voltage sent by the external device and rated voltage of the data processing device.

[0074] The data packet (including the first data packet and other data packets hereinafter) can be transmitted in any suitable manner, such as a bus, a communication interface, etc. The bus can include, but is not limited to, a CAN (Controller Area Network) bus, an Ethernet bus, etc. The communication interface can be any suitable interface, such as an LVDS (Low-Voltage Differential Signaling) interface, an SRIO (Serial RapidIO) interface, an Ethernet interface, an FT3 interface, a GT (Gigabyte Transceiver) interface, etc. In implementation, the first processor parses the first data packet to obtain the first data, and stores the first data in the memory in time for sharing with the first core, the second core, etc.

[0075] In some embodiments, the external device can assemble the communication information and the first data according to a communication protocol corresponding to the communication interface to obtain a first data packet. The communication protocol refers to rules and agreements that must be followed by both entities to complete communication or services. Different communication interfaces can correspond to different communication protocols. In some embodiments, the communication information can be different for the same communication protocol. For example, the FT3 data packet generated for the FT3 protocol can include but is not limited to a frame header, a frame length, a frame format, etc., and the frame format can define any number of data blocks. In implementation, because FT3 interfaces of different manufacturers use different frame formats, different rates, different encoding information, etc., FT3 interfaces of different manufacturers correspond to different communication information. The encoding information can include but is not limited to encoding methods, polarities, etc. The encoding method can include but is not limited to Manchester encoding, differential Manchester encoding, etc. The polarity can include but is not limited to 0, 1, etc., 1 can represent a low-to-high transition, and 0 can represent a high-to-low transition.

[0076] In some embodiments, the step S11 of "the first core obtaining the first data from the memory" includes a step S111, in which:

[0077] The step S111 includes a step S1111, in which:

[0078] Here, the trigger event (including the first trigger event and other trigger events mentioned later) can be any suitable event, for example, a timing trigger event, a random trigger event, a specified trigger event, etc. The timing trigger event is mainly an event triggered by a timer. The random trigger event can be a trigger event generated by a random number. The specified trigger event can be a pre-specified trigger event. For example, a timer is set in the first processor, and an interrupt (corresponding to the first trigger event) is generated by the timer timing. For another example, the first trigger event is generated after the first processor stores the first data to the memory.

[0079] In implementation, when the first core detects the first trigger event, the first data is obtained from the memory again.

[0080] In the embodiments of the present disclosure, the first core obtains the first data shared by the first processor from the memory through the trigger event generated by the first processor, which improves the frequency and accuracy of data sharing between the first core and the first processor, and reduces the possibility of access exception of the memory.

[0081] The first processing result can be any suitable result. For example, a control result of starting and stopping, protection, etc. in a power device. For another example, a parameter calculated according to the first data. In some embodiments, the first core can determine the first processing result through an internal second processing module. The second processing module can be any suitable module capable of achieving the function, for example, a control software. In implementation, the control software can be a program with a running period of milliseconds and above, the control software has low requirements for real-time performance, periodicity, and has certain fault tolerance.

[0082] In implementation, when the first core determines the first processing result, the first processing result is written into the memory in time, so as to be shared to the second core, the first processor, etc.

[0083] In step S12, the second core acquires second data from the memory, generates a second processing result based on the second data, and stores the second processing result into the memory; wherein the second data includes at least one of the following: the first data, the first processing result.

[0084] Here, the second core acquires the second data by reading the memory. In some embodiments, different second data corresponds to different storage locations.

[0085] In some embodiments, the step S12 of "the second core acquiring the second data from the memory" includes step S121, wherein:

[0086] In step S121, the second core acquires the second data from the memory in response to detecting a second trigger event generated by the first core.

[0087] Here, the second trigger event can be any suitable event. For example, after the first core stores the first processing result into the memory, a software interrupt (corresponding to the second trigger event) is generated. In implementation, when the second core detects the second trigger event, the second data is acquired from the memory again.

[0088] In the embodiments of the present disclosure, the second core acquires the second data shared by the first core and the first processor from the memory through the trigger event generated by the first core, which improves the frequency and accuracy of data sharing between the second core, the first core and the first processor, and further reduces the possibility of access exception of the memory.

[0089] The second processing result can be any suitable result. For example, the result of execution of an algorithm. In some embodiments, the second core can determine the second processing result by an internal third processing module. The third processing module can be any suitable module capable of achieving the function, for example, an algorithm software. In implementation, the algorithm software can be a program with a running period of microsecond to hundred microsecond, and the algorithm software has high requirements on real-time and periodicity. In some embodiments, the third processing module takes less time to generate the second processing result than the second processing module takes to generate the first processing result.

[0090] In implementation, when the second core determines the second processing result, the second processing result is written into the memory in time so as to be shared to the first processor.

[0091] In step S13, the first processor acquires third data from the memory, generates a second data packet based on the third data, and sends the second data packet to an external device; wherein the third data comprises at least one of the first processing result and the second processing result.

[0092] Here, the first processor acquires the third data by reading the memory. In some embodiments, different third data correspond to different storage locations.

[0093] The second data packet can be the third data, or can be obtained by assembling or packaging the third data. The sending manner of the second data packet can be any suitable manner, for example, a bus, a communication interface, etc. In some embodiments, the first processor can directly send the third data to the external device, or can assemble the third data according to a communication protocol corresponding to a target communication interface to obtain the second data packet.

[0094] In some embodiments, when the second core writes the second processing result into the memory, the first processor is notified to acquire the third data from the memory. The notifying manner can be any suitable manner, for example, broadcasting, writing a register, etc. For example, the second core writes a certain register of the first processor to notify the first processor to read the third data in time.

[0095] In the embodiments of the present disclosure, first, the data processing is completed by the mutual cooperation among the first processor, the first core and the second core, the characteristics of different processors and different cores are fully utilized, not only the multi-level control of data is realized, the requirements of complex functions and high real-time are met, but also the development cycle is shortened and the cost is reduced; second, the first processor, the first core and the second core access the memory in a ring mode to realize the data sharing among the first processor, the first core and the second core, not only the efficiency and real-time of data sharing are improved, but also the possibility of access exception of the memory is reduced, and since the first processor does not need to communicate with the second processor to share data, the data communication inside the device is simplified and the complexity of communication is reduced; finally, the first core and the second core in the second processor only need to write the corresponding processing results into the memory, and do not need to pay attention to the transmission, update and the like of subsequent data, thereby reducing the development complexity of the second processor and improving the real-time of data.

[0096] In some embodiments, the memory comprises a receiving storage space and a sending storage space, and the method further comprises a step S14, in which:

[0097] In step S14, the first core initializes the memory based on the configuration file corresponding to the data processing device, and obtains the receiving storage space and the sending storage space.

[0098] Here, the receiving storage space is used to store the to-be-processed data, and the to-be-processed data comprises at least one of the first data and the first processing result. The receiving storage space can comprise at least one storage block, and the size of each storage block can be consistent. In some embodiments, the memory can be divided into a plurality of storage blocks in advance according to a set size. In some embodiments, the receiving storage space can comprise at least one of a first receiving storage space corresponding to the first core, a second receiving storage space corresponding to the second core and the like. The first receiving storage space is used to store the data processed by the first core, and in the implementation, the first processor can store the first data into the first receiving storage space. The second receiving storage space is used to store the data processed by the second core, and in the implementation, the first core can store the first processing result into the second receiving storage space. In some embodiments, the size of the first receiving storage space and the second receiving storage space can be the same or different.

[0099] The sending storage space is used to store the to-be-sent data, and the to-be-sent data includes at least one of the first processing result and the second processing result. The sending storage space can also include at least one storage block, and the size of each storage block can be consistent. In implementation, the sending storage space is different from the receiving storage space. In some embodiments, the sending storage space can include at least one of a first sending storage space corresponding to the first core, a second sending storage space corresponding to the second core, and the like. The first sending storage space is used to store the data sent by the first core, and in implementation, the first core can store the first processing result to the first sending storage space. The second sending storage space is used to store the data sent by the second core, and in implementation, the second core can store the second processing result to the second sending storage space. In some embodiments, the size of the first sending storage space and the second sending storage space can be the same or different.

[0100] The configuration file can include at least configuration information of the storage spaces (including the sending storage space and the receiving storage space), and the memory is dynamically configured according to the configuration information to obtain the storage spaces. The configuration information of the storage space can include, but is not limited to, the identification, size, base address, offset address, and belonging object of the storage space. The belonging object is used to describe the user of the storage space. The configuration file can be any form of file, for example, an XML (Extensible Markup Language) file, a WORD file, an EXCEL file, an HTML (Hyper Text Markup Language) file, and the like.

[0101] The configuration file can be obtained in any suitable manner. For example, the configuration file is pre-stored in the data processing device. For another example, the configuration file is sent to the data processing device by another device.

[0102] Taking the configuration file shown below as an example:

[0103] The receiving storage space is allocated through the baddr field and the size field in the tag RRAM CFG in the configuration file, the base address of the receiving storage space is 0x10000, and the size is 4096 KB. The first receiving storage space and the second receiving storage space are allocated through the id, user, offset, and size fields in the tag RAM, the identification of the first receiving storage space is 1, the belonging object is the first core, the offset address is 0x1000, and the size is 256 KB, the identification of the second receiving storage space is 2, the belonging object is the second core, the offset address is 0x2000, and the size is 1024 KB.

[0104] The sending storage space is allocated through the baddr field and the size field in the tag TRAM CFG of the configuration file, the base address of the sending storage space is 0x20000, and the size is 2048 KB; the first sending storage space and the second sending storage space are allocated through the id, the user, the offset, and the size field in the tag RAM, the identification of the first sending storage space is 1, the belonging object is the first core, the offset address is 0x1000, and the size is 64 KB, and the identification of the second receiving storage space is 2, the belonging object is the second core, the offset address is 0x1100, and the size is 128 KB.

[0105] In the embodiment of the present disclosure, the memory is allocated in real time by the configuration file corresponding to the data processing device, so as to obtain various storage spaces for storing shared data, which not only improves the accuracy of the storage space, but also stores different types of data through different storage spaces, thereby reducing the possibility of data interference and the possibility of access exception of the memory.

[0106] In some embodiments, the receiving storage space includes a first receiving storage space corresponding to the first core and a second receiving storage space corresponding to the second core, and the sending storage space includes a first sending storage space corresponding to the first core and a second sending storage space corresponding to the second core; the "first core obtains the first data from the memory" in the step S11 includes a step S151, the "first core stores the first processing result into the memory" in the step S11 includes a step S152, the "second core obtains the second data from the memory" in the step S12 includes a step S153, and the "second core stores the second processing result into the memory" in the step S12 includes a step S154, wherein:

[0107] The step S151 includes that the first core obtains the first data from the first receiving storage space.

[0108] Here, the first processor writes the first data into the first receiving storage space through a write operation.

[0109] The step S152 includes that the first core stores the first processing result into the second receiving storage space and / or the first core stores the first processing result into the first sending storage space.

[0110] Here, the first core can write the first processing result into the second receiving storage space and / or the first sending storage space according to actual needs through a write operation. In implementation, if the first processing result needs to be transmitted to the second core, the first processing result needs to be written into the second receiving storage space at this time; if the first processing result does not need to be transmitted to the second core, the first processing result does not need to be written into the second receiving storage space at this time; if the first processing result needs to be transmitted to the first processor, the first processing result needs to be written into the first sending storage space at this time; if the first processing result does not need to be transmitted to the first processor, the first processing result does not need to be written into the first sending storage space at this time.

[0111] In step S153, the second core obtains the first data from the first receiving storage space and / or the first processing result from the second receiving storage space.

[0112] Here, the second core reads the first data and / or the first processing result according to actual needs through a read operation. In implementation, when the second core needs to further process the first processing result, the first processing result can be obtained through a read operation at this time; when the second core needs to process the first data, the first data can be obtained through a read operation at this time.

[0113] In step S154, the second core stores the second processing result into the second sending storage space.

[0114] Here, the second core stores the second processing result into the second sending storage space through a write operation.

[0115] For example, for a PI (Proportional Integral, proportional and integral) control algorithm of a valve control device, the first data can include a rated voltage value of the data processing device and an actual voltage value sent by an external device. In implementation, the first processor writes the first data into the first receiving storage space through a write operation;

[0116] The first core obtains the rated voltage from the first receiving storage space through a read operation.

[0117] The first core calculates a PI parameter (corresponding to the first processing result) according to the rated voltage, and stores the PI parameter into the second receiving storage space through a write operation.

[0118] The second core obtains the rated voltage and the actual voltage from the first receiving storage space and the PI parameter from the second receiving storage space through a read operation.

[0119] The second core stores the PI calculation result (corresponding to the aforementioned second processing result) in the second sending storage space through a write operation according to the rated voltage, the actual voltage, and the PI parameters.

[0120] In the embodiments of the present disclosure, on the one hand, by respectively assigning the first core and the second core with corresponding receiving storage spaces to store corresponding to-be-processed data, the possibility of crosstalk between different to-be-processed data is reduced, thereby improving the accuracy of the to-be-processed data; on the other hand, by respectively assigning the first core and the second core with corresponding sending storage spaces to store corresponding to-be-sent data, the possibility of crosstalk between different to-be-sent data is reduced, thereby improving the accuracy of the to-be-sent data.

[0121] In some embodiments, the first processor includes at least one communication interface of at least one type, and the method further includes steps S161 to S162, in which:

[0122] In step S161, the first processor receives a first data packet sent by an external device through a target communication interface; the target communication interface is one of the at least one communication interface of at least one type.

[0123] Here, the first processor includes a plurality of types of communication interfaces, such as an FT3 interface, a GT interface, an LVDS interface, an Ethernet interface, etc., and the number of each type of interface can be at least one. For example, the first processor includes a gigabit network interface, a hundred-megabit network interface, etc. The target communication interface can be any communication interface, such as an FT3 interface. In implementation, the first processor receives a first data packet containing an actual voltage (corresponding to first data) sent by an external device through an FT3 interface.

[0124] In step S162, the first processor parses the first data packet according to a communication protocol corresponding to the target communication interface to obtain initial data, determines first data based on the initial data, and stores the first data in the memory.

[0125] Here, the first data can be the initial data, or data obtained after preprocessing the initial data. The preprocessing can include, but is not limited to, splitting, sorting, assembling, etc. In some embodiments, the first processor can integrate a first processing module to preprocess the initial data. The first processing module can be any suitable module capable of achieving this function, such as a data processing software. In implementation, the data processing software can be a program with a running cycle of nanoseconds and hundreds of nanoseconds, and the data processing software has a high requirement for real-time performance. In some embodiments, the first processing module determines that the time length of the first data is less than the time length of the second processing result determined by the third processing module.

[0126] In some embodiments, before the first data packet is parsed, the first data packet can be checked according to a preset checking rule, and the first data packet is parsed again if the checking is passed. In implementation, the checking rules corresponding to different communication protocols can be different. The checking rule can include, but is not limited to, whether the content of the communication information of the first data packet is legal, correct, and the like.

[0127] In implementation, the first processor writes the first data into the memory through a write operation.

[0128] In the embodiments of the present disclosure, firstly, the performance of the first processor is fully utilized through the communication between the different types of communication interfaces of the first processor and the external device, the compatibility of the data processing device is improved, and the use scenario of the data processing device is widened. Secondly, the first processor parses the data packet in real time through the communication protocol corresponding to the target communication interface, and the accuracy of the shared data is improved. Finally, the first processor stores the first data in the memory in a timely manner, so as to realize the sharing of data between the first core and the second core.

[0129] In some embodiments, the step S13 of "generating, by the first processor, a second data packet based on the third data, and sending the second data packet to the external device" includes the step S131 of:

[0130] In step S131, the first processor generates a second data packet based on the third data and the communication protocol corresponding to the target communication interface, and sends the second data packet to the external device through the target communication interface.

[0131] Here, the target communication interface can be any communication interface, for example, an FT3 interface, a GT interface, and the like. The communication protocols corresponding to different communication interfaces can be different. In implementation, the first processor packages the third data according to the communication protocol corresponding to the target communication interface to obtain the second data packet, and sends the second data packet to the external device.

[0132] In the embodiments of the present disclosure, on the one hand, the first processor generates a data packet in real time through the communication protocol corresponding to the target communication interface, and improves the accuracy of the data packet. On the other hand, the first processor sends the data packet through the target communication interface, and improves the precision of data sending.

[0133] Based on the above embodiments, the embodiments of the present disclosure further provide a data processing device, and FIG. 2 is a schematic structural diagram of a data processing device according to an embodiment of the present disclosure. As shown in FIG. 2, the data processing device 20 includes a first processor 21, a second processor 22, and a memory 23. The second processor is of a type different from that of the first processor. The second processor 22 includes a first core 221 and a second core 222. The first core 221 is configured to: obtain the first data from the memory; generate a first processing result based on the first data; and store the first processing result in the memory. The second core 222 is configured to: obtain second data from the memory; generate a second processing result based on the second data; and store the second processing result in the memory. The second data includes at least one of the first data and the first processing result.

[0134] The first processor 21 is configured to: receive a first data packet sent by an external device; determine first data based on the first data packet; and store the first data in the memory.

[0135] The first core 221 is configured to: obtain the first data from the memory; generate a first processing result based on the first data; and store the first processing result in the memory.

[0136] The second core 222 is configured to: obtain second data from the memory; generate a second processing result based on the second data; and store the second processing result in the memory. The second data includes at least one of the first data and the first processing result.

[0137] The first processor 21 is further configured to: obtain third data from the memory; generate a second data packet based on the third data; and send the second data packet to the external device. The third data includes at least one of the first processing result and the second processing result.

[0138] Here, the data processing device can be any suitable device. In implementation, the data processing device has more functions and is more complex, and has higher requirements for control accuracy, real-time performance, and the like.

[0139] The first processor can be any suitable processor, for example, an FPGA. The first data packet can be any suitable data packet. In some embodiments, the first data packet includes at least the first data. The first data can refer to the payload data in the first data packet. In implementation, the external device can packetize the first data according to a communication protocol corresponding to a target communication interface, to obtain the first data packet. The target communication interface refers to an interface through which the external device communicates with the data processing device. The target communication interface can include but is not limited to an FT3 interface, a GT interface, and the like. The process in which the first processor determines the first data can refer to the specific implementation of step S162.

[0140] In some embodiments, the first processor includes a first interrupt module. The first interrupt module is configured to generate a first trigger event, so that the first core obtains the first data from the memory based on the first trigger event.

[0141] Here, the first interrupt module can be any suitable module capable of achieving the function. The first trigger event can be any suitable event, for example, a timing trigger event, a random trigger event, a specified trigger event, etc. In some embodiments, the first interrupt module can generate the first trigger event by using a timer. In some embodiments, the first interrupt module can generate the first trigger event after detecting that the first processor writes the first data to the memory. In implementation, when the first core detects the first trigger event, the first data is obtained from the memory again.

[0142] In the embodiments of the present disclosure, the first core obtains the first data shared by the first processor triggered by the trigger event generated by the first interrupt module integrated in the first processor, which improves the frequency and accuracy of data sharing between the first core and the first processor, and reduces the possibility of access exception of the memory.

[0143] The second processor can be any suitable processor, for example, an ARM processor, a CPU, a DSP, etc. The second processor at least includes the first core and the second core. The first core and the second core can be configured to run in an AMP (Asymmetric Multi-Processing) architecture, an SMP (Symmetric Multi-Processing) architecture, a BMP (Bond Multi-Processing) architecture, etc. In the AMP architecture, the first core and the second core are configured to include master cores and slave cores, each core independently runs different tasks, each core can carry and run different operating systems or bare metal programs, and each core is started in order and does not interfere with each other.

[0144] In some embodiments, the first core carries an operating system or a bare metal program, and the second core carries a bare metal program.

[0145] Here, the operating system can be any suitable operating system, for example, Microsoft Windows, macOS, Linux, Google chromeOS, iOS, Android, etc. In some embodiments, part of the power equipment uses a visual development method, and the running environment of the visual development is relatively complex, and usually needs the participation of an operating system, so the operating system can be carried in the first core.

[0146] The bare metal program usually refers to a program developed with specific functions on the basis of no operating system, and the program does not depend on the operating system to run. In implementation, considering the real-time requirement, the second core mainly implements various algorithms in power control, and can not carry an operating system to ensure the accuracy and real-time performance of algorithm execution.

[0147] In the embodiments of the present disclosure, by loading the operating system or the bare machine program on different cores, the characteristics of the dual-core are fully utilized to achieve accurate processing of data by deploying different software with different real-time requirements on different cores, so as to improve the overall control performance while meeting the requirements of speed, accuracy and the like.

[0148] The first processing result can be any suitable result. For example, the control result of starting and stopping, protection and the like in the power equipment. For another example, the parameter calculated according to the first data. In some embodiments, the first core determines the first processing result by the internal control software. In implementation, the process of determining the first processing result by the first core can refer to the specific embodiments of the foregoing step S11.

[0149] In some embodiments, the first core comprises a second interrupt module, and the second interrupt module is configured to generate a second trigger event, so that the second core acquires the second data from the memory based on the second trigger event.

[0150] Here, the second interrupt module can be any suitable module capable of achieving the function. The second trigger event can be any suitable event, for example, a timing trigger event, a random trigger event, a specified trigger event and the like. In some embodiments, the second interrupt module can generate the second trigger event by using a timer. In some embodiments, the second interrupt module can generate the second trigger event after detecting that the first core writes the second data into the memory. In implementation, the second core acquires the second data from the memory after detecting the second trigger event.

[0151] In the embodiments of the present disclosure, the second core acquires the second data shared by the first core and the first processor by the trigger event generated by the second interrupt module integrated in the first core, which improves the frequency and accuracy of data sharing between the second core, the first core and the first processor, and reduces the possibility of access exception of the memory.

[0152] The second processing result can be any suitable result. For example, the execution result of the algorithm. In some embodiments, the second core determines the second processing result by the internal algorithm software. In implementation, the process of determining the second processing result by the second core can refer to the specific embodiments of the foregoing step S12.

[0153] The memory can be any suitable unit capable of achieving the data storage function, for example, RAM, OCM and the like.

[0154] In some embodiments, the memory includes a receiving storage space and a sending storage space, the receiving storage space is used to store to-be-processed data, the sending storage space is used to store to-be-sent data, the to-be-processed data includes at least one of the first data and the first processing result, the to-be-sent data includes at least one of the first processing result and the second processing result, and the receiving storage space and the sending storage space are generated by the first core based on the configuration file of the data processing device.

[0155] Here, the receiving storage space can include at least one storage block, and the size of each storage block can be consistent. The sending storage space can also include at least one storage block, and the size of each storage block can be consistent.

[0156] The configuration file can be any form of file, for example, an XML file, a WORD, an EXCEL, an HTML file, etc. The configuration file can at least include configuration information of the storage space (including the sending storage space and the receiving storage space), and the memory is dynamically configured according to the configuration information to obtain each storage space. In implementation, the generation process of the receiving storage space and the sending storage space can refer to the specific embodiments of the foregoing step S14.

[0157] FIG. 3 is a schematic diagram of an implementation flow of a memory initialization method provided by an embodiment of the present disclosure, as shown in FIG. 3, the method includes steps S301 to S305, wherein:

[0158] Step S301, the first core determines whether the configuration file exists, if yes, step S302 is entered, otherwise, step S304 is entered;

[0159] Step S302, the first core determines whether the configuration file is parsed successfully, if yes, step S303 is entered, otherwise, step S304 is entered;

[0160] Step S303, the first core initializes the memory according to the configuration information in the configuration file to obtain each storage space, and step S305 is entered;

[0161] Here, after the initialization of the memory is completed, the first core can synchronize each storage space to the first processor and the second core.

[0162] Step S304, the first core reports initialization failure;

[0163] Step S305, end.

[0164] In the embodiments of the present disclosure, the memory is allocated in real time by the corresponding configuration file of the data processing device to obtain various storage spaces for storing shared data, which not only improves the accuracy of the storage space, but also stores different types of data through different storage spaces, thereby reducing the possibility of data interference and the possibility of access exception of the memory.

[0165] In some embodiments, the first processor includes a first processing module, the first core includes a second processing module, and the second core includes a third processing module. The first processing module is configured to determine first data based on a first data packet. The second processing module is configured to generate a first processing result based on the first data. The third processing module is configured to generate a second processing result based on second data.

[0166] Here, the first processing module can be any suitable module capable of achieving this function, and the first processing module is mainly used for preprocessing such as splitting, sorting, and assembling data. In some embodiments, the first processing module can be a program with a running period of nanoseconds and hundreds of nanoseconds, and the first processing module has high real-time requirements.

[0167] The second processing module can be any suitable module capable of achieving this function, and the second processing module is mainly used for generating a control result of the device. In some embodiments, the second processing module can be a program with a running period of milliseconds and above, and the second processing module has low real-time and periodic requirements and has certain fault tolerance.

[0168] The third processing module can be any suitable module capable of achieving this function, and the third processing module is mainly used for generating an execution result of an algorithm. In some embodiments, the third processing module can be a program with a running period of microseconds to hundreds of microseconds, and the third processing module has high real-time and periodic requirements.

[0169] In implementation, the data processing time of each processing module is different to meet the real-time, accuracy, and complexity requirements of the device. In some embodiments, the first processing time is less than the third processing time, and the third processing time is less than the second processing time. The first processing time is the time for the first processing module to determine the first data, the second processing time is the time for the second processing module to generate the first processing result, and the third processing time is the time for the third processing module to generate the second processing result.

[0170] In the embodiments of the present disclosure, different processing modules with different processing times are deployed in different processors and different cores to process data, which fully utilizes the characteristics of different processors and different cores, and meets the complex functions of the device while improving the real-time of data processing.

[0171] In some embodiments, the data processing device integrates a system on chip, the first processor, the second processor and the memory are located in the system on chip, and the first processor, the second processor and the memory communicate through a bus of the system on chip.

[0172] Here, the SoC can include but is not limited to the first processor, the second processor, the bus, the memory and the like. In implementation, the first processor, the second processor and the memory can be mounted on the bus and communicate through the bus.

[0173] In the embodiments of the present disclosure, by integrating the SoC in the data processing device, the characteristics of different processors and different cores in the SoC are fully utilized, not only the requirements of high real-time performance, high precision and high complexity are met, but also the development cost is reduced and the development efficiency is improved, thereby improving the safety and stability of the power equipment.

[0174] FIG. 4 is a schematic diagram of a component structure of a data processing device according to an embodiment of the present disclosure. As shown in FIG. 4, the data processing device integrates an SoC, the SoC includes a first processor 21, a second processor, a memory 23 and a bus 24, the second processor includes a first core 221 and a second core 222, and the bus 24 is connected to the first processor 21, the second processor and the memory 23.

[0175] The memory 23 includes a receiving storage space 231 and a sending storage space 232, the receiving storage space 231 includes a first receiving storage space corresponding to the first core and a second receiving storage space corresponding to the second core, and the sending storage space 232 includes a first sending storage space corresponding to the first core and a second sending storage space corresponding to the second core.

[0176] The first processor 21 includes a plurality of communication interfaces 211 and a data processing software 212 (corresponding to the first processing module) therein, receives a first data packet sent by an external device through a target communication interface in the plurality of communication interfaces 211, pre-processes initial data in the first data packet through the data processing software 212 to obtain first data, and stores the first data into the first receiving storage space.

[0177] The first core 221 carries an operating system 2211, a visualization software 2212 and a control software 2213 (corresponding to the second processing module) therein, the visualization software 2212 is used to realize the visualization operation of the data processing device, the control software 2213 is used to determine a first processing result based on the first data, and the first processing result is stored into the second receiving storage space and / or the first sending storage space according to actual needs.

[0178] The second core 222 includes algorithm software 2221 (corresponding to the third processing module) for determining a second processing result based on the second data, and storing the second processing result to a second sending storage space;

[0179] The first processor 21 is further configured to acquire the first processing result from the first sending storage space and / or the second processing result from the second sending storage space according to actual needs, and generate a second data packet, and send the second data packet to an external device through a target communication interface in the plurality of communication interfaces 211.

[0180] FIG. 5 is a second implementation flowchart of a data processing method according to an embodiment of the present disclosure. As shown in FIG. 5, the method includes steps S501 to S507, wherein:

[0181] In step S501, the FPGA (corresponding to the first processor) determines first data based on a first data packet sent by an external device, and stores the first data to a first receiving storage space;

[0182] In step S502, the FPGA generates a timing interrupt (corresponding to the first trigger event) according to a set processing period, to notify the CPU0 (corresponding to the first core) to process;

[0183] In step S503, the CPU0 acquires the first data from the first receiving storage space after responding to the timing interrupt, and determines a first processing result based on the first data;

[0184] In step S504, the CPU0 stores the first processing result to a second receiving storage space and / or a first sending storage space according to actual needs, and generates a software interrupt (corresponding to the second trigger event) to notify the CPU1 (corresponding to the second core) to process;

[0185] In step S505, the CPU1 acquires the first data from the first receiving storage space and / or the first processing result from the second receiving storage space according to actual needs after responding to the software interrupt, and determines a second processing result based on the first data and / or the first processing result;

[0186] In step S506, the CPU1 stores the second processing result to a second sending storage space, and notifies the FPGA to process through a write register operation;

[0187] In step S507, the FPGA generates a second data packet based on the first processing result and / or the second processing result after receiving the notification, and sends the second data packet to the external device.

[0188] Fig. 6 is a schematic diagram of an implementation flow of a data processing method according to an embodiment of the present disclosure, as shown in Fig. 6, the method comprises steps S601-S615, wherein:

[0189] In step S601, the FPGA receives a first data packet sent by an external device through an FT3 interface (corresponding to the target communication interface), parses the first data packet, and obtains an actual voltage (corresponding to the initial data).

[0190] In step S602, the FPGA obtains a rated voltage of the data processing device through an Ethernet interface.

[0191] In step S603, the FPGA stores the rated voltage and the actual voltage (corresponding to the first data) into a first receiving storage space.

[0192] In step S604, the FPGA determines whether a processing period is reached, if yes, proceeds to step S605, otherwise, proceeds to step S604.

[0193] In step S605, the FPGA generates a timing interrupt.

[0194] In step S606, the CPU0 responds to the timing interrupt.

[0195] In step S607, the CPU0 obtains the rated voltage from the first receiving storage space, and calculates PI parameters of a PI control algorithm (corresponding to the first processing result) according to the rated voltage.

[0196] In step S608, the CPU0 stores the PI parameters into a second receiving storage space and / or a first sending storage space according to actual requirements.

[0197] In step S609, the CPU0 generates a software interrupt.

[0198] In step S610, the CPU1 responds to the software interrupt.

[0199] In step S611, the CPU1 obtains the rated voltage and the actual voltage from the first receiving storage space, and obtains the PI parameters from the second receiving storage space according to actual requirements.

[0200] In step S612, the CPU1 determines a PI control result (corresponding to the second processing result) according to the rated voltage, the actual voltage and the PI parameters.

[0201] In step S613, the CPU1 stores the PI control result into a second sending storage space, and notifies the FPGA to process through a write register operation.

[0202] In step S614, the FPGA acquires the PI control result from the second sending storage space after receiving the notification, and packetizes the PI control result to generate a second data packet.

[0203] In step S615, the FPGA sends the second data packet to the external device.

[0204] In the embodiments of the present disclosure, first, the data processing is completed by the mutual cooperation between the first processor, the first core and the second core, the characteristics of different processors and different cores are fully utilized, not only the multi-level control of data is realized, the requirements of complex functions and high real-time are met, but also the development cycle is shortened and the cost is reduced; second, the first processor, the first core and the second core access the memory in a ring mode to realize the data sharing between the first processor, the first core and the second core, not only the efficiency and real-time of data sharing are improved, but also the possibility of access exception of the memory is reduced, and since the first processor does not need to communicate with the second processor to share data, the data communication inside the device is simplified and the complexity of communication is reduced; finally, the first core and the second core in the second processor only need to write the corresponding processing result into the memory, and do not need to pay attention to the transmission, update and the like of subsequent data, which reduces the development complexity of the second processor and improves the real-time of data.

[0205] In some embodiments, the first processor includes at least one communication interface of at least one type; the first processor is further configured to receive a first data packet sent by an external device through a target communication interface; the target communication interface is one of the at least one communication interface of at least one type; the first data packet is parsed according to a communication protocol corresponding to the target communication interface to obtain initial data, and the first data is determined based on the initial data.

[0206] In some embodiments, the first processor is further configured to generate a second data packet based on the third data and the communication protocol corresponding to the target communication interface, and send the second data packet to the external device through the target communication interface.

[0207] In some embodiments, the first core is further configured to acquire the first data from the memory in response to detecting a first trigger event generated by the first processor; and the second core is further configured to acquire the second data from the memory in response to detecting a second trigger event generated by the first core.

[0208] In some embodiments, the receiving storage space includes a first receiving storage space corresponding to the first core and a second receiving storage space corresponding to the second core, and the sending storage space includes a first sending storage space corresponding to the first core and a second sending storage space corresponding to the second core; the first core is further configured to acquire the first data from the first receiving storage space, store the first processing result in the second receiving storage space, and / or store the first processing result in the first sending storage space; and the second core is further configured to acquire the first data from the first receiving storage space and / or acquire the first processing result from the second receiving storage space, and store the second processing result in the second sending storage space.

[0209] The above description of the device embodiments is similar to the description of the method embodiments, and has similar beneficial effects. For technical details not disclosed in the device embodiments of the present disclosure, please refer to the description of the method embodiments of the present disclosure.

[0210] It should be noted that, if the above method is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the embodiments of the present disclosure can be embodied in the form of a software product, which is stored in a storage medium and includes a number of instructions for making an electronic device (which can be a personal computer, a server, or a network device, etc.) execute all or part of the methods of the embodiments of the present disclosure. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a magnetic disk or an optical disk, and various other storage media that can store program codes. Thus, the embodiments of the present disclosure are not limited to any particular hardware and software combination.

[0211] It should be understood that every feature, structure, or characteristic described above that is recited in means-plus-function or other functional claim is implemented by a method described herein and is not a signal per se. It should be understood that "one embodiment" or "an embodiment" as described throughout this specification means that a particular feature, structure, or characteristic described is included in at least one embodiment of the disclosure. Thus, appearances of "in one embodiment" or "in an embodiment" are not necessarily referring to the same embodiment. Furthermore, the particular features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that the sequence of processes described above in various embodiments of the disclosure does not mean the order of execution, and the execution order of the processes should be determined according to their functions and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the disclosure. The sequence number of the above-mentioned embodiments of the disclosure is only for description, and does not represent the advantages and disadvantages of the embodiments. It should be noted that in this paper, the term "include", "contain" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or includes elements inherent to such process, method, article or device. Without more limitations, the element defined by the statement "including a" does not exclude the presence of other identical elements in the process, method, article or device including the element.

[0212] In several embodiments provided by the disclosure, it should be understood that the disclosed devices and methods can be implemented in other manners. The above-described device embodiments are only schematic. For example, the division of the units is only a logical function division. There can be other division manners in actual implementation. For example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed coupling, direct coupling or communication connection between the components can be indirect coupling or communication connection through some interface, device or unit, and can be electrical, mechanical or in other forms.

[0213] The units described as separate components can or can not be physically separate, and the components shown as units can or can not be physical units; they can be located in one place, or distributed on a plurality of network units; some or all of the units can be selected according to actual needs to achieve the purpose of the embodiment. In addition, each functional unit in the embodiments of the disclosure can be integrated into a processing unit, or each unit can be a separate unit, or two or more units can be integrated into a unit; the integrated unit can be implemented in the form of hardware, or in the form of hardware plus software functional unit.

[0214] Those skilled in the art can understand that all or part of the steps of the above-mentioned method embodiments can be completed by program instruction related hardware, and the foregoing program can be stored in a computer readable storage medium, and the program executes the steps of the method embodiments when executed; and the foregoing storage medium includes a mobile storage device, a read only memory (ROM), a magnetic disc or an optical disc, and various storage medium that can store program codes.

[0215] Alternatively, the integrated units of the present disclosure can be stored in a computer readable storage medium if they are implemented in the form of software function modules and sold or used as independent products. Based on this understanding, the technical solutions of the present disclosure can be embodied in the form of a software product, and the computer software product is stored in a storage medium, includes a plurality of instructions to make an electronic device (which can be a personal computer, a server, or a network device, etc.) execute all or part of the embodiments of the present disclosure. The foregoing storage medium includes a mobile storage device, a ROM, a magnetic disc or an optical disc, and various storage medium that can store program codes.

[0216] The above is only an embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present disclosure, which should be covered by the protection scope of the present disclosure.

Claims

1. A data processing method applied to a data processing device, the data processing device comprising a first processor, a second processor and a memory, the second processor being of a type different from that of the first processor, the second processor comprising a first core and a second core, the method comprising: the first core acquiring first data from the memory, generating a first processing result based on the first data, and storing the first processing result into the memory, wherein the first data is determined by the first processor based on a first data packet sent by an external device; the second core acquiring second data from the memory, generating a second processing result based on the second data, and storing the second processing result into the memory, wherein the second data comprises at least one of the first data and the first processing result; and the first processor acquiring third data from the memory, generating a second data packet based on the third data, and sending the second data packet to the external device, wherein the third data comprises at least one of the first processing result and the second processing result.

2. The data processing method of claim 1, wherein the first core acquires the first data from the memory in response to detecting a first trigger event generated by the first processor; and the second core acquires the second data from the memory in response to detecting a second trigger event generated by the first core. The memory comprises a receiving storage space and a sending storage space, and the method further comprises: the first core initializing the memory based on a configuration file corresponding to the data processing device to obtain the receiving storage space and the sending storage space; wherein the receiving storage space is used to store to-be-processed data, the sending storage space is used to store to-be-sent data, the to-be-processed data comprises at least one of the first data and the first processing result, and the to-be-sent data comprises at least one of the first processing result and the second processing result. The receiving storage space comprises a first receiving storage space corresponding to the first core and a second receiving storage space corresponding to the second core, and the sending storage space comprises a first sending storage space corresponding to the first core and a second sending storage space corresponding to the second core; the first core acquires the first data from the first receiving storage space; and the first core stores the first processing result into the second receiving storage space and / or the first sending storage space. ​ ​ ​ 3. The data processing method according to claim 1 or 2, wherein, ​ ​ 4. The data processing method of claim 3, wherein, ​ ​ ​ The second core obtains second data from the memory, including that the second core obtains the first data from the first receiving storage space and / or the second core obtains the first processing result from the second receiving storage space; The second core stores the second processing result into the memory, including that the second core stores the second processing result into the second sending storage space.

5. The data processing method according to any one of claims 1 to 4, wherein, The first processor includes at least one communication interface of at least one type, and the method further includes: The first processor receives the first data packet sent by the external device through a target communication interface, wherein the target communication interface is one of the at least one communication interface of the at least one type; The first processor analyzes the first data packet according to a communication protocol corresponding to the target communication interface to obtain initial data, determines the first data based on the initial data, and stores the first data into the memory.

6. The data processing method according to claim 5, wherein The first processor generates a second data packet based on third data, and sends the second data packet into the external device, including that the first processor generates the second data packet based on the third data and a communication protocol corresponding to the target communication interface, and sends the second data packet into the external device through the target communication interface.

7. A data processing device, including a first processor, a second processor and a memory, the type of the second processor being different from the type of the first processor, the second processor including a first core and a second core, wherein: The first processor is configured to receive a first data packet sent by an external device; determine first data based on the first data packet; store the first data into the memory; The first core is configured to obtain the first data from the memory; generate a first processing result based on the first data; store the first processing result into the memory; The second core is configured to obtain second data from the memory; generate a second processing result based on the second data; store the second processing result into the memory; wherein the second data includes at least one of the first data and the first processing result; The first processor is further configured to obtain third data from the memory, generate a second data packet based on the third data, and send the second data packet into the external device; wherein the third data includes at least one of the first processing result and the second processing result.

8. The data processing device of claim 7, wherein, The first processor includes at least one communication interface of at least one type; The first processor is further configured to receive the first data packet sent by the external device through a target communication interface, wherein the target communication interface is one of the at least one communication interface of the at least one type; parse the first data packet according to a communication protocol corresponding to the target communication interface to obtain initial data, and determine the first data based on the initial data.

9. The data processing device of claim 8, wherein, The first processor is further configured to generate the second data packet based on the third data and the communication protocol corresponding to the target communication interface, and send the second data packet to the external device through the target communication interface.

10. The data processing device of any one of claims 7 to 9, wherein, The first core is further configured to obtain the first data from the memory in response to detecting a first trigger event generated by the first processor. The second core is further configured to obtain the second data from the memory in response to detecting a second trigger event generated by the first core.

11. The data processing device according to any one of claims 7 to 10, wherein, The first processor comprises a first processing module, the first core comprises a second processing module, and the second core comprises a third processing module, wherein: The first processing module is configured to determine the first data based on the first data packet. The second processing module is configured to generate a first processing result based on the first data. The third processing module is configured to generate a second processing result based on the second data. The first processing time is shorter than the third processing time, and the third processing time is shorter than the second processing time, wherein the first processing time is a time for the first processing module to determine the first data, the second processing time is a time for the second processing module to generate the first processing result, and the third processing time is a time for the third processing module to generate the second processing result.

12. The data processing device according to any one of claims 7 to 11, wherein, The first core is loaded with an operating system or a bare machine program, and the second core is loaded with a bare machine program.

13. The data processing device according to any one of claims 7 to 12, wherein, The data processing device comprises a system on chip, and the first processor, the second processor, and the memory are located in the system on chip and communicate through a bus of the system on chip.

14. The data processing device according to any one of claims 7 to 13, wherein, The first processor comprises a first interrupt module. The first interrupt module is configured to generate a first trigger event to enable the first core to obtain the first data from the memory based on the first trigger event.

15. The data processing device according to any one of claims 7 to 14, wherein, The first core comprises a second interrupt module. The second interrupt module is configured to generate a second trigger event to enable the second core to obtain the second data from the memory based on the second trigger event.

16. The data processing device according to any one of claims 7 to 15, wherein, The memory comprises a receiving storage space and a sending storage space, the receiving storage space is used for storing to-be-processed data, the sending storage space is used for storing to-be-sent data, the to-be-processed data comprises at least one of the first data and the first processing result, the to-be-sent data comprises at least one of the first processing result and the second processing result, and the receiving storage space and the sending storage space are generated by the first core based on a configuration file corresponding to the data processing device.

17. The data processing device of claim 16, wherein, The receiving storage space comprises a first receiving storage space corresponding to the first core and a second receiving storage space corresponding to the second core, and the sending storage space comprises a first sending storage space corresponding to the first core and a second sending storage space corresponding to the second core. The first core is further configured to acquire the first data from the first receiving storage space. The first processing result is stored into the second receiving storage space and / or the first sending storage space. The second core is further configured to acquire the first data from the first receiving storage space and / or the first processing result from the second receiving storage space. The second processing result is stored into the second sending storage space.

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