Display panel and display apparatus

Abstract

Provided in the embodiments of the present application are a display panel and a display apparatus. The display panel comprises pixel circuits and signal lines, wherein each pixel circuit comprises a data writing transistor and a voltage regulation transistor; and the signal lines comprise data signal lines and voltage regulation signal lines. The display panel further comprises a display region and a fan-out region located on one side of the display region, wherein the display region comprises a first display region and a second display region, the second display region being located on at least one side of the first display region; the fan-out region comprises a plurality of fan-out traces, and the first display region and the second display region each comprise a plurality of data signal lines; and the data signal lines are connected to the fan-out traces. The display panel further comprises dummy connection traces located in the display region, wherein the dummy connection traces are insulated from the data connection traces, and there are dummy connection traces disposed in the same layer as the data connection traces; and at least some of the voltage regulation signal lines comprise the dummy connection traces.

Description

Display panel and display device

[0001] The present application claims priority to the Chinese patent application No. 202410874622.0, filed on July 1, 2024, to the Chinese Patent Office, the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] Embodiments of the present application relate to the display technical field, for example, to a display panel and a display device. BACKGROUND

[0003] With the continuous development of display technology, display panels have been widely used in people's production and life. In order to better meet people's needs, the display panel can be adjusted, for example, part of the wiring is adjusted, so as to improve the overall effect of the display panel.

[0004] SUMMARY

[0005] Embodiments of the present application provide a display panel and a display device, by adjusting at least part of the voltage adjustment signal line to include a virtual connection wiring, the utilization rate of the wiring can be improved, and the yield can be improved.

[0006] In a first aspect, embodiments of the present application provide a display panel, comprising a pixel circuit and a signal line;

[0007] The pixel circuit comprises a data write transistor and a voltage adjustment transistor; the signal line comprises a data signal line and a voltage adjustment signal line, the data signal line is electrically connected with the first electrode of the data write transistor, and the voltage adjustment signal line is electrically connected with the first electrode of the voltage adjustment transistor;

[0008] A plurality of data signal lines extend along a first direction and are arranged along a second direction, and the first direction and the second direction intersect;

[0009] The display panel further comprises a display area and a fan-out area located on one side of the display area;

[0010] The display area comprises a first display area and a second display area, and the second display area is located on at least one side of the first display area;

[0011] The fan-out area comprises a plurality of fan-out wirings, and the first display area and the second display area each comprise a plurality of data signal lines;

[0012] The data signal line is connected with the fan-out wiring; wherein the data signal line of the second display area is connected with the fan-out wiring through a data connection wiring located in the display area;

[0013] The display panel further comprises a virtual connection wire in the display area, the virtual connection wire is arranged in an insulating manner with the data connection wire, and the virtual connection wire and the data connection wire are arranged in the same layer.

[0014] At least part of the voltage adjustment signal line comprises the virtual connection wire.

[0015] In a second aspect, an embodiment of the present application provides a display device comprising the display panel of the first aspect. BRIEF DESCRIPTION OF DRAWINGS

[0016] FIG. 1 is a structural schematic diagram of a first display panel according to an embodiment of the present application;

[0017] FIG. 2 is a structural schematic diagram of a first pixel circuit according to an embodiment of the present application;

[0018] FIG. 3 is a timing of an embodiment of signals provided to the pixel circuit shown in FIG. 2 in a driving cycle according to an embodiment of the present application;

[0019] FIG. 4 is a structural schematic diagram of a second display panel according to an embodiment of the present application;

[0020] FIG. 5 is a film layer structural schematic diagram of the first pixel circuit according to an embodiment of the present application;

[0021] FIG. 6 is a film layer structural schematic diagram of the first display panel according to an embodiment of the present application;

[0022] FIG. 7 is a structural schematic diagram of the first semiconductor layer to the fourth metal layer in FIG. 6;

[0023] FIG. 8 is a structural schematic diagram of the fourth metal layer to the fifth metal layer in FIG. 6;

[0024] FIG. 9 is a structural schematic diagram of the first semiconductor layer in FIG. 6;

[0025] FIG. 10 is a structural schematic diagram of the first metal layer in FIG. 6;

[0026] FIG. 11 is a structural schematic diagram of the second metal layer in FIG. 6;

[0027] FIG. 12 is a structural schematic diagram of the fourth metal layer in FIG. 6;

[0028] FIG. 13 is a structural schematic diagram of the fifth metal layer in FIG. 6;

[0029] FIG. 14 is a structural schematic diagram of an anode layer in a display panel according to an embodiment of the present application;

[0030] FIG. 15 is a structural schematic diagram of a fourth metal layer in the related art;

[0031] FIG. 16 is a structural diagram of a fifth metal layer in the related art;

[0032] FIG. 17 is a structural diagram of a film layer of a second display panel according to an embodiment of the present application;

[0033] FIG. 18 is a structural diagram of a first semiconductor layer to a fourth metal layer in FIG. 17;

[0034] FIG. 19 is a structural diagram of a fourth metal layer to a fifth metal layer in FIG. 17;

[0035] FIG. 20 is a structural diagram of the fourth metal layer in FIG. 17;

[0036] FIG. 21 is a structural diagram of the fifth metal layer in FIG. 17;

[0037] FIG. 22 is a structural diagram of a second pixel circuit according to an embodiment of the present application;

[0038] FIG. 23 is a timing of an embodiment of signals provided to the pixel circuit shown in FIG. 22 in one driving period according to an embodiment of the present application;

[0039] FIG. 24 is a structural diagram of a film layer of the second pixel circuit according to an embodiment of the present application;

[0040] FIG. 25 is a structural diagram of a film layer of a third display panel according to an embodiment of the present application;

[0041] FIG. 26 is a structural diagram of a first semiconductor layer to a fourth metal layer in FIG. 24;

[0042] FIG. 27 is a structural diagram of a fourth metal layer to a fifth metal layer in FIG. 24;

[0043] FIG. 28 is a structural diagram of the first semiconductor layer in FIG. 24;

[0044] FIG. 29 is a structural diagram of a first metal layer in FIG. 24;

[0045] FIG. 30 is a structural diagram of a second metal layer in FIG. 24;

[0046] FIG. 31 is a structural diagram of a second semiconductor layer in FIG. 24;

[0047] FIG. 32 is a structural diagram of a third metal layer in FIG. 24;

[0048] FIG. 33 is a structural diagram of a fourth metal layer in FIG. 24;

[0049] FIG. 34 is a structural diagram of a fifth metal layer in FIG. 24;

[0050] FIG. 35 is a structural diagram of an anode layer in another display panel according to an embodiment of the present application;

[0051] FIG. 36 is a structural schematic diagram of a third metal layer in the related art;

[0052] FIG. 37 is a structural schematic diagram of a fourth metal layer in the related art;

[0053] FIG. 38 is a structural schematic diagram of a fifth metal layer in the related art;

[0054] FIG. 39 is a structural schematic diagram of a third pixel circuit provided by an embodiment of the present application;

[0055] FIG. 40 is a structural schematic diagram of a film layer of a fourth display panel provided by an embodiment of the present application;

[0056] FIG. 41 is a structural schematic diagram of a first semiconductor layer to a fourth metal layer in FIG. 40;

[0057] FIG. 42 is a structural schematic diagram of a fourth metal layer to a fifth metal layer in FIG. 40;

[0058] FIG. 43 is a structural schematic diagram of the first semiconductor layer in FIG. 40;

[0059] FIG. 44 is a structural schematic diagram of a first metal layer in FIG. 40;

[0060] FIG. 45 is a structural schematic diagram of a second metal layer in FIG. 40;

[0061] FIG. 46 is a structural schematic diagram of the fourth metal layer in FIG. 40;

[0062] FIG. 47 is a structural schematic diagram of the fifth metal layer in FIG. 40;

[0063] FIG. 48 is a structural schematic diagram of an anode layer in another display panel provided by an embodiment of the present application;

[0064] FIG. 49 is a structural schematic diagram of another fourth metal layer in the related art;

[0065] FIG. 50 is a structural schematic diagram of another fifth metal layer in the related art;

[0066] FIG. 51 is a structural schematic diagram of a film layer of a fifth display panel provided by an embodiment of the present application;

[0067] FIG. 52 is a structural schematic diagram of a first semiconductor layer to a fourth metal layer in FIG. 51;

[0068] FIG. 53 is a structural schematic diagram of a fourth metal layer to a fifth metal layer in FIG. 51;

[0069] FIG. 54 is a structural schematic diagram of the fourth metal layer in FIG. 51;

[0070] FIG. 55 is a structural schematic diagram of the fifth metal layer in FIG. 51;

[0071] FIG. 56 is a structural schematic diagram of a display device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0072] The present application will be described in detail below with reference to the drawings and embodiments. It can be understood that the specific embodiments described herein are merely intended for explaining the present application, but not limiting the present application. In addition, it should be noted that, for the convenience of description, only the parts related to the present application are shown in the drawings, but not all the structures.

[0073] It should be noted that the terms "first", "second", and the like in the description and claims of the present application and the above-described drawings are used to distinguish similar objects, but not necessarily to describe a specific order or sequence. It should be understood that the data used in this way can be exchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a system, product or device including a series of elements does not necessarily have to be limited to those steps or elements clearly listed, but can include other elements not clearly listed or inherent to these products or devices.

[0074] Fig. 1 is a structural schematic diagram of a first display panel provided by an embodiment of the present application, Fig. 2 is a structural schematic diagram of a first pixel circuit provided by an embodiment of the present application, Fig. 3 is a timing of an implementation of signals provided to the pixel circuit shown in Fig. 2 in one driving period provided by an embodiment of the present application, and Fig. 4 is a structural schematic diagram of a second display panel provided by an embodiment of the present application. Referring to Figs. 1 to 4, an embodiment of the present application provides a display panel 10, which includes a pixel circuit 100 and a signal line 200. The pixel circuit 100 includes a data writing transistor 110 and a voltage adjusting transistor 120. The signal line 200 includes a data signal line 210 and a voltage adjusting signal line 220. The data signal line 210 is electrically connected with a first electrode of the data writing transistor 110, and the voltage adjusting signal line 220 is electrically connected with a first electrode of the voltage adjusting transistor 120. A plurality of data signal lines 210 extend along a first direction X and are arranged along a second direction Y. The first direction X and the second direction Y intersect. The display panel 10 further includes a display area AA and a fan-out area A1 located at one side of the display area AA. The display area AA includes a first display area AA1 and a second display area AA2. The second display area AA2 is located at least one side of the first display area AA1. The fan-out area A1 includes a plurality of fan-out wires S0. The first display area AA1 and the second display area AA2 each include a plurality of data signal lines 210. The data signal line 210 is connected with the fan-out wire S0. The data signal line 210 of the second display area AA2 is connected with the fan-out wire S0 through a data connection wire L0 located in the display area AA. The display panel 10 further includes a virtual connection wire L3 located in the display area AA. The virtual connection wire L3 is insulatively arranged with the data connection wire L0 and there is a virtual connection wire L3 and a data connection wire L0 arranged in the same layer. At least part of the voltage adjusting signal line 220 includes the virtual connection wire L3.

[0075] An embodiment of the present application provides a display panel. A pixel circuit of the display panel includes a data writing transistor and a voltage adjusting transistor. The data writing transistor is electrically connected with a data signal line, and the voltage adjusting transistor is electrically connected with a voltage adjusting signal line. The data signal line is located in a display area of the display panel, and a fan-out wire is located in a fan-out area of the display panel. The data signal line located in a first display area is electrically connected with the fan-out wire, and the data signal line located in a second display area is electrically connected with the fan-out wire through a data connection wire. The display panel further includes a virtual connection wire located in the display area. The virtual connection wire is insulatively arranged with the data connection wire and arranged in the same layer. Part of the voltage adjusting signal line includes the virtual connection wire. In this way, the utilization rate of the wires in the display panel can be improved. By multiplexing the virtual connection wire as the voltage adjusting signal line, the voltage adjusting signal line can be saved in the original setting film layer of the voltage adjusting signal line, the wiring space of the original setting film layer of the display panel is improved, and the yield is improved, and the process preparation cost of the display panel is reduced.

[0076] Referring to FIG. 1, the display panel 10 includes a pixel circuit 100, which is electrically connected with a light emitting element 300 in the display panel 10, to realize the driving of the light emitting element 300 and ensure the light emitting display of the light emitting element 300. The display panel 10 further includes a signal line 200, which is configured to provide a voltage signal and / or a current signal to the pixel circuit 100, so as to realize the driving of the light emitting element 300 by the pixel circuit 100. The pixel circuit 100 includes a data writing transistor 110 and a voltage regulating transistor 120, and the signal line 200 includes a data signal line 210 and a voltage regulating signal line 220, wherein the data signal line 210 is electrically connected with the data writing transistor 110, and the voltage regulating signal line 220 is electrically connected with the voltage regulating transistor 120. Since the setting mode of the pixel circuit 100 has diversity, the structure of the pixel circuit 100 is not shown in FIG. 1, and the electrical connection positions of the transistors in the signal line 200 and the pixel circuit 100 are not explicitly shown, so that the electrical connection relationship between the two is only shown in the figure by the way that the signal line 200 and the pixel circuit 100 overlap, but it is not limited to the position and area of the overlap.

[0077] The setting mode of the pixel circuit 100 has diversity. For example, referring to FIG. 2, the pixel circuit 100 is exemplified as “7T1C”. Based on the setting mode of the pixel circuit 100, those skilled in the art can make adaptive adjustment according to the needs. Referring to FIG. 2, the pixel circuit 100 can include a first light emitting control transistor T1, a data writing transistor T2, a driving transistor T3, a threshold compensation transistor T4, an initialization reset transistor T5, a second light emitting control transistor T6, an anode reset transistor T7 and a storage capacitor Cst. Optionally, the types of the transistors in the pixel circuit 100 can have diversity. The transistors can include a low temperature poly-silicon transistor (LTPS), which has the advantages of high switching speed, high carrier mobility and small power.

[0078] For the timing operation of the pixel circuit 100, referring to FIG. 3, the scan signal line (shown as S1 in the figure) connected to the control terminal of the initialization reset transistor T5 can control the on and off of the initialization reset transistor T5, and write the reset signal in the voltage adjustment signal line 220 (shown as the initialization reset signal line Vref1 in the figure) connected to the input terminal of the initialization reset transistor T5 to the gate of the driving transistor T3 when the initialization reset transistor T5 is on, to reset the first node N1. The storage capacitor Cst can ensure the stability of the potential of the first node N1. The scan signal line (shown as S3 in the figure) connected to the control terminal of the data writing transistor T2 can control the on and off of the data writing transistor T2, and write the data signal on the data signal line (shown as Vdata in the figure) to the first electrode of the driving transistor T3 when the data writing transistor T2 is on. The scan signal line (shown as S2 in the figure) connected to the control terminal of the threshold compensation transistor T4 can control the on and off of the threshold compensation transistor T4, and compensate the threshold voltage of the driving transistor T3 when the threshold compensation transistor T4 is on; at the same time, the scan signal line (shown as S3 in the figure) connected to the control terminal of the anode reset transistor T7 can control the on and off of the anode reset transistor T7, and reset the anode of the light emitting element 300 connected to the pixel circuit 100 when the anode reset transistor T7 is on, i.e. write the reset signal on the voltage adjustment signal line 220 (shown as the anode reset signal line Vref2 in the figure) to the anode of the light emitting element 300. The light emitting control signal line Emit connected to the control terminal of the first light emitting control transistor T1 and the control terminal of the second light emitting control transistor T6 can control the on and off of the control terminal of the first light emitting control transistor T1 and the second light emitting control transistor T6, and write the power supply signal transmitted by the power supply signal line PVDD to the light emitting element 300 when the first light emitting control transistor T1 and the second light emitting control transistor T6 are on, to realize the display and light emission of the light emitting element 300. For example, referring to FIG. 3, one frame time of the display panel 10 at least includes an initialization writing stage Y1, a data writing stage Y2 and a light emitting stage Y3. In the initialization stage Y1, the initialization reset transistor T5 is on under the control of the scan signal S1, the reset signal in the initialization reset signal line Vref1 is written to the first node N1 electrically connected to the gate of the driving transistor T3, to initialize the gate of the driving transistor T3, and at the same time, since the threshold compensation transistor T4 is on, the reset signal in the initialization reset signal line Vref1 is also written to the second electrode of the driving transistor T3, i.e. the N3 node.In the data writing stage Y2, the data writing transistor T2 is turned on under the control of the scanning signal S3, and the threshold compensation transistor T4 is turned on under the control of the scanning signal S2, so that the data signal Vdata is written into the gate of the driving transistor T3 through the data writing transistor T2, the driving transistor T3 and the threshold compensation transistor T4 in turn. At the same time, in the data writing stage Y2, the anode reset transistor T7 is turned on under the control of the scanning signal S3, so that the reset signal in the anode reset signal line Vref2 is written into the anode of the light emitting element 300, and the anode of the light emitting element 300 is initialized. In the light emitting stage Y3, the first light emitting transistor T1 and the second light emitting control transistor T6 are turned on under the control of the light emitting control signal Emit, so that the driving transistor T3 generates a driving current and transmits the driving current to the anode of the light emitting element 300, and the light emitting element 300 is driven to emit light.

[0079] For example, as shown in FIGS. 1 to 3, in the pixel circuit 100, the data writing transistor 110 includes the data writing transistor T2, the voltage adjusting transistor 120 can include the initialization reset transistor T5 and the anode reset transistor T7, the data signal Vdata is transmitted in the data signal line 210, the voltage adjusting signal line 220 connected with the initialization reset transistor T5 is the initialization reset signal line Vref1, and the voltage adjusting signal line 220 connected with the anode reset transistor T7 is the anode reset signal line Vref2. In different pixel circuits 100, the number and position of the transistors can be adjusted adaptively, and the number and position of the data writing transistor 110 and the voltage adjusting transistor 120 can also be adjusted adaptively.

[0080] For example, as shown in FIG. 4, the display panel 10 includes a display area AA and a non-display area NA, the display area AA includes a light emitting element and a data signal line 210 connected with the light emitting element, and the display area AA is configured to realize the display function of the display panel 10. The non-display area NA includes a display controller connected with the data signal line 210, such as a driving chip, and the display controller provides a display signal to the data signal line 210, and the display panel 10 is driven to realize the display function. The non-display area NA surrounds at least part of the display area AA, and the positions of the display area AA and the non-display area NA are not limited in the embodiments of the present application.

[0081] For example, as shown in FIG. 4, the non-display area NA further includes a fan-out area A1, the fan-out area A1 includes a plurality of fan-out lines S0, and the fan-out lines S0 are electrically connected with the plurality of data signal lines 210, so as to ensure stable transmission of the data signal.

[0082] Exemplarily, the display area AA includes a first display area AA1 and a second display area AA2, the second display area AA2 is located on both sides of the first display area AA1, and the second display area AA2 is closer to the boundary of the display area AA than the first display area AA1. Among them, the data signal lines 210 in the first display area AA1 extend along the first direction X and are arranged along the second direction Y, and the data signal lines 210 can be directly electrically connected with the fan-out wire S0; the data signal lines 210 in the second display area AA2 also extend along the first direction X and are arranged along the second direction Y, and the data signal lines 210 are electrically connected with the fan-out wire S0 through the data connection wire L0, so that the occupied space of the fan-out wire S0 can be reduced, and the setting area of the fan-out area A1 is further reduced, the proportion of the non-display area NA is effectively reduced, the proportion of the display area AA of the display panel 10 is increased, and the display effect of the display panel 10 is increased.

[0083] Exemplarily, the display panel 10 further includes a virtual connection wire L3 located in the display area AA, the virtual connection wire L3 is insulated from the data connection wire L0 but is arranged in the same layer, and the virtual connection wire L3 can also ensure the uniformity of the overall wire arrangement, and will not affect the normal transmission of the signal in the data connection wire L0. For example, the virtual connection wire L3 can be arranged in the area where the data connection wire L0 does not extend. That is, by arranging the virtual connection wire L3, the data connection wire L0 setting area is uniformly arranged in the whole, the density of wire arrangement in different areas is balanced, and the light reflectivity of different areas in the display panel 10 caused by unbalanced wire arrangement is avoided, and the display effect of the display panel 10 is avoided. The display panel 10 is not balanced.

[0084] The virtual connection wire L3 arranged in the display panel 10 is insulated from the data connection wire L0, and the virtual connection wire L3 does not originally transmit data signals, but in order to ensure the uniformity of the display panel 10, the virtual connection wire L3 is additionally arranged in the display panel 10. At least part of the additionally arranged virtual connection wire L3 can be reused as a voltage adjustment signal line 220, and the original wire part of the part of the voltage adjustment signal line 220 can be removed. It can be understood that part of the voltage adjustment signal line 220 is removed, and the virtual connection wire L3 is used for signal transmission. In this way, the utilization rate of the metal wire in the display panel 10 can be improved, and the wiring space of the original voltage adjustment signal line setting film layer is improved, which is beneficial to improve the yield and reduce the process preparation cost of the display panel 10.

[0085] The display panel 10 is overlapped by multiple film layers, FIG. 5 is a schematic diagram of a film layer structure of a first pixel circuit according to an embodiment of the present application. The film layer structure of the pixel circuit 100 shown in FIG. 5 can correspond to the pixel circuit 100 shown in FIG. 2. The film layer structure of the pixel circuit 100 can be, from bottom to the light-emitting side of the display panel 10, a substrate 500, a buffer layer 510, a first semiconductor layer 520, a first insulating layer 530, a first metal layer 540, an interlayer insulating layer 550, a second metal layer 560, a second insulating layer 570, a fourth metal layer 580, a third insulating layer 590, a fifth metal layer 5100, a planarization layer 5110, and an anode layer 5120. The film layer structure of the pixel circuit 100 can be adjusted as needed, such as adding or removing some film layers. Any of the above film layers can include at least one sub-layer, which is not limited in the present application.

[0086] FIG. 6 is a schematic diagram of a film layer structure of a first display panel according to an embodiment of the present application. FIG. 7 is a schematic diagram of the first semiconductor layer to the fourth metal layer in FIG. 6. FIG. 8 is a schematic diagram of the fourth metal layer to the fifth metal layer in FIG. 6. FIG. 9 is a schematic diagram of the first semiconductor layer in FIG. 6. FIG. 10 is a schematic diagram of the first metal layer in FIG. 6. FIG. 11 is a schematic diagram of the second metal layer in FIG. 6. FIG. 12 is a schematic diagram of the fourth metal layer in FIG. 6. FIG. 13 is a schematic diagram of the fifth metal layer in FIG. 6. FIG. 14 is a schematic diagram of an anode layer in a display panel according to an embodiment of the present application. If the pixel circuit 100 in the display panel 10 is the pixel circuit 100 shown in FIG. 2, the film layer structure of the display panel 10 can be shown in FIG. 6, and FIG. 7 to FIG. 13 are used to show different film layers in FIG. 6 from bottom to top.

[0087] For example, referring to Figs. 6-14, in the film layer structure corresponding to the pixel circuit 100, referring to Figs. 12 and 13, part of the virtual connection wire L3 is located in the film layer where the fourth metal layer 580 is located (see the virtual connection wire L3 in Fig. 12), and part of the virtual connection wire L3 is located in the film layer where the fifth metal layer 5100 is located (see the virtual connection wire L3 in Fig. 13). Part of the voltage adjustment signal line 220 electrically connected to the initialization reset transistor T5 is located in the film layer where the second metal layer 560 is located (see the initialization reset signal line Vref1 in Fig. 11). Part of the voltage adjustment signal line 220 electrically connected to the initialization reset transistor T5 is also located in the film layer where the fifth metal layer 5100 is located (see the initialization reset signal line Vref1 in Fig. 13), at this time, the virtual connection wire L3 is multiplexed as the initialization reset signal line Vref1, that is, the voltage adjustment signal line 220 includes the virtual connection wire L3. Part of the voltage adjustment signal line 220 electrically connected to the anode reset transistor T7 is located in the film layer where the second metal layer 560 is located (see the anode reset signal line Vref2 in Fig. 11). Part of the voltage adjustment signal line 220 electrically connected to the anode reset transistor T7 is also located in the film layer where the fifth metal layer 5100 is located (see the anode reset signal line Vref2 in Fig. 13), at this time, the virtual connection wire L3 is multiplexed as the anode reset signal line Vref2, that is, the voltage adjustment signal line 220 includes the virtual connection wire L3.

[0088] Figs. 15 and 16 are structural schematic diagrams of the fourth metal layer and the fifth metal layer in the related art, respectively. In Fig. 15, part of the initialization reset signal line Vref1 and part of the anode reset signal line Vref2 are not arranged in the film layer where the fifth metal layer 5100 is located, that is, the voltage adjustment signal line does not include the virtual connection wire L3. Correspondingly, part of the initialization reset signal line Vref1 needs to be arranged in another metal layer, that is, referring to Fig. 15, part of the initialization reset signal line Vref1 is located in the film layer where the fourth metal layer 580 is located. Similarly, referring to Fig. 15, part of the anode reset signal line Vref2 is located in the film layer where the fourth metal layer 580 is located. Therefore, referring to Figs. 13 and 16, the virtual connection wire L3 which does not transmit data signals is multiplexed as the voltage adjustment signal line 220 in the embodiment of the present application, so as to improve the utilization rate of the wire. Referring to Figs. 15 and 12, the wire originally arranged in the fourth metal layer 580 can be moved to the fifth metal layer 5100 in the embodiment of the present application, so that the voltage adjustment signal line 220 in the fourth metal layer 580 can be removed, so as to improve the wiring space of the film layer where the voltage adjustment signal line 220 of the display panel 10 is arranged, and also helps to improve the yield and reduce the process preparation cost of the display panel 10.

[0089] FIG. 17 is a schematic diagram of a film layer structure of a second display panel according to an embodiment of the present application, FIG. 18 is a schematic diagram of a structure of a first semiconductor layer to a fourth metal layer in FIG. 17, FIG. 19 is a schematic diagram of a structure of the fourth metal layer to a fifth metal layer in FIG. 17, FIG. 20 is a schematic diagram of a structure of the fourth metal layer in FIG. 17, and FIG. 21 is a schematic diagram of a structure of the fifth metal layer in FIG. 17. Referring to FIGS. 17 to 21, the corresponding pixel circuit 100 is also the pixel circuit 100 shown in FIG. 2. Similarly, part of the virtual connection wire L3 is multiplexed as the voltage adjustment signal line 220, which is different from the multiplexing of the virtual connection wire L3 provided in FIGS. 6 to 14, but the film layer arrangement between the first semiconductor layer 520 and the second metal layer 560 is the same, and thus no further description is given here.

[0090] Optionally, FIG. 22 is a schematic diagram of a structure of a second pixel circuit according to an embodiment of the present application, and FIG. 23 is a timing of an embodiment of signals provided to the pixel circuit shown in FIG. 22 in one driving period. For the arrangement of the pixel circuit 100, reference can also be made to FIG. 22, and the pixel circuit 100 is exemplarily illustrated as "8T1C". The pixel circuit 100 can include a first light emitting control transistor T1, a data writing transistor T2, a driving transistor T3, a threshold compensation transistor T4, an initialization reset transistor T5, a second light emitting control transistor T6, an anode reset transistor T7, a bias transistor T8, and a storage capacitor Cst. The working process of the pixel circuit 100 is similar to that of the pixel circuit 100 corresponding to FIG. 2, and thus no further description is given here. Exemplarily, in the pixel circuit 100 of FIG. 22, the scan signal line (shown as Sp in the figure) connected to the control end of the bias transistor T8 can control the turn-on and turn-off of the bias transistor T8, and when the bias transistor T8 is turned on, the bias signal transmitted by the voltage adjustment signal line 220 (shown as the bias adjustment signal line DVH in the figure) is written to the bias transistor T8, and the second node N2 is biased and adjusted. Optionally, the types of the transistors in the pixel circuit 100 can be diverse. In addition to low-temperature polysilicon transistors, the transistors can also include oxide transistors (Indium Gallium Zinc Oxide, IGZO), which have the advantages of small leakage current, and the low-temperature polysilicon transistors have the advantages of high switching speed, high carrier mobility, and small power. Referring to FIG. 2, the pixel circuit 100 can include low-temperature polysilicon transistors, or referring to FIG. 22, the pixel circuit 100 can simultaneously include oxide transistors and low-temperature polysilicon transistors, and the types of the transistors in the pixel circuit 100 can be adaptively adjusted according to actual needs, which is not limited in the embodiments of the present application.

[0091] For example, referring to FIG. 23, in one driving period Y of the pixel circuit 100, the driving period Y includes a data writing stage Y1, a light emitting stage Y2, and a light emitting maintaining stage Y3. The data writing stage Y1 includes a non-enabling stage of the light emitting control signal Emit. The light emitting stage Y2 includes an enabling stage of the light emitting control signal Emit. The light emitting maintaining stage Y3 includes a plurality of non-enabling stages and at least one enabling stage (one enabling stage is shown in FIG. 23 as an example). The biasing level of the biasing signal line DVH in the data writing stage Y1 and the light emitting stage Y2 can be the same as or different from the biasing level of the biasing signal line DVH in the light emitting maintaining stage Y3 (shown in FIG. 23). For example, the data writing stage Y1 includes a first biasing stage Y11. In the first biasing stage Y11, the signal transmitted by the scan signal line SP includes at least one low voltage period, and the signal transmitted by the scan signal line S2N includes at least one high voltage period. In other words, in the first biasing stage Y11, at least the biasing transistor T8 and the threshold compensation transistor T4 are turned on, the biasing signal of the biasing signal line DVH is transmitted to the driving transistor T3 through the biasing transistor T8, and is further transmitted to the gate of the driving transistor T3 through the threshold compensation transistor T4. In other words, in the first biasing stage Y11, the biasing signal can be used to bias the first node N1, the second node N2, and the third node N3. The data writing stage Y1 further includes an initialization and second biasing stage Y12. In the initialization and second biasing stage Y12, the signal transmitted by the scan signal line S1N includes at least one high voltage period, and the signal transmitted by the scan signal line S2N includes at least one high voltage period. In other words, in the initialization and second biasing stage Y12, the initialization transistor T5 is turned on, and the threshold compensation transistor T4 is turned on later. The initialization reset signal line Vref1 can be used to adjust the gate of the driving transistor T3 through the initialization transistor T5, and can be used to adjust the third node N3 through the initialization transistor T5 and the threshold compensation transistor T4. The data writing stage Y1 further includes a data signal writing stage Y13. In the data signal writing stage Y13, the signal transmitted by the scan signal line S2N includes a high voltage period, and the signal transmitted by the scan signal line SP* includes at least one low voltage period. In other words, in the data signal writing stage Y13, the data writing transistor T2 and the threshold compensation transistor T4 are turned on, and the data signal Vdata can be transmitted to the gate of the driving transistor T3 through the data writing transistor T2 and the threshold compensation transistor T4.The data writing stage Y1 further comprises a third bias adjusting stage Y14, in which the signal transmitted by the scan signal line SP comprises at least one low level period, and the second node N2 can be further biased by the bias transistor T8 during the time period.

[0092] In combination with FIG. 1, FIG. 22 and FIG. 23, in the pixel circuit 100, the data writing transistor 110 comprises the data writing transistor T2, and the voltage adjusting transistor 120 can comprise the initialization reset transistor T5, the anode reset transistor T7 and the bias transistor T8. The data signal Vdata transmitted by the data signal line 210, the voltage adjusting signal line 220, i.e., the initialization reset signal line Vref1, electrically connected with the initialization reset transistor T5, the voltage adjusting signal line 220, i.e., the anode reset signal line Vref2, electrically connected with the anode reset transistor T7, and the voltage adjusting signal line 220, i.e., the bias adjusting signal line DVH, electrically connected with the bias transistor T8. In different pixel circuits 100, the number and position of the transistors can be adjusted adaptively, and the number and position of the data writing transistor 110 and the voltage adjusting transistor 120 can also be adjusted adaptively.

[0093] FIG. 24 is a schematic diagram of a film layer structure of a second pixel circuit according to an embodiment of the present application, i.e., FIG. 24 corresponds to the schematic diagram of the film layer structure of the pixel circuit 100 provided in FIG. 22. The film layer structure of the pixel circuit 100 can sequentially comprise, from the bottom to the light-emitting side of the display panel 10, a substrate 600, a buffer layer 610, a first semiconductor layer 620, a first insulating layer 630, a first metal layer 640, an interlayer insulating layer 650, a second metal layer 660, a second insulating layer 670, a second semiconductor layer 680, a third insulating layer 690, a third metal layer 6100, a fourth insulating layer 6110, a fourth metal layer 6120, a fifth insulating layer 6130, a fifth metal layer 6140, a planarization layer 6150 and an anode layer 6160. For the film layer structure of the pixel circuit 100, adaptive adjustment can be made according to actual needs, such as adding or removing part of the film layer, and any one of the above film layers can comprise at least one sub-layer, which is not limited in the embodiments of the present application.

[0094] FIG. 25 is a schematic view of a film layer structure of a third display panel according to an embodiment of the present application, FIG. 26 is a schematic view of the first semiconductor layer to the fourth metal layer in FIG. 24, FIG. 27 is a schematic view of the fourth metal layer to the fifth metal layer in FIG. 24, FIG. 28 is a schematic view of the first semiconductor layer in FIG. 24, FIG. 29 is a schematic view of the first metal layer in FIG. 24, FIG. 30 is a schematic view of the second metal layer in FIG. 24, FIG. 31 is a schematic view of the second semiconductor layer in FIG. 24, FIG. 32 is a schematic view of the third metal layer in FIG. 24, FIG. 33 is a schematic view of the fourth metal layer in FIG. 24, FIG. 34 is a schematic view of the fifth metal layer in FIG. 24, and FIG. 35 is a schematic view of an anode layer in another display panel according to an embodiment of the present application. If the pixel circuit 100 in the display panel 10 is the pixel circuit 100 shown in FIG. 22, the film layer structure relationship of the display panel 10 can be shown with reference to FIG. 25, and FIGS. 26 to 34 are used to show different film layers in FIG. 25 from bottom to top.

[0095] Referring to FIGS. 26 to 35, in the film layer structure corresponding to the pixel circuit 100, referring to FIGS. 33 and 34, part of the virtual connection wire L3 is located in the film layer where the fourth metal layer 6120 is located (see the virtual connection wire L3 in FIG. 33), and part of the virtual connection wire L3 is located in the film layer where the fifth metal layer 6140 is located (see the virtual connection wire L3 in FIG. 34).

[0096] Part of the voltage adjustment signal line 220 electrically connected to the bias transistor T8 is located in the film layer where the second metal layer 660 is located (see the bias adjustment signal line DVH in FIG. 30). Part of the voltage adjustment signal line 220 electrically connected to the bias transistor T8 is also located in the film layer where the fifth metal layer 6140 is located (see the bias adjustment signal line DVH in FIG. 34), and at this time, the virtual connection wire L3 can be multiplexed as the bias adjustment signal line DVH, that is, the voltage adjustment signal line 220 includes the virtual connection wire L3. Part of the voltage adjustment signal line 220 electrically connected to the anode reset transistor T7 is located in the film layer where the third metal layer 6100 is located (see the anode reset signal line Vref2 in FIG. 32). Part of the voltage adjustment signal line 220 electrically connected to the anode reset transistor T7 is also located in the film layer where the fifth metal layer 6140 is located (see the anode reset signal line Vref2 in FIG. 34), and at this time, the virtual connection wire L3 can be multiplexed as the anode reset signal line Vref2, that is, the voltage adjustment signal line 220 includes the virtual connection wire L3.

[0097] FIG. 36 is a structural schematic diagram of a third metal layer in the related art, FIG. 37 is a structural schematic diagram of a fourth metal layer in the related art, FIG. 38 is a structural schematic diagram of a fifth metal layer in the related art, and in FIG. 38, the dummy connection wire L3 (for example, L31) is not multiplexed as the bias adjustment signal line DVH and the partial anode reset signal line Vref2, that is, the voltage adjustment signal line 220 does not include the dummy connection wire L3. Compared with the embodiments of the present application, by multiplexing the dummy connection wire L3 which does not transmit data signals as the voltage adjustment signal line 220, the utilization rate of the wires is improved.

[0098] Optionally, FIG. 39 is a structural schematic diagram of a third pixel circuit provided by the embodiments of the present application, and the pixel circuit 100 is exemplified as “8T1C”. The pixel circuit 100 can include a first light emitting control transistor T1, a data writing transistor T2, a driving transistor T3, a threshold compensation transistor T4, an initialization reset transistor T5, a second light emitting control transistor T6, an anode reset transistor T7, a bias transistor T8, and a storage capacitor Cst. The working process of the pixel circuit 100 is similar to the working process of the pixel circuit 100 corresponding to FIG. 22, and is not repeatedly described here. Meanwhile, the working timing of the pixel circuit 100 is similar to the working timing of the pixel circuit 100 corresponding to FIG. 23, and is not repeatedly described here.

[0099] FIG. 40 is a film layer structure schematic diagram of a fourth display panel provided by the embodiments of the present application, FIG. 41 is a structural schematic diagram of the first semiconductor layer to the fourth metal layer in FIG. 40, FIG. 42 is a structural schematic diagram of the fourth metal layer to the fifth metal layer in FIG. 40, FIG. 43 is a structural schematic diagram of the first semiconductor layer in FIG. 40, FIG. 44 is a structural schematic diagram of the first metal layer in FIG. 40, FIG. 45 is a structural schematic diagram of the second metal layer in FIG. 40, FIG. 46 is a structural schematic diagram of the fourth metal layer in FIG. 40, FIG. 47 is a structural schematic diagram of the fourth metal layer in FIG. 40, and FIG. 48 is a structural schematic diagram of an anode layer in another display panel provided by the embodiments of the present application. If the pixel circuit 100 in the display panel 10 is the pixel circuit 100 shown in FIG. 39, the film layer structure relationship of the display panel 10 can be shown with reference to FIG. 40, and FIGS. 41 to 47 are used to show the different film layers in FIG. 40 from bottom to top.

[0100] Referring to FIGS. 41-48, in the film layer structure corresponding to the pixel circuit 100, referring to FIGS. 46 and 47, part of the virtual connection wire L3 is located in the film layer where the fourth metal layer 580 is located (see the virtual connection wire L3 in FIG. 46), and part of the virtual connection wire L3 is located in the film layer where the fifth metal layer 5100 is located (see the virtual connection wire L3 in FIG. 47). Part of the voltage adjustment signal line 220 electrically connected to the bias transistor T8 is located in the film layer where the second metal layer 560 is located (see the bias adjustment signal line DVH in FIG. 45). Part of the voltage adjustment signal line 220 electrically connected to the bias transistor T8 is also located in the film layer where the fifth metal layer 5100 is located (see the bias adjustment signal line DVH in FIG. 47), at which time the virtual connection wire L3 can be multiplexed as the bias adjustment signal line DVH, that is, the voltage adjustment signal line 220 includes the virtual connection wire L3. Part of the voltage adjustment signal line 220 electrically connected to the anode reset transistor T7 is located in the film layer where the second metal layer 560 is located (see the anode reset signal line Vref2 in FIG. 45). Part of the voltage adjustment signal line 220 electrically connected to the anode reset transistor T7 is located in the film layer where the fifth metal layer 5100 is located (see the anode reset signal line Vref2 in FIG. 47), at which time the virtual connection wire L3 can be multiplexed as the anode reset signal line Vref2, that is, the voltage adjustment signal line 220 includes the virtual connection wire L3.

[0101] FIG. 49 is a structural schematic diagram of a fourth metal layer in the related art, and FIG. 50 is a structural schematic diagram of a fifth metal layer in the related art. In FIG. 50, part of the bias adjustment signal line DVH and part of the anode reset signal line Vref2 are not disposed in the film layer where the fifth metal layer 5100 is located, that is, the voltage adjustment signal line 220 does not include the virtual connection wire L3. Instead, part of the bias adjustment signal line DVH needs to be disposed in another metal layer, that is, referring to FIG. 49, part of the bias adjustment signal line DVH is located in the film layer where the fourth metal layer 580 is located. Similarly, referring to FIG. 49, part of the anode reset signal line Vref2 is located in the film layer where the fourth metal layer 580 is located. Therefore, in combination with FIGS. 47 and 50, the virtual connection wire L3 that does not transmit data signals is multiplexed as the voltage adjustment signal line 220 in the embodiments of the present application, thereby improving the utilization rate of the wire. In combination with FIGS. 46 and 49, the wire originally located at the fourth metal layer 580 can be moved to the fifth metal layer 5100 in the embodiments of the present application, and thus the voltage adjustment signal line 220 at the fourth metal layer 580 can be removed, thereby improving the wiring space of the film layer where the voltage adjustment signal line 220 of the display panel 10 is disposed, and also being beneficial to improving the yield and reducing the process preparation cost of the display panel 10.

[0102] FIG. 51 is a schematic view of a film layer structure of a fifth display panel according to an embodiment of the present application, FIG. 52 is a schematic view of a structure of a first semiconductor layer to a fourth metal layer in FIG. 51, FIG. 53 is a schematic view of a structure of the fourth metal layer to a fifth metal layer in FIG. 51, FIG. 54 is a schematic view of a structure of the fourth metal layer in FIG. 51, and FIG. 55 is a schematic view of a structure of the fifth metal layer in FIG. 51. Referring to FIGS. 51 to 55, the corresponding pixel circuit 100 is also the pixel circuit 100 shown in FIG. 39. Similarly, part of the virtual connection wire L3 is multiplexed as the voltage adjustment signal line 220. The multiplexing of the virtual connection wire L3 in FIGS. 51 to 55 is different from that in FIGS. 40 to 48, but the film layer arrangement between the first semiconductor layer 520 and the second metal layer 560 is the same, and thus is not described here.

[0103] In summary, the display panel provided by the embodiments of the present application sets part of the voltage adjustment signal lines to include virtual connection wires. In this way, the utilization rate of the wires in the display panel can be improved, the pixel space of the display panel can be improved, the yield can be improved, the process preparation cost of the display panel can be reduced, and the display effect of the display panel can be improved.

[0104] With reference to FIGS. 4 to 13, 17 to 34, 40 to 47, 51 to 55, the data connection wire L0 includes a first data connection line segment L1 extending along the first direction X; the virtual connection wire L3 includes a first virtual connection line segment L31 extending along the first direction X, and the first virtual connection line segment L31 is arranged in the same layer as and insulated from the first data connection line segment L1; and the voltage adjustment signal line 220 includes a first voltage adjustment signal line 221, and the first virtual connection line segment L31 is multiplexed as the first voltage adjustment signal line 221.

[0105] Referring to FIG. 4, the data connection wire L0 includes the first data connection line segment L1 extending along the first direction X and the second data connection line segment L2 extending along the second direction Y. The first data connection line segment L1 and the second data connection line segment L2 can be arranged in different film layers and electrically connected by a via.

[0106] The first virtual connection line segment L31 and the second virtual connection line segment L32 are insulated from the first data connection line segment L1 and the second data connection line segment L2, respectively. The virtual connection line L3 can ensure the uniformity of the lines and does not affect the normal transmission of signals in the data connection line L0. For example, as shown in FIGS. 6, 10, 9, 17-21, 40, 46, 47, 51-55, the first virtual connection line segment L31 can be located at the film layer of the fifth metal layer 5100, and the second virtual connection line segment L32 can be located at the film layer of the fourth metal layer 580. As shown in FIGS. 25, 33, and 34, the first virtual connection line segment L31 can be located at the film layer of the fifth metal layer 6140, and the second virtual connection line segment L32 can be located at the film layer of the fourth metal layer 6120.

[0107] For example, the voltage adjustment signal line 220 includes the first voltage adjustment signal line 221, and the first virtual connection line segment L31 is multiplexed as the first voltage adjustment signal line 221. It can be understood that the original first voltage adjustment signal line 221 in the voltage adjustment signal line 220 can be removed, and the first virtual connection line segment L31 is used as the first voltage adjustment signal line 221. In this way, the original first voltage adjustment signal line 221 can be removed, which is beneficial to improve the pixel space of the display panel. The voltage adjustment signal transmitted in the original first voltage adjustment signal line 221 is transmitted through the first virtual connection line segment L31, which does not affect the normal transmission of signals in the display panel 10 and improves the utilization rate of the lines in the display panel 10.

[0108] For example, as shown in FIGS. 6, 12, 13, 17-21, the pixel circuit 100 includes the virtual connection line L0, the original first voltage adjustment signal line 221 located at the film layer of the fourth metal layer 580 is removed, the first voltage adjustment signal line 221 is arranged at the film layer of the fifth metal layer 5100, and further, the first virtual connection line segment L31 is multiplexed as the first voltage adjustment signal line 221. For example, one of the first virtual connection line segments L31 is multiplexed as the first voltage adjustment signal line 221 (for example, the initialization reset signal line Vref1 in FIG. 13), and the other first virtual connection line segment L31 is multiplexed as the first voltage adjustment signal line 221 (for example, the anode reset signal line Vref2 in FIG. 13).

[0109] For example, referring to FIGS. 25, 33 and 34, the pixel circuit 100 includes the data connection wire L0, and the first voltage adjustment signal line 221 originally arranged at the film layer of the fifth metal layer 6140 is removed, and the first virtual connection wire segment L31 is multiplexed as the first voltage adjustment signal line 221. For example, one of the first virtual connection wire segments L31 is multiplexed as the first voltage adjustment signal line 221 (for example, the bias adjustment signal line DVH in FIG. 34), and the other first virtual connection wire segment L31 is multiplexed as the first voltage adjustment signal line 221 (for example, the anode reset signal line Vref2 in FIG. 34).

[0110] For example, referring to FIGS. 40, 46, 47, 51 to 55, the pixel circuit 100 includes the virtual connection wire L0, and the first voltage adjustment signal line 221 originally arranged at the film layer of the fourth metal layer 580 is removed, and the first voltage adjustment signal line 221 is arranged at the film layer of the fifth metal layer 5100, and further, the first virtual connection wire segment L31 is multiplexed as the first voltage adjustment signal line 221. For example, one of the first virtual connection wire segments L31 is multiplexed as the first voltage adjustment signal line 221 (for example, the bias adjustment signal line DVH in FIG. 47), and the other first virtual connection wire segment L31 is multiplexed as the first voltage adjustment signal line 221 (for example, the anode reset signal line Vref2 in FIG. 47).

[0111] Continuing to refer to FIGS. 6 to 14, the display panel 10 further includes a plurality of pixel circuit groups 100A, each of which includes two pixel circuits 100 arranged adjacent to each other along the second direction Y; along the second direction Y, the first virtual connection wire segment L31 is located between two data signal lines 210 electrically connected to the two pixel circuits 100 in the same pixel circuit group 100A.

[0112] For example, referring to FIG. 13, the pixel circuit group 100A includes two pixel circuits 100 arranged adjacent to each other along the second direction Y, and it can be understood that the plurality of pixel circuits 100 in the display panel 10 are divided by the pixel circuit group 100A. For the sake of clarity of the division of the pixel circuit group 100A, only FIG. 13 is shown, and the pixel circuit group 100A is divided in the same area as in FIGS. 6 to 12, and for the sake of clarity of the picture, not all are shown. Referring to FIGS. 6 and 13, the pixel circuit 100 is electrically connected to the data signal line 210, and the electrical connection relationship between the data signal line 210 and the pixel circuit 100 is shown in the form of overlapping, and the arrangement position of the data signal line 210 is adjusted based on the type of the pixel circuit 100, which is not described here.

[0113] For example, referring to FIG. 13, in the pixel circuit group 100A, the first virtual connection line segment L31 is located between two data signal lines 210 electrically connected to two pixel circuits 100 in the same pixel circuit group 100A in the second direction Y. It can be understood that the first virtual connection line segment L31 is located between the two data signal lines 210 in the same direction as the arrangement direction and the wiring direction of the data signal lines 210. Alternatively, refer to FIGS. 21, 34, 47, and 55. When the first virtual connection line segment L31 is multiplexed as the first voltage adjustment signal line 221, the first virtual connection line segment L31 can reduce the interference of the electrical signal coupling between the two data signal lines 210 on both sides, thereby ensuring the reliability of the signal transmitted by the data signal line 210 to the pixel circuit 100, and further ensuring the display effect of the display panel 10.

[0114] Alternatively, referring to FIG. 11, the display panel 10 further includes a shielding structure 400, which can be located between the signal line where the signal jumps and the first node N1, and the shielding structure 400 can be electrically connected to a fixed potential, so that the jump of other signals can be avoided to affect the potential of the first node N1, the potential of the first node N1 is ensured to be stable, and the pixel circuit is ensured to work normally. For example, referring to FIG. 11, the shielding structure 400 is located in the film layer where the second metal layer 560 is located. In other types of pixel circuits 100, the shielding structure 400 can also be located in the film layer where the top gate of the oxide transistor is located, and the film layer of the shielding structure is not limited in the embodiments of the present application.

[0115] Referring to FIGS. 6-14, 17-21, 25-35, 40-48, 51-55, the first virtual connection line segment L31 is arranged in the same layer as the data signal line 210.

[0116] For example, the data signal line 210 extends in the first direction X in the display area AA, and the first virtual connection line segment L31 also extends in the first direction X, that is, the wiring arrangement trend of the data signal line 210 and the first virtual connection line segment L31 is similar, and then the two are placed in the same film layer, and there is no need to arrange another film layer for the first virtual connection line segment L31, so that the number of film layers of the display panel 10 can be reduced. For example, referring to FIGS. 6-14, 17-21, 40-48, 51-55, the first virtual connection line segment L31 and the data signal line 210 are arranged in the film layer where the fifth metal layer 5100 is located, and referring to FIGS. 25-35, the first virtual connection line segment L31 and the data signal line 210 are arranged in the film layer where the fifth metal layer 6140 is located. Therefore, under the premise of ensuring the display effect of the display panel 10, the process preparation cost and process preparation difficulty of the display panel 10 are reduced, which is beneficial to realize the thin design of the display panel 10.

[0117] With reference to FIGS. 6-14, 25-35, 40-48, the voltage adjustment signal line 220 further includes a second voltage adjustment signal line 222 extending at least partially along the second direction Y, and the second voltage adjustment signal line 222 is electrically connected with the first voltage adjustment signal line 221.

[0118] The voltage adjustment signal line 220 further includes a second voltage adjustment signal line 222 extending along the second direction Y, and the first voltage adjustment signal line 221 and the second voltage adjustment signal line 222 intersect in the extending directions. The film layer position of the first voltage adjustment signal line 221 has diversity, which can be adaptively adjusted according to different pixel circuits 100. Similarly, the film layer position of the second voltage adjustment signal line 222 has diversity, which can be adaptively adjusted according to different pixel circuits 100.

[0119] For example, the second voltage adjustment signal line 222 is electrically connected with the first voltage adjustment signal line 221, and the first voltage adjustment signal line 221 and the second voltage adjustment signal line 222 can be provided in the form of a mesh-shaped trace, which improves the setting flexibility of the voltage adjustment signal line 220 and provides more possibilities to multiplex part of the voltage adjustment signal line 220 as a virtual connection trace L0.

[0120] With reference to FIGS. 6, 13, 40 and 47, the display panel 10 further includes a via connection portion 700 which is in the same layer and electrically connected with the first virtual connection line segment L31; along the second direction Y, the via connection portion 700 is located at least one side of the first virtual connection line segment L31 connected therewith; and the second voltage adjustment signal line 222 is electrically connected with the via connection portion 700 through a via.

[0121] The first virtual connection line segment L31 is multiplexed as the first voltage adjustment signal line 221, and the first voltage adjustment signal line 221 and the second voltage adjustment signal line 222 can be a mesh structure. For example, with reference to FIGS. 6 and 13, or with reference to FIGS. 40 and 47, the display panel 10 further includes a via connection portion 700 which is provided to electrically connect the first virtual connection line segment L31 and the second voltage adjustment signal line 222, i.e., to electrically connect the first voltage adjustment signal line 221 and the second voltage adjustment signal line 222 through the via connection portion 700 to realize signal transmission.

[0122] Exemplarily, referring to FIG. 13 or FIG. 47, the via connection part 700 is located at the film layer where the fifth metal layer 5100 is located, and is in the same layer as the first virtual connection line segment L31. The via connection part 700 is located at least one side of the first virtual connection line segment L31 to which the via connection part 700 is connected, so as to ensure the electrical connection relationship between the via connection part 700 and the first virtual connection line segment L31.

[0123] Continuing to refer to FIG. 4, FIG. 6 to FIG. 14, FIG. 17 to FIG. 21, FIG. 25 to FIG. 35, FIG. 40 to FIG. 48, FIG. 51 to FIG. 55, the data connection wire L0 further includes a second data connection line segment L2 extending along the second direction Y, and the second data connection line segment L2 is electrically connected with the first data connection line segment L1 and the data signal line 210 respectively; the virtual connection wire L3 further includes a second virtual connection line segment L32 extending along the second direction Y, and the second virtual connection line segment L32 is in the same layer as the second data connection line segment L2 and is insulated; and the second virtual connection line segment L32 is electrically connected with the fixed potential signal terminal.

[0124] Referring to FIG. 4, the fan-out wire S0 is electrically connected with the data signal line 210 through the second data connection line segment L2 extending along the second direction Y and the first data connection line segment L1 extending along the first direction X, so as to ensure that the pixel circuit 100 in the second display area AA2 can obtain the data signal. Exemplarily, the first virtual connection line segment L31 and the first data connection line segment L1 have the same extension direction, and the second virtual connection line segment L32 and the second data connection line segment L2 have the same extension direction, but the virtual connection wire L3 and the data connection wire L0 are insulated, so the first virtual connection line segment L31 and the first data connection line segment L1 are insulated, and the second virtual connection line segment L32 and the second data connection line segment L2 are insulated.

[0125] The first virtual connection line segment L31 can be reused as a first voltage adjustment signal line, and the second virtual connection line segment L32 can be electrically connected with the fixed potential signal terminal, so that the second virtual connection line segment L32 is connected with the fixed potential signal. In this case, the first virtual connection line segment L31 is not electrically connected with the second virtual connection line segment L32, and the two transmit different signals. The second virtual connection line segment L32 can reduce the loss in the transmission process of the fixed potential signal, so as to ensure the display effect of the display panel 10.

[0126] Optionally, the fixed potential signal terminal includes a voltage adjustment signal terminal and / or a power signal terminal.

[0127] Exemplarily, the fixed potential signal terminal accessed by the second virtual connection line segment L32 can be a voltage adjustment signal terminal or a power signal terminal. For example, the second virtual connection line segment L32 accesses a positive power signal PVDD, or the second virtual connection line segment L32 accesses a negative power signal PVEE, etc. Based on the type of the fixed potential signal terminal, adaptive adjustment can be made according to different display panels 10.

[0128] With continuous reference to FIGS. 17-21, 25-34, 51-55, the display panel 10 further includes a transition portion 800, at least part of the transition portion 800 extends along the second direction Y and is electrically connected with the second voltage adjustment signal line 222 and the first virtual connection line segment L31, respectively; the film layer where the transition portion 800 is located is between the film layer where the second voltage adjustment signal line 222 is located and the film layer where the first virtual connection line segment L31 is located.

[0129] In the case where the first virtual connection line segment L31 is multiplexed as the first voltage adjustment signal line 221, when the first voltage adjustment signal line 221 and the second voltage adjustment signal line 222 are electrically connected, i.e., the voltage adjustment signal line 220 is in a mesh shape, the display panel 10 includes the transition portion 800, the second voltage adjustment signal line 222 and the first virtual connection line segment L31 can be kept electrically connected through the transition portion 800, thereby realizing the electrical connection relationship between the first voltage adjustment signal line 221 and the second voltage adjustment signal line 222.

[0130] Exemplarily, the transition portion 800 serves as a “bridge” between the second voltage adjustment signal line 222 and the first virtual connection line segment L31, and the two are electrically connected through the transition portion 800, so the film layer where the transition portion 800 is located is between the film layer where the second voltage adjustment signal line 222 is located and the film layer where the first virtual connection line segment L31 is located.

[0131] Exemplarily, with reference to FIGS. 17-21, the second voltage adjustment signal line 222 is located at the film layer where the second metal layer 560 is located, and the first virtual connection line segment L31 is located at the film layer where the fifth metal layer 5100 is located, then the transition portion 800 can be located at the film layer where the fourth metal layer 580 is located. With reference to FIGS. 25-34, the second voltage adjustment signal line 222 is located at the film layer where the second metal layer 660 is located, or the second voltage adjustment signal line 222 is located at the film layer where the third metal layer 6100 is located, and the first virtual connection line segment L31 is located at the film layer where the fifth metal layer 6140 is located, then the transition portion 800 can be located at the film layer where the fourth metal layer 6120 is located. As shown in FIGS. 51-55, the second voltage adjustment signal line 222 is located at the film layer where the second metal layer 560 is located, and the first virtual connection line segment L31 is located at the film layer where the fifth metal layer 5100 is located, then the transition portion 800 can be located at the film layer where the fourth metal layer 580 is located.

[0132] With reference to FIGS. 17-21, 25-34, 51-55, the adapter 800 includes at least a first adapter sub-portion 810 and a second adapter sub-portion 820, which are arranged alternately along the second direction Y; the voltage adjustment transistor 120 includes at least two voltage adjustment transistors, and the first voltage adjustment signal line 221 includes at least a first sub-voltage adjustment signal line and a second sub-voltage adjustment signal line, which transmit different voltage adjustment signals and are arranged alternately along the second direction Y; the first sub-voltage adjustment signal line is electrically connected to the first adapter sub-portion 810, and the second sub-voltage adjustment signal line is electrically connected to the second adapter sub-portion 820.

[0133] For example, with reference to FIGS. 2, 22 and 39, the voltage adjustment transistor 120 can include at least two voltage adjustment transistors. For example, in FIG. 2, the voltage adjustment transistor 120 includes an initialization reset transistor T5 and an anode reset transistor T7, wherein the first voltage adjustment signal line 221 includes a first sub-voltage adjustment signal line (an initialization reset signal line Vref1) electrically connected to the initialization reset transistor T5, and a second sub-voltage adjustment signal line (an anode reset signal line Vref2) electrically connected to the anode reset transistor T7. For example, in FIGS. 22 and 39, the voltage adjustment transistor 120 includes an initialization reset transistor T5, an anode reset transistor T7 and a bias transistor T8, wherein the first voltage adjustment signal line 221 includes a first sub-voltage adjustment signal line (a bias adjustment signal line DVH) electrically connected to the bias transistor T8, and a second sub-voltage adjustment signal line (an anode reset signal line Vref2) electrically connected to the anode reset transistor T7.

[0134] For example, the adapter 800 includes a first adapter sub-portion 810 and a second adapter sub-portion 820, wherein the first adapter sub-portion 810 can be used to electrically connect the first sub-voltage adjustment signal line to the corresponding second voltage adjustment signal line 222, and the second adapter sub-portion 820 can be used to electrically connect the second sub-voltage adjustment signal line to the corresponding second voltage adjustment signal line 222.

[0135] For example, referring to FIGS. 20 and 21, and in combination with FIG. 11, taking the initialization reset signal line vref1 provided to the initialization reset transistor T5 as an example, the corresponding second voltage adjustment signal line 222 in FIG. 11 is electrically connected to the corresponding first virtual connection line segment L31 in FIG. 21 through the first adapter sub-portion 810 in FIG. 20; taking the anode reset signal line Vref2 provided to the anode reset transistor T7 as an example, the corresponding second voltage adjustment signal line 222 in FIG. 11 is electrically connected to the corresponding first virtual connection line segment L31 in FIG. 21 through the second adapter sub-portion 820 in FIG. 20.

[0136] For example, referring to FIGS. 33 and 34, and in combination with FIGS. 30 and 32, taking the bias condition signal line DVH provided to the bias transistor T8 as an example, the corresponding second voltage adjustment signal line 222 in FIG. 30 is electrically connected to the corresponding first virtual connection line segment L31 in FIG. 34 through the first adapter sub-portion 810 in FIG. 33; taking the anode reset signal line Vref2 provided to the anode reset transistor T7 as an example, the corresponding second voltage adjustment signal line 222 in FIG. 32 is electrically connected to the corresponding first virtual connection line segment L31 in FIG. 34 through the second adapter sub-portion 820 in FIG. 33.

[0137] For example, referring to FIGS. 51 to 55, and in combination with FIG. 54, taking the bias condition signal line DVH provided to the bias transistor T8 as an example, the corresponding second voltage adjustment signal line 222 is electrically connected to the corresponding first virtual connection line segment L31 in FIG. 55 through the first adapter sub-portion 810 in FIG. 54; taking the anode reset signal line Vref provided to the anode reset transistor T7 as an example, the corresponding second voltage adjustment signal line 222 is electrically connected to the corresponding first virtual connection line segment L31 in FIG. 55 through the second adapter sub-portion 820 in FIG. 54.

[0138] Continuing to refer to FIGS. 17 to 21, 33 to 34, and 54 to 55, the data connection trace L1 further includes a second data connection line segment L2 extending along the second direction Y, the second data connection line segment L2 being electrically connected to the first data connection line segment L1 and the data signal line 210, respectively; the virtual connection trace L0 further includes a second virtual connection line segment L32 extending along the second direction Y, the second virtual connection line segment L32 being insulatively arranged with the second data connection line segment L2 in the same layer; the second virtual connection line segment L32 is multiplexed as the adapter portion 800.

[0139] Referring to FIG. 4, the fan-out wire S0 is electrically connected with the data signal line 210 through the second data connection line segment L2 extending along the second direction Y and the first data connection line segment L1 extending along the first direction X, so as to ensure that the pixel circuit 100 in the second display area AA2 can obtain the data signal. Exemplarily, the first virtual connection line segment L31 has the same extension direction as the first data connection line segment L1, and the second virtual connection line segment L32 has the same extension direction as the second data connection line segment L2, but the virtual connection wire L3 and the data connection wire L0 are insulatively arranged, so that the first virtual connection line segment L31 and the first data connection line segment L1 are insulatively arranged, and the second virtual connection line segment L32 and the second data connection line segment L2 are insulatively arranged.

[0140] In the case, the first virtual connection line segment L31 can be reused as the first voltage adjustment signal line, which does not affect the normal transmission of signals in the display panel 10, improves the utilization rate of wires in the display panel 10, reduces the process preparation cost and process preparation difficulty of the display panel 10, and is beneficial to the thin design of the display panel 10.

[0141] Exemplarily, referring to FIGS. 17-21 and 54-55, the adapter 800 in the corresponding pixel circuit 100 is located at the film layer where the fourth metal layer 580 is located. Referring to FIGS. 33-34, the adapter 800 in the corresponding pixel circuit 100 is located at the film layer where the fourth metal layer 6120 is located.

[0142] Continuing to refer to FIGS. 6-13, 25-34 and 40-47, the second voltage adjustment signal line 222 includes a first voltage adjustment sub-portion 222a; the first voltage adjustment sub-portion 222a extends along the second direction Y, and at least two pixel circuits 100 arranged along the second direction Y share the same first voltage adjustment sub-portion 222a.

[0143] Exemplarily, the second voltage adjustment signal line 222 includes the first voltage adjustment sub-portion 222a, wherein the first voltage adjustment sub-portion 222a extends along the second direction Y and is electrically connected with a plurality of pixel circuits 100. It can be understood that the first voltage adjustment sub-portion 222a is continuously arranged at the same film layer and penetrates the display area of the display panel 10, i.e., the first voltage adjustment sub-portion 222a is in an unbroken state at the film layer where it is located, and the extension length along the second direction Y can be equivalent to the length of the display area of the display panel 10.

[0144] For example, referring to FIGS. 6-14, and specifically to FIG. 11, in the pixel circuit 100, the first voltage adjustment subpart 222a can include an initialization reset signal line Vref1 and an anode reset signal line Vref2, and in the film layer shown in FIG. 11, the initialization reset signal line Vref1 and the anode reset signal line Vref2 both extend along the second direction Y and continuously pass through the display area of the display panel 10, and thus the first voltage adjustment subpart 222a can be the initialization reset signal line Vref1 and the anode reset signal line Vref2 under the film layer.

[0145] For example, referring to FIGS. 25-35, and specifically to FIG. 30, in the pixel circuit 100, the first voltage adjustment subpart 222a can include an initialization reset signal line Vref1 and a bias adjustment signal line DVH, and in the film layer shown in FIG. 30, the initialization reset signal line Vref1 and the bias adjustment signal line DVH both extend along the second direction Y and continuously pass through the display area of the display panel 10, and thus the first voltage adjustment subpart 222a can be the initialization reset signal line Vref1 and the bias adjustment signal line DVH under the film layer.

[0146] For example, referring to FIGS. 40-48, and specifically to FIG. 45, in the pixel circuit 100, the first voltage adjustment subpart 222a can include an initialization reset signal line Vref1 and a bias adjustment signal line DVH, and in the film layer shown in FIG. 45, the initialization reset signal line Vref1 and the bias adjustment signal line DVH both extend along the second direction Y and continuously pass through the display area of the display panel 10, and thus the first voltage adjustment subpart 222a can be the initialization reset signal line Vref1 and the bias adjustment signal line DVH under the film layer.

[0147] Continuing to refer to FIGS. 2-14, 17-21, 39-48, 51-55, the pixel circuit 100 includes at least one transistor including a first active layer poly, and the pixel circuit 100 further includes a storage capacitor Cst including a first plate M1 and a second plate MC oppositely arranged, the second plate MC being located on a side of the first plate M1 away from the first active layer poly, and the display panel 10 further includes a first semiconductor layer 520, a first metal layer 540, and a second metal layer 560, the first active layer poly being located on the first semiconductor layer 520, the first plate M1 being located on the first metal layer 540, and the second plate MC being located on the second metal layer 560, and the first voltage adjustment subpart 222a is located in at least one of the first semiconductor layer 520, the first metal layer 540, or the second metal layer 560.

[0148] Exemplarily, referring to FIG. 2 and FIG. 39, the transistors in the pixel circuit 100 can include low-temperature polysilicon transistors. Referring to FIG. 5, along the direction away from the substrate, the film layer structure included in the pixel circuit 100 can be the substrate 500, the buffer layer 510, the first semiconductor layer 520, the first insulating layer 530, the first metal layer 540, the interlayer insulating layer 550, the second metal layer 560, the second insulating layer 570, the fourth metal layer 580, the third insulating layer 590, the fifth metal layer 5100, the planarization layer 5110, and the anode layer 5120. The pixel circuit 100 includes a storage capacitor Cst, and the storage capacitor Cst includes a corresponding first plate M1 and a second plate MC. The first active layer poly is located at the film layer of the first semiconductor layer 520, the first plate M1 is located at the film layer of the first metal layer 540, and the second plate MC is located at the film layer of the second metal layer 560.

[0149] Exemplarily, in the pixel circuit 100 described above, the first voltage adjustment part 222a can be located in the same layer as at least one of the first semiconductor layer 520, the first metal layer 540, or the second metal layer 560. In this way, the first voltage adjustment part 222a can be in the same layer as one of the above-mentioned film layers, or can be in the same layer as at least two of the above-mentioned film layers, and can be flexibly adjusted based on the film layer position of the first voltage adjustment part 222a. Moreover, when the first voltage adjustment part 222a is arranged in the same layer as at least two of the first active layer poly, the first plate M1, or the second plate MC, the first voltage adjustment part 222a arranged in each film layer can continuously pass through the display area of the display panel 10 along the second direction Y.

[0150] Exemplarily, the first voltage adjustment part 222a can be located in the film layer of the second metal layer 560, i.e., the first voltage adjustment part 222a is arranged in the same layer as the second plate MC. Based on the film layer position of the arrangement of the first voltage adjustment part 222a, adaptive adjustment can be made according to actual conditions, which is not limited by the embodiments of the present application. In this way, the arrangement of the first voltage adjustment part 222a can be flexible.

[0151] With reference to FIGS. 24-35, the pixel circuit 100 includes at least one first type transistor and at least one second type transistor, the first type transistor including a first active layer poly and a first gate M1, the second type transistor including a second active layer igzo, a second top gate MG, and a second bottom gate MC, the first gate M1 being located on a side of the first active layer poly close to the second active layer igzo or on a side of the first active layer poly away from the second active layer igzo, the second top gate MG being located on a side of the second active layer igzo away from the first active layer poly, and the second bottom gate MC being located on a side of the second active layer igzo close to the first active layer poly; the display panel 10 further includes a first semiconductor layer 620, a first metal layer 640, a second metal layer 660, a second semiconductor layer 680, and a third metal layer 6100; the first active layer poly is located on the first semiconductor layer 620, the first gate M1 is located on the first metal layer 640, the second bottom gate MC is located on the second metal layer 660, the second active layer igzo is located on the second semiconductor layer 680, and the second top gate MG is located on the third metal layer 6100; the first voltage adjustment subunit 222a is located on at least one of the first semiconductor layer 620, the first metal layer 640, the second metal layer 660, the second semiconductor layer 680, or the third metal layer 6100.

[0152] For example, the pixel circuit 100 includes the first type transistor and the second type transistor, the first type transistor including the first active layer poly, and the first active layer poly including a silicon semiconductor portion, and the first type transistor can be understood as a low-temperature polysilicon transistor. The second type transistor includes the second active layer igzo, and the second active layer igzo includes an oxide semiconductor portion, and the second type transistor can be understood as an oxide transistor. Further, the pixel circuit 100 includes both the low-temperature polysilicon transistor and the oxide transistor, and the pixel circuit 100 has the advantages of small leakage current of the oxide transistor, and also has the advantages of high switching speed, high carrier mobility, and small power of the low-temperature polysilicon transistor.

[0153] Exemplarily, the first type transistor includes the first active layer poly and the first gate M1, the second type transistor includes the second active layer igzo, the second top gate MG and the second bottom gate MC, and for the film layers, the first gate M1 is located on one side of the first active layer poly close to the second active layer igzo or on one side of the first active layer poly away from the second active layer igzo, the second top gate MG is located on one side of the second active layer igzo away from the first active layer poly, and the second bottom gate MC is located on one side of the second active layer igzo close to the first active layer poly. The film layer where the first gate M1 is located is located on the film layer where the first metal layer 640 is located, the film layer where the second bottom gate MC is located is located on the film layer where the second metal layer 660 is located, and the film layer where the second top gate MG is located is located on the film layer where the third metal layer 6100 is located. At this time, the first gate M1 is located on one side of the first active layer poly away from the substrate 600, and the first type transistor is a transistor in a top gate structure. For the first gate M1, it can also be located on one side of the first active layer poly away from the second active layer igzo. At this time, the first type transistor is a transistor in a bottom gate structure, and the present embodiment does not limit the positional relationship between the first gate and the first active layer.

[0154] Exemplarily, referring to FIG. 24, the film layer structure of the pixel circuit 100 can be, from bottom to the light-emitting side of the display panel 10, the substrate 600, the buffer layer 610, the first semiconductor layer 620, the first insulating layer 630, the first metal layer 640, the interlayer insulating layer 650, the second metal layer 660, the second insulating layer 670, the second semiconductor layer 680, the third insulating layer 690, the third metal layer 6100, the fourth insulating layer 6110, the fourth metal layer 6120, the fifth insulating layer 6130, the fifth metal layer 6140, the planarization layer 6150 and the anode layer 6160. In the above pixel circuit 100, the first voltage adjustment subpart 222a can be located on at least one of the first semiconductor layer 620, the first metal layer 640, the second metal layer 660, the second semiconductor layer 680 or the third metal layer 6100.

[0155] Exemplarily, referring to FIG. 30, the first voltage adjustment subpart 222a is located on the film layer where the second metal layer 660 is located, that is, the first voltage adjustment subpart 222a is arranged in the same layer as the second bottom gate MC. Based on the film layer position of the arrangement of the first voltage adjustment subpart 222a, the film layer position can be adaptively adjusted according to actual conditions, and the present embodiment does not limit this. In this way, the arrangement of the first reset subpart 223 can be flexible.

[0156] With reference to FIGS. 24-35, the second voltage adjustment line 222 includes a second voltage adjustment section 222b and a third voltage adjustment section 222c which are disposed in different layers and electrically connected; the second voltage adjustment section 222b extends at least partially along the second direction Y, the third voltage adjustment section 222c extends at least partially along the second direction Y, and along the second direction Y, the second voltage adjustment section 222b and the third voltage adjustment section 222c are alternately disposed.

[0157] For example, the second voltage adjustment line 222 includes the second voltage adjustment section 222b and the third voltage adjustment section 222c which are disposed in different layers and electrically connected, and both the second voltage adjustment section 222b and the third voltage adjustment section 222c extend at least partially along the second direction Y; the two wire sections disposed in different layers have the same extending direction and are electrically connected to each other, which ensures that the electrically connected second voltage adjustment section 222b and the third voltage adjustment section 222c can transmit the same signal. For example, along the second direction Y, the second voltage adjustment section 222b and the third voltage adjustment section 222c are alternately disposed, i.e., along the second direction Y, the signal transmitted in the second voltage adjustment line 222 is transmitted from the second voltage adjustment section 222b to the third voltage adjustment section 222c, and then to the second voltage adjustment section 222b, and so on. The second voltage adjustment line 222 is designed in layers through the second voltage adjustment section 222b and the third voltage adjustment section 222c, which embodies the flexible setting mode of the second voltage adjustment line 222.

[0158] For example, with reference to FIGS. 25-35, in this embodiment, the second voltage adjustment line 222 can be an anode reset signal line Vref2, the anode reset signal line Vref2 includes the second voltage adjustment section 222b (see FIG. 32) and the third voltage adjustment section 222c (see FIG. 33), and the second voltage adjustment section 222b and the third voltage adjustment section 222c disposed in different layers are electrically connected along the second direction Y, thereby realizing the transmission of the reset signal to the anode along the second direction Y. In FIGS. 38 and 39, the second voltage adjustment section 222b is disposed in the layer where the third metal layer 6100 is located, and the third voltage adjustment section 222c is disposed in the layer where the fourth metal layer 6120 is located. The positions of the second voltage adjustment section 222b and the third voltage adjustment section 222c can be adjusted or exchanged adaptively, which is not limited in the embodiments of the present application.

[0159] The above embodiment is exemplified by the anode reset signal line Vref2, and the type of the second voltage adjustment line 222 can be adjusted adaptively based on the adjustment of the layer structure of the display panel 10.

[0160] With reference to FIGS. 2-14, 17-21, 39-48, 51-55, the pixel circuit 100 includes at least one transistor including a first active layer poly; the pixel circuit 100 further includes a storage capacitor Cst including a first plate M1 and a second plate MC oppositely arranged, the second plate MC being located on a side of the first plate M1 away from the first active layer poly; the display panel 10 further includes a first semiconductor layer 520, a first metal layer 540, a second metal layer 560, and a fourth metal layer 580; the first active layer poly is located on the first semiconductor layer 520, the first plate M1 is located on the first metal layer 540, and the second plate MC is located on the second metal layer 540; the second voltage adjustment subpart 222b is located on at least one of the first semiconductor layer 520, the first metal layer 540, the second metal layer 560, or the fourth metal layer 580; and the third voltage adjustment subpart 222c is located on at least one of the first semiconductor layer 520, the first metal layer 540, the second metal layer 560, or the fourth metal layer 580.

[0161] For example, referring to FIGS. 2 and 39, the transistor of the pixel circuit 100 can include a low-temperature polysilicon transistor. Referring to FIG. 5, in the pixel circuit 100, the film layer structure can be, in a direction away from the substrate 500, the substrate 500, a buffer layer 510, a first semiconductor layer 520, a first insulating layer 530, a first metal layer 540, an interlayer insulating layer 550, a second metal layer 560, a second insulating layer 570, a fourth metal layer 580, a third insulating layer 590, a fifth metal layer 5100, a planarization layer 5110, and an anode layer 5120. The pixel circuit 100 includes a storage capacitor Cst including a corresponding first plate M1 and a second plate MC.

[0162] For example, in the pixel circuit 100 described above, the second voltage adjustment subpart 222b is located on at least one of the first semiconductor layer 520, the first metal layer 540, the second metal layer 560, or the fourth metal layer 580; and the third voltage adjustment subpart 222c is located on at least one of the first semiconductor layer 520, the first metal layer 540, the second metal layer 560, or the fourth metal layer 580. In this way, the second voltage adjustment subpart 222b and the third voltage adjustment subpart 222c can be in the same layer as one of the film layers mentioned above, or can be in the same layer as at least two of the film layers mentioned above, and can be flexibly adjusted based on the film layer positions of the second voltage adjustment subpart 222b and the third voltage adjustment subpart 222c. Based on the film layer positions of the second voltage adjustment subpart 222b and the third voltage adjustment subpart 222c, adaptive adjustments can be made according to actual conditions, and the present application does not limit this, so that the second voltage adjustment subpart 222b and the third voltage adjustment subpart 222c can be flexibly adjusted.

[0163] Optionally, the display panel 10 further comprises a cross-connection portion 900, the cross-connection portion 900 is located at a side of the second plate MC away from the first plate M1, and the cross-connection portion 900 is located at the fourth metal layer 580. Exemplarily, the first active layer poly is located at a film layer of the first semiconductor layer 520, the first plate M1 is located at a film layer of the first metal layer 540, the second plate MC is located at a film layer of the second metal layer 560, and the cross-connection portion 900 for electrically connecting the second voltage adjustment sub-portion 222b and the third voltage adjustment sub-portion 222c is located at a side of the second plate MC away from the first plate M1, that is, the second voltage adjustment sub-portion 222b and the third voltage adjustment sub-portion 222c can be electrically connected through the cross-connection portion 900. Exemplarily, the third voltage adjustment sub-portion 222c is located in at least one of the first semiconductor layer 520, the first metal layer 540, the second metal layer 560, and the fourth metal layer 580, which means that the setting position of the third voltage adjustment sub-portion 222c has flexibility.

[0164] With continuous reference to FIGS. 24-35, the pixel circuit 100 comprises at least one first type transistor and at least one second type transistor, the first type transistor comprises a first active layer poly and a first gate M1, the second type transistor comprises a second active layer igzo, a second top gate MG and a second bottom gate MC, the first gate M1 is located at a side of the first active layer poly close to the second active layer igzo or at a side of the first active layer poly away from the second active layer igzo, the second top gate MG is located at a side of the second active layer igzo away from the first active layer poly, and the second bottom gate MC is located at a side of the second active layer igzo close to the first active layer poly; the display panel 10 further comprises a first semiconductor layer 620, a first metal layer 640, a second metal layer 660, a second semiconductor layer 680, a third metal layer 6100 and a fourth metal layer 6120; the first active layer poly is located at the first semiconductor layer 620, the first gate M1 is located at the first metal layer 640, the second bottom gate MC is located at the second metal layer 660, the second active layer igzo is located at the second semiconductor layer 680, and the second top gate MG is located at the third metal layer 6100; the second voltage adjustment sub-portion 222b is located in at least one of the first semiconductor layer 620, the first metal layer 640, the second metal layer 660, the second semiconductor layer 680, the third metal layer 6100 or the fourth metal layer 6120, and the third voltage adjustment sub-portion 222c is located in at least one of the first semiconductor layer 620, the first metal layer 640, the second metal layer 660, the second semiconductor layer 680, the third metal layer 6100 or the fourth metal layer 6120.

[0165] Exemplarily, the pixel circuit 100 comprises a first type transistor and a second type transistor, wherein the first type transistor comprises a first active layer poly, and the first active layer poly comprises a silicon semiconductor part, and the first type transistor can be understood as a low-temperature polysilicon transistor. The second type transistor comprises a second active layer igzo, and the second active layer igzo comprises an oxide semiconductor part, and the second type transistor can be understood as an oxide transistor. Further, the pixel circuit 100 comprises the low-temperature polysilicon transistor and the oxide transistor at the same time, and the pixel circuit 100 has the advantages of small leakage current of the oxide transistor, and also has the advantages of high switching speed, high carrier mobility and small power of the low-temperature polysilicon transistor.

[0166] Exemplarily, the first type transistor comprises the first active layer poly and the first gate M1, the second type transistor comprises the second active layer igzo, the second top gate MG and the second bottom gate MC, and for the film layers, the first gate M1 is located on one side of the first active layer poly close to the second active layer igzo or on one side of the first active layer poly away from the second active layer igzo, the second top gate MG is located on one side of the second active layer igzo away from the first active layer poly, and the second bottom gate MC is located on one side of the second active layer igzo close to the first active layer poly. The film layer where the first gate M1 is located is located on the film layer where the first metal layer 640 is located, the film layer where the second bottom gate MC is located is located on the film layer where the second metal layer 660 is located, and the film layer where the second top gate MG is located is located on the film layer where the third metal layer 6100 is located. At this time, the first gate M1 is located on one side of the first active layer poly away from the substrate 600, and the first type transistor is a transistor in a top gate structure. The first gate M1 can also be located on one side of the first active layer poly away from the second active layer igzo, and at this time, the first type transistor is a transistor in a bottom gate structure, and the present embodiment does not limit the positional relationship between the first gate and the first active layer.

[0167] For example, referring to FIG. 24, the film layer structure of the pixel circuit 100 can be, from bottom to the light-emitting side of the display panel 10, a substrate 600, a buffer layer 610, a first semiconductor layer 620, a first insulating layer 630, a first metal layer 640, an interlayer insulating layer 650, a second metal layer 660, a second insulating layer 670, a second semiconductor layer 680, a third insulating layer 690, a third metal layer 6100, a fourth insulating layer 6110, a fourth metal layer 6120, a fifth insulating layer 6130, a fifth metal layer 6140, a planarization layer 6150, and an anode layer 6160. In the pixel circuit 100, the second voltage adjustment sub-portion 222b can be located in at least one of the first semiconductor layer 620, the first metal layer 640, the second metal layer 660, the second semiconductor layer 680, the third metal layer 6100, or the fourth metal layer 6120; and the third voltage adjustment sub-portion 222c can be located in at least one of the first semiconductor layer 620, the first metal layer 640, the second metal layer 660, the second semiconductor layer 680, the third metal layer 6100, or the fourth metal layer 6120.

[0168] Optionally, the display panel 10 further includes a cross-connection portion 900, the cross-connection portion 900 is located on a side of the second top gate MG away from the first active layer poly; and the cross-connection portion 900 is located in the fourth metal layer 6120. By providing the cross-connection portion 900, the second voltage adjustment sub-portion 222b and the third voltage adjustment sub-portion 222c can be electrically connected. Thus, the third voltage adjustment sub-portion 220c is located in the film layer where the fourth metal layer 6120 is located.

[0169] For example, referring to FIG. 25, referring to FIG. 32 and FIG. 33, the second voltage adjustment sub-portion 222b is located in the film layer where the third metal layer 6100 is located, that is, the second voltage adjustment sub-portion 222b is provided in the same layer as the second top gate MG, and the third voltage adjustment sub-portion 222c is located in the film layer where the fourth metal layer 6120 is located.

[0170] Based on the film layer positions of the second voltage adjustment sub-portion 222b and the third voltage adjustment sub-portion 222c, the actual situation can be adapted, and the embodiments of the present application do not limit this, so that the second voltage adjustment signal line 222 can be flexibly provided.

[0171] With reference to FIGS. 2, 24 and 39, the voltage adjustment transistor 120 includes an initialization reset transistor T5 and an anode reset transistor T4; the voltage adjustment signal line 220 includes an initialization reset signal line Vref1 and an anode reset signal line Vref2; the pixel circuit 100 further includes a driving transistor T3, and the display panel 10 further includes a light emitting element 300; the initialization reset transistor T5 is electrically connected between the initialization reset signal line Vref1 and the gate of the driving transistor T3; and the anode reset transistor T7 is electrically connected between the anode reset signal line Vref2 and the light emitting element 300.

[0172] For example, referring to FIG. 2, the voltage adjustment transistor 120 in the pixel circuit 100 includes the initialization reset transistor T5 and the anode reset transistor T7; the input terminal of the initialization reset transistor T5 is electrically connected to the initialization reset signal line Vref1, and the output terminal of the initialization reset transistor T5 is connected to the gate of the driving transistor T3; when the initialization reset transistor T5 is turned on, the reset signal in the initialization reset signal line Vref1 can reset the gate of the driving transistor T3, which can also be understood as resetting the first node N1 in FIG. 2.

[0173] For example, the voltage adjustment transistor 120 in the pixel circuit 100 further includes the anode reset transistor T7; the input terminal of the anode reset transistor T7 is electrically connected to the anode reset signal line Vref2, and the output terminal of the anode reset transistor T7 is electrically connected to the light emitting element 300; when the anode reset transistor T7 is turned on, the reset signal in the anode reset signal line Vref2 can reset the light emitting element 300. It should be noted that in some pixel circuits 100, the initialization reset signal line Vref1 can be multiplexed as the anode reset signal line Vref2, that is, the anode reset transistor T7 and the initialization reset transistor T5 are connected to the same reset signal.

[0174] In the pixel circuit 100, at least one of the initialization reset signal line Vref1 and the anode reset signal line Vref2 can be the first voltage adjustment signal line 221.

[0175] With reference to FIGS. 2, 5 to 13, 17 to 21, the initialization reset signal line Vref1 includes a first initialization reset line Vref1a, and a plurality of first initialization reset lines Vref1a extend along the first direction X and are arranged along the second direction Y; the first voltage adjustment signal line 221 includes the first initialization reset line Vref1a; and / or, the anode reset signal line Vref2 includes a first anode reset line Vref2a, and a plurality of first anode reset lines Vref2a extend along the first direction X and are arranged along the second direction Y; the first voltage adjustment signal line 221 includes the first anode reset line Vref2a.

[0176] For example, referring to FIG. 2, the voltage adjustment signal line 220 includes an initialization reset signal line Vref1 and an anode reset signal line Vref2, as shown in FIGS. 6-13 and 17-21. The initialization reset signal line Vref1 and / or the anode reset signal line Vref2 can include a wire segment extending in the first direction X, i.e., the same as the wire setting trend of the first virtual connection line segment L31, so as to multiplex the first virtual connection line segment L31 corresponding to the voltage adjustment signal line 220, thereby providing utilization of the wire.

[0177] For example, referring to FIGS. 13 and 21, the initialization reset signal line Vref1 includes a first initialization reset line Vref1a, wherein the first initialization reset line Vref1a extends in the first direction X and is arranged in the second direction Y, i.e., the arrangement direction and the extension direction of the first initialization reset line Vref1a are the same as the first virtual connection line segment L31, so that the first virtual connection line segment L31 can be multiplexed to include the first initialization reset line Vref1a, i.e., the first voltage adjustment signal line 221 includes the first initialization reset line Vref1a.

[0178] For example, referring to FIGS. 13 and 21, the anode reset signal line Vref2 includes a first anode reset line Vref2a, wherein the first anode reset line Vref2a extends in the first direction X and is arranged in the second direction Y, i.e., the arrangement direction and the extension direction of the first anode reset line Vref2a are the same as the first virtual connection line segment L31, so that the first virtual connection line segment L31 can also be multiplexed to include the first anode reset line Vref2a, i.e., the first voltage adjustment signal line 221 includes the first anode reset line Vref2a.

[0179] For example, in the pixel circuit 100, the first voltage adjustment signal line 221 can include the first initialization reset line Vref1a or the first anode reset line Vref2a, or in the pixel circuit 100, different first voltage adjustment signal lines 221 simultaneously include the first initialization reset line Vref1a and the first anode reset line Vref2a.

[0180] Optionally, continuing to refer to FIGS. 2, 5-13, and 17-21, the first voltage adjustment signal line 221 includes the first initialization reset line Vref1a and the first anode reset line Vref2a; along the second direction Y, the first initialization reset line Vref1a and the first anode reset line Vref2a are arranged alternately.

[0181] For example, when the first voltage adjustment signal line 221 includes the first initialization reset line Vref1a and the first anode reset line Vref2a, that is, the first initialization reset line Vref1a is present in the initialization reset signal line Vref1, and the first anode reset line Vref2a is present in the anode reset signal line Vref2. It can be understood that the initialization reset signal line Vref1 is set in the form of a mesh trace, and the anode reset signal line Vref2 is also set in the form of a mesh trace. In this case, along the second direction Y, the first initialization reset line Vref1a and the first anode reset line Vref2a are arranged alternately, which can ensure that the first voltage adjustment signal line 221 is set to be balanced, and the reset signal transmission effects of the initialization reset signal line Vref1 and the anode reset signal line Vref2 are balanced, which is beneficial to ensure the display effect of the display panel 10.

[0182] With continuous reference to FIGS. 22, 25-34, 39-47, 51-55, the voltage adjustment transistor 120 further includes a bias adjustment transistor T8; the voltage adjustment signal line 220 further includes a bias adjustment signal line DVH; and the bias adjustment transistor T8 is electrically connected between the bias adjustment signal line DVH and the first electrode and / or the second electrode of the driving transistor T3.

[0183] For example, with reference to FIGS. 22 and 39, the pixel circuit 100 can further include the bias adjustment transistor T8, the input end of the bias adjustment transistor T8 is electrically connected with the bias adjustment signal line DVH, and the output end is connected with the driving transistor T3, so as to perform bias adjustment on the driving transistor T3, ensure the stability of the driving transistor T3, and ensure the working stability of the display panel 10 and the display effect of the display panel 10. The bias adjustment transistor T8 can be connected at the first electrode (with reference to FIGS. 24 or 39) of the driving transistor T3, that is, the second node N2; the bias adjustment transistor T8 can also be connected at the second electrode of the driving transistor T3, that is, the third node N3; the bias adjustment transistor T8 can also be connected between the first electrode and the second electrode of the driving transistor T3. Based on the position of the output end of the bias adjustment transistor T8, adaptive adjustment can be made according to the actual bias adjustment of the driving transistor T3, and the embodiments of the present application do not limit this.

[0184] In addition to the first voltage adjustment signal line 221 (multiplexed as the first virtual connection line segment L31) present in at least one of the initialization reset signal line Vref1 and the anode reset signal line Vref2, the bias adjustment signal line DVH mentioned in the embodiments can also include the first voltage adjustment signal line 221 (multiplexed as the first virtual connection line segment L31).

[0185] With reference to FIGS. 22, 25-34, 39-47, 51-55, the bias adjustment signal line DVH includes a first bias adjustment line DVHa, and the plurality of first bias adjustment lines DVHa extend along the first direction X and are arranged along the second direction Y; the first voltage adjustment signal line 221 includes the first bias adjustment line DVHa.

[0186] As shown in FIGS. 22 and 39, the voltage adjustment signal line 220 further includes a bias adjustment signal line DVH. As shown, the bias adjustment signal line DVH can include a wire section extending along the first direction X, and the wire setting trend of the section is the same as that of the first virtual connection line segment L31, so that the first virtual connection line segment L31 corresponding to the setting can be multiplexed by the voltage adjustment signal line 220, and the utilization rate of the wire is provided.

[0187] For example, as shown in FIGS. 34, 47 and 54, the first bias adjustment line DVHa includes a first bias adjustment line DVHa, wherein the first bias adjustment line DVHa extends along the first direction X and is arranged along the second direction Y, that is, the arrangement direction and the extension direction of the first bias adjustment line DVHa are the same as those of the first virtual connection line segment L31, so that the first virtual connection line segment L31 can be multiplexed as the first bias adjustment line DVHa, that is, the first voltage adjustment signal line 221 includes the first bias adjustment line DVHa.

[0188] With reference to FIGS. 22 and 39, the initialization reset signal line Vrefl includes first initialization reset lines Vrefla, a plurality of the first initialization reset lines Vrefla extend along the first direction X and are arranged along the second direction Y; the first voltage adjustment signal line 221 further includes the first initialization reset lines Vrefla; along the second direction Y, the first initialization reset lines Vrefla and the first bias adjustment line DVHa are arranged alternately; or, with reference to FIGS. 22, 25-34, 39-47, 51-55, the anode reset signal line Vref2 includes first anode reset lines Vref2a, a plurality of the first anode reset lines Vref2a extend along the first direction X and are arranged along the second direction Y, the first voltage adjustment signal line 221 further includes the first anode reset lines Vref2a; along the second direction Y, the first anode reset lines Vref2a and the first bias adjustment line DVHa are arranged alternately; or, with reference to FIGS. 24 and 39, the initialization reset signal line Vrefl includes first initialization reset lines Vrefla, a plurality of the first initialization reset lines Vrefla extend along the first direction X and are arranged along the second direction Y; the anode reset signal line Vref2 includes first anode reset lines Vref2a, a plurality of the first anode reset lines Vref2a extend along the first direction X and are arranged along the second direction Y; the first voltage adjustment signal line 221 further includes the first initialization reset lines Vrefla and the first anode reset lines Vref2a; along the second direction Y, the first initialization reset lines Vrefla, the first anode reset lines Vref2a and the first bias adjustment line DVHa are arranged alternately.

[0189] For example, referring to FIG. 22 and FIG. 39, the voltage adjustment signal line 220 includes the initial reset signal line Vref1, the anode reset signal line Vref2, and the bias adjustment signal line DVH, referring to FIG. 34, FIG. 47, and FIG. 54, the anode reset signal line Vref2 includes the first anode reset line Vref2a, wherein the first anode reset line Vref2a extends along the first direction X and is arranged along the second direction Y, that is, the arrangement direction and the extension direction of the first anode reset line Vref2a are both the same as the first virtual connection line segment L31, and the bias adjustment signal line DVH includes the first bias adjustment line DVHa, wherein the first bias adjustment line DVHa also extends along the first direction X and is arranged along the second direction Y, that is, the arrangement direction and the extension direction of the first bias adjustment line DVHa are also both the same as the first virtual connection line segment L31, and the first voltage adjustment signal line 221 can include the first anode reset line Vref2a and the first bias adjustment line DVHa. For example, referring to FIG. 28, FIG. 39, and FIG. 44, along the second direction Y, the first anode reset line Vref2a and the first bias adjustment line DVHa can be alternately arranged, that is, one first bias adjustment line DVHa is arranged between two adjacent first anode reset lines Vref2a, or one first anode reset line Vref2a is arranged between two adjacent first bias adjustment lines DVHa, and through the alternate arrangement, the balanced arrangement of the display panel 10 can be ensured, and the regularity of the display panel 10 can be ensured.

[0190] For example, referring to FIG. 22 and FIG. 39, the voltage adjustment signal line 220 includes the initial reset signal line Vref1 and the bias adjustment signal line DVH, wherein the initial reset signal line Vref1 can include the first initial reset line Vref1a, that is, the initial reset signal line Vref1 includes a wire extending along the first direction X and arranged along the second direction Y, and the bias adjustment signal line DVH includes the first bias adjustment line DVHa, wherein the first bias adjustment line DVHa also extends along the first direction X and is arranged along the second direction Y, that is, the arrangement direction and the extension direction of the first bias adjustment line DVHa are also both the same as the first virtual connection line segment L31, and the first voltage adjustment signal line 221 includes the first initial reset line Vref1a and the first bias adjustment line DVHa. For example, along the second direction Y, the first initial reset line Vref1a and the first bias adjustment line DVH can be alternately arranged, that is, one first bias adjustment line DVH is arranged between two adjacent first initial reset lines Vref1a, or one first initial reset line Vref1a is arranged between two adjacent first bias adjustment lines DVH, and through the alternate arrangement, the balanced arrangement of the display panel 10 can be ensured, and the regularity of the display panel 10 can be ensured.

[0191] For example, referring to FIG. 22 and FIG. 39, the voltage adjustment signal line 220 includes an initialization reset signal line Vref1, an anode reset signal line Vref2, and a bias adjustment signal line DVH, wherein the initialization reset signal line Vref1 can include a first initialization reset line Vref1a, the anode reset signal line Vref2 includes a first anode reset line Vref2a, and the bias adjustment signal line DVH includes a first bias adjustment line DVHa, and the first voltage adjustment signal line 221 includes the first initialization reset line Vref1a, the first anode reset line Vref2a, and the first bias adjustment line DVHa. In the second direction Y, the first initialization reset line Vref1a, the first anode reset line Vref2a, and the first bias adjustment line DVHa can be arranged alternately, and the alternately arranged lines can ensure the balanced arrangement of the lines of the display panel 10 and the regularity of the display panel 10. When the first voltage adjustment signal line 221 includes the first initialization reset line Vref1a, the first anode reset line Vref2a, and the first bias adjustment line DVHa, the alternately arranged lines have diversity. For example, the first initialization reset line Vref1a is denoted by "a", the first anode reset line Vref2a is denoted by "b", and the first bias adjustment line DVHa is denoted by "c", and the arrangement of the first voltage adjustment signal line 221 can be "abcabc", "abcacb", or "abcbac", and the arrangement of the first initialization reset line Vref1a, the first anode reset line Vref2a, and the first bias adjustment line DVHa in the first direction X can be adjusted adaptively according to the actual display panel 10, and the embodiments of the present application do not limit this.

[0192] For example, the display panel 10 further includes a power signal line (PVDD or PVEE), the power signal line extends in the first direction X, and a plurality of power signal lines are arranged in the second direction Y. In the second direction Y, the data signal line 210 and the first voltage adjustment signal line 221 are located between two adjacent power signal lines.

[0193] The power signal line in the display panel 10 includes a positive power signal line PVDD and a negative power signal line PVEE. For example, referring to FIG. 2, FIG. 22, and FIG. 39, the pixel circuit 100 is electrically connected to the positive power signal line PVDD, and the positive power signal line PVDD is transmitted to the pixel circuit 100, so as to ensure that the driving transistor T3 generates a corresponding driving current, and further ensure the normal display of the light emitting element 300 in the display panel 10.

[0194] For the positive power signal lines PVDD in the display panel 10, as shown in FIGS. 5-13, 17-21, 25-34, 40-47, 51-55, the positive power signal lines PVDD are arranged along the second direction Y and extend along the first direction X. That is, the trace direction and arrangement direction of the positive power signal lines PVDD and the data signal lines 210 are also the same. For example, the data signal lines 210 and the first voltage adjustment signal lines 211 can be located between two adjacent positive power signal lines PVDD.

[0195] In FIGS. 13 and 21, the first voltage adjustment signal lines 211 include the first anode reset lines Vref2a and the first initialization reset lines Vref1a, and the data signal lines 210 and the first voltage adjustment signal lines 211 are arranged between two adjacent positive power signal lines PVDD along the second direction Y. In FIGS. 34, 47 and 55, the first voltage adjustment signal lines 211 include the first anode reset lines Vref2a and the first bias adjustment lines DVHa, and the data signal lines 210 and the first voltage adjustment signal lines 211 are arranged between two adjacent positive power signal lines PVDD along the second direction Y. Based on the trace arrangement mode, adaptive adjustment can be made according to actual conditions.

[0196] With reference to FIGS. 2-14, 17-21, 39-48, 51-55, the pixel circuit 100 includes at least one transistor including a first active layer poly, and the pixel circuit 100 further includes a storage capacitor Cst including a first plate M1 and a second plate MC oppositely arranged, the second plate MC being located on a side of the first plate M1 away from the first active layer poly, and the display panel 10 further includes a first semiconductor layer 520, a first metal layer 540 and a second metal layer 560, a fourth metal layer 580 and a fifth metal layer 5100, the first active layer poly being located at a film layer of the first semiconductor layer 520, the first plate M1 being located at a film layer of the first metal layer 540, and the second plate MC being located at a film layer of the second metal layer 560, and the display panel 10 further includes a power supply signal line (PVDD or PVEE) extending along a first direction X, the power supply signal line (PVDD or PVEE) being located at the fourth metal layer 580 and / or the fifth metal layer 5100, and the data signal line 210 being located at the fourth metal layer 580 and / or the fifth metal layer 5100, and the data connection wire L0 includes a first data connection line segment L1 extending along the first direction X and a second data connection line segment L2 extending along a second direction Y, and the virtual connection wire L3 includes a first virtual connection line segment L31 extending along the first direction X and a second virtual connection line segment L32 extending along the second direction Y, the first data connection line segment L1 and the first virtual connection line segment L31 being located at the fifth metal layer 5100, and the second data connection line segment L2 and the second virtual connection line segment L32 being located at the fourth metal layer 580.

[0197] For example, referring to FIGS. 2 and 39, the transistor of the pixel circuit 100 can include a low-temperature polysilicon transistor. Referring to FIG. 5, in the pixel circuit 100, the film layer structure can be a substrate 500, a buffer layer 510, a first semiconductor layer 520, a first insulating layer 530, a first metal layer 540, an interlayer insulating layer 550, a second metal layer 560, a second insulating layer 570, a fourth metal layer 580, a third insulating layer 590, a fifth metal layer 5100, a planarization layer 5110, and an anode layer 5120, in a direction away from the substrate. The pixel circuit 100 includes a storage capacitor Cst including a corresponding first plate M1 and a second plate MC. The first active layer poly is located at a film layer of the first semiconductor layer 520, the first plate M1 is located at a film layer of the first metal layer 540, and the second plate MC is located at a film layer of the second metal layer 560.

[0198] For example, referring to FIGS. 2, 5-13, 17-21, 39-47, 51-55, in the pixel circuit 100, the power signal line (for example, the positive power signal line PVDD), the data signal line 210, and the first virtual connection line segment L31 are all located on the fifth metal layer 5100, so that the film layer thickness of the display panel 10 as a whole can be reduced, and the thin design of the display panel 10 can be facilitated.

[0199] For example, referring to FIGS. 34-36, in the pixel circuit 100, the power signal line (for example, the positive power signal line PVDD), the data signal line 210, and the first virtual connection line segment L31 are all located on the fifth metal layer 6140, so that the film layer thickness of the display panel 10 as a whole can be reduced, and the thin design of the display panel 10 can be facilitated.

[0200] Alternatively, the power signal line (for example, the positive power signal line PVDD) can also be partially located on the fifth metal layer 5100 and partially located on the fourth metal layer 580, and the data signal line 210 can be partially located on the fifth metal layer 5100 and partially located on the fourth metal layer 580, so that the film layer thickness of the display panel 10 as a whole can be reduced, and the thin design of the display panel 10 can be facilitated.

[0201] In combination with FIG. 14, the display panel 10 further includes a light emitting element 300, which is electrically connected to the pixel circuit 100. The light emitting element 300 includes a first color light emitting element 300a, a second color light emitting element 300b, and a third color light emitting element 300c, which are different from each other and are one of a red light emitting element, a blue light emitting element, and a green light emitting element. A plurality of first color light emitting elements 300a and second color light emitting elements 300b form a first virtual quadrilateral 21. The first color light emitting element 300a is located at a first vertex of the first virtual quadrilateral 21, and the center of the second color light emitting element 300b is located at a second vertex of the first virtual quadrilateral 21. The first vertex and the second vertex are alternately and spaced apart, and the third color light emitting element 300c is located inside the first virtual quadrilateral 21. A plurality of third color light emitting elements 300c form a second virtual quadrilateral 22. The centers of the plurality of third color light emitting elements 300c are respectively located at the vertices of the second virtual quadrilateral, and the first color light emitting element 300a or the second color light emitting element 300b is located inside the second virtual quadrilateral 22.

[0202] For example, referring to FIG. 14, the plurality of first color light emitting elements 300a and the plurality of second color light emitting elements 300b form a first virtual quadrilateral 21, two first color light emitting elements 300a are located at opposite corners of the first virtual quadrilateral 21, and two second color light emitting elements 300b are located at the other two opposite corners of the first virtual quadrilateral 21. In addition, a third color light emitting element 300c is disposed at the center of the first virtual quadrilateral 21.

[0203] For example, the plurality of third color light emitting elements 300c can also form a second virtual quadrilateral 22, in which a first color light emitting element 300a can be located at the center or a second color light emitting element 300b can be located at the center.

[0204] For example, the first color, the second color, and the third color correspond to one of red, blue, and green, respectively. Through the above arrangement of the light emitting elements 300, the rendering effect of the light emitting elements 300 can be better, and the color display effect of the display panel 10 can be ensured.

[0205] It should be noted that only the anodes corresponding to the light emitting elements 300 are shown in FIG. 14, and the anodes represent light emitting elements of different colors.

[0206] In the thickness direction of the display panel 10, the anodes of the first color light emitting elements 300a and the anodes of the second color light emitting elements 300b overlap the data signal lines 210 and the virtual connection traces L3.

[0207] By adjusting the positions of the data signal lines 210 and the virtual connection traces L3, it is ensured that, in the thickness direction of the display panel 10, the anodes of the first color light emitting elements 300a and the anodes of the second color light emitting elements 300b overlap the data signal lines 210 and the virtual connection traces L3. This can increase the coverage area of the anodes on the data signal lines 210 and the virtual connection traces L3, that is, more areas of the data signal lines 210 and more areas of the virtual connection traces L3 are arranged within the coverage range of the anodes, so that the degree of being raised by the metal traces on the entire area of the anodes is similar, thereby avoiding color deviation or color dispersion in the display panel and ensuring the display effect of the display panel. On the other hand, the overlap of the anodes with the data signal lines 210 and the virtual connection traces L3 can reduce the obstruction of the data signal lines 210 and the virtual connection traces L3 to light transmission, which is conducive to improving the transmittance of the display panel 10 and ensuring the display effect of the display panel 10.

[0208] Based on the same inventive concept, the embodiment of the present application further provides a display device. FIG. 56 is a structural schematic diagram of a display device provided by the embodiment of the present application. As shown in FIG. 56, the display device 1 includes the display panel 10 described in any of the above embodiments. For example, the display device 1 can be a mobile phone, a computer, a smart wearable device (for example, a smart watch), a vehicle-mounted display device, or the like, and the embodiment of the present application is not limited thereto.

[0209] It should be noted that the above is only an optional embodiment of the present application and the technical principle applied. Those skilled in the art will understand that the present application is not limited to the specific embodiments described herein, and those skilled in the art can make various obvious changes, readjustments and substitutions without departing from the scope of the present application. Therefore, although the present application has been described in more detail through the above embodiments, the present application is not limited to the above embodiments, and can include more other equivalent embodiments without departing from the concept of the present application, and the scope of the present application is determined by the scope of the appended claims.

Claims

1. A display panel, comprising a pixel circuit and a signal line; the pixel circuit comprises a data writing transistor and a voltage regulating transistor; the signal line comprises a data signal line and a voltage regulating signal line, the data signal line is electrically connected with a first electrode of the data writing transistor, and the voltage regulating signal line is electrically connected with a first electrode of the voltage regulating transistor; a plurality of the data signal lines extend along a first direction and are arranged along a second direction, the first direction and the second direction intersect; the display panel further comprises a display area and a fan-out area located at one side of the display area; the display area comprises a first display area and a second display area, and the second display area is located at least one side of the first display area; the fan-out area comprises a plurality of fan-out wires, and the first display area and the second display area each comprise a plurality of the data signal lines; The data signal line is connected with the fan-out wire; wherein the data signal lines of the second display area are connected with the fan-out wires through data connection wires located in the display area; the display panel further comprises virtual connection wires located in the display area, the virtual connection wires are insulatively arranged with the data connection wires, and there exists a same layer arrangement of the virtual connection wires and the data connection wires; at least part of the voltage regulating signal lines comprises the virtual connection wires.

2. The display panel of claim 1, wherein, the data connection wires comprise a first data connection line segment extending along the first direction; the virtual connection wires comprise a first virtual connection line segment extending along the first direction, the first virtual connection line segment is insulatively arranged with the first data connection line segment in the same layer; the voltage regulating signal lines comprise a first voltage regulating signal line, and the first virtual connection line segment is multiplexed as the first voltage regulating signal line. 3.The display panel of claim 2, further comprising a plurality of pixel circuit groups, each of the pixel circuit groups comprises two pixel circuits arranged adjacently along the second direction; along the second direction, the first virtual connection line segment is located between two data signal lines electrically connected with two pixel circuits in a same pixel circuit group respectively. the first virtual connection line segment is arranged in the same layer with the data signal lines.

4. The display panel of claim 2, wherein, the voltage regulating signal lines further comprise a second voltage regulating signal line, the second voltage regulating signal line extends at least partially along the second direction, and the second voltage regulating signal line is electrically connected with the first voltage regulating signal line.

5. The display panel of claim 2, wherein, 6.The display panel of claim 5, further comprising a via connection part, the via connection part is arranged in the same layer with and is electrically connected with the first virtual connection line segment; along the second direction, the via connection part is located at least one side of the first virtual connection line segment connected therewith; the second voltage regulating signal line is electrically connected with the via connection part through a via. the data connection wires further comprise a second data connection line segment extending along the second direction, the second data connection line segment is electrically connected with the first data connection line segment and the data signal line respectively; 7. The display panel of claim 6, wherein, the virtual connection wires further comprise a second virtual connection line segment extending along the second direction, the second virtual connection line segment is insulatively arranged with the second data connection line segment in the same layer; and ​ The second virtual connection line segment is electrically connected with the fixed potential signal terminal.

8. The display panel of claim 7, wherein, The fixed potential signal terminal comprises at least one of a voltage regulating signal terminal and a power signal terminal.

9. The display panel of claim 5, further comprising a transition portion, at least part of the transition portion extending along the second direction and electrically connected with the second voltage regulating signal line and the first virtual connection line segment, respectively; The film layer where the transition portion is located is between the film layer where the second voltage regulating signal line is located and the film layer where the first virtual connection line segment is located.

10. The display panel of claim 9, wherein, The transition portion comprises at least a first transition sub-portion and a second transition sub-portion, the first transition sub-portion and the second transition sub-portion being alternately arranged along the second direction; The voltage regulating transistor comprises at least two kinds of voltage regulating transistors, the first voltage regulating signal line comprises at least a first sub-voltage regulating signal line and a second sub-voltage regulating signal line for transmitting different voltage regulating signals, the first sub-voltage regulating signal line and the second sub-voltage regulating signal line being alternately arranged along the second direction; The first sub-voltage regulating signal line is electrically connected with the first transition sub-portion, and the second sub-voltage regulating signal line is electrically connected with the second transition sub-portion.

11. The display panel of claim 10, wherein, The data connection wire further comprises a second data connection line segment extending along the second direction, the second data connection line segment being electrically connected with the first data connection line segment and the data signal line, respectively; The virtual connection wire further comprises a second virtual connection line segment extending along the second direction, the second virtual connection line segment being insulatively arranged in the same layer as the second data connection line segment; The second virtual connection line segment is multiplexed as the transition portion.

12. The display panel of claim 5, wherein, The second voltage regulating signal line comprises a first voltage regulating sub-portion; The first voltage regulating sub-portion extends along the second direction, and at least two pixel circuits arranged along the second direction share the same first voltage regulating sub-portion.

13. The display panel of claim 12, wherein, The pixel circuit comprises at least one transistor, the transistor comprising a first active layer; The pixel circuit further comprises a storage capacitor, the storage capacitor comprising a first plate and a second plate arranged oppositely, the second plate being located on a side of the first plate away from the first active layer; The display panel further comprises a first semiconductor layer, a first metal layer and a second metal layer, the first active layer being located in the first semiconductor layer, the first plate being located in the first metal layer, and the second plate being located in the second metal layer; The first voltage regulating sub-portion is located in at least one of the first semiconductor layer, the first metal layer or the second metal layer.

14. The display panel of claim 12, wherein, The pixel circuit comprises at least one first type transistor and at least one second type transistor, the first type transistor comprises a first active layer and a first gate, the second type transistor comprises a second active layer, a second top gate and a second bottom gate, the first gate is located on a side of the first active layer close to the second active layer or the first gate is located on a side of the first active layer away from the second active layer, the second top gate is located on a side of the second active layer away from the first active layer, and the second bottom gate is located on a side of the second active layer close to the first active layer. The display panel further comprises a first semiconductor layer, a first metal layer, a second metal layer, a second semiconductor layer and a third metal layer; the first active layer is located on the first semiconductor layer, the first gate is located on the first metal layer, the second bottom gate is located on the second metal layer, the second active layer is located on the second semiconductor layer, and the second top gate is located on the third metal layer. The first voltage adjusting part is located on at least one of the first semiconductor layer, the first metal layer, the second metal layer, the second semiconductor layer or the third metal layer.

15. The display panel of claim 5, wherein, The second voltage adjusting line comprises a second voltage adjusting part and a third voltage adjusting part which are arranged in different layers and are electrically connected. The second voltage adjusting part extends at least partially along the second direction, the third voltage adjusting part extends at least partially along the second direction, and along the second direction, the second voltage adjusting part and the third voltage adjusting part are arranged alternately.

16. The display panel of claim 15, wherein, The pixel circuit comprises at least one transistor, and the transistor comprises a first active layer. The pixel circuit further comprises a storage capacitor, and the storage capacitor comprises a first plate and a second plate which are arranged oppositely, and the second plate is located on a side of the first plate away from the first active layer. The display panel further comprises a first semiconductor layer, a first metal layer, a second metal layer and a fourth metal layer; the first active layer is located on the first semiconductor layer, the first plate is located on the first metal layer, and the second plate is located on the second metal layer. The second voltage adjusting part is located on at least one of the first semiconductor layer, the first metal layer, the second metal layer or the fourth metal layer; and the third voltage adjusting part is located on at least one of the first semiconductor layer, the first metal layer, the second metal layer or the fourth metal layer. The pixel circuit comprises at least one first type transistor and at least one second type transistor, the first type transistor comprises a first active layer and a first gate, the second type transistor comprises a second active layer, a second top gate and a second bottom gate, the first gate is located on a side of the first active layer close to the second active layer or the first gate is located on a side of the first active layer away from the second active layer, the second top gate is located on a side of the second active layer away from the first active layer, and the second bottom gate is located on a side of the second active layer close to the first active layer.

17. The display panel of claim 15, wherein, ​ The display panel further comprises a first semiconductor layer, a first metal layer, a second metal layer, a second semiconductor layer, a third metal layer and a fourth metal layer; the first active layer is located on the first semiconductor layer, the first gate electrode is located on the first metal layer, the second bottom gate electrode is located on the second metal layer, the second active layer is located on the second semiconductor layer, and the second top gate electrode is located on the third metal layer. The second voltage adjustment sub is located on at least one of the first semiconductor layer, the first metal layer, the second metal layer, the second semiconductor layer, the third metal layer or the fourth metal layer, and the third voltage adjustment sub is located on at least one of the first semiconductor layer, the first metal layer, the second metal layer, the second semiconductor layer, the third metal layer or the fourth metal layer.

18. The display panel of claim 2, wherein, The voltage adjustment transistor comprises an initialization reset transistor and an anode reset transistor. The voltage adjustment signal line comprises an initialization reset signal line and an anode reset signal line. The pixel circuit further comprises a driving transistor, and the display panel further comprises a light emitting element. The initialization reset transistor is electrically connected between the initialization reset signal line and the gate electrode of the driving transistor, and the anode reset transistor is electrically connected between the anode reset signal line and the light emitting element.

19. The display panel of claim 18, wherein, The display panel satisfies at least one of the following conditions: The initialization reset signal line comprises a first initialization reset line, a plurality of the first initialization reset lines extend along the first direction and are arranged along the second direction, and the first voltage adjustment signal line comprises the first initialization reset line. The anode reset signal line comprises a first anode reset line, a plurality of the first anode reset lines extend along the first direction and are arranged along the second direction, and the first voltage adjustment signal line comprises the first anode reset line.

20. The display panel of claim 19, wherein, The first voltage adjustment signal line comprises the first initialization reset line and the first anode reset line. Along the second direction, the first initialization reset line and the first anode reset line are arranged alternately.

21. The display panel of claim 18, wherein, The voltage adjustment transistor further comprises a bias adjustment transistor. The voltage adjustment signal line further comprises a bias adjustment signal line. The bias adjustment transistor is electrically connected between the bias adjustment signal line and the first electrode and / or the second electrode of the driving transistor.

22. The display panel of claim 21, wherein, The bias adjustment signal line comprises a first bias adjustment line, a plurality of the first bias adjustment lines extend along the first direction and are arranged along the second direction. The first voltage adjustment signal line comprises the first bias adjustment line.

23. The display panel of claim 22, wherein, The initialization reset signal line comprises a first initialization reset line, a plurality of the first initialization reset lines extend along the first direction and are arranged along the second direction; the first voltage adjustment signal line further comprises the first initialization reset line; along the second direction, the first initialization reset line and the first bias adjustment line are arranged alternately. Or, The anode reset signal lines comprise first anode reset lines, a plurality of the first anode reset lines extend along the first direction and are arranged along the second direction, the first voltage adjustment signal lines further comprise the first anode reset lines; Along the second direction, the first anode reset lines and the first bias adjustment lines are arranged alternately; Or, The initialization reset signal lines comprise first initialization reset lines, a plurality of the first initialization reset lines extend along the first direction and are arranged along the second direction; the anode reset signal lines comprise first anode reset lines, a plurality of the first anode reset lines extend along the first direction and are arranged along the second direction; the first voltage adjustment signal lines further comprise the first initialization reset lines and the first anode reset lines; along the second direction, the first initialization reset lines, the first anode reset lines and the first bias adjustment lines are arranged alternately.

24. The display panel of claim 2, further comprising power supply signal lines, the power supply signal lines extend along the first direction, a plurality of the power supply signal lines are arranged along the second direction; Along the second direction, the data signal lines and the first voltage adjustment signal lines are located between two adjacent power supply signal lines.

25. The display panel of claim 1, wherein, The pixel circuit comprises at least one transistor, the transistor comprises a first active layer; The pixel circuit further comprises a storage capacitor, the storage capacitor comprises a first plate and a second plate arranged oppositely, the second plate is located on a side of the first plate away from the first active layer; The display panel further comprises a first semiconductor layer, a first metal layer, a second metal layer, a fourth metal layer and a fifth metal layer; the first active layer is located on the first semiconductor layer, the first plate is located on the first metal layer, the second plate is located on the second metal layer, The display panel further comprises power supply signal lines, the power supply signal lines extend along the first direction; the power supply signal lines are located in at least one of the fourth metal layer and the fifth metal layer; the data signal lines are located in at least one of the fourth metal layer and the fifth metal layer; The data connection traces comprise first data connection line segments extending along the first direction and second data connection line segments extending along the second direction; The virtual connection traces comprise first virtual connection line segments extending along the first direction and second virtual connection line segments extending along the second direction; The first data connection line segments and the first virtual connection line segments are located on the fifth metal layer, and the second data connection line segments and the second virtual connection line segments are located on the fourth metal layer.

26. The display panel of claim 1, further comprising light emitting elements, the light emitting elements are electrically connected with the pixel circuits; The light emitting elements comprise first color light emitting elements, second color light emitting elements and third color light emitting elements, the first color light emitting elements, the second color light emitting elements and the third color light emitting elements are respectively one of red light emitting elements, blue light emitting elements and green light emitting elements and are different from each other. The first color light emitting elements and the second color light emitting elements constitute a first virtual quadrangle, the first color light emitting elements are located at first vertices of the first virtual quadrangle, centers of the second color light emitting elements are located at second vertices of the first virtual quadrangle, the first vertices and the second vertices are alternated and spaced apart, and the third color light emitting elements are located inside the first virtual quadrangle; The third color light emitting elements constitute a second virtual quadrangle, centers of the third color light emitting elements are respectively located at vertices of the second virtual quadrangle, and the first color light emitting elements or the second color light emitting elements are located inside the second virtual quadrangle.

27. The display panel of claim 26, wherein, In a thickness direction of the display panel, anodes of the first color light emitting elements overlap the data signal lines and the virtual connection traces, and anodes of the second color light emitting elements overlap the data signal lines and the virtual connection traces.

28. A display device comprising the display panel of any one of claims 1-27.

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