Nitride semiconductor device and method for manufacturing same

Abstract

This nitride semiconductor device (1) comprises: a substrate (30); a semiconductor laminate (40) that includes a 2DEG (43); a source structure (50S), a drain structure (50D), and a gate structure (50G) for an FET (11); and an anode structure (50A) and a cathode structure (50K) for a diode (12). The gate structure (50G) includes a first p-type semiconductor layer (51G) and a first metal layer (55G). The anode structure (50A) includes a second p-type semiconductor layer (51A) and a second metal layer (55A). The second p-type semiconductor layer (51A) has the same layer configuration as the first p-type semiconductor layer (51G). The source structure (50S) is electrically connected to the anode structure (50A). The drain structure (50D) is electrically connected to the cathode structure (50K). The second metal layer (55A) is formed using a material which is different from that of the first metal layer (55G).

Description

Nitride semiconductor device and manufacturing method thereof

[0001] The present disclosure relates to a nitride semiconductor device and a method for manufacturing the same.

[0002] Japanese Patent Laid-Open No. 2006-129999 discloses a semiconductor device including a field effect transistor (FET) and a protection diode. The protection diode is provided to prevent the FET from being destroyed by electrostatic discharge (ESD). The semiconductor device disclosed in Japanese Patent Laid-Open No. 2006-129999 includes a two-dimensional electron gas (2DEG) as a channel of the FET and as a current path for an ESD current flowing through the protection diode.

[0003] The FET and the protection diode are formed in the same process and have the same configuration. Specifically, the anode of the protection diode has the same configuration as the gate of the FET and is electrically connected to the source of the FET. The cathode of the protection diode has the same configuration as the drain of the FET and is electrically connected to the gate of the FET.

[0004] JP 2011-165749 A

[0005] In the semiconductor device described in Patent Document 1, there is room for improvement in the ESD withstand voltage provided by the protection diode.

[0006] Therefore, the present disclosure provides a nitride semiconductor device capable of improving ESD resistance, and a method for manufacturing the same.

[0007] a semiconductor stack including a first region for the field-effect transistor; and an anode structure and a cathode structure for the diode, the anode structure including a first p-type semiconductor layer and a second p-type semiconductor layer, the second p-type semiconductor layer having the same layer structure as the first p-type semiconductor layer. The nitride semiconductor device according to one aspect of the present disclosure is a nitride semiconductor device including an enhancement type field-effect transistor and a diode, the nitride semiconductor device comprising: a substrate; a semiconductor stack including a two-dimensional electron gas provided above the substrate; a source structure, a drain structure, and a gate structure for the field-effect transistor provided in a first region; and an anode structure and a cathode structure for the diode provided in a second region different from the first region. The gate structure includes a first p-type semiconductor layer and a first metal layer provided above the first p-type semiconductor layer. The anode structure includes a second p-type semiconductor layer and a second metal layer provided above the second p-type semiconductor layer. The second p-type semiconductor layer has the same layer structure as the first p-type semiconductor layer. The source structure is electrically connected to the anode structure, and the gate structure is electrically connected to the cathode structure. The second metal layer is formed using a material different from that of the first metal layer.

[0008] A nitride semiconductor device according to one aspect of the present disclosure is a nitride semiconductor device including an enhancement type field effect transistor and a diode, the nitride semiconductor device including: a substrate; a semiconductor stack including a two-dimensional electron gas provided above the substrate; a source structure, a drain structure, and a gate structure for the field effect transistor provided in a first region; and an anode structure and a cathode structure for the diode provided in a second region different from the first region, the gate structure including a first p-type semiconductor layer and a second p-type semiconductor layer. the anode structure includes a second p-type semiconductor layer and a second metal layer provided above the second p-type semiconductor layer, the second p-type semiconductor layer having the same layer configuration as the first p-type semiconductor layer, the source structure is electrically connected to the anode structure, the gate structure is electrically connected to the cathode structure, the first metal layer is Schottky-connected to the first p-type semiconductor layer, and the second metal layer is ohmic-connected to the second p-type semiconductor layer.

[0009] a gate structure for the field-effect transistor in a first region and an anode structure for the diode in a second region different from the first region; a step of electrically connecting the source structure to the anode structure; and a step of electrically connecting the gate structure to the cathode structure, wherein the gate structure includes a first p-type semiconductor layer and a first metal layer provided above the first p-type semiconductor layer; the anode structure includes a second p-type semiconductor layer and a second metal layer provided above the second p-type semiconductor layer; the first p-type semiconductor layer and the second p-type semiconductor layer are formed simultaneously, and at least a portion of the first metal layer and at least a portion of the second metal layer are formed in different steps.

[0010] A method for manufacturing a nitride semiconductor device according to one aspect of the present disclosure is a method for manufacturing a nitride semiconductor device including an enhancement type field effect transistor and a diode, the method including the steps of: forming a semiconductor stack containing two-dimensional electron gas above a substrate; forming a source structure, a drain structure, and a gate structure for the field effect transistor in a first region; forming an anode structure and a cathode structure for the diode in a second region different from the first region; electrically connecting the source structure and the anode structure; and electrically connecting a gate structure and the cathode structure, wherein the gate structure includes a first p-type semiconductor layer and a first metal layer provided above the first p-type semiconductor layer, the anode structure includes a second p-type semiconductor layer and a second metal layer provided above the second p-type semiconductor layer, the first p-type semiconductor layer and the second p-type semiconductor layer being formed simultaneously, the first metal layer being Schottky-connected to the first p-type semiconductor layer, and the second metal layer being ohmic-connected to the second p-type semiconductor layer.

[0011] According to the present disclosure, it is possible to provide a nitride semiconductor device capable of improving ESD resistance.

[0012] FIG. 1 is a circuit diagram of a nitride semiconductor device according to a first embodiment. FIG. 2 is a cross-sectional view of the nitride semiconductor device according to the first embodiment. FIG. 3 is a cross-sectional view of a nitride semiconductor device according to a second embodiment. FIG. 4 is a cross-sectional view of a nitride semiconductor device according to a third embodiment. FIG. 5 is a cross-sectional view of a nitride semiconductor device according to a fourth embodiment. FIG. 6 is a cross-sectional view of a nitride semiconductor device according to a fifth embodiment. FIG. 7 is a cross-sectional view of a nitride semiconductor device according to a sixth embodiment. FIG. 8 is a plan view showing a first example of a layout of an anode structure and a cathode structure of a nitride semiconductor device according to each embodiment. FIG. 9 is a plan view showing a second example of a layout of an anode structure and a cathode structure of a nitride semiconductor device according to each embodiment. FIG. 10A is a plan view showing a third example of a layout of an anode structure and a cathode structure of a nitride semiconductor device according to each embodiment. FIG. 10B is a cross-sectional view showing a third example of a layout of an anode structure and a cathode structure of a nitride semiconductor device according to each embodiment. FIG. 11A is a plan view showing a fourth example of a layout of an anode structure and a cathode structure of a nitride semiconductor device according to each embodiment. FIG. 11B is a cross-sectional view showing a fourth example of the layout of the anode structure and the cathode structure of the nitride semiconductor device according to each embodiment. FIG. 12 is a cross-sectional view of the nitride semiconductor device according to Example 1. FIG. 13 is a plan view of the nitride semiconductor device according to Example 1. FIG. 14A is a cross-sectional view for explaining a step of a manufacturing method of the nitride semiconductor device according to Example 1. FIG. 14B is a cross-sectional view for explaining a step of a manufacturing method of the nitride semiconductor device according to Example 1. FIG. 14C is a cross-sectional view for explaining a step of a manufacturing method of the nitride semiconductor device according to Example 1. FIG. 14D is a cross-sectional view for explaining a step of a manufacturing method of the nitride semiconductor device according to Example 1. FIG. 14E is a cross-sectional view for explaining a step of a manufacturing method of the nitride semiconductor device according to Example 1. FIG. 14F is a cross-sectional view for explaining a step of a manufacturing method of the nitride semiconductor device according to Example 1. FIG. 14G is a cross-sectional view for explaining a step of a manufacturing method of the nitride semiconductor device according to Example 1. FIG. 14H is a cross-sectional view for explaining a step of a manufacturing method of the nitride semiconductor device according to Example 1.FIG. 14I is a cross-sectional view illustrating a step of a manufacturing method of a nitride semiconductor device in accordance with Example 1. FIG. 15A is a plan view illustrating a step of a manufacturing method of a nitride semiconductor device in accordance with Example 1. FIG. 15B is a plan view illustrating a step of a manufacturing method of a nitride semiconductor device in accordance with Example 1. FIG. 15C is a plan view illustrating a step of a manufacturing method of a nitride semiconductor device in accordance with Example 1. FIG. 15D is a plan view illustrating a step of a manufacturing method of a nitride semiconductor device in accordance with Example 1. FIG. 15E is a plan view illustrating a step of a manufacturing method of a nitride semiconductor device in accordance with Example 1. FIG. 15F is a plan view illustrating a step of a manufacturing method of a nitride semiconductor device in accordance with Example 1. FIG. 15G is a plan view illustrating a step of a manufacturing method of a nitride semiconductor device in accordance with Example 1. FIG. 15H is a plan view illustrating a step of a manufacturing method of a nitride semiconductor device in accordance with Example 1. FIG. 16A is a cross-sectional view illustrating a step of a manufacturing method of a nitride semiconductor device in accordance with Example 2. FIG. 16B is a cross-sectional view illustrating a step of a manufacturing method of a nitride semiconductor device in accordance with Example 2. FIG. 16C is a cross-sectional view illustrating a step of a manufacturing method of a nitride semiconductor device in accordance with Example 2. 17A and 17B are cross-sectional views illustrating a step in a method for manufacturing a nitride semiconductor device according to Example 3.

[0013] (Findings that Form the Basis of the Present Disclosure) The present inventors have found that the following problems arise with the conventional semiconductor devices described in the "Background Art" section.

[0014] To improve FET characteristics such as reduced power consumption and increased switching speed, it is necessary to reduce the gate current. To reduce the gate current, a configuration can be adopted in which the gate metal layer of the FET and the p-type semiconductor layer are connected with high resistance. When a Schottky connection is adopted as an example of a high-resistance connection, in the semiconductor device described in Patent Document 1, the gate of the FET and the anode of the protection diode have the same configuration, so that the anode metal layer of the protection diode and the p-type semiconductor layer are connected with a Schottky connection. In other words, the anode contact of the ESD protection diode is connected with a Schottky connection.

[0015] When a reverse bias is applied to a Schottky diode, the ESD current applied from the anode flows from a localized area of ​​the anode contact where the Schottky diode breakdown voltage is low to a specific area in the p-type semiconductor layer. As a result, the area where the current is concentrated becomes hot due to Joule heating, melting the diode and destroying it. This causes a short circuit between the gate and source of the FET, and it ceases to function.

[0016] Therefore, an object of the present disclosure is to provide a nitride semiconductor device capable of improving the characteristics and ESD resistance of an FET, and a method for manufacturing the same.

[0017] A nitride semiconductor device according to a first aspect of the present disclosure is a nitride semiconductor device including an enhancement type field effect transistor and a diode, comprising: a substrate; a semiconductor stack including a two-dimensional electron gas provided above the substrate; a source structure, a drain structure, and a gate structure for the field effect transistor provided in a first region; and an anode structure and a cathode structure for the diode provided in a second region different from the first region, wherein the gate structure includes a first p-type semiconductor layer and a first metal layer provided above the first p-type semiconductor layer, the anode structure includes a second p-type semiconductor layer and a second metal layer provided above the second p-type semiconductor layer, the second p-type semiconductor layer has the same layer structure as the first p-type semiconductor layer, the source structure is electrically connected to the anode structure, the gate structure is electrically connected to the cathode structure, and the second metal layer is formed using a material different from that of the first metal layer.

[0018] This allows the first metal layer of the gate structure and the second metal layer of the anode structure to use materials suitable for their respective electrical connections. For example, a material that can form a Schottky contact with the first p-type semiconductor layer can be used as the material for the first metal layer, thereby reducing the gate current. Furthermore, by using a material that can form an ohmic contact with the second p-type semiconductor layer as the material for the second metal layer, local current concentration can be suppressed. Since heat generation due to local current concentration is suppressed and metal melting can be suppressed, the breakdown current of the ESD protection diode can be increased and the ESD breakdown voltage can be improved. This makes it possible to provide a nitride semiconductor device that can improve the characteristics and ESD breakdown voltage of an FET.

[0019] A nitride semiconductor device according to a second aspect of the present disclosure is the nitride semiconductor device according to the first aspect, wherein the first p-type semiconductor layer and the second p-type semiconductor layer each contain a Group III nitride semiconductor as a main component, and the second metal layer contains an alloy of Ti and Al.

[0020] This allows for ohmic contact between the second metal layer and the second p-type semiconductor layer in the anode structure. Since the contact of the anode structure of the protection diode does not become a Schottky contact, the ESD breakdown current increases, and the ESD withstand voltage can be improved.

[0021] A nitride semiconductor device according to a third aspect of the present disclosure is a nitride semiconductor device including an enhancement type field effect transistor and a diode, comprising: a substrate; a semiconductor stack including a two-dimensional electron gas provided above the substrate; a source structure, a drain structure, and a gate structure for the field effect transistor provided in a first region; and an anode structure and a cathode structure for the diode provided in a second region different from the first region, wherein the gate structure is a first p-type semiconductor layer and a second p-type semiconductor layer. the anode structure includes a second p-type semiconductor layer and a second metal layer provided above the second p-type semiconductor layer, the second p-type semiconductor layer having the same layer configuration as the first p-type semiconductor layer, the source structure being electrically connected to the anode structure, the gate structure being electrically connected to the cathode structure, the first metal layer being Schottky-connected to the first p-type semiconductor layer, and the second metal layer being ohmic-connected to the second p-type semiconductor layer.

[0022] As a result, in the gate structure, the first metal layer and the first p-type semiconductor layer are connected in a Schottky contact, thereby reducing the gate current. Also, since the contact of the anode structure does not form a Schottky contact, the ESD breakdown current increases, thereby improving the ESD breakdown voltage. This makes it possible to provide a nitride semiconductor device that can improve the FET characteristics and ESD breakdown voltage.

[0023] A nitride semiconductor device according to a fourth aspect of the present disclosure is a nitride semiconductor device according to any one of the first to third aspects, wherein the first metal layer is in contact with an upper surface of the first p-type semiconductor layer, and the second metal layer is in contact with an upper surface of the second p-type semiconductor layer.

[0024] This simplifies the layer configuration of the anode structure and gate structure, making it possible to simplify the manufacturing process and reduce costs.

[0025] A nitride semiconductor device according to a fifth aspect of the present disclosure is the nitride semiconductor device according to any one of the first to third aspects, wherein the gate structure further includes a first semiconductor layer provided between the first p-type semiconductor layer and the first metal layer, and the anode structure further includes a second semiconductor layer provided between the second p-type semiconductor layer and the second metal layer.

[0026] This allows the first semiconductor layer and the second semiconductor layer to have predetermined functions, thereby enabling further improvement in the characteristics of the FET or further improvement in the ESD withstand voltage of the ESD protection diode.

[0027] A nitride semiconductor device according to a sixth aspect of the present disclosure is the nitride semiconductor device according to the fifth aspect, wherein the first metal layer is in contact with an upper surface of the first semiconductor layer, and the second metal layer is in contact with an upper surface of the second semiconductor layer.

[0028] This allows the anode structure and the gate structure to have the same layer structure, which simplifies the manufacturing process and reduces costs.

[0029] A nitride semiconductor device according to a seventh aspect of the present disclosure is the nitride semiconductor device according to the sixth aspect, wherein the first semiconductor layer is a p-type semiconductor layer having a higher p-type impurity concentration than the first p-type semiconductor layer, and the second semiconductor layer is a p-type semiconductor layer having a higher p-type impurity concentration than the second p-type semiconductor layer.

[0030] This allows the variation in resistance and the resistance value of the ohmic connection of the anode structure to be sufficiently reduced, and heat generation due to local current concentration to be sufficiently suppressed, thereby increasing the ESD breakdown current of the diode and improving the ESD withstand voltage.

[0031] A nitride semiconductor device according to an eighth aspect of the present disclosure is the nitride semiconductor device according to the seventh aspect, wherein the first semiconductor layer is an i-type semiconductor layer having a larger band gap than the first p-type semiconductor layer, and the second semiconductor layer is an i-type semiconductor layer having a larger band gap than the second p-type semiconductor layer.

[0032] This increases the resistance of the gate structure, further reducing the gate current, thereby further improving the characteristics of the FET.

[0033] A nitride semiconductor device according to a ninth aspect of the present disclosure is the nitride semiconductor device according to the eighth aspect, wherein the second semiconductor layer and the second p-type semiconductor layer are provided with impurity regions doped with p-type impurities, the p-type impurity concentration of the impurity regions is higher than the p-type impurity concentration of a region of the second p-type semiconductor layer other than the impurity regions, and the second metal layer is in contact with the impurity regions.

[0034] This reduces the resistance of the ohmic connection of the anode structure, and suppresses heat generation due to local current concentration, thereby increasing the ESD breakdown current of the diode and improving the ESD breakdown voltage.

[0035] A nitride semiconductor device according to a tenth aspect of the present disclosure is the nitride semiconductor device according to the fifth aspect, wherein the second semiconductor layer has a recess, the second metal layer is in contact with the bottom surface of the recess, and the first metal layer is in contact with the top surface of the first semiconductor layer.

[0036] This reduces the resistance of the ohmic connection of the anode structure, and suppresses heat generation due to local current concentration, thereby increasing the ESD breakdown current of the diode and improving the ESD breakdown voltage.

[0037] A nitride semiconductor device according to an eleventh aspect of the present disclosure is the nitride semiconductor device according to the tenth aspect, wherein the recess is an opening penetrating the second semiconductor layer, and the second metal layer is in contact with the second p-type semiconductor layer at the bottom surface of the recess.

[0038] This reduces the resistance of the ohmic connection of the anode structure, and suppresses heat generation due to local current concentration, thereby increasing the ESD breakdown current of the diode and improving the ESD breakdown voltage.

[0039] A nitride semiconductor device according to a twelfth aspect of the present disclosure is the nitride semiconductor device according to the eleventh aspect, wherein the second p-type semiconductor layer has an impurity region doped with p-type impurities, the p-type impurity concentration of the impurity region is higher than the p-type impurity concentration of a region of the second p-type semiconductor layer other than the impurity region, and the second metal layer is in contact with the impurity region.

[0040] This reduces the resistance of the ohmic connection of the anode structure, and suppresses heat generation due to local current concentration, thereby increasing the ESD breakdown current of the diode and improving the ESD breakdown voltage.

[0041] A nitride semiconductor device according to a thirteenth aspect of the present disclosure is a nitride semiconductor device according to any one of the first to twelfth aspects, wherein the second metal layer has an elongated shape in one direction in a planar view, and the connection between the second metal layer and the second p-type semiconductor layer is discrete along the one direction.

[0042] This allows the ESD current to flow evenly within the p-type semiconductor layer and suppresses heat generation due to local current concentration, thereby increasing the ESD breakdown current of the diode and improving the ESD breakdown voltage.

[0043] A nitride semiconductor device according to a fourteenth aspect of the present disclosure is a nitride semiconductor device according to any one of the first to twelfth aspects, wherein the cathode structure is arranged in a lattice pattern in a planar view, and the anode structure is arranged at each opening of the lattice-shaped cathode structure in a planar view.

[0044] This allows the ESD current to flow evenly within the p-type semiconductor layer and suppresses heat generation due to local current concentration, thereby increasing the ESD breakdown current of the diode and improving the ESD breakdown voltage.

[0045] A nitride semiconductor device according to a fifteenth aspect of the present disclosure is a nitride semiconductor device according to any one of the first to twelfth aspects, wherein the cathode structure is provided in a ring shape along the outer periphery of the second region in a planar view, and the anode structure is surrounded by the cathode structure in a planar view.

[0046] This allows the anode structure to have a larger area, thereby suppressing heat generation due to local current concentration, thereby increasing the ESD breakdown current of the diode and improving the ESD breakdown voltage.

[0047] a gate structure for the field-effect transistor in a first region and an anode structure and a cathode structure for the diode in a second region different from the first region; electrically connecting the source structure to the anode structure; and electrically connecting the gate structure to the cathode structure, wherein the gate structure includes a first p-type semiconductor layer and a first metal layer provided above the first p-type semiconductor layer; the anode structure includes a second p-type semiconductor layer and a second metal layer provided above the second p-type semiconductor layer; the first p-type semiconductor layer and the second p-type semiconductor layer are formed simultaneously, and at least a portion of the first metal layer and at least a portion of the second metal layer are formed in different steps.

[0048] This allows the first metal layer of the gate structure and the second metal layer of the anode structure to use materials suitable for their respective electrical connections. For example, a material that can form a Schottky contact with the first p-type semiconductor layer can be used as the material for the first metal layer, thereby reducing the gate current. Furthermore, by using a material that can form an ohmic contact with the second p-type semiconductor layer as the material for the second metal layer, local current concentration can be suppressed. Heat generation due to local current concentration is suppressed, and metal melting can be suppressed, thereby ensuring the function as an ESD protection diode. This allows the manufacture of a nitride semiconductor device that can improve the characteristics and ESD breakdown voltage of the FET.

[0049] A method for manufacturing a nitride semiconductor device according to a seventeenth aspect of the present disclosure is the method for manufacturing a nitride semiconductor device according to the sixteenth aspect, wherein in the step of forming the anode structure, a Ti film and an Al film are formed in this order on the second p-type semiconductor layer as the second metal layer, and then heat treatment is performed to alloy the Ti of the Ti film and the Al of the Al film.

[0050] This allows for ohmic contact between the second metal layer and the second p-type semiconductor layer in the anode structure. Since the contact of the anode structure of the protection diode is not a Schottky contact, the ESD breakdown current increases and the ESD breakdown voltage increases. Thus, according to this aspect, the ESD breakdown current increases and the ESD breakdown voltage can be improved.

[0051] A method for manufacturing a nitride semiconductor device according to an eighteenth aspect of the present disclosure is the method for manufacturing a nitride semiconductor device according to the seventeenth aspect, wherein the heat treatment is performed by laser annealing.

[0052] This allows alloying of Ti and Al.

[0053] A nineteenth aspect of the present disclosure provides a method for manufacturing a nitride semiconductor device including an enhancement type field effect transistor and a diode, the method including the steps of: forming a semiconductor stack containing two-dimensional electron gas above a substrate; forming a source structure, a drain structure, and a gate structure for the field effect transistor in a first region; and forming an anode structure and a cathode structure for the diode in a second region different from the first region; electrically connecting the source structure and the anode structure; and electrically connecting a gate structure and the cathode structure, wherein the gate structure includes a first p-type semiconductor layer and a first metal layer provided above the first p-type semiconductor layer, the anode structure includes a second p-type semiconductor layer and a second metal layer provided above the second p-type semiconductor layer, the first p-type semiconductor layer and the second p-type semiconductor layer being formed simultaneously, the first metal layer being Schottky-connected to the first p-type semiconductor layer, and the second metal layer being ohmic-connected to the second p-type semiconductor layer.

[0054] As a result, in the gate structure, the first metal layer and the first p-type semiconductor layer are connected in a Schottky contact, thereby reducing the gate current. Also, since the contact of the anode structure of the protection diode is not a Schottky contact, the ESD breakdown current increases and the ESD breakdown voltage can be improved. This makes it possible to manufacture a nitride semiconductor device that can improve the FET characteristics and ESD breakdown voltage.

[0055] A method for manufacturing a nitride semiconductor device according to a twentieth aspect of the present disclosure is a method for manufacturing a nitride semiconductor device according to any one of the sixteenth to nineteenth aspects, wherein in the step of forming the gate structure and the anode structure, a first semiconductor layer is formed on the first p-type semiconductor layer, and a second semiconductor layer is formed on the second p-type semiconductor layer, and the first semiconductor layer and the second semiconductor layer are formed simultaneously.

[0056] This simplifies the layer configuration of the anode structure and gate structure, making it possible to simplify the manufacturing process and reduce costs.

[0057] A method for manufacturing a nitride semiconductor device according to a twenty-first aspect of the present disclosure is the method for manufacturing a nitride semiconductor device according to the twentieth aspect, wherein in the step of forming the anode structure, p-type impurities are added by performing ion implantation into the second semiconductor layer and the second p-type semiconductor layer, and the p-type impurity concentration in the region where the ion implantation has been performed is higher than the p-type impurity concentration in the region of the second p-type semiconductor layer where the ion implantation has not been performed.

[0058] This reduces the resistance of the ohmic connection of the anode structure, and suppresses heat generation due to local current concentration, thereby increasing the ESD breakdown current of the diode and improving the ESD breakdown voltage.

[0059] A manufacturing method of a nitride semiconductor device according to a 22nd aspect of the present disclosure is the manufacturing method of a nitride semiconductor device according to the 20th aspect, wherein in the step of forming the anode structure, a recess or an opening exposing the second p-type semiconductor layer is formed by removing at least a portion of the second semiconductor layer, and the second metal layer is formed so as to cover a bottom surface of the recess or to be in contact with the second p-type semiconductor layer through the opening.

[0060] This reduces the resistance of the ohmic connection of the anode structure, and suppresses heat generation due to local current concentration, thereby increasing the ESD breakdown current of the diode and improving the ESD breakdown voltage.

[0061] Hereinafter, the embodiments will be specifically described with reference to the drawings.

[0062] The embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, component placement and connection configurations, steps, and step order shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Furthermore, among the components in the following embodiments, components not described in the independent claims are described as optional components.

[0063] Furthermore, each figure is a schematic diagram and is not necessarily an exact illustration. Therefore, for example, the scales of the figures do not necessarily match. Furthermore, in each figure, substantially the same components are given the same reference numerals, and redundant explanations are omitted or simplified.

[0064] Furthermore, in this specification, terms indicating the relationship between elements, such as parallel and perpendicular, terms indicating the shape of elements, and numerical ranges are not expressions that only express a strict meaning, but are expressions that also include a substantially equivalent range, for example, a difference of about a few percent.

[0065] In addition, in this specification, the terms "above" and "below" do not refer to the upward direction (vertically upward) and downward direction (vertically downward) in absolute spatial recognition, but are used as terms defined by a relative positional relationship based on the stacking order in a stacked structure. Furthermore, the terms "above" and "below" are applied not only to a case where two components are arranged with a gap between them and another component is present between the two components, but also to a case where two components are arranged closely together and the two components are in contact with each other. In this specification, the direction in which the gate electrode is provided with respect to the substrate is considered to be "above."

[0066] In this specification, unless otherwise specified, the term "plan view" refers to a view from a direction perpendicular to the top or bottom surface of the substrate.

[0067] In this specification, a nitride semiconductor refers to a Group III nitride semiconductor containing one or more Group III elements and nitrogen. Examples of Group III elements include aluminum (Al), gallium (Ga), and indium (In). Examples of Group III nitride semiconductors include GaN, AlN, InN, AlGaN, InGaN, and AlInGaN. Group III nitride semiconductors may also contain one or more elements other than Group III elements, such as silicon (Si), phosphorus (P), and magnesium (Mg). In the following description, unless otherwise specified, the term "AlInGaN" means that the Group III nitride semiconductor contains all of Al, In, Ga, and N. The same applies to other designations such as AlGaN and GaN.

[0068] In this specification, the term "metal layer" refers not only to a layer having electrical conductivity mainly composed of a metal or alloy, but also to a layer having electrical conductivity mainly composed of a metal compound. For example, a layer containing a conductive metal nitride such as TiN or TaN as a main component is also considered to be an example of a metal layer.

[0069] In this specification, the composition ratio of a group III element in a nitride semiconductor (layer) refers to the ratio of the number of atoms of a target group III element among a plurality of group III elements contained in the nitride semiconductor. ａ In ｂ Ga ｃ In the case where the nitride semiconductor layer is made of N (a+b+c=1, a≧0, b≧0, c≧0), the Al composition ratio of the nitride semiconductor layer can be expressed as a / (a+b+c). Similarly, the In composition ratio and the Ga composition ratio can be expressed as b / (a+b+c) and c / (a+b+c), respectively.

[0070] In this specification, n-type and p-type refer to the conductivity type of a semiconductor, and are conductivity types of opposite polarity. The i-type typically refers to a so-called undoped state in which no n-type or p-type dopant is added. An i-type semiconductor layer may be doped with an n-type or p-type dopant, provided that the n-type or p-type dopant is not activated. The i-type semiconductor layer may be doped with impurities other than n-type or p-type dopants.

[0071] In this specification, the term "major component" refers to the component with the highest content among all components constituting a member. For example, a component with a content of 50% or more is a major component. A component may be a material, an element, or a compound.

[0072] First Embodiment First, the circuit configuration of a nitride semiconductor device according to a first embodiment will be described with reference to Fig. 1. Fig. 1 is a circuit diagram of a nitride semiconductor device 1 according to the present embodiment.

[0073] As shown in FIG. 1 , the nitride semiconductor device 1 includes an enhancement-type (normally-off) FET 11 and a diode 12. The FET 11 is also called a HEMT (High Electron Mobility Transistor). The diode 12 is provided for ESD protection of the FET 11 and is connected between the gate and source of the FET 11. Specifically, the anode of the diode 12 is connected to the source of the FET 11, and the cathode of the diode 12 is connected to the gate of the FET 11. Note that a plurality of diodes 12 may be connected in series or in parallel between the source and gate of the FET 11.

[0074] When assembling a chip into a package and wire-bonding it, or when mounting the finished product on a substrate, a surge is instantaneously applied from the source pad or source pin. In this case, as shown by the dotted arrow in Figure 1, a current (ESD current) flows between the source and gate of FET 11 via diode 12. This prevents the ESD current from flowing between the source and gate of FET 11 and destroying FET 11.

[0075] Next, a cross-sectional configuration of the nitride semiconductor device 1 according to this embodiment will be described with reference to Fig. 2. Fig. 2 is a cross-sectional view of the nitride semiconductor device 1 according to this embodiment. In Fig. 2, the electrical connection between the source structure 50S and gate structure 50G of the FET 11 and the anode structure 50A and cathode structure 50K of the diode 12 is schematically represented by thick solid lines. Furthermore, the source pad 70S, drain pad 70D, and gate pad 70G are schematically represented by circles.

[0076] As shown in FIG. 2 , the nitride semiconductor device 1 includes a first active region 21 and a second active region 22. The first active region 21 is an example of a first region, and is a region where the main components of the FET 11 are provided. The second active region 22 is an example of a second region, and is a region where the main components of the diode 12 are provided. The second active region 22 is a region different from the first active region 21. Specifically, the first active region 21 and the second active region 22 are spatially separated in a planar view. "Spatial separation" means that the two regions are provided without overlapping or mixing. The first active region 21 and the second active region 22 are separated by an inactive region 44.

[0077] The nitride semiconductor device 1 includes a substrate 30, a semiconductor stack 40, a source structure 50S, a drain structure 50D, and a gate structure 50G for the FET 11, an anode structure 50A and a cathode structure 50K for the diode 12, and an insulating layer 60. The source structure 50S, the drain structure 50D, and the gate structure 50G are provided in a first active region 21. The anode structure 50A and the cathode structure 50K are provided in a second active region 22. The nitride semiconductor device 1 also includes a source pad 70S, a drain pad 70D, and a gate pad 70G. The nitride semiconductor device 1 may also include source wiring, drain wiring, and gate wiring. Each wiring and each pad may be formed integrally.

[0078] In the example shown in FIG. 2 , two anode structures 50A are provided sandwiching a cathode structure 50K therebetween, but this is not limiting. The nitride semiconductor device 1 may include one anode structure 50A and one cathode structure 50K. Alternatively, in the second active region 22, a plurality of diode units may be provided repeatedly, each including an anode structure 50A and a cathode structure 50K. Furthermore, in the first active region 21, a plurality of FET units may be provided repeatedly, each including a source structure 50S, a gate structure 50G, and a drain structure 50D. Adjacent FET units may share the source structure 50S or the drain structure 50D.

[0079] The substrate 30 is a semiconductor substrate such as a Si substrate, but may also be a substrate including an insulating portion such as an SOI (Silicon On Insulator) substrate, or may be an insulating substrate. For example, the substrate 30 may be a substrate containing SiC, sapphire, diamond, GaN, AlN, or the like as a main component.

[0080] The semiconductor stack 40 is provided above the substrate 30. Specifically, the semiconductor stack 40 contacts and covers the upper surface of the substrate 30. The semiconductor stack 40 has a stacked structure of nitride semiconductor layers. Specifically, the semiconductor stack 40 includes a channel layer 41 and a barrier layer 42. The semiconductor stack 40 also includes a 2DEG 43. The semiconductor stack further includes an inactive region 44.

[0081] The channel layer 41 is a layer containing a nitride semiconductor as a main component, such as an undoped GaN layer or an undoped InGaN layer. The thickness of the channel layer 41 is, for example, 100 nm to 200 nm, for example, 150 nm. The channel layer 41 includes a 2DEG 43 that functions as a main current path of the nitride semiconductor device 1.

[0082] The barrier layer 42 is a layer containing a nitride semiconductor as a main component, and is provided above the channel layer 41. For example, the barrier layer 42 contacts and covers the upper surface of the channel layer 41. The barrier layer 42 has a larger band gap than the channel layer 41. The barrier layer 42 is, for example, an undoped AlGaN layer. The thickness of the barrier layer 42 is, for example, 40 nm to 80 nm, for example, 60 nm. The barrier layer 42 functions as a supply source of electrons for the 2DEG 43.

[0083] The 2DEG 43 is generated near the interface between the channel layer 41 and the barrier layer 42. The channel layer 41 and the barrier layer 42 are formed using different types of materials, and the interface between the channel layer 41 and the barrier layer 42 is called a heterointerface. For example, if the channel layer 41 is a GaN layer and the barrier layer 42 is an AlGaN layer, electrons generated due to piezoelectric polarization and spontaneous polarization caused by the difference in lattice constants between GaN and AlGaN migrate to the channel layer 41, which has a smaller band gap, and are confined in the thickness direction near the heterointerface. Electrons gathered near the heterointerface can move laterally (in a direction parallel to the major surface of the substrate 30). In this way, the 2DEG 43 is formed in the channel layer 41 near the interface between the channel layer 41 and the barrier layer 42.

[0084] In this embodiment, the 2DEG 43 generated in the first active region 21 is a path (channel) through which the drain current of the FET 11 flows. The 2DEG 43 generated in the second active region 22 is a path through which the ESD current flows. The 2DEG 43 has high electron mobility and high concentration, making it possible to realize a high-speed, large-current FET 11. Furthermore, because the 2DEG 43 can pass a large ESD current, the breakdown current of the diode 12 increases, thereby improving the ESD breakdown voltage.

[0085] The inactive region 44 is a part of the barrier layer 42 and the channel layer 41, and is a region into which impurities (e.g., boron) are implanted to inactivate the 2DEG 43. The inactive region 44 is also called an ion-implanted region, an element isolation region, or the like. By providing the inactive region 44, the 2DEG 43 can be electrically isolated between the first active region 21 and the second active region 22.

[0086] As long as the 2DEG 43 can be separated, a groove that penetrates the barrier layer 42 and removes a part of the channel layer 41 may be provided instead of the inactive region 44. An insulating layer may be buried in the groove.

[0087] The semiconductor stack 40 may further include other nitride semiconductor layers such as a buffer layer. For example, the buffer layer is a nitride semiconductor layer provided between the substrate 30 and the channel layer 41. The buffer layer is provided to reduce lattice mismatch between the channel layer 41 and the substrate 30. The buffer layer may be a single layer of AlN or a stacked structure of an AlN layer and an AlGaN layer, but is not particularly limited thereto.

[0088] The source structure 50S functions as the source of the FET 11. The source structure 50S is electrically connected to the anode structure 50A of the diode 12. The source structure 50S is also electrically connected to a source pad 70S. The source pad 70S is, for example, a pad to which a bonding wire is connected, and is connected to a circuit external to the nitride semiconductor device 1. An example of a specific configuration of the source pad 70S will be described later based on an embodiment.

[0089] The source structure 50S includes a conductive source electrode 55S. The source electrode 55S is electrically connected to the 2DEG 43 in the first active region 21. Specifically, the source electrode 55S is provided in the first active region 21 and is ohmic-connected to the 2DEG 43 in the first active region 21.

[0090] The source electrode 55S includes a stacked structure of a TiAl alloy layer 56S and an Al layer 57S. The TiAl alloy layer 56S is in contact with the upper surface of the semiconductor stack 40 (the upper surface of the barrier layer 42) through an opening 61S provided in the insulating layer 60. The TiAl alloy layer 56S is a conductive layer containing an alloy of Ti and Al as a main component, for example, an alloy layer containing substantially only TiAl alloy. The thickness of the TiAl alloy layer 56S is 10 nm to 40 nm, for example, 20 nm. The Al layer 57S covers and contacts the upper surface of the TiAl alloy layer 56S. The Al layer 57S is a conductive layer containing Al as a main component, for example, a metal element layer containing substantially only Al. The thickness of the Al layer 57S is 200 nm to 600 nm, for example, 400 nm.

[0091] The drain structure 50D functions as the drain of the FET 11. The drain structure 50D is electrically connected to a drain pad 70D. The drain pad 70D is, for example, a pad to which a bonding wire is connected, and is connected to a circuit external to the nitride semiconductor device 1. An example of a specific configuration of the drain pad 70D will be described later based on an embodiment.

[0092] The drain structure 50D includes a conductive drain electrode 55D. The drain electrode 55D is electrically connected to the 2DEG 43 in the first active region 21. Specifically, the drain electrode 55D is provided in the first active region 21 and is ohmic-connected to the 2DEG 43 in the first active region 21.

[0093] The drain electrode 55D includes a stacked structure of a TiAl alloy layer 56D and an Al layer 57D. The TiAl alloy layer 56D is in contact with the upper surface of the semiconductor stack 40 (the upper surface of the barrier layer 42) through an opening 61D provided in the insulating layer 60. The TiAl alloy layer 56D is a conductive layer containing an alloy of Ti and Al as a main component, for example, an alloy layer containing substantially only TiAl alloy. The thickness of the TiAl alloy layer 56D is 10 nm to 40 nm, for example, 20 nm. The Al layer 57D contacts and covers the upper surface of the TiAl alloy layer 56D. The Al layer 57D is a conductive layer containing Al as a main component, for example, a metal element layer containing substantially only Al. The thickness of the Al layer 57D is 200 nm to 600 nm, for example, 400 nm.

[0094] The gate structure 50G functions as the gate of the FET 11. The gate structure 50G is provided between the source structure 50S and the drain structure 50D. The gate structure 50G is electrically connected to the cathode structure 50K of the diode 12. The gate structure 50G is also electrically connected to a gate pad 70G. The gate pad 70G is, for example, a pad to which a bonding wire is connected, and is connected to a circuit external to the nitride semiconductor device 1. An example of a specific configuration of the gate pad 70G will be described later based on an embodiment.

[0095] The gate structure 50G includes a first p-type semiconductor layer 51G and a conductive gate electrode 55G.

[0096] The first p-type semiconductor layer 51G is provided above the semiconductor stack 40 (barrier layer 42) in the first active region 21. Specifically, the first p-type semiconductor layer 51G is in contact with the upper surface of the barrier layer 42. The first p-type semiconductor layer 51G contains a p-type nitride semiconductor as a main component. For example, the first p-type semiconductor layer 51G has a single layer or stacked layer structure of a p-type GaN layer or a p-type InGaN layer. The first p-type semiconductor layer 51G is doped with, for example, Mg as a p-type impurity. The p-type impurity concentration of the first p-type semiconductor layer 51G is 1×10 １７ cm －３ 1x10 or more １８ cm －３ As an example, １７ cm －３ The thickness of the first p-type semiconductor layer 51G is, for example, 100 nm or more and 300 nm or less, and is, for example, 180 nm. By providing the first p-type semiconductor layer 51G, a depletion layer from the first p-type semiconductor layer 51G extends to the region where the 2DEG 43 is formed, and when the first p-type semiconductor layer 51G is at 0 V, the 2DEG 43 below the first p-type semiconductor layer 51G is cut off. This makes it possible to realize a normally-off (enhancement type) FET 11.

[0097] The gate electrode 55G is an example of a first metal layer and is provided above the first p-type semiconductor layer 51G. Specifically, the gate electrode 55G is in contact with the upper surface of the first p-type semiconductor layer 51G through an opening 61G provided in the insulating layer 60. The gate electrode 55G is electrically connected to the first p-type semiconductor layer 51G. Specifically, the gate electrode 55G is Schottky-connected to the first p-type semiconductor layer 51G.

[0098] The gate electrode 55G includes a stacked structure of a TiN layer 56G and an Al layer 57G. The TiN layer 56G is in contact with the upper surface of the first p-type semiconductor layer 51G through an opening 61G provided in the insulating layer 60. The TiN layer 56G is a conductive layer containing TiN as a main component, for example, a conductive metal nitride layer containing substantially only TiN. The thickness of the TiN layer 56G is 10 nm to 40 nm, for example, 20 nm. The Al layer 57G contacts and covers the upper surface of the TiN layer 56G. The Al layer 57G is a conductive layer containing Al as a main component, for example, a metal element layer containing substantially only Al. The thickness of the Al layer 57G is 200 nm to 600 nm, for example, 400 nm.

[0099] The anode structure 50A functions as the anode of the diode 12. The anode structure 50A is provided alongside the cathode structure 50K in a plan view. The anode structure 50A is electrically connected to the source structure 50S of the FET 11. The anode structure 50A includes a second p-type semiconductor layer 51A and a conductive anode electrode 55A.

[0100] The second p-type semiconductor layer 51A is provided above the semiconductor stack 40 (barrier layer 42) in the second active region 22. Specifically, the second p-type semiconductor layer 51A is in contact with the upper surface of the barrier layer 42. The second p-type semiconductor layer 51A contains a p-type nitride semiconductor as a main component. For example, the second p-type semiconductor layer 51A has a single layer or stacked layer structure of a p-type GaN layer or a p-type InGaN layer. The second p-type semiconductor layer 51A is doped with, for example, Mg as a p-type impurity. The p-type impurity concentration of the second p-type semiconductor layer 51A is 1×10 １７ cm －３ 1x10 or more １８ cm －３ As an example, １７ cm －３The thickness of the second p-type semiconductor layer 51A is, for example, 100 nm to 300 nm, for example, 180 nm. The second p-type semiconductor layer 51A forms a pn junction with the 2DEG 43. In other words, the diode 12 is a pn diode formed by the second p-type semiconductor layer 51A and the 2DEG 43.

[0101] The anode electrode 55A is an example of a second metal layer and is provided above the second p-type semiconductor layer 51A. Specifically, the anode electrode 55A is in contact with the upper surface of the second p-type semiconductor layer 51A through an opening 61A provided in the insulating layer 60. The anode electrode 55A is electrically connected to the second p-type semiconductor layer 51A. Specifically, the anode electrode 55A is ohmically connected to the second p-type semiconductor layer 51A. Furthermore, for example, the anode electrode 55A is formed using a different material from that of the gate electrode 55G. Specifically, at least a portion of the anode electrode 55A includes an alloy of Ti and Al.

[0102] The anode electrode 55A includes a stacked structure of a TiAl alloy layer 56A and an Al layer 57A. The TiAl alloy layer 56A is in contact with the upper surface of the second p-type semiconductor layer 51A through an opening 61A provided in the insulating layer 60. The TiAl alloy layer 56A is a conductive layer containing an alloy of Ti and Al as a main component, for example, an alloy layer containing substantially only TiAl alloy. The thickness of the TiAl alloy layer 56A is 10 nm to 40 nm, for example, 20 nm. The Al layer 57A contacts and covers the upper surface of the TiAl alloy layer 56A. The Al layer 57A is a conductive layer containing Al as a main component, for example, an elemental metal layer containing substantially only Al. The thickness of the Al layer 57A is 200 nm to 600 nm, for example, 400 nm.

[0103] The cathode structure 50K functions as the cathode of the diode 12. The cathode structure 50K is electrically connected to the gate structure 50G of the FET 11. The cathode structure 50K includes a conductive cathode electrode 55K. The cathode electrode 55K is electrically connected to the 2DEG 43 in the second active region 22. Specifically, the cathode electrode 55K is provided in the second active region 22 and is ohmic-connected to the 2DEG 43 in the second active region 22.

[0104] The cathode electrode 55K includes a stacked structure of a TiAl alloy layer 56K and an Al layer 57K. The TiAl alloy layer 56K is in contact with the upper surface of the semiconductor stack 40 (the upper surface of the barrier layer 42) through an opening 61K provided in the insulating layer 60. The TiAl alloy layer 56K is a conductive layer containing an alloy of Ti and Al as a main component, for example, an alloy layer containing substantially only TiAl alloy. The thickness of the TiAl alloy layer 56K is 10 nm to 40 nm, for example, 20 nm. The Al layer 57K contacts and covers the upper surface of the TiAl alloy layer 56K. The Al layer 57K is a conductive layer containing Al as a main component, for example, a metal element layer containing substantially only Al. The thickness of the Al layer 57K is 200 nm to 600 nm, for example, 400 nm.

[0105] In this embodiment, the source structure 50S, the drain structure 50D, and the cathode structure 50K have the same layer structure. "The same layer structure" means that one or more layers constituting the two structures are formed using the same film formation process. Layers formed using the same film formation process have the same composition, impurity concentration, film thickness, etc. Note that after being formed using the same film formation process, other processes such as ion implantation and etching may be performed on only one of the structures. If other processes are performed, the impurity concentration and film thickness may differ even if the "same layer structure" is used.

[0106] For example, the TiAl alloy layer 56S of the source structure 50S, the TiAl alloy layer 56D of the drain structure 50D, and the TiAl alloy layer 56K of the cathode structure 50K have the same layer structure. The TiAl alloy layer 56A of the anode structure 50A also has the same layer structure. Specifically, the TiAl alloy layers 56S, 56D, 56K, and 56A are formed using the same film formation process, and each has the same composition and film thickness. The Al layer 57S of the source structure 50S, the Al layer 57D of the drain structure 50D, the Al layer 57K of the cathode structure 50K, and the Al layer 57A of the anode structure 50A also have the same layer structure. Specifically, the Al layers 57S, 57D, 57K, and 57A are formed using the same film formation process, and each has the same composition and film thickness.

[0107] The second p-type semiconductor layer 51A of the anode structure 50A has the same layer configuration as the first p-type semiconductor layer 51G of the gate structure 50G. The second p-type semiconductor layer 51A and the first p-type semiconductor layer 51G are formed in the same film formation process, and have the same composition and film thickness.

[0108] The insulating layer 60 is an insulating protective layer that covers the upper surface of the semiconductor laminate 40. Specifically, the insulating layer 60 covers the upper surface of the semiconductor laminate 40 and the upper and side surfaces of each of the first p-type semiconductor layer 51G and the second p-type semiconductor layer 51A. The insulating layer 60 has a single layer structure of, for example, a SiN film, but may also have a SiO ２ The insulating layer 60 may have a laminated structure including a film. The thickness of the insulating layer 60 is 100 nm or more and 200 nm or less, for example, 140 nm.

[0109] The insulating layer 60 also has openings 61S, 61D, 61G, 61A, and 61K. The opening 61S is provided to electrically connect the source electrode 55S and the 2DEG 43, and the barrier layer 42 is exposed at the bottom of the opening 61S. The opening 61D is provided to electrically connect the drain electrode 55D and the 2DEG 43, and the barrier layer 42 is exposed at the bottom of the opening 61D. The opening 61G is provided to electrically connect the gate electrode 55G and the first p-type semiconductor layer 51G, and the first p-type semiconductor layer 51G is exposed at the bottom of the opening 61G. The opening 61K is provided to electrically connect the cathode electrode 55K and the 2DEG 43, and the barrier layer 42 is exposed at the bottom of the opening 61K. The opening 61A is provided to electrically connect the anode electrode 55A and the second p-type semiconductor layer 51A, and the second p-type semiconductor layer 51A is exposed at the bottom of the opening 61A.

[0110] As described above, in the nitride semiconductor device 1 according to the present embodiment, the anode structure 50A of the diode 12 is electrically connected to the source structure 50S of the FET 11, and the cathode structure 50K of the diode 12 is electrically connected to the gate structure 50G of the FET 11. Therefore, even if a surge is applied from the source to the gate, the ESD current flows to the gate via the diode 12. As a result, the ESD current does not flow to the gate structure 50G of the FET 11, and therefore the FET 11 is not destroyed, and the FET 11 can be protected.

[0111] In this embodiment, the gate electrode 55G of the gate structure 50G and the anode electrode 55A of the anode structure 50A are formed using different materials. Specifically, the gate electrode 55G includes a TiN layer 56G, while the anode electrode 55A includes a TiAl alloy layer 56A. This allows the TiN layer 56G to be Schottky-connected to the first p-type semiconductor layer 51G, thereby reducing the gate current and improving the characteristics of the FET 11.

[0112] Furthermore, since the TiAl alloy layer 56A is ohmically connected to the second p-type semiconductor layer 51A, local current concentration between the second p-type semiconductor layer 51A and the TiAl alloy layer 56A can be suppressed. This allows the ESD current to flow evenly through the second p-type semiconductor layer 51A, suppressing high temperatures due to Joule heating. Since metal melting due to heat generation is suppressed, the function of the diode 12 is maintained and the ESD resistance voltage can be improved. Thus, according to this embodiment, a nitride semiconductor device 1 can be realized that can improve the characteristics and ESD resistance voltage of the FET 11.

[0113] Next, a second embodiment will be described. The second embodiment is mainly different from the first embodiment in that the gate structure 50G and the anode structure 50A have a semiconductor stack structure including a p-type semiconductor layer. Below, the differences from the first embodiment will be described, and the description of the commonalities will be omitted or simplified.

[0114] 3 is a cross-sectional view of the nitride semiconductor device 2 according to this embodiment. As shown in FIG. 3, the nitride semiconductor device 2 is different from the nitride semiconductor device 1 shown in FIG. 2 in the configurations of the gate structure 50G and the anode structure 50A. Specifically, the gate structure 50G of the nitride semiconductor device 2 is a first p ＋ The anode structure 50A of the nitride semiconductor device 2 further includes a second p-type semiconductor layer 52G. ＋ The semiconductor layer 52A is further provided.

[0115] First p ＋ The p-type semiconductor layer 52G is an example of a first semiconductor layer, and is provided between the first p-type semiconductor layer 51G and the gate electrode 55G. ＋ The p-type semiconductor layer 52G ＋ The first p-type nitride semiconductor is a main component. ＋ The p-type semiconductor layer 52G ＋ GaN layer or p ＋ It has a single layer or multilayer structure such as a p-type AlGaN layer. ＋ The first p-type semiconductor is a type of p-type semiconductor and is also called a heavily doped semiconductor. ＋The first p-type semiconductor layer 52G has a higher p-type impurity concentration than the first p-type semiconductor layer 51G. ＋ The p-type impurity concentration of the p-type semiconductor layer 52G is 1×10 １８ cm －３ 1x10 or more ２０ cm －３ For example, 5×10 １９ cm －３ The first p ＋ The thickness of the gate electrode 55G (specifically, the TiN layer 56G) is the first p ＋ The insulating layer 52G is in contact with the upper surface of the insulating layer 52G.

[0116] Second p ＋ The p-type semiconductor layer 52A is an example of a second semiconductor layer, and is provided between the second p-type semiconductor layer 51A and the anode electrode 55A. ＋ The p-type semiconductor layer 52A is ＋ The second p ＋ The p-type semiconductor layer 52A is ＋ GaN layer or p ＋ The second p-type AlGaN layer has a single layer or a multilayer structure. ＋ The second p-type semiconductor layer 52A has a higher p-type impurity concentration than the second p-type semiconductor layer 51A. ＋ The p-type impurity concentration of the p-type semiconductor layer 52A is 1×10 １８ cm －３ 1x10 or more ２０ cm －３ For example, 5×10 １９ cm －３ The second p ＋ The thickness of the anode electrode 55A (specifically, the TiAl alloy layer 56A) is 5 nm or more and 100 nm or less, for example, 5 nm. ＋ The TiAl alloy layer 56A is in contact with the upper surface of the second p-type semiconductor layer 52A. ＋ The p-type semiconductor layer 52A and the second p-type semiconductor layer 51A are ohmic-connected.

[0117] Also, the second p of the anode structure 50A ＋ The first p-type semiconductor layer 52A of the gate structure 50G ＋ The second p-type semiconductor layer 52G has the same layer structure as the second p-type semiconductor layer 52G. ＋ The first p-type semiconductor layer 52A and the second p-type semiconductor layer 52B ＋ The second semiconductor layer 52G is formed in the same film formation process, and has the same composition and film thickness.

[0118] As described above, in the anode structure 50A of the nitride semiconductor device 2 according to this embodiment, the second p ＋ The contact between the type semiconductor layer 52A and the TiAl alloy layer 56A can suppress variations in contact resistance at the contact surface. ＋ Since a low-resistance ohmic contact can be realized between the second p-type semiconductor layer 52A and the TiAl alloy layer 56A, the ESD current is ＋ This allows the metal layer 52A to flow more uniformly. This further suppresses Joule heat-induced temperature rises, thereby suppressing metal melting due to heat generation. This maintains the functionality of the diode 12 and improves ESD resistance.

[0119] (Embodiment 3) Next, embodiment 3 will be described. In embodiment 3, a main difference from embodiment 1 is that the gate structure 50G and the anode structure 50A have a semiconductor stack structure including an i-type semiconductor layer. Below, the differences from embodiment 1 will be described, and the description of the commonalities will be omitted or simplified.

[0120] 4 is a cross-sectional view of a nitride semiconductor device 3 according to this embodiment. As shown in Fig. 4, the nitride semiconductor device 3 differs from the nitride semiconductor device 1 shown in Fig. 2 in the configurations of a gate structure 50G and an anode structure 50A. Specifically, the gate structure 50G of the nitride semiconductor device 3 further includes a first i-type semiconductor layer 53G. The anode structure 50A of the nitride semiconductor device 3 further includes a second i-type semiconductor layer 53A.

[0121] The first i-type semiconductor layer 53G is an example of a first semiconductor layer and is provided between the first p-type semiconductor layer 51G and the gate electrode 55G. The first i-type semiconductor layer 53G has a larger band gap than the first p-type semiconductor layer 51G. The first i-type semiconductor layer 53G contains an i-type nitride semiconductor as a main component. For example, the first i-type semiconductor layer 53G has a single layer or multilayer structure of an i-type AlGaN layer or an i-type GaN layer. The thickness of the first i-type semiconductor layer 53G is 10 nm to 50 nm, for example, 20 nm. In this embodiment, the gate electrode 55G (specifically, a TiN layer 56G) is in contact with the upper surface of the first i-type semiconductor layer 53G. The TiN layer 56G is Schottky-coupled to the first p-type semiconductor layer 51G via the first i-type semiconductor layer 53G.

[0122] The second i-type semiconductor layer 53A is an example of a second semiconductor layer and is provided between the second p-type semiconductor layer 51A and the anode electrode 55A. The second i-type semiconductor layer 53A has a larger band gap than the second p-type semiconductor layer 51A. The second i-type semiconductor layer 53A contains an i-type nitride semiconductor as a main component. For example, the second i-type semiconductor layer 53A has a single layer or multilayer structure of an i-type AlGaN layer or an i-type GaN layer. The thickness of the second i-type semiconductor layer 53A is 10 nm to 50 nm, for example, 20 nm. In this embodiment, the anode electrode 55A (specifically, the TiAl alloy layer 56A) is in contact with the upper surface of the second i-type semiconductor layer 53A. The TiAl alloy layer 56A is ohmically connected to the second p-type semiconductor layer 51A via the second i-type semiconductor layer 53A.

[0123] The second i-type semiconductor layer 53A of the anode structure 50A has the same layer configuration as the first i-type semiconductor layer 53G of the gate structure 50G. The second i-type semiconductor layer 53A and the first i-type semiconductor layer 53G are formed in the same film formation process, and have the same composition and film thickness.

[0124] As described above, in the anode structure 50A of the nitride semiconductor device 3 according to this embodiment, the TiAl alloy layer 56A is ohmically connected to the second p-type semiconductor layer 51A via the second i-type semiconductor layer 53A. Although the presence of the second i-type semiconductor layer 53A, which has a large bandgap, increases the resistance component, the resistance variation is suppressed compared to when a Schottky contact is formed. Therefore, the ESD current flows more evenly through the second p-type semiconductor layer 51A, suppressing the temperature rise due to Joule heating and the melting of metal due to heat generation. This maintains the functionality of the diode 12 and improves the ESD breakdown voltage.

[0125] In the gate structure 50G, the TiN layer 56G is Schottky-connected to the first p-type semiconductor layer 51G via the first i-type semiconductor layer 53G. The presence of the first i-type semiconductor layer 53G having a large band gap can further reduce the gate current and further improve the characteristics of the FET 11. As described above, according to the present embodiment, it is possible to realize a nitride semiconductor device 3 that can improve the characteristics and ESD resistance of the FET 11.

[0126] Fourth Embodiment Next, a fourth embodiment will be described. In the fourth embodiment, compared to the third embodiment, the gate structure 50G and the anode structure 50A are p ＋ The main difference between the second embodiment and the third embodiment is that it includes an impurity region of the same type. In the following, the differences from the third embodiment will be explained, and explanation of the commonalities will be omitted or simplified.

[0127] Fig. 5 is a cross-sectional view of the nitride semiconductor device 4 according to the present embodiment. As shown in Fig. 5, the nitride semiconductor device 4 differs from the nitride semiconductor device 3 shown in Fig. 4 in the configuration of the anode structure 50A. Specifically, the anode structure 50A of the nitride semiconductor device 4 includes an impurity region 54.

[0128] The impurity region 54 is a region doped with p-type impurities. The p-type impurities doped in the impurity region 54 are, for example, Mg, and are doped by ion implantation or the like. The p-type impurity concentration in the impurity region 54 is higher than the p-type impurity concentration in the second p-type semiconductor layer 51A other than the impurity region 54. The impurity region 54 is a p ＋ For example, the p-type impurity concentration of the impurity region 54 is 1×10 １８ cm －３ 1x10 or more ２０ cm －３ For example, 5×10 １９ cm －３ is.

[0129] The impurity region 54 is provided in the range from the upper surface of the second i-type semiconductor layer 53A to the inside of the second p-type semiconductor layer 51A. That is, the impurity region 54 is provided in the second i-type semiconductor layer 53A and the second p-type semiconductor layer 51A. For example, when the second i-type semiconductor layer 53A is an i-type AlGaN layer and the second p-type semiconductor layer 51A is a p-type GaN layer, the impurity region 54 is provided in the p ＋ type AlGaN layer and p ＋ The impurity region 54 has a layered structure with a GaN layer of the type. The thickness (ion implantation depth) of the impurity region 54 is, for example, 20 nm to 100 nm, for example, 50 nm.

[0130] In this embodiment, the anode electrode 55A (specifically, the TiAl alloy layer 56A) is in contact with the impurity region 54. The TiAl alloy layer 56A is in ohmic contact with the impurity region 54 and the second p-type semiconductor layer 51A.

[0131] As described above, in the anode structure 50A of the nitride semiconductor device 4 according to this embodiment, the contact between the impurity region 54 and the TiAl alloy layer 56A can suppress variations in contact resistance at the contact surface. Because low-resistance ohmic contact can be achieved between the impurity region 54 and the TiAl alloy layer 56A, ESD current tends to flow more evenly through the second p-type semiconductor layer 51A and the impurity region 54. High temperature caused by Joule heating is further suppressed, thereby suppressing metal melting due to heat generation. This maintains the functionality of the diode 12 and improves ESD breakdown voltage.

[0132] Furthermore, the gate structure 50G does not include an impurity region 54. That is, in the gate structure 50G, the first i-type semiconductor layer 53G is not doped with p-type impurities. The gate electrode 55G (specifically, the TiN layer 56G) is in contact with the upper surface of the first i-type semiconductor layer 53G. The TiN layer 56G is Schottky-connected to the first p-type semiconductor layer 51G via the first i-type semiconductor layer 53G. The presence of the first i-type semiconductor layer 53G with a large bandgap can further reduce the gate current and further improve the characteristics of the FET 11. As such, according to this embodiment, a nitride semiconductor device 4 can be realized that can improve the characteristics and ESD resistance of the FET 11.

[0133] In the anode structure 50A of the nitride semiconductor device 4, the anode electrode 55A may have the same layer structure as the gate electrode 55G. Specifically, the anode electrode 55A may include a TiN layer instead of the TiAl alloy layer 56A, and the TiN layer may be in contact with the impurity region 54. Since the impurity region 54 has a high p-type impurity concentration, the TiN layer and the impurity region 54 can be electrically connected with low resistance. This increases the ESD breakdown current of the diode 12 and improves the ESD breakdown voltage. Since the anode electrode 55A and the gate electrode 55G can be formed in the same process, the manufacturing method can be simplified.

[0134] Fifth Embodiment Next, a fifth embodiment will be described. The fifth embodiment is mainly different from the third embodiment in that an opening is provided in the i-type semiconductor layer of the anode structure 50A. Below, the differences from the third embodiment will be described, and the description of the commonalities with the third embodiment will be omitted or simplified.

[0135] Fig. 6 is a cross-sectional view of a nitride semiconductor device 5 according to this embodiment. As shown in Fig. 6, the nitride semiconductor device 5 is different from the nitride semiconductor device 3 shown in Fig. 4 in an anode structure 50A. Specifically, a recess 53a is provided in the second i-type semiconductor layer 53A of the anode structure 50A.

[0136] The recess 53a is recessed downward from the upper surface of the second i-type semiconductor layer 53A. In this embodiment, the recess 53a is an opening that penetrates the second i-type semiconductor layer 53A. That is, the bottom surface of the recess 53a is the upper surface of the second p-type semiconductor layer 51A. The shape of the recess 53a in a plan view is the same as the shape of the opening 61A in a plan view. The inner wall surface of the opening 61A is flush with the sidewall of the recess 53a. Note that the inner wall surface of the opening 61A and the sidewall of the recess 53a are perpendicular to the main surface of the substrate 30, but may be inclined obliquely.

[0137] The anode electrode 55A (specifically, the TiAl alloy layer 56A) is in contact with the bottom surface of the recess 53a. In this embodiment, since the recess 53a penetrates the second i-type semiconductor layer 53A, the anode electrode 55A is in contact with the second p-type semiconductor layer 51A at the bottom surface of the recess 53a. That is, the anode electrode 55A is in direct ohmic contact with the second p-type semiconductor layer 51A. This reduces resistance compared to when the anode electrode 55A is in ohmic contact with the second p-type semiconductor layer 51A via the second i-type semiconductor layer 53A. This allows the ESD current to flow more evenly through the second p-type semiconductor layer 51A, suppressing temperature increases due to Joule heating and preventing metal melting due to heat generation. This maintains the functionality of the diode 12 and improves the ESD breakdown voltage.

[0138] The gate structure 50G does not have a recess. The gate electrode 55G (specifically, the TiN layer 56G) is in contact with the upper surface of the first i-type semiconductor layer 53G. The TiN layer 56G is Schottky-connected to the first p-type semiconductor layer 51G via the first i-type semiconductor layer 53G. The presence of the first i-type semiconductor layer 53G with a large bandgap can further reduce the gate current, thereby further improving the characteristics of the FET 11. As described above, according to this embodiment, a nitride semiconductor device 5 can be realized that can improve the characteristics and ESD resistance of the FET 11.

[0139] The recess 53a does not necessarily have to penetrate the second i-type semiconductor layer 53A. In this case, the anode electrode 55A (specifically, the TiAl alloy layer 56A) contacts the second i-type semiconductor layer 53A at the bottom of the recess 53a. The TiAl alloy layer 56A is ohmically connected to the second p-type semiconductor layer 51A via the second i-type semiconductor layer 53A at the bottom of the recess 53a. Because the second i-type semiconductor layer 53A is thinner at the bottom of the recess 53a, lower resistance is possible than when the recess 53a is not formed. This facilitates uniform flow of ESD current, suppresses Joule heating-induced temperature increases, and suppresses metal melting due to heat generation. This maintains the functionality of the diode 12 and improves ESD resistance.

[0140] Alternatively, the recess 53a may also be provided in the second p-type semiconductor layer 51A. Specifically, the bottom surface of the recess 53a may be located below the interface between the second p-type semiconductor layer 51A and the second i-type semiconductor layer 53A. As will be described in detail later, the recess 53a is formed by removing a portion of the second i-type semiconductor layer 53A by etching. At this time, the portion of the second p-type semiconductor layer 51A may be removed immediately after the removal of the second i-type semiconductor layer 53A. Since there is no need to strictly control the timing of stopping the etching, the manufacturing method can be simplified.

[0141] Furthermore, in the anode structure 50A of the nitride semiconductor device 5, the anode electrode 55A may have the same layer structure as the gate electrode 55G. Specifically, the anode electrode 55A may include a TiN layer instead of the TiAl alloy layer 56A, and the TiN layer may be in contact with the second p-type semiconductor layer 51A at the bottom surface of the recess 53a. In the anode structure 50A, the TiN layer is electrically connected to the second p-type semiconductor layer 51A without the second i-type semiconductor layer 53A, thereby achieving electrical connection with lower resistance than in the gate structure 50G. This improves the ESD withstand voltage of the diode 12. Since the anode electrode 55A and the gate electrode 55G can be formed in the same process, the manufacturing method can be simplified.

[0142] Sixth Embodiment Next, a sixth embodiment will be described. In the sixth embodiment, compared to the fifth embodiment, the anode structure 50A is p ＋ The main difference between the fifth embodiment and the fifth embodiment is that it includes an impurity region of the same type. In the following, the differences from the fifth embodiment will be explained, and explanation of the commonalities will be omitted or simplified.

[0143] Fig. 7 is a cross-sectional view of a nitride semiconductor device 6 according to this embodiment. As shown in Fig. 7, the nitride semiconductor device 6 differs from the nitride semiconductor device 5 shown in Fig. 6 in the configuration of an anode structure 50A. Specifically, the anode structure 50A of the nitride semiconductor device 6 includes an impurity region 54.

[0144] The impurity region 54 is a region doped with p-type impurities. The p-type impurities doped in the impurity region 54 are, for example, Mg, and are doped by ion implantation or the like. The p-type impurity concentration in the impurity region 54 is higher than the p-type impurity concentration in the second p-type semiconductor layer 51A other than the impurity region 54. The impurity region 54 is a p ＋ For example, the p-type impurity concentration of the impurity region 54 is 1×10 １８ cm －３ 1x10 or more ２０ cm －３ For example, 5×10 １９ cm －３ is.

[0145] The impurity region 54 is provided in the range from the bottom surface of the recess 53a to the inside of the second p-type semiconductor layer 51A. That is, the impurity region 54 is provided in the second p-type semiconductor layer 51A. For example, when the second p-type semiconductor layer 51A is a p-type GaN layer, the impurity region 54 is provided in the range from the bottom surface of the recess 53a to the inside of the second p-type semiconductor layer 51A. ＋ The impurity region 54 has a thickness (ion implantation depth) of, for example, 20 nm to 100 nm, for example, 50 nm.

[0146] In this embodiment, the anode electrode 55A (specifically, the TiAl alloy layer 56A) is in contact with the impurity region 54. The TiAl alloy layer 56A is in ohmic contact with the impurity region 54 and the second p-type semiconductor layer 51A.

[0147] As described above, in the anode structure 50A of the nitride semiconductor device 6 according to this embodiment, contact between the impurity region 54 and the TiAl alloy layer 56A can suppress variations in contact resistance at the contact surface. Because low-resistance ohmic contact can be achieved between the impurity region 54 and the TiAl alloy layer 56A, ESD current tends to flow more evenly through the second p-type semiconductor layer 51A and the impurity region 54. High temperature caused by Joule heating is further suppressed, thereby suppressing metal melting due to heat generation. This maintains the functionality of the diode 12 and improves ESD breakdown voltage.

[0148] Furthermore, the gate structure 50G does not include either a recess 53a or an impurity region 54. That is, in the gate structure 50G, the first i-type semiconductor layer 53G is not doped with p-type impurities. The gate electrode 55G (specifically, the TiN layer 56G) is in contact with the upper surface of the first i-type semiconductor layer 53G. The TiN layer 56G is Schottky-connected to the first p-type semiconductor layer 51G via the first i-type semiconductor layer 53G. The presence of the first i-type semiconductor layer 53G with a large bandgap can further reduce the gate current and further improve the characteristics of the FET 11. As such, according to this embodiment, a nitride semiconductor device 6 can be realized that can improve the characteristics and ESD resistance of the FET 11.

[0149] The recess 53a does not necessarily have to penetrate the second i-type semiconductor layer 53A. In this case, the impurity region 54 is also formed in the second i-type semiconductor layer 53A. The TiAl alloy layer 56A of the anode electrode 55A contacts the impurity region 54 at the bottom of the recess 53a, thereby suppressing variations in contact resistance at the contact surface. Low-resistance ohmic contact is achieved between the impurity region 54 and the TiAl alloy layer 56A, allowing ESD current to flow more evenly through the second p-type semiconductor layer 51A and the impurity region 54. High temperature caused by Joule heating is further suppressed, thereby suppressing metal melting due to heat generation. This maintains the functionality of the diode 12 and improves ESD breakdown voltage.

[0150] Alternatively, the recess 53a may also be provided in the second p-type semiconductor layer 51A. Specifically, the bottom surface of the recess 53a may be located below the interface between the second p-type semiconductor layer 51A and the second i-type semiconductor layer 53A. As will be described in detail later, the recess 53a is formed by removing a portion of the second i-type semiconductor layer 53A by etching. At this time, the portion of the second p-type semiconductor layer 51A may be removed immediately after the removal of the second i-type semiconductor layer 53A. Since there is no need to strictly control the timing of stopping the etching, the manufacturing method can be simplified.

[0151] In the anode structure 50A of the nitride semiconductor device 6, the anode electrode 55A may have the same layer structure as the gate electrode 55G. Specifically, the anode electrode 55A may include a TiN layer instead of the TiAl alloy layer 56A, and the TiN layer may be in contact with the impurity region 54. Since the impurity region 54 has a high p-type impurity concentration, the TiN layer and the impurity region 54 can be electrically connected with low resistance. This improves the ESD breakdown voltage of the diode 12. Since the anode electrode 55A and the gate electrode 55G can be formed in the same process, the manufacturing method can be simplified.

[0152] (Plane Layout of Diode) Next, an example of the plane layout of the diode 12 of the nitride semiconductor devices 1 to 6 according to each embodiment will be described.

[0153] 8 is a plan view showing a first example of the layout of the anode structure 50A and the cathode structure 50K of the nitride semiconductor device according to each embodiment. The cross section taken along line II-II in FIG. 8 corresponds to the cross section of the diode 12 (second active region 22) shown in FIGS. 2 to 7.

[0154] 8, both the anode structure 50A and the cathode structure 50K have shapes that are elongated in the same direction in a plan view. The two anode structures 50A are disposed so as to sandwich the cathode structure 50K therebetween, and are positioned in an axisymmetric relationship with respect to the center line extending in the longitudinal direction of the cathode structure 50K.

[0155] In a plan view, the second p-type semiconductor layer 51A is larger than the anode electrode 55A. An opening 61A provided in the insulating layer 60 (not shown) to bring the anode electrode 55A into contact with the second p-type semiconductor layer 51A is smaller than the anode electrode 55A. The second p-type semiconductor layer 51A may be the same size as the anode electrode 55A or smaller than the anode electrode 55A. The opening 61A may be the same size as the anode electrode 55A or larger than the anode electrode 55A.

[0156] In plan view, an opening 61K provided in the insulating layer 60 (not shown) for contacting the cathode electrode 55K with the semiconductor stack 40 (barrier layer 42) is smaller than the cathode electrode 55K. Note that the opening 61K may be the same size as the cathode electrode 55K or may be larger than the cathode electrode 55K.

[0157] As an example, assuming that the second active region 22 in which the diode 12 is provided has a rectangular shape measuring 350 μm × 160 μm in plan view, the dimensions of the anode structure 50A and the cathode structure 50K can be set as follows: Specifically, the width (horizontal length) of the anode contact opening 61A is 20 μm and the vertical length is 330 μm. The anode electrode 55A is slightly larger than the opening 61A by a margin of 0.2 μm on each side, and the width of the anode electrode 55A is 20.4 μm and the vertical length is 330.4 μm. The second p-type semiconductor layer 51A is slightly larger than the anode electrode 55A by a margin of 0.4 μm on each side, and the width of the second p-type semiconductor layer 51A is 21.2 μm and the vertical length is 331.2 μm. The cathode contact opening 61K has a width (horizontal length) of 10 μm and a vertical length of 330 μm. The cathode electrode 55K is slightly larger than the opening 61K with a margin of 0.2 μm on each side, and has a width of 10.4 μm and a length of 330.4 μm. The spacing between the anode electrode 55A and the cathode electrode 55K is 9 μm. Note that these numerical values ​​are merely examples.

[0158] Furthermore, the width of the opening 61A for the anode contact is larger than the width of the opening 61K for the cathode contact. For example, the width of the opening 61A is 1.2 times or more the width of the opening 61K. Note that since the vertical length of the opening 61A is equal to the vertical length of the opening 61K, the ratio of the widths corresponds to the area ratio of the openings 61A and 61K. Making the opening 61A larger than the opening 61K can improve the ESD breakdown voltage of the diode 12.

[0159] 9 is a plan view showing a second example of the layout of the anode structures 50A and the cathode structures 50K of the nitride semiconductor device according to each embodiment. In the example shown in Fig. 9, a plurality of anode structures 50A and a plurality of cathode structures 50K are provided. The plurality of anode structures 50A and the plurality of cathode structures 50K are each elongated in the same direction, and the anode structures 50A and the cathode structures 50K are alternately arranged one by one along the short side direction.

[0160] The anode electrodes 55A of the multiple anode structures 50A are electrically connected to one another via anode wiring 80A. The cathode electrodes 55K of the multiple cathode structures 50K are electrically connected to one another via cathode wiring 80K. While FIG. 9 illustrates an example in which the anode wiring 80A and the anode electrode 55A have the same layer structure, and the cathode wiring 80K and the cathode electrode 55K have the same layer structure, this is not limiting. The anode wiring 80A may be provided above the anode electrode 55A, and the cathode wiring 80K may be provided above the cathode electrode 55K.

[0161] In the anode structure 50A of the second example, the anode electrode 55A is in contact with the second p-type semiconductor layer 51A at multiple locations. Specifically, the connections between the anode electrode 55A and the second p-type semiconductor layer 51A are discrete along the longitudinal direction of the anode electrode 55A. More specifically, as shown in an enlarged partial view in FIG. 9 , anode contact openings 61A are discretely provided along the longitudinal direction of the anode electrode 55A. The multiple openings 61A are arranged at equal intervals along the longitudinal direction of the anode electrode 55A. The anode electrode 55A is provided in a striped pattern, with multiple openings 61A provided in each stripe.

[0162] The configuration of the cathode structure 50K is the same as that of the first example shown in Fig. 8. In the second example, the cathode structure 50K is provided in a stripe pattern, and one opening 61A is provided for each stripe.

[0163] The dimensions of the anode structure 50A and the cathode structure 50K shown in the second example can be set, for example, as follows: Specifically, the anode contact opening 61A has a square shape in plan view, with each side measuring 10 μm. The spacing between two adjacent openings 61A is 5 μm. The anode electrode 55A has a width of 10.8 μm. The second p-type semiconductor layer 51A has a width of 11.2 μm. The cathode contact opening 61K has a width of 10 μm. The cathode electrode 55K has a width of 10.8 μm. Note that these numerical values ​​are merely examples. The plan view shape of the opening 61A may be rectangular or circular.

[0164] In the diode 12 shown in the second example, the contact between the anode electrode 55A and the second p-type semiconductor layer 51A is made discrete, so that the ESD current flows evenly through the second p-type semiconductor layer 51A. This makes it possible to avoid localized concentration of the ESD current, thereby improving the ESD breakdown voltage of the diode 12.

[0165] 10A is a plan view showing a third example of the layout of the anode structure 50A and the cathode structure 50K of the nitride semiconductor device according to each embodiment, and FIG. 10B is a cross-sectional view taken along line XB-XB of FIG.

[0166] In the example shown in FIGS. 10A and 10B , the cathode structure 50K is arranged in a lattice pattern in a plan view. Specifically, the cathode electrodes 55K of the cathode structure 50K are arranged in a lattice pattern in a plan view. The openings 61K for cathode contacts are also arranged in a lattice pattern in a plan view. The lattice portions of the cathode structure 50K are arranged at equal intervals in both the vertical and horizontal directions. Therefore, the openings of the lattice-shaped cathode structure 50K have a square shape in a plan view. However, the openings of the cathode structure 50K may also have a rectangular shape in a plan view.

[0167] In a plan view, the anode structure 50A is provided for each opening of the lattice-shaped cathode structure 50K. Specifically, the second p-type semiconductor layer 51A and the anode electrode 55A of the anode structure 50A are provided discretely for each opening of the cathode structure 50K. The discretely provided anode electrodes 55A are electrically connected via anode wiring 80A. The anode wiring 80A is provided so as to cover the discretely provided anode electrodes 55A and the lattice-shaped cathode electrode 55K.

[0168] 10B, an insulating layer 66 is provided between the anode wiring 80A and the cathode electrode 55K. The insulating layer 66 covers the upper and side surfaces of the cathode electrode 55K and the anode electrode 55A, as well as the upper surface of the insulating layer 60. The insulating layer 66 is made of, for example, a SiN film or a SiO ２ Although it is a single layer structure of a film, it is a SiN film or SiO２ It may also be a laminated structure including a film.

[0169] An opening 67A is also provided in the insulating layer 66. The opening 67A is an opening for electrically connecting the anode wiring 80A and the anode electrode 55A. The upper surface of the Al layer 57A of the anode electrode 55A is exposed at the bottom of the opening 67A. The anode wiring 80A comes into contact with and is electrically connected to the Al layer 57A through the opening 67A. The anode wiring 80A is formed using a conductive metal material such as Ti or Al.

[0170] The dimensions of the anode structure 50A and the cathode structure 50K shown in the third example can be set, for example, as follows. Specifically, the grid-shaped opening 61K and the cathode electrode 55K have the same width in both the vertically extending portion and the horizontally extending portion. The width of the cathode contact opening 61K is 4.2 μm. The width of the cathode electrode 55K is 5 μm. The second p-type semiconductor layer 51A of the anode structure 50A has a square shape in a planar view, with each side measuring 5.4 μm. The anode contact opening 61A has a square shape in a planar view, with each side measuring 4 μm. The anode electrode 55A has a square shape in a planar view, with each side measuring 5 μm. The opening 67A for connecting the anode wiring 80A to the anode electrode 55A has a square shape in a planar view, with each side measuring 3 μm. The spacing between the anode electrode 55A and the cathode electrode 55K is 5 μm. The second p-type semiconductor layer 51A, the opening 61A, the anode electrode 55A, and the opening 67A may each have a rectangular or circular shape in plan view.

[0171] In the diode 12 shown in the third example, the contact between the anode electrode 55A and the second p-type semiconductor layer 51A is made discrete, so that the ESD current flows evenly through the second p-type semiconductor layer 51A. This makes it possible to avoid localized concentration of the ESD current, thereby improving the ESD breakdown voltage of the diode 12.

[0172] 11A is a plan view showing a fourth example of the layout of the anode structure 50A and the cathode structure 50K of the nitride semiconductor device according to each embodiment. FIG. 11B is a cross-sectional view taken along line XIB-XIB in FIG. 11A.

[0173] 11A and 11B , the cathode structure 50K is provided in a ring shape along the outer periphery of the second active region 22 in a plan view. Specifically, the cathode electrode 55K of the cathode structure 50K is provided in a ring shape along the outer periphery of the second active region 22 in a plan view. For example, the outer periphery of the second active region 22 and the outer contour of the cathode electrode 55K may coincide with each other. In addition, the cathode contact opening 61K is also provided in a ring shape along the outer periphery of the second active region 22 in a plan view.

[0174] A portion of the annular cathode structure 50K is discontinuous, leaving a gap, and the anode wiring 80A connected to the anode electrode 55A of the anode structure 50A through the gap extends outside the cathode structure 50K, thereby facilitating electrical connection between the anode structure 50A and the source structure 50S (not shown) of the FET 11.

[0175] In a plan view, the anode structure 50A is surrounded by the cathode structure 50K. Specifically, the second p-type semiconductor layer 51A and the anode electrode 55A of the anode structure 50A are surrounded by the cathode structure 50K. The anode electrode 55A and the cathode electrode 55K are provided with a fixed spacing therebetween.

[0176] 11A and 11B, the area of ​​the opening 61A for the anode contact and the area of ​​the anode electrode 55A are made sufficiently larger than the area of ​​the cathode electrode 55K. For example, the area of ​​the opening 61A and the area of ​​the anode electrode 55A are 60% or more of the area of ​​the second active region 22.

[0177] The dimensions of the anode structure 50A and the cathode structure 50K shown in the fourth example can be set, for example, as follows. Specifically, the annular opening 61K and the cathode electrode 55K both have the same width in the vertically extending portion and the horizontally extending portion. The width of the cathode contact opening 61K is 4.2 μm. The width of the cathode electrode 55K is 5 μm. The second p-type semiconductor layer 51A of the anode structure 50A has a square shape in a planar view, with each side measuring 300 μm. The anode contact opening 61A has a square shape in a planar view, with each side measuring 100 μm. The anode electrode 55A has a square shape in a planar view, with each side measuring 100.8 μm. The spacing between the anode electrode 55A and the cathode electrode 55K is 6 μm. Note that these numerical values ​​are merely examples. The second p-type semiconductor layer 51A, the opening 61A, and the anode electrode 55A may each have a rectangular or circular shape in a plan view. The cathode electrode 55K and the opening 61K may each have a rectangular or circular ring shape in a plan view.

[0178] In the diode 12 shown in the fourth example, the contact area between the anode electrode 55A and the second p-type semiconductor layer 51A is increased, so that the ESD current flows evenly through the second p-type semiconductor layer 51A. This makes it possible to prevent the ESD current from concentrating locally, thereby improving the ESD breakdown voltage of the diode 12.

[0179] (Manufacturing Method) Next, a manufacturing method for the nitride semiconductor devices 1 to 6 according to each embodiment will be described. Below, the configuration of a specific example of the nitride semiconductor devices 1 to 6 according to each embodiment will be described with reference to FIGS.

[0180] Fig. 12 is a cross-sectional view of the nitride semiconductor device 100 in accordance with Example 1. Fig. 13 is a plan view of the nitride semiconductor device 100 in accordance with Example 1.

[0181] The nitride semiconductor device 100 shown in FIGS. 12 and 13 is an example of the nitride semiconductor device 3 according to the third embodiment shown in FIG. 4 . The nitride semiconductor device 100 includes a FET 111 and two diodes 112 and 113. The diode 113 has the same configuration as the diode 112. In the nitride semiconductor device 100, the two diodes 112 and 113 are connected in series between the source and gate of the FET 111 to function as an ESD protection element. Specifically, the anode structure 50A of the diode 112 is electrically connected to the source structure 150S of the FET 111. The cathode structure 50K of the diode 112 is electrically connected to the anode structure 50A of the diode 113. The cathode structure 50K of the diode 113 is electrically connected to the gate structure 150G of the FET 111. In FIG. 12 , the electrical connections are indicated by thick solid lines.

[0182] 13 , the nitride semiconductor device 100 includes a substrate 30 that is rectangular in plan view. The nitride semiconductor device 100 includes a first active region 121, a second active region 122, and a third active region 123 in plan view. The first active region 121 includes a FET 111. The second active region 122 includes a diode 112. The third active region 123 includes a diode 113. An inactive region 44 is provided in an area other than the first active region 121, the second active region 122, and the third active region 123. This allows spatial separation between the first active region 121, the second active region 122, and the third active region 123, thereby preventing leakage current from occurring between the FET 111 and the diodes 112 and 113. An annular element isolation region 31 is provided along the outer periphery of the substrate 30. The element isolation region 31 is, for example, a recess (groove) formed by removing a part of the semiconductor laminate 40, and is also called a mesa isolation region.

[0183] 12 as one FET unit, a plurality of FET units are repeatedly provided. Adjacent units share the drain structure 150D or the source structure 150S. The source structure 150S, gate structure 150G, and drain structure 150D are each provided in a stripe pattern.

[0184] 12 as one diode unit, a plurality of diode units are repeatedly provided in the second active region 122 and the third active region 123. The anode structure 50A and the cathode structure 50K are each provided in a stripe shape.

[0185] The electrode structure of the FET 111 is the same as that of the FET 11 according to the third embodiment. Specifically, the FET 111 includes a source structure 150S, a drain structure 150D, and a gate structure 150G. The source structure 150S includes a source electrode 55S, similar to the source structure 50S shown in FIG. 4. The gate structure 150G includes a gate electrode 55G, a first p-type semiconductor layer 51G, and a first i-type semiconductor layer 53G, similar to the gate structure 50G shown in FIG. 4.

[0186] The drain structure 150D includes a third p-type semiconductor layer 51D and a third i-type semiconductor layer 53D in addition to the drain electrode 55D shown in FIG.

[0187] The third p-type semiconductor layer 51D is provided above the semiconductor stack 40 (barrier layer 42) in the first active region 121. Specifically, the third p-type semiconductor layer 51D is in contact with the upper surface of the barrier layer 42. The third p-type semiconductor layer 51D is provided between the gate structure 150G and a portion where the drain electrode 55D is in contact with the barrier layer 42. The third p-type semiconductor layer 51D contains a p-type nitride semiconductor as a main component. For example, the third p-type semiconductor layer 51D has a single layer or stacked layer structure of a p-type GaN layer or a p-type InGaN layer. The third p-type semiconductor layer 51D is doped with, for example, Mg as a p-type impurity. The p-type impurity concentration of the third p-type semiconductor layer 51D is 1×10１７ cm －３ 1x10 or more １８ cm －３ As an example, １７ cm －３ The thickness of the third p-type semiconductor layer 51D is, for example, not less than 100 nm and not more than 300 nm, and is, for example, 180 nm.

[0188] The third i-type semiconductor layer 53D is an example of a third semiconductor layer and is provided between the third p-type semiconductor layer 51D and the drain electrode 55D. The third i-type semiconductor layer 53D has a larger band gap than the third p-type semiconductor layer 51D. The third i-type semiconductor layer 53D contains an i-type nitride semiconductor as a main component. For example, the third i-type semiconductor layer 53D has a single layer or multilayer structure of an i-type AlGaN layer or an i-type GaN layer. The thickness of the third i-type semiconductor layer 53D is 10 nm or more and 50 nm or less, for example, 20 nm.

[0189] In this embodiment, the drain electrode 55D is electrically connected to the third p-type semiconductor layer 51D. Specifically, the drain electrode 55D is electrically connected to the third p-type semiconductor layer 51D via the third i-type semiconductor layer 53D. The drain electrode 55D is in contact with the upper surface and side surfaces of the third i-type semiconductor layer 53D and the side surfaces of the third p-type semiconductor layer 51D. The third p-type semiconductor layer 51D is connected to the drain electrode 55D and has a hole injection effect. Since electrons trapped during operation of the FET 111 can be neutralized with holes, current collapse can be suppressed.

[0190] The electrode structure of the diodes 112 and 113 is the same as the electrode structure of the diode 12 according to the third embodiment.

[0191] The nitride semiconductor device 100 includes an interconnect structure that electrically connects the electrode structure of the FET 111 with the electrode structures of the diodes 112 and 113. Specifically, as shown in FIG. 12 , the nitride semiconductor device 100 includes insulating layers 65 and 66, a source interconnect 80S, a drain interconnect 80D, an anode interconnect 80A, a cathode interconnect 80K, and an insulating layer 90. Two anode interconnects 80A and two cathode interconnects 80K are provided, one for the diode 112 and one for the diode 113. Although not shown in FIG. 12 , the nitride semiconductor device 100 also includes a gate interconnect 80G (see FIG. 13 ). The nitride semiconductor device 100 further includes a gate pad 70G, a source pad 70S, and a drain pad 70D (see FIG. 13 ).

[0192] The insulating layer 65 covers the upper and side surfaces of the source electrode 55S, the drain electrode 55D, the anode electrode 55A, and the cathode electrode 55K, as well as the upper surface of the insulating layer 60. The insulating layer 65 does not cover the upper surface of the gate electrode 55G. A portion of the insulating layer 65 is located between a portion of the gate electrode 55G and the first p-type semiconductor layer 51G. The insulating layer 65 is made of, for example, a SiN film or SiO ２ The insulating layer 65 has a single layer structure or a multilayer structure, and the thickness thereof is, for example, 120 nm.

[0193] The insulating layer 66 covers the upper and side surfaces of the gate electrode 55G and the upper surface of the insulating layer 65. The insulating layer 66 is, for example, a SiN film or a SiO ２ The insulating layer 66 has a single layer structure or a multilayer structure, and the thickness thereof is, for example, 300 nm.

[0194] The insulating layers 65 and 66 are provided with openings for connecting electrodes and wiring. Specifically, the insulating layers 65 and 66 are provided with openings 67S, 67D, 67A, and 67K. The opening 67S is provided to electrically connect the source electrode 55S and the source wiring 80S, and the Al layer 57S of the source electrode 55S is exposed at the bottom of the opening 67S. The opening 67D is provided to electrically connect the drain electrode 55D and the drain wiring 80D, and the Al layer 57D of the drain electrode 55D is exposed at the bottom of the opening 67D. The opening 67K is provided to electrically connect the cathode electrode 55K and the cathode wiring 80K, and the Al layer 57K of the cathode electrode 55K is exposed at the bottom of the opening 67K. The opening 67A is provided to electrically connect the anode electrode 55A and the anode wiring 80A, and the Al layer 57A of the anode electrode 55A is exposed at the bottom of the opening 67A. Although not shown in Fig. 12, the insulating layers 65 and 66 may have openings to electrically connect the gate wiring 80G (see Fig. 13) and the gate electrode 55G.

[0195] The source wiring 80S is a conductive wiring electrically connected to the source electrode 55S. As shown in FIG. 13 , the source wiring 80S is formed in a comb-like shape, and the finger portions of the comb-like shape are connected to the striped source electrode 55S. A source pad 70S is provided in a common portion bundling the finger portions of the source wiring 80S. The source pad 70S is electrically connected to the source wiring 80S through an opening provided in the insulating layer 90 (see FIG. 12 ). Both the source wiring 80S and the source pad 70S are formed using a conductive material such as metal. For example, the source wiring 80S and the source pad 70S have a single-layer structure or a multilayer structure of a metal layer containing Ti, Al, Au, or the like as a main component. The thickness of the source wiring 80S is, for example, 470 nm.

[0196] 12, the source wiring 80S extends beyond the gate electrode 55G to the drain electrode 55D side. This allows the source wiring 80S to relax the electric field applied between the gate and the drain. A part of the source wiring 80S functions as a source field plate.

[0197] The drain wiring 80D is a conductive wiring electrically connected to the drain electrode 55D. As shown in FIG. 13 , the drain wiring 80D is formed in a comb-like shape, and the finger portions of the comb-like shape are connected to the drain electrode 55D arranged in a stripe pattern. A drain pad 70D is provided in a common portion bundling the finger portions of the drain wiring 80D. The drain pad 70D is electrically connected to the drain wiring 80D through an opening provided in the insulating layer 90 (see FIG. 12 ). Both the drain wiring 80D and the drain pad 70D are formed using a conductive material such as metal. For example, the drain wiring 80D and the drain pad 70D have a single-layer structure or a multilayer structure of a metal layer containing Ti, Al, Au, or the like as a main component. The thickness of the drain wiring 80D is, for example, 470 nm.

[0198] The gate wiring 80G is a conductive wiring electrically connected to the gate electrode 55G. Although not shown in FIG. 13 , the gate wiring 80G is disposed in a position overlapping the common portion of the source wiring 80S and connected to the end of the striped gate electrode 55G. A gate pad 70G is also provided at the end of the gate wiring 80G. The gate pad 70G is electrically connected to the gate wiring 80G through an opening provided in the insulating layer 90 (see FIG. 12 ). Both the gate wiring 80G and the gate pad 70G are formed using a conductive material such as metal. For example, the gate wiring 80G and the gate pad 70G have a single-layer structure or a multilayer structure of a metal layer containing Ti, Al, Au, or the like as a main component. The thickness of the gate wiring 80G is, for example, 470 nm.

[0199] The anode wiring 80A is a conductive wiring electrically connected to the anode electrode 55A. As shown in FIG. 13 , the anode wiring 80A is formed in a comb-like shape, and the fingers of the comb-like shape are connected to the striped anode electrode 55A. The anode wiring 80A for the diode 113 is routed outside the third active region 123 (at a position overlapping the inactive region 44) and electrically connected to the source wiring 80S. The anode wiring 80A for the diode 112 is formed integrally with the cathode wiring 80K for the diode 113. The anode wiring 80A is formed using a conductive material such as metal. For example, the anode wiring 80A has a single-layer structure or a multilayer structure of a metal layer containing Ti, Al, Au, or the like as a main component. The thickness of the anode wiring 80A is, for example, 470 nm.

[0200] The cathode wiring 80K is a conductive wiring electrically connected to the cathode electrode 55K. As shown in FIG. 13 , the cathode wiring 80K is formed in a comb-like shape, and the finger portions of the comb-like shape are connected to the striped cathode electrode 55K. The cathode wiring 80K for the diode 112 is electrically connected to the gate wiring 80G at a common portion bundling the finger portions, or is formed integrally with the gate wiring 80G. The cathode wiring 80K for the diode 113 is formed integrally with the anode wiring 80A for the diode 112. The cathode wiring 80K is formed using a conductive material such as metal. For example, the cathode wiring 80K has a single-layer structure or a multilayer structure of a metal layer containing Ti, Al, Au, or the like as a main component. The thickness of the cathode wiring 80K is, for example, 470 nm.

[0201] The insulating layer 90 covers the upper and side surfaces of the source wiring 80S, the drain wiring 80D, the anode wiring 80A, and the cathode wiring 80K, as well as the upper surface of the insulating layer 66. The insulating layer 90 is made of, for example, a SiN film or a SiO ２ The insulating layer 90 has a single-layer structure or a multi-layer structure. Although not shown in Fig. 12, openings are provided in the insulating layer 90 for electrically connecting the wiring and the pads. The thickness of the insulating layer 90 is, for example, 1000 nm.

[0202] Next, a method for manufacturing the nitride semiconductor device 100 according to the first example will be described with reference to FIGS. 14A to 14I and 15A to 15H. FIGS. 14A to 14I are cross-sectional views illustrating the steps of the method for manufacturing the nitride semiconductor device 100 according to the first example. FIGS. 15A to 15H are plan views illustrating the steps of the method for manufacturing the nitride semiconductor device according to the first example. FIGS. 15A to 15H correspond to simplified views obtained by reducing the number of electrodes and the like compared to the plan view shown in FIG. 13.

[0203] First, an outline of a method for manufacturing the nitride semiconductor device 100 will be described. The manufacturing method of the nitride semiconductor device 100 includes the steps of forming a semiconductor stack 40 including a 2DEG 43 above a substrate 30 (corresponding to Figures 14A and 15A); forming a source structure 150S, a drain structure 150D, and a gate structure 150G for an FET 111 in a first active region 121, and forming an anode structure 50A and a cathode structure 50K for a diode 112 in a second active region 122 different from the first active region 121 (corresponding to Figures 14B to 14G and 15A to 15F); electrically connecting the source structure 150S and the anode structure 50A (corresponding to Figures 14H, 14I, 15G, and 15H); and electrically connecting the gate structure 150G and the cathode structure 50K (corresponding to Figures 14H, 14I, 15G, and 15H).

[0204] The first p-type semiconductor layer 51G of the gate structure 150G and the second p-type semiconductor layer 51A of the anode structure 50A are formed simultaneously. Furthermore, in the process of forming the gate structure 150G and the anode structure 50A, a first i-type semiconductor layer 53G is formed on the first p-type semiconductor layer 51G, and a second i-type semiconductor layer 53A is formed on the second p-type semiconductor layer 51A, so that the first i-type semiconductor layer 53G and the second i-type semiconductor layer 53A are formed simultaneously. Furthermore, in the process of forming the anode structure 50A, a Ti film and an Al film are formed in this order on the second p-type semiconductor layer 51A as the anode electrode 55A, and then a heat treatment is performed to alloy the Ti of the Ti film and the Al of the Al film. The heat treatment is performed by laser annealing. Details of each process are described below with reference to the drawings.

[0205] First, as shown in FIG. 14A , a nitride semiconductor stack structure is formed on a substrate 30 by epitaxial growth such as MOCVD (Metal Organic Chemical Vapor Deposition). Specifically, a semiconductor stack 40, a p-type semiconductor layer 51X, and an i-type semiconductor layer 53X are formed in this order on the substrate 30. As the semiconductor stack 40, a buffer layer (not shown), a channel layer 41, and a barrier layer 42 are formed in this order. A 2DEG 43 is generated between the channel layer 41 and the barrier layer 42. As shown in FIG. 15A , the semiconductor stack 40, the p-type semiconductor layer 51X, and the i-type semiconductor layer 53X are formed over the entire main surface of the substrate 30. The p-type semiconductor layer 51X is a layer that will become the first p-type semiconductor layer 51G, the second p-type semiconductor layer 51A, and the third p-type semiconductor layer 51D. The i-type semiconductor layer 53X is a layer that will become the first i-type semiconductor layer 53G, the second i-type semiconductor layer 53A, and the third i-type semiconductor layer 53D.

[0206] Next, as shown in FIG. 14B , an inactive region 44 is formed in the semiconductor stack 40. Specifically, the inactive region 44 is formed by implanting impurities such as boron by ion implantation. By forming the inactive region 44, the first active region 121, the second active region 122, and the third active region 123 are spatially separated, as shown in FIGS. 14B and 15B . Note that the inactive region 44 may also be formed in the p-type semiconductor layer 51X and the i-type semiconductor layer 53X.

[0207] Next, portions of the i-type semiconductor layer 53X and the p-type semiconductor layer 51X are removed by lithography and etching. As a result, as shown in FIGS. 14C and 15C , a first i-type semiconductor layer 53G, a second i-type semiconductor layer 53A, and a third i-type semiconductor layer 53D, and a first p-type semiconductor layer 51G, a second p-type semiconductor layer 51A, and a third p-type semiconductor layer 51D are formed. Note that the third i-type semiconductor layer 53D and the third p-type semiconductor layer 51D do not necessarily have to be formed. In this case, the nitride semiconductor devices 1 to 6 shown in FIGS. 2 to 7 can be formed.

[0208] Next, as shown in FIGS. 14D and 15D , an insulating layer 60 is formed and then partially removed to form openings 61D, 61S, 61A, and 61K. For example, the insulating layer 60 is formed over the entire surface by plasma CVD (chemical vapor deposition), and then partially removed by lithography and etching. In this process, an opening 61G is not formed. The top surface of the barrier layer 42 is exposed at the bottom of each of the openings 61K, 61S, and 61D. The side surface of the third p-type semiconductor layer 51D and the top and side surfaces of the third i-type semiconductor layer 53D are also exposed at the opening 61D. The top surface of the second i-type semiconductor layer 53A is exposed at the bottom of the opening 61A. Note that the third i-type semiconductor layer 53D and the third p-type semiconductor layer 51D are not shown in FIG. 15D .

[0209] Next, a metal film is formed to cover the openings 61D, 61S, 61A, and 61K. The metal film is formed by, for example, sputtering or vapor deposition. Specifically, a Ti layer and an Al layer are formed in this order, and then portions of the Ti layer and the Al layer are removed by lithography and etching. As a result, as shown in FIG. 14E , a layered structure of a Ti layer 58D and an Al layer 57D is formed in the opening 61D. A layered structure of a Ti layer 58S and an Al layer 57S is formed in the opening 61S. A layered structure of a Ti layer 58K and an Al layer 57K is formed in the opening 61K. A layered structure of a Ti layer 58A and an Al layer 57A is formed in the opening 61A.

[0210] Next, a heat treatment is performed to alloy Ti and Al. The heat treatment is performed, for example, by laser annealing. Specifically, the heat treatment is performed at 535°C for 60 seconds using an RTA (Rapid Thermal Annealing) furnace. The time and temperature of the heat treatment can be appropriately changed depending on the type of metal, film thickness, etc. Through the heat treatment, the Ti layers 58D, 58S, 58K, and 58A are alloyed and transformed into TiAl alloy layers 56D, 56S, 56K, and 56A, respectively. As a result, as shown in FIGS. 14F and 15E, a drain electrode 55D, a source electrode 55S, a cathode electrode 55K, and an anode electrode 55A are formed. The drain electrode 55D, the source electrode 55S, and the cathode electrode 55K are ohmically connected to the 2DEG 43. The anode electrode 55A is ohmically connected to the second p-type semiconductor layer 51A.

[0211] Next, as shown in FIG. 14G , an insulating layer 65 is formed and then a portion of the insulating layer 65 is removed to form an opening 61G. For example, the insulating layer 65 is formed over the entire surface by plasma CVD, and then a portion of the insulating layer 65 is removed by lithography and etching to form the opening 61G. The opening 61G penetrates not only the insulating layer 65 but also the insulating layer 60. The first i-type semiconductor layer 53G is exposed at the bottom of the opening 61G. After the opening 61G is formed, a gate electrode 55G is formed. Specifically, a TiN layer and an Al layer are formed in this order by sputtering or the like, and then portions of the TiN layer and the Al layer are removed by lithography and etching. As a result, as shown in FIGS. 14G and 15F , a gate electrode 55G including a stacked structure of a TiN layer 56G and an Al layer 57G is formed to cover the opening 61G.

[0212] 15F, the gate wiring 80G can be formed simultaneously with the formation of the gate electrode 55G. For example, the gate wiring 80G and the gate electrode 55G have the same layer structure. Alternatively, the gate pad 70G may be formed after the gate wiring 80G is formed.

[0213] 14H and 15G, an insulating layer 66 is formed, and then portions of the insulating layer 66 are removed to form openings 67D, 67S, 67A, and 67K. For example, the insulating layer 66 is formed over the entire surface by plasma CVD, and portions of the insulating layer 66 are then removed by lithography and etching. The top surfaces of the Al layers of the electrodes are exposed at the bottoms of the openings 67K, 67A, 67S, and 67D.

[0214] Next, as shown in FIG. 14I, a source wiring 80S, a drain wiring 80D, a cathode wiring 80K, and an anode wiring 80A are formed. Specifically, first, a metal film is formed to cover the openings 67D, 67S, 67A, and 67K. The metal film is formed by, for example, sputtering or vapor deposition. Specifically, a Ti layer and an Al layer are formed in this order, and then portions of the Ti layer and the Al layer are removed by lithography and etching. This results in the formation of the source wiring 80S, the drain wiring 80D, the cathode wiring 80K, and the anode wiring 80A, as shown in FIGS. 14I and 15H. Note that FIG. 15H shows an example in which the source wiring 80S does not overlap the gate electrode 55G, but as shown in FIG. 14I, a portion of the source wiring 80S may extend beyond the gate electrode 55G toward the drain electrode 55D.

[0215] Next, an insulating layer 90 is formed, and then a source pad 70S and a drain pad 70D are formed. For example, the insulating layer 90 is formed over the entire surface by plasma CVD, and then portions of the formed insulating layer 90 are removed by lithography and etching to form openings (not shown). Metal layers are formed by sputtering, plating, or the like to cover the formed openings, and then portions of each metal layer are removed by lithography and etching. As a result, the source pad 70S and the drain pad 70D are formed, as shown in FIGS. 12 and 15H.

[0216] Through the above steps, the nitride semiconductor device 100 according to Example 1 (nitride semiconductor device 3 according to Embodiment 3) can be manufactured.

[0217] In the steps described with reference to FIGS. 14A and 15A, a p ＋ Alternatively, an i-type semiconductor layer 53X may be formed in the nitride semiconductor device 2 according to the second embodiment shown in FIG. 3 . Alternatively, the nitride semiconductor device 1 according to the first embodiment shown in FIG. 2 may be manufactured without forming the i-type semiconductor layer 53X.

[0218] Furthermore, the nitride semiconductor device 100 is similar to the nitride semiconductor device 4 according to the fourth embodiment in that it has p ＋ A manufacturing method of Example 2 having a type impurity region 54 will be described with reference to Figures 16A to 16C. Figures 16A to 16C are cross-sectional views illustrating a step of the manufacturing method of the nitride semiconductor device according to Example 2. Note that, below, differences from the manufacturing method of Example 1 will be described, and descriptions of commonalities will be omitted or simplified.

[0219] In the manufacturing method of Example 2, in the step of forming the anode structure 50A in the manufacturing method of Example 1, p-type impurities are added by ion implantation into the second i-type semiconductor layer 53A and the second p-type semiconductor layer 51A. Specifically, as described with reference to FIGS. 14A to 14C, first, nitride semiconductor film formation (crystal growth), formation of the inactive region 44, and patterning of the i-type semiconductor layer 53X and the p-type semiconductor layer 51X are performed. Next, as shown in FIG. 16A, an insulating layer 60 is formed and then a portion of the insulating layer 60 is removed to form an opening 61A. For example, the insulating layer 60 is formed over the entire surface by plasma CVD, and then a portion of the formed insulating layer 60 is removed by lithography and etching. In this step, unlike Example 1, openings 61D, 61S, and 61K are not formed. The top surface of the second i-type semiconductor layer 53A is exposed at the bottom of the opening 61A.

[0220] 16B, ions are implanted using the insulating layer 60 with the openings 61A as a mask to form the impurity regions 54. For example, ions such as Mg that can make the nitride semiconductor p-type are implanted. As a result, p-type ions are implanted into the second i-type semiconductor layer 53A exposed in the openings 61A and the second p-type semiconductor layer 51A located thereunder. ＋ A doped impurity region 54 is formed.

[0221] 16C , openings 61S, 61D, and 61K are formed by removing portions of the insulating layer 60 by lithography and etching. The top surface of the barrier layer 42 is exposed at the bottom of each of the openings 61K, 61S, and 61D. The side surface of the third p-type semiconductor layer 51D and the top and side surfaces of the third i-type semiconductor layer 53D are also exposed at the opening 61D.

[0222] 14E to 14I. As a result, like the nitride semiconductor device 4 according to the fourth embodiment shown in FIG. ＋ It is possible to manufacture a nitride semiconductor device having the impurity region 54 of the type.

[0223] Next, a manufacturing method of Example 3 in which the nitride semiconductor device 100 has a recess 53a provided in the second i-type semiconductor layer 53A, as in the nitride semiconductor devices 5 and 6 according to the fifth and sixth embodiments, will be described with reference to FIGS. 17A and 17B. FIGS. 17A and 17B are cross-sectional views illustrating a step of the manufacturing method of the nitride semiconductor device according to Example 3. Note that, below, differences from the manufacturing method of Example 1 will be described, and descriptions of commonalities will be omitted or simplified.

[0224] In the manufacturing method according to Example 3, in the step of forming the anode structure 50A in the manufacturing method according to Example 1, a recess 53a is formed by removing at least a portion of the second i-type semiconductor layer 53A, and the anode electrode 55A is formed so as to cover the bottom surface of the recess 53a. Note that the recess 53a may be formed as an opening that exposes the second p-type semiconductor layer 51A, and the anode electrode 55A may be formed so as to contact the second p-type semiconductor layer 51A through the opening.

[0225] Specifically, as described with reference to FIGS. 14A to 14C, first, nitride semiconductor film formation (crystal growth), formation of the inactive region 44, and patterning of the i-type semiconductor layer 53X and the p-type semiconductor layer 51X are performed. Next, as shown in FIG. 17A, an insulating layer 60 is formed, and then a portion of the insulating layer 60 is removed to form an opening 61A. For example, the insulating layer 60 is formed over the entire surface by plasma CVD, and then a portion of the formed insulating layer 60 is removed by lithography and etching. In this process, unlike Example 1, openings 61D, 61S, and 61K are not formed. The top surface of the second i-type semiconductor layer 53A is exposed at the bottom of the opening 61A. Furthermore, etching is performed using the insulating layer 60 with the opening 61A as a mask, thereby removing a portion of the second i-type semiconductor layer 53A to form a recess 53a. This makes it easy to make the size and shape of the opening 61A and the recess 53a the same.

[0226] 17B , openings 61S, 61D, and 61K are formed by removing portions of the insulating layer 60 by lithography and etching. The top surface of the barrier layer 42 is exposed at the bottom of each of the openings 61K, 61S, and 61D. The side surface of the third p-type semiconductor layer 51D and the top and side surfaces of the third i-type semiconductor layer 53D are also exposed at the opening 61D.

[0227] 14E to 14I , a nitride semiconductor device can be manufactured in which a recess 53 a is provided and an anode electrode 55A and a second p-type semiconductor layer 51A are in contact with each other at the bottom surface of the recess 53 a, as in the nitride semiconductor device 5 according to the fifth embodiment shown in FIG.

[0228] Note that Mg ion implantation may be performed before forming the openings 61S, 61D, and 61K. This allows the impurity region 54 to be formed near the bottom of the recess 53a. As in the nitride semiconductor device 6 according to the sixth embodiment shown in FIG. 7, it is possible to manufacture a nitride semiconductor device in which the anode electrode 55A and the impurity region 54 are in contact with each other at the bottom of the recess 53a.

[0229] While nitride semiconductor devices according to one or more aspects have been described above based on the embodiments, the present disclosure is not limited to these embodiments. As long as they do not deviate from the gist of the present disclosure, various modifications conceivable by those skilled in the art to the present embodiments and configurations constructed by combining components of different embodiments are also included within the scope of the present disclosure.

[0230] For example, the source structure 50S, the drain structure 50D, and the cathode structure 50K may be in direct contact with the 2DEG 43. Specifically, a source opening, a drain opening, and a cathode opening may be provided that penetrate the barrier layer 42 and reach the channel layer 41. In this case, a source electrode 55S is provided to cover the bottom and side surfaces of the source opening. A drain electrode 55D is provided to cover the bottom and side surfaces of the drain opening. A cathode electrode 55K is provided to cover the bottom and side surfaces of the cathode opening. The bottom surfaces of the source opening, the drain opening, and the cathode opening are located below the heterointerface between the channel layer 41 and the barrier layer 42. This brings the source electrode 55S into contact with the 2DEG 43 at the side surface of the source opening. The drain electrode 55D is in contact with the 2DEG 43 at the side surface of the drain opening. The cathode electrode 55K is in contact with the 2DEG 43 at the side surface of the cathode opening. The contact resistance can be reduced by bringing the source electrode 55S, the drain electrode 55D, and the cathode electrode 55K into contact with the 2DEG 43. As a result, the on-resistance of the FET 11 and the resistance of the diode 12 can be reduced.

[0231] Furthermore, for example, a recess (gate recess) may be provided on the upper surface of the barrier layer 42 at a position overlapping the gate structure 50G in a plan view. A first p-type semiconductor layer 51G is provided to cover the recess provided in the barrier layer 42. Since the barrier layer 42 is thinner in the portion where the recess is provided, 2DEG 43 is less likely to be generated directly below the recess. This makes it easy to achieve a normally-off state for the FET 11.

[0232] For example, although a TiAl alloy has been given as an example of the main component of the metal layer that forms an ohmic contact with the nitride semiconductor, this is not intended to be limiting. For example, Ta, Ni, Au, or the like may be used as the main component of the metal layer. Furthermore, although TiN has been given as an example of the main component of the conductive layer that forms a Schottky contact with the nitride semiconductor, this is not intended to be limiting. For example, Pd, TaN, or the like may be used as the main component of the conductive layer.

[0233] Furthermore, various modifications, substitutions, additions, omissions, etc. can be made to the above-described embodiments within the scope of the claims or their equivalents.

[0234] The present disclosure can be used, for example, in a power amplifier for high-output or high-frequency applications, a wireless communication base station or terminal device in which the power amplifier is used, or a wireless power supply device that transmits power using microwaves.

[0235] 1, 2, 3, 4, 5, 6, 100 Nitride semiconductor device 11, 111 FET 12, 112, 113 Diode 21, 121 First active region 22, 122 Second active region 30 Substrate 31 Element isolation region 40 Semiconductor laminate 41 Channel layer 42 Barrier layer 43 2DEG 44 Inactive region 50A Anode structure 50D, 150D Drain structure 50G, 150G Gate structure 50K Cathode structure 50S, 150S Source structure 51A Second p-type semiconductor layer 51D Third p-type semiconductor layer 51G First p-type semiconductor layer 51X p-type semiconductor layer 52A Second p ＋ First p-type semiconductor layer 52G ＋i-type semiconductor layer 53A Second i-type semiconductor layer 53a Recess 53D Third i-type semiconductor layer 53G First i-type semiconductor layer 53X i-type semiconductor layer 54 Impurity region 55A Anode electrode 55D Drain electrode 55G Gate electrode 55K Cathode electrode 55S Source electrode 56A, 56D, 56K, 56S TiAl alloy layer 56G TiN layer 57A, 57D, 57G, 57K, 57S Al layer 58A, 58D, 58K, 58S Ti layer 60, 65, 66, 90 Insulating layer 61A, 61D, 61G, 61K, 61S, 67A, 67D, 67K, 67S Opening 70D Drain pad 70G Gate pad 70S Source pad 80A Anode wiring 80D Drain wiring 80G Gate wiring 80K Cathode wiring 80S Source wiring 123 Third active region

Claims

1. A nitride semiconductor device including an enhancement type field effect transistor and a diode, comprising: a substrate; a semiconductor stack including a two-dimensional electron gas provided above the substrate; a source structure, a drain structure, and a gate structure for the field effect transistor provided in a first region; and an anode structure and a cathode structure for the diode provided in a second region different from the first region, wherein the gate structure includes a first p-type semiconductor layer and a first metal layer provided above the first p-type semiconductor layer, the anode structure includes a second p-type semiconductor layer and a second metal layer provided above the second p-type semiconductor layer, the second p-type semiconductor layer has the same layer structure as the first p-type semiconductor layer, the source structure is electrically connected to the anode structure, and the gate structure is electrically connected to the cathode structure, and the second metal layer is formed using a material different from that of the first metal layer.

2. The nitride semiconductor device according to claim 1, wherein the first p-type semiconductor layer and the second p-type semiconductor layer each contain a Group III nitride semiconductor as a main component, and the second metal layer contains an alloy of Ti and Al.

3. A nitride semiconductor device including an enhancement type field effect transistor and a diode, comprising: a substrate; a semiconductor stack including a two-dimensional electron gas provided above the substrate; a source structure, a drain structure, and a gate structure for the field effect transistor provided in a first region; and an anode structure and a cathode structure for the diode provided in a second region different from the first region, wherein the gate structure includes a first p-type semiconductor layer and a first metal layer provided above the first p-type semiconductor layer, the anode structure includes a second p-type semiconductor layer and a second metal layer provided above the second p-type semiconductor layer, the second p-type semiconductor layer has the same layer structure as the first p-type semiconductor layer, the source structure is electrically connected to the anode structure, the gate structure is electrically connected to the cathode structure, and the first metal layer is Schottky-connected to the first p-type semiconductor layer, the second metal layer is in ohmic contact with the second p-type semiconductor layer.

4. The nitride semiconductor device according to any one of claims 1 to 3, wherein the first metal layer is in contact with an upper surface of the first p-type semiconductor layer, and the second metal layer is in contact with an upper surface of the second p-type semiconductor layer.

5. The nitride semiconductor device according to any one of claims 1 to 3, wherein the gate structure further includes a first semiconductor layer provided between the first p-type semiconductor layer and the first metal layer, and the anode structure further includes a second semiconductor layer provided between the second p-type semiconductor layer and the second metal layer.

6. The nitride semiconductor device according to claim 5, wherein the first metal layer is in contact with an upper surface of the first semiconductor layer, and the second metal layer is in contact with an upper surface of the second semiconductor layer.

7. The nitride semiconductor device according to claim 6, wherein the first semiconductor layer is a p-type semiconductor layer having a higher p-type impurity concentration than the first p-type semiconductor layer, and the second semiconductor layer is a p-type semiconductor layer having a higher p-type impurity concentration than the second p-type semiconductor layer.

8. The nitride semiconductor device according to claim 6, wherein the first semiconductor layer is an i-type semiconductor layer having a larger band gap than the first p-type semiconductor layer, and the second semiconductor layer is an i-type semiconductor layer having a larger band gap than the second p-type semiconductor layer.

9. The nitride semiconductor device according to claim 8, wherein the second semiconductor layer and the second p-type semiconductor layer are provided with impurity regions doped with p-type impurities, the p-type impurity concentration of the impurity regions is higher than the p-type impurity concentration of a region of the second p-type semiconductor layer other than the impurity regions, and the second metal layer is in contact with the impurity regions.

10. The nitride semiconductor device according to claim 5, wherein the second semiconductor layer has a recess, the second metal layer is in contact with a bottom surface of the recess, and the first metal layer is in contact with an upper surface of the first semiconductor layer.

11. The nitride semiconductor device according to claim 10, wherein the recess is an opening that penetrates the second semiconductor layer, and the second metal layer is in contact with the second p-type semiconductor layer at the bottom surface of the recess.

12. The nitride semiconductor device according to claim 11, wherein the second p-type semiconductor layer is provided with an impurity region doped with p-type impurities, the p-type impurity concentration of the impurity region is higher than the p-type impurity concentration of a region of the second p-type semiconductor layer other than the impurity region, and the second metal layer is in contact with the impurity region.

13. The nitride semiconductor device according to any one of claims 1 to 3, wherein the second metal layer has a shape that is elongated in one direction in a plan view, and the connection between the second metal layer and the second p-type semiconductor layer is discrete along the one direction.

14. The nitride semiconductor device according to any one of claims 1 to 3, wherein the cathode structure is provided in a lattice pattern in a plan view, and the anode structure is provided for each opening of the lattice-shaped cathode structure in a plan view.

15. The nitride semiconductor device according to any one of claims 1 to 3, wherein the cathode structure is provided in an annular shape along the outer periphery of the second region in a plan view, and the anode structure is surrounded by the cathode structure in a plan view.

16. A method for manufacturing a nitride semiconductor device including an enhancement type field effect transistor and a diode, comprising the steps of: forming a semiconductor laminate containing a two-dimensional electron gas above a substrate; forming a source structure, a drain structure, and a gate structure for the field effect transistor in a first region, and forming an anode structure and a cathode structure for the diode in a second region different from the first region; electrically connecting the source structure and the anode structure; and electrically connecting the gate structure and the cathode structure, wherein the gate structure includes a first p-type semiconductor layer and a first metal layer provided above the first p-type semiconductor layer, and the anode structure includes a second p-type semiconductor layer and a second metal layer provided above the second p-type semiconductor layer, the first p-type semiconductor layer and the second p-type semiconductor layer being formed simultaneously, and at least a portion of the first metal layer and at least a portion of the second metal layer being formed in different steps.

17. The method for manufacturing a nitride semiconductor device according to claim 16, wherein in the step of forming the anode structure, a Ti film and an Al film are formed in this order on the second p-type semiconductor layer as the second metal layer, and then heat treatment is performed to alloy the Ti of the Ti film and the Al of the Al film.

18. The method for manufacturing a nitride semiconductor device according to claim 17, wherein the heat treatment is performed by laser annealing.

19. A method for manufacturing a nitride semiconductor device including an enhancement type field effect transistor and a diode, comprising the steps of: forming a semiconductor laminate including a two-dimensional electron gas above a substrate; forming a source structure, a drain structure, and a gate structure for the field effect transistor in a first region, and forming an anode structure and a cathode structure for the diode in a second region different from the first region; electrically connecting the source structure and the anode structure; and electrically connecting the gate structure and the cathode structure, wherein the gate structure includes a first p-type semiconductor layer and a first metal layer provided above the first p-type semiconductor layer, the anode structure includes a second p-type semiconductor layer and a second metal layer provided above the second p-type semiconductor layer, the first p-type semiconductor layer and the second p-type semiconductor layer are formed simultaneously, and the first metal layer is Schottky-connected to the first p-type semiconductor layer, the second metal layer is in ohmic contact with the second p-type semiconductor layer.

20. The method for manufacturing a nitride semiconductor device according to any one of claims 16 to 19, wherein in the step of forming the gate structure and the anode structure, a first semiconductor layer is formed on the first p-type semiconductor layer, and a second semiconductor layer is formed on the second p-type semiconductor layer, and the first semiconductor layer and the second semiconductor layer are formed simultaneously.

21. The method for manufacturing a nitride semiconductor device according to claim 20, wherein in the step of forming the anode structure, p-type impurities are added by implanting ions into the second semiconductor layer and the second p-type semiconductor layer, and the p-type impurity concentration in the region where the ion implantation has been performed is higher than the p-type impurity concentration in the region of the second p-type semiconductor layer where the ion implantation has not been performed.

22. The method for manufacturing a nitride semiconductor device according to claim 20, wherein in the step of forming the anode structure, a recess or an opening exposing the second p-type semiconductor layer is formed by removing at least a portion of the second semiconductor layer, and the second metal layer is formed so as to cover the bottom surface of the recess or to be in contact with the second p-type semiconductor layer through the opening.

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