Semiconductor package bonding method and semiconductor package bonding apparatus used therefor

Abstract

Provided is a semiconductor package bonding method. This semiconductor package bonding method may comprise the steps of: preparing a semiconductor substrate having a metal pad on one surface thereof, and a semiconductor chip having a bump on one surface thereof and bonded to the semiconductor substrate; positioning the semiconductor chip on the semiconductor substrate such that the metal pad and the bump are aligned in a vertical direction; and bonding the semiconductor substrate and the semiconductor chip to each other under a flux-less condition so that the metal pad and the bump are in electrical contact, wherein, in the step of bonding the semiconductor chip, a bonding interface between the metal pad and the bump is irradiated with ultraviolet rays, and the ultraviolet irradiation energy is relatively greater than the metal oxide film formation energy such that the formation of the metal oxide film at the bonding interface between the metal pad and the bump is inhibited by the ultraviolet rays.

Description

Semiconductor package bonding method and semiconductor package bonding device used therefor

[0001] The present invention relates to a semiconductor package bonding method and a semiconductor package bonding device used therein, and more specifically, to a semiconductor package bonding method and a semiconductor package bonding device used therein, which can bond a semiconductor chip and a semiconductor substrate under flux-less process conditions using ultraviolet irradiation.

[0002] During the semiconductor package bonding process, an oxide film is formed on metal surfaces such as copper and solder (balls, Cu-filler bumps, etc.) at high temperatures.

[0003] These oxide films prevent direct bonding between metals. To prevent this, flux is essential in conventional semiconductor package bonding processes.

[0004] The above flux removes the oxide film on the metal surface to create a clean surface, enabling bonding, and improves the wettability of the metal surface, allowing the solder to spread well on the metal surface, thereby improving the reliability of the bonding.

[0005] Likewise, in the case of a conventional semiconductor package bonding process using flux, a cleaning process to remove any remaining flux residue is essential once the bonding process is completed.

[0006] However, as advanced semiconductor packaging becomes more miniaturized, there is a problem of increased flux residue within the semiconductor package.

[0007] These residues reduce the electrical reliability of semiconductor packages and are a major cause of corrosion defects.

[0008] Accordingly, a flux-less joining technology that does not use flux has been proposed.

[0009] Conventional fluxless bonding technologies include methods using formic acid and methods using plasma.

[0010] The method using the above formic acid removes the oxide film of the solder using formic acid gas and then proceeds with soldering.

[0011] However, it was confirmed that the method using formic acid had a lower reliability due to more voids than when flux was used.

[0012] Additionally, the method using formic acid is a process that uses a very hazardous gas, so there are clear safety issues, and the reliability of the process has not yet been secured.

[0013] Meanwhile, the method using the above plasma has the advantage of enabling soldering even in ultra-fine pitch through a fluxless bonding process utilizing argon (Ar) and hydrogen (H2) plasma treatment.

[0014] However, the method using plasma has the problem that the process equipment is complex and costs a lot.

[0015] The technical problem to be solved by the present invention is to provide a semiconductor package bonding method and a semiconductor package bonding device used therefor, which can bond a semiconductor chip and a semiconductor substrate under flux-less process conditions using ultraviolet irradiation.

[0016] The technical problems to be solved by the present invention are not limited to those described above.

[0017] To solve the above technical problem, the present invention provides a semiconductor package bonding method.

[0018] According to one embodiment, the semiconductor package bonding method includes the steps of preparing a semiconductor substrate having a metal pad provided on one surface and a semiconductor chip having a bump provided on one surface and bonded to the semiconductor substrate; positioning the semiconductor chip on the semiconductor substrate such that the metal pad and the bump are aligned in a vertical direction; and bonding the semiconductor substrate and the semiconductor chip under flux-less conditions such that the metal pad and the bump make electrical contact, wherein in the step of bonding the semiconductor chip, ultraviolet rays are irradiated to a bonding interface between the metal pad and the bump, and the ultraviolet irradiation energy may be relatively greater than the metal oxide film formation energy such that the ultraviolet rays prevent the formation of a metal oxide film at the bonding interface between the metal pad and the bump.

[0019] According to one embodiment, when heat is used as energy for bonding the semiconductor substrate and the semiconductor chip, in the step of positioning the semiconductor chip, heat is applied to the semiconductor chip while simultaneously irradiating ultraviolet rays to the bump, and in the step of bonding the semiconductor chip, when the temperature of the bump reaches a preset target temperature, the semiconductor chip is lowered onto the semiconductor substrate to bond the bump to the metal pad, while continuously irradiating the ultraviolet rays to the bonding interface between the metal pad and the bump.

[0020] According to one embodiment, in the step of bonding the semiconductor chip, an IMC (Intermetallic Compound) layer may be created at the bonding interface between the metal pad and the bump through interatomic bonding by diffusion of the metal forming the metal pad and the metal forming the bump.

[0021] According to one embodiment, when the metal pad is made of a Cu pad and the bump is made of a solder bump, an IMC layer made of Cu6Sn5 can be formed at the bonding interface between the Cu pad and the solder bump.

[0022] According to one embodiment, the angle at which the ultraviolet ray is irradiated to the bonding interface between the metal pad and the bump can be adjusted within a range of 0° to 90°.

[0023] According to one embodiment, the ultraviolet ray can be irradiated to the bonding interface of the metal pad and the bump with an intensity of 10 mV to 2000 mV.

[0024] In one embodiment, the ultraviolet ray may be irradiated to the bump for a time greater than 0 seconds and less than or equal to 70 seconds.

[0025] In one embodiment, the ultraviolet ray may be either UV-C or UV-C (Ozone).

[0026] According to one embodiment, the temperature of the heat applied to the semiconductor chip can be controlled to 250°C to 300°C.

[0027] According to one embodiment, the method comprises a step of moving the semiconductor chip onto the semiconductor substrate, wherein during the moving step, a flipping step of the semiconductor chip is included, and the moving step may include a step of applying heat and the ultraviolet ray to the semiconductor chip.

[0028] According to one embodiment, the semiconductor substrate may be prepared as any one of a wafer chip, a PCB, a glass substrate, an interposer, and a carrier.

[0029] According to one embodiment, the semiconductor substrate may be surface treated using any one of the surface treatment methods of OSP (Organic Solderability Preservative), ENIG (Electroless Nickel Immersion Gold), and ENEPIG (Electroless Nickel Electroless Palladium Immersion Gold).

[0030] Meanwhile, the present invention provides a semiconductor package bonding device.

[0031] According to one embodiment, the semiconductor package bonding device may include a lower chuck on which a semiconductor substrate having a metal pad provided on one surface is vacuum-absorbed; an upper chuck that is movably provided on the lower chuck and on which a semiconductor chip having a bump provided on one surface is vacuum-absorbed so as to be aligned vertically with the semiconductor substrate; a heater that is linked to the lifting and lowering operation of the upper chuck and applies heat to the semiconductor chip; a first ultraviolet irradiation unit that is removably installed between the lower chuck and the upper chuck and irradiates ultraviolet rays toward the bump when heat is applied from the heater to the semiconductor chip vacuum-absorbed to the upper chuck; and a second ultraviolet irradiation unit that is installed on the lower chuck and irradiates ultraviolet rays toward a bonding interface between the metal pad and the bump when the upper chuck is lowered under a flux-less condition to bond the bump to the metal pad.

[0032] According to one embodiment, when the bump is bonded to the metal pad, an IMC layer may be created at the bonding interface between the metal pad and the bump through interatomic bonding by diffusion between the metal forming the metal pad and the metal forming the bump.

[0033] According to an embodiment of the present invention, there is provided a method for manufacturing a semiconductor chip, comprising: preparing a semiconductor substrate having a metal pad provided on one surface thereof and a semiconductor chip having a bump provided on one surface thereof and bonded to the semiconductor substrate; positioning the semiconductor chip on the semiconductor substrate such that the metal pad and the bump are aligned in a vertical direction; and bonding the semiconductor substrate and the semiconductor chip under flux-less conditions such that the metal pad and the bump make electrical contact, wherein in the step of bonding the semiconductor chip, ultraviolet rays are irradiated to a bonding interface between the metal pad and the bump, and the ultraviolet irradiation energy may be relatively greater than the metal oxide film formation energy such that the ultraviolet rays prevent formation of a metal oxide film at the bonding interface between the metal pad and the bump.

[0034] Thus, according to an embodiment of the present invention, a semiconductor package bonding method and a semiconductor package bonding device used therefor, which can bond a semiconductor chip and a semiconductor substrate under flux-less process conditions through ultraviolet irradiation, can be provided.

[0035] That is, according to an embodiment of the present invention, by irradiating with ultraviolet rays instead of flux, it is possible to prevent the formation of a metal oxide film at the bonding interface between the bump and the metal pad, which interferes with their direct bonding.

[0036] In addition, according to an embodiment of the present invention, physical and mechanical damage caused by flux residue can be prevented through a fluxless process, thereby enabling reliable bonding.

[0037] In this way, according to an embodiment of the present invention, the flux dipping and de-flux processes can be omitted, thereby simplifying the bonding process and maximizing efficiency.

[0038] In addition, according to an embodiment of the present invention, a high-reliability bonding process may be possible even in an ultra-fine pitch bonding process of advanced semiconductors, thereby enabling the production of high value-added products in the semiconductor industry.

[0039] Figure 1 is a flowchart illustrating a semiconductor package bonding method according to one embodiment of the present invention.

[0040] Figures 2 and 3 are schematic diagrams for explaining step S110 of Figure 1.

[0041] Figure 4 is a schematic diagram for explaining step S120 of Figure 1.

[0042] Figure 5 is a schematic diagram for explaining step S130 of Figure 1.

[0043] FIGS. 6 and 7 are exemplary diagrams showing a heat source used in a semiconductor package bonding method according to one embodiment of the present invention.

[0044] FIG. 8 is a set of images of a cross-section of a semiconductor package taken using a scanning electron microscope according to the type of ultraviolet ray used in a semiconductor package bonding method according to an embodiment of the present invention.

[0045] FIG. 9 is a graph showing the temperature profile of a semiconductor chip in a semiconductor package bonding method according to an embodiment of the present invention.

[0046] FIG. 10 is a graph showing the relationship between temperature and bump deformation over time in a semiconductor package bonding method according to an embodiment of the present invention.

[0047] Figure 11 is an image of a cross-section of a semiconductor package manufactured according to Example 1 and Comparative Example 1, taken using an optical microscope.

[0048] Figures 12 and 13 are images of cross-sections of semiconductor packages manufactured according to Comparative Example 1 taken with a scanning electron microscope at different magnifications.

[0049] Figures 14 to 16 are images of cross-sections of semiconductor packages manufactured according to Example 1 taken with a scanning electron microscope at different magnifications.

[0050] Figures 17 to 19 are EDS analysis results for a semiconductor package manufactured according to Example 1.

[0051] Figure 20 is an image of a cross-section of a semiconductor package manufactured according to Examples 2 and 3 and Comparative Examples 2 and 3, taken using an optical microscope and a scanning electron microscope.

[0052] Figure 21 is a schematic diagram illustrating Experimental Example 1.

[0053] Figure 22 is an image of the upper surface of a copper plate directly irradiated with ultraviolet rays.

[0054] Figure 23 is an image of the lower surface of a copper plate in contact only with a heat source.

[0055] Figure 24 shows the XPS analysis results for the upper and lower surfaces of the copper plate according to Experimental Example 1.

[0056] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings. However, the technical concept of the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed content is thorough and complete and to sufficiently convey the spirit of the present invention to those skilled in the art.

[0057] In this specification, when a component is referred to as being on another component, it means that it can be formed directly on the other component, or a third component may be interposed between them. Furthermore, in the drawings, shapes and sizes are exaggerated for the purpose of effectively explaining the technical contents.

[0058] Additionally, although terms such as first, second, and third have been used to describe various components in various embodiments of this specification, these components should not be limited by these terms. These terms are only used to distinguish one component from another. Thus, what is referred to as a first component in one embodiment may be referred to as a second component in another embodiment. Each embodiment described and illustrated herein also includes its complementary embodiments. Additionally, the term "and / or" has been used herein to mean including at least one of the components listed before and after.

[0059] In the specification, singular expressions include plural expressions unless the context clearly dictates otherwise. In addition, terms such as "comprise" or "have" are intended to specify the presence of a feature, number, step, component, or combination thereof described in the specification, and should not be construed as excluding the presence or addition of one or more other features, numbers, steps, components, or combinations thereof. In addition, the term "connection" is used in the present specification to mean both indirectly connecting multiple components and directly connecting them.

[0060] Additionally, terms such as “part,” “unit,” and “module” described in the specification mean a unit that processes at least one function or operation, which may be implemented by hardware, software, or a combination of hardware and software.

[0061] In addition, when describing the present invention below, if it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the gist of the present invention, the detailed description will be omitted.

[0062]

[0063] FIG. 1 is a flowchart showing a semiconductor package bonding method according to an embodiment of the present invention, FIG. 2 and FIG. 3 are schematic diagrams for explaining step S110 of FIG. 1, FIG. 4 is a schematic diagram for explaining step S120 of FIG. 1, FIG. 5 is a schematic diagram for explaining step S130 of FIG. 1, FIG. 6 and FIG. 7 are exemplary diagrams showing a heat source used in a semiconductor package bonding method according to an embodiment of the present invention, FIG. 8 is images of a cross-section of a semiconductor package taken with a scanning electron microscope according to the type of ultraviolet ray used in a semiconductor package bonding method according to an embodiment of the present invention, FIG. 9 is a graph showing a temperature profile of a semiconductor chip in a semiconductor package bonding method according to an embodiment of the present invention, and FIG. 10 is a graph showing a relationship between temperature and bump deformation over time in a semiconductor package bonding method according to an embodiment of the present invention.

[0064]

[0065] A semiconductor package bonding method according to an embodiment of the present invention is a method of bonding a semiconductor substrate (100 in FIG. 2) and a semiconductor chip (200 in FIG. 3) without using flux, wherein, during a bonding process using any one of Mass Reflow (MR), Thermal Compression Bonding (TCB), Laser Assisted Bonding (LAB), and Intense Pulsed Light (IPL) bonding, simultaneous ultraviolet (UV) irradiation is performed to enable metal-to-metal bonding between a metal pad (110 in FIG. 2) of a semiconductor substrate (100 in FIG. 2) and a bump (210 in FIG. 3) of a semiconductor chip (200 in FIG. 3) under flux-less conditions.

[0066] A semiconductor package bonding method according to an embodiment of the present invention is not a complicated process, does not generate additional heat when irradiated with ultraviolet rays, and can enable fast bonding, compared to a semiconductor package bonding method that does not use flux, such as a semiconductor package bonding method that uses flux, a bonding method that uses formic acid, or a bonding method that uses plasma.

[0067] That is, the semiconductor package bonding method according to one embodiment of the present invention can maximize efficiency by omitting the flux dipping and de-flux processes, and can fundamentally solve various problems caused by flux residue in a process using flux, thereby achieving excellent bonding reliability.

[0068]

[0069] Referring to FIG. 1, a semiconductor package bonding method according to one embodiment of the present invention may include steps S110, S120, and S130.

[0070]

[0071] Hereinafter, each step of a semiconductor package bonding method according to an embodiment of the present invention will be described in detail.

[0072]

[0073] S110 stage

[0074] As illustrated in FIG. 2, the S110 step is a step of preparing a semiconductor substrate (100) on which a metal pad (110) is provided on one surface.

[0075] The above semiconductor substrate (100) is a substrate on which a semiconductor chip (200 in FIG. 3) is mounted, and can provide electrical connection and mechanical support.

[0076] That is, the semiconductor substrate (100) is responsible for signal transmission between the semiconductor chip (200 in FIG. 3) and an external circuit, and plays a role in maintaining heat dissipation and mechanical strength in a semiconductor package formed by joining the semiconductor substrate (100) and the semiconductor chip (200 in FIG. 3).

[0077] According to one embodiment of the present invention, the semiconductor substrate (100) may be prepared using any one of a wafer chip, a printed circuit board (PCB), a glass plate (glass panel), an interposer, and a carrier.

[0078] In the above step S110, a metal pad (110) can be formed on one side of the semiconductor substrate (100), the upper surface based on the drawing.

[0079] The above metal pad (110) can be provided in a pattern that enables electrical connection with a bump (210 in FIG. 3) provided on one surface of a semiconductor chip (200 in FIG. 3) that is flip-chip bonded to the semiconductor substrate (100).

[0080] According to one embodiment of the present invention, a Cu pad may be provided as the metal pad (110).

[0081] Meanwhile, in the above step S110, a semiconductor substrate (100) having a metal pad (110) provided on the upper surface can be surface-treated using any one of the surface treatment methods of OSP (Organic Solderability Preservative), ENIG (Electroless Nickel Immersion Gold), and ENEPIG (Electroless Nickel Electroless Palladium Immersion Gold).

[0082] That is, the semiconductor package bonding method according to one embodiment of the present invention can bond a semiconductor chip (200 in FIG. 3) to a surface-treated semiconductor substrate (100) under fluxless conditions, which will be described in more detail below.

[0083] Here, the OSP is a surface treatment method that forms a thin organic protective film on a metal pad (110) provided on one side of a semiconductor substrate (100) to prevent oxidation and maintain solderability, and is widely used because it is environmentally friendly and inexpensive.

[0084] These OSPs may include a degreasing process for removing contaminants on the surface of a semiconductor substrate (100), a rinsing process for removing chemicals remaining after degreasing, a micro-etching process for removing an oxide film by finely etching the surface of a metal pad (110), an acid treatment process for activating the surface of a metal pad (110), an OSP coating process for forming a protective film using an OSP solution of the benzotriazole or imidazole series, and a drying process for drying the protective film using hot air or infrared (IR).

[0085] In addition, the ENIG is a surface treatment method that improves oxidation prevention and solderability by plating electroless nickel on the surface of a metal pad (110) and then applying immersion gold.

[0086] Such ENIG may include a degreasing process to remove contaminants on the surface of a semiconductor substrate (100), a micro-etching process to activate the surface of a metal pad (110) to increase the adhesion of nickel plating, an electroless nickel plating process to form a protective film by plating nickel on the surface of the metal pad (110), and an immersion gold plating process to form a thin gold (Au) film on the surface of nickel to prevent oxidation and improve electrical contact.

[0087] And the above ENEPIG is a surface treatment method that increases reliability and corrosion resistance by sequentially plating electroless nickel (Ni), electroless palladium (Pd), and immersion gold (Au).

[0088] Such ENEPIG may include a pretreatment process for treating the surface of a metal pad (110) of a semiconductor substrate (100) to enable smooth plating, an electroless nickel plating process for plating nickel on the surface of the metal pad (110) to form a protective film, an electroless palladium plating process for plating palladium on the nickel protective film to prevent oxidation and enhance reliability, and an immersion gold plating process for forming a thin gold (Au) film on palladium to improve solderability and electrical contact.

[0089] Meanwhile, as illustrated in FIG. 3, in step S110, a semiconductor chip (200) can be prepared along with preparing a semiconductor substrate (100) having a metal pad (110) provided on one side.

[0090] At this time, according to one embodiment of the present invention, the semiconductor chip (200) can be bonded to the semiconductor substrate (100) through a flip chip bonding process.

[0091] For this purpose, a bump (210) may be provided on one side of the semiconductor chip (200), the upper surface based on the drawing.

[0092] These bumps (210) can be provided in a form that is electrically connectable to a metal pad (110), for example, a Cu pad, provided on the upper surface of a semiconductor substrate (100).

[0093] In the above step S110, a solder bump having a size of several micrometers to several hundred micrometers can be provided on the upper surface of the semiconductor chip (200) as the bump (210).

[0094] In this way, a bump (210) made of solder bumps can be formed into a ball shape through a reflow process.

[0095] However, this is merely an example, and a gold (Au) bump may be provided as the bump (210). Such a gold bump is formed by plating and may be maintained in a square pillar shape. The gold bump can provide high electrical reliability and corrosion resistance.

[0096] Additionally, a copper pillar bump may be provided as the bump (210). This copper pillar bump may be formed by electroplating. The copper pillar bump has higher mechanical strength than a solder bump and may be suitable for micro-pitch packages. This copper pillar bump has recently been widely used in high-speed signal transmission and 3D IC packages.

[0097] Additionally, a conductive polymer bump may be provided as the bump (210). The conductive polymer bump may be formed using a conductive resin mixed with metal particles. Such a conductive polymer bump can be processed at low temperatures and is utilized in flexible substrates. The conductive polymer bump is environmentally friendly and inexpensive.

[0098] In this way, a semiconductor chip (200) bonded to a semiconductor substrate (100) through a flip chip bonding process can be prepared as a single chip or multiple chips for one semiconductor substrate (100).

[0099] Here, the semiconductor chip (200) may include EMC (epoxy molding compound).

[0100] The above EMC can protect the semiconductor chip (200) from dust, moisture, impact, etc., and prevent interference between internal circuits, thereby supporting stable operation. In addition, the EMC can effectively disperse heat generated from the semiconductor chip (200) to prevent overheating, and increase the durability of the semiconductor chip (200) to enable it to withstand external impact.

[0101] In this way, in the above step S110, a semiconductor substrate (100) having a metal pad (110) provided on one side and a semiconductor chip (200) having a bump (210) provided on one side so as to be bonded to the semiconductor substrate (100) through a flip chip bonding process can be prepared.

[0102]

[0103] S120 stage

[0104] The above step S120 is a step for positioning the semiconductor substrate (100) and semiconductor chip (200) prepared through the above step S110 so that they can be bonded.

[0105] According to one embodiment of the present invention, in the step S120, the semiconductor chip (200) can be positioned on the semiconductor substrate (100) so that the semiconductor chip (200) is flip-chip bonded to the semiconductor substrate (100).

[0106] That is, in the above step S120, the semiconductor chip (200) can be positioned on the semiconductor substrate (100) so that the metal pad (110) provided on one surface of the semiconductor substrate (100) and the bump (210) provided on one surface of the semiconductor chip (200) are aligned in the vertical direction facing each other.

[0107] At this time, in the above step S120, the semiconductor chip (200) can be preheated to a temperature required for bonding the semiconductor substrate (100) and the semiconductor chip (200).

[0108] More specifically, in the step S120, a bump (210) provided on one side of a semiconductor chip (200) can be heated by any one heat source selected from among an electric heater used as a heat source for MR (Mass Reflow) and TCB (Thermal Compression Bonding), a laser used as a heat source for LAB (Laser Assisted Bonding), and an IPL used as a heat source for IPL (Intense Pulsed Light) bonding.

[0109] According to one embodiment of the present invention, in the step S120, the temperature of the heat applied to the semiconductor chip (200), more specifically, the bump (210) provided on one surface of the semiconductor chip (200), through the heat source can be controlled to 250°C to 300°C.

[0110] At this time, according to one embodiment of the present invention, in the step S120, heat may be applied to the semiconductor chip (200) as described above, while ultraviolet rays may be irradiated to the bump (210).

[0111] Through this, it is possible to prevent a metal oxide film from being formed on the surface of the bump (210).

[0112] That is, according to one embodiment of the present invention, by irradiating the bump (210) with ultraviolet rays during a high-temperature process, it is possible to prevent a metal oxide film that interferes with direct bonding between metals from being formed on the surface of the bump (210).

[0113] At this time, the irradiation energy of the ultraviolet ray irradiated to the bump (210) may be relatively greater than the energy at which a metal oxide film is formed on the surface of the bump (210) so as to prevent the formation of a metal oxide film on the surface of the bump (210) by the ultraviolet ray.

[0114] This can be understood as the metal oxide film generated on the surface of the bump (210) during the high-temperature process being decomposed by ultraviolet rays having energy greater than its generation energy.

[0115] According to one embodiment of the present invention, as the ultraviolet ray irradiated to the bump (210), one of UV-A having a wavelength of 325 nm to 400 nm, UV-B having a wavelength of 280 nm to 315 nm, UV-C having a wavelength of 200 nm to 280 nm, and UV-C (Ozone) having a wavelength of 100 nm to 200 nm may be selected depending on the type, structure, and conditions of the semiconductor package.

[0116] At this time, if the bump (210) is made of a solder bump, either UV-C or UV-C (Ozone) can be used as the ultraviolet ray irradiated to the bump (210).

[0117] According to one embodiment of the present invention, such ultraviolet rays can be irradiated to the bump (210) at an intensity of 10 mV to 2000 mV.

[0118] Additionally, the above ultraviolet rays can be irradiated to the bump (210) for a time exceeding 0 seconds and less than or equal to 70 seconds.

[0119] Through this, even if the semiconductor chip (200) is preheated to 250°C to 300°C, a metal oxide film that interferes with direct bonding with the metal pad (110) provided on one surface of the semiconductor substrate (100) may not be formed on the surface of the bump (210) provided on one surface of the semiconductor chip (200).

[0120] Meanwhile, for flip chip bonding, when a semiconductor chip (200) is positioned on a semiconductor substrate (100) and then the semiconductor chip (200) is heated, time is wasted while the temperature is raised to the target temperature, and the bonding process is not continued and a break occurs.

[0121] Accordingly, according to a modified embodiment, a step of moving the semiconductor chip (200) prepared through the above step S110 onto a semiconductor substrate (100) may be included.

[0122] At this time, according to a modified embodiment, during the moving step, a flipping step of the semiconductor chip (200) may be included.

[0123] The above moving step may include a step of applying heat and ultraviolet rays to the semiconductor chip (200).

[0124] That is, according to a modified embodiment, the semiconductor chip (200) can be preheated so that the semiconductor chip (200) reaches a bonding temperature while moving the semiconductor chip (200) onto the semiconductor substrate (100) for flip chip bonding.

[0125] Accordingly, after positioning the semiconductor chip (200) on the semiconductor substrate (100), the semiconductor chip (200) and the semiconductor substrate (100) can be bonded immediately without additional heating.

[0126] Through this, the bonding process time can be shortened and the bonding process can be carried out continuously without interruption.

[0127] In addition, by continuously applying heat to the semiconductor chip (200) while moving the semiconductor chip (200) so that the semiconductor chip (200) is positioned correctly on the semiconductor substrate (100) for flip chip bonding and simultaneously irradiating ultraviolet rays to the bump (210) provided on one surface of the semiconductor chip (200), even if heat is applied to the semiconductor chip (200) while moving the semiconductor chip (200), the formation of a metal oxide film on the surface of the bump (210) provided on one surface of the semiconductor chip (200) can be prevented.

[0128] Meanwhile, as illustrated in FIG. 4, a semiconductor package bonding device (10) may be used in a semiconductor package bonding method according to an embodiment of the present invention.

[0129] At this time, the semiconductor package bonding device (10) may be a bonding device of the TCB (Thermal Compression Bonding) method.

[0130] According to one embodiment of the present invention, such a semiconductor package bonding device (10) may include a lower chuck (11), an upper chuck (12), a heater (13), a first ultraviolet irradiation unit (14), and a second ultraviolet irradiation unit (15).

[0131]

[0132] The lower chuck (11) can support a semiconductor substrate (100) having a metal pad (110) provided on one surface. For this purpose, the semiconductor substrate (100) can be fixed to the upper surface of the lower chuck (11).

[0133] At this time, the semiconductor substrate (100) can be vacuum-absorbed on the upper surface of the lower chuck (11). Accordingly, the semiconductor substrate (100) can be easily fixed to the upper surface of the lower chuck (11) and can be easily separated from the upper surface of the lower chuck (11).

[0134] The semiconductor substrate (100) vacuum-absorbed on the upper surface of the lower chuck (11) can be placed on the upper surface of the lower chuck (11) so that the metal pad (110) faces upward.

[0135] The upper chuck (12) can be vertically aligned on the lower chuck (11). The upper chuck (12) can be provided to be movable on the lower chuck (11). That is, the upper chuck (12) can be lowered toward the lower chuck (11) and can be raised in a direction away from the lower chuck (11).

[0136] The above upper chuck (12) can support a semiconductor chip (200) having a bump (210) provided on one surface.

[0137] According to one embodiment of the present invention, the semiconductor chip (200) can be bonded to the semiconductor substrate (100) through flip chip bonding. Accordingly, since the semiconductor substrate (100) is vacuum-absorbed on the upper surface of the lower chuck (11) in a direction in which the metal pad (110) faces upward, the semiconductor chip (200) can be vacuum-absorbed on the lower surface of the upper chuck (12).

[0138] At this time, the upper chuck (12) can be positioned so that the bump (210) provided on one surface of the semiconductor chip (200) is aligned vertically with the metal pad (110) of the semiconductor substrate (100) fixed to the lower chuck (11).

[0139] The upper chuck (12) on which the semiconductor chip (200) is vacuum-absorbed is lowered toward the lower chuck (11), thereby pressurizing the semiconductor chip (200) and inducing bonding between the semiconductor chip (200) and the semiconductor substrate (100).

[0140] The heater (13) may be connected to the upper chuck (12). The heater (13) may be provided on the upper surface of the upper chuck (12) on which the semiconductor chip (200) is vacuum-absorbed. Accordingly, the heater (13) may apply heat to the semiconductor chip (200) through the upper chuck (12).

[0141] In this way, as the heater (13) and the upper chuck (12) are connected, the heater (13) can be linked to the lifting and lowering operation of the upper chuck (12).

[0142] Through this, the heater (13) can continuously apply heat to the semiconductor chip (200) from the time the semiconductor chip (200) is vacuum-absorbed to the lower surface of the upper chuck (12) until the semiconductor chip (200) and the semiconductor substrate (100) are bonded.

[0143] The first ultraviolet irradiation unit (14) may be installed between the lower chuck (11) and the upper chuck (12). At this time, the first ultraviolet irradiation unit (14) may be installed in a form capable of irradiating ultraviolet rays toward the upper chuck (12).

[0144] When heat is applied from a heater (13) to a semiconductor chip (200) vacuum-absorbed on the lower surface of the upper chuck (12), a metal oxide film may be formed on the surface of a bump (210) provided on the lower surface of the semiconductor chip (200).

[0145] The above first ultraviolet irradiation unit (14) can irradiate ultraviolet rays toward the bump (210) provided on the lower surface of the semiconductor chip (200) when heat is applied from the heater (13) to the semiconductor chip (200) vacuum-absorbed on the lower surface of the upper chuck (12) to prevent the formation of such a metal oxide film.

[0146] At this time, the first ultraviolet irradiation unit (14) can be removed between the lower chuck (11) and the upper chuck (12) when the upper chuck (12) is lowered toward the lower chuck (11) for bonding between the semiconductor substrate (100) fixed to the lower chuck (11) and the semiconductor chip (200) fixed to the upper chuck (12), and from another perspective, when the semiconductor chip (200) is lowered toward the semiconductor substrate (100) so that the bump (210) comes into contact with the metal pad (110).

[0147] That is, the first ultraviolet irradiation unit (14) can be provided so that it can be freely moved and installed.

[0148] The second ultraviolet irradiation unit (15) may be installed on the lower chuck (11). The second ultraviolet irradiation unit (15) may irradiate ultraviolet rays toward the bonding interface between the metal pad (110) and the bump (210) when the upper chuck (12) is lowered under flux-less conditions and the bump (210) provided on the lower surface of the semiconductor chip (200) is bonded to the metal pad (110) provided on the upper surface of the semiconductor substrate (100) fixed to the upper surface of the lower chuck (11).

[0149] Accordingly, even if the first ultraviolet irradiation unit (14) is removed between the lower chuck (11) and the upper chuck (12) due to the lowering of the upper chuck (12), continuous ultraviolet irradiation can be performed by the second ultraviolet irradiation unit (15).

[0150] Accordingly, the formation of a metal oxide film at the bonding interface between the metal pad (110) and the bump (210) can be prevented, and through this, direct bonding between the metal pad (110) and the bump (210) can be achieved.

[0151] The above step S120 can be executed through such a semiconductor package bonding device (10).

[0152] That is, in the above S120 step, first, the semiconductor substrate (100) can be vacuum-absorbed on the upper surface of the lower chuck (11) so that the metal pad (110) faces upward.

[0153] Next, in the above step S120, the semiconductor chip (200) can be vacuum-absorbed to the lower surface of the upper chuck (12) so that the bump (210) faces downward and is aligned vertically with the metal pad (110).

[0154] Next, in the above S120 step, the heater (13) can be operated, and through this, the semiconductor chip (200) can be preheated to a temperature required for bonding the semiconductor substrate (100) and the semiconductor chip (200).

[0155] At this time, in the above step S120, the temperature of the heater (13) can be adjusted to 250°C to 300°C.

[0156] At the same time, in step S120, the first ultraviolet irradiation unit (14) can be operated. Through this, ultraviolet rays can be irradiated toward the bump (210) in step S120.

[0157] At this time, in the step S120, the intensity of the ultraviolet ray irradiated from the first ultraviolet irradiation unit (14) toward the bump (210) can be adjusted to 10 mV to 2000 mV, and the ultraviolet ray can be irradiated to the bump (210) for a time exceeding 0 seconds and less than or equal to 70 seconds.

[0158] Accordingly, the formation of a metal oxide film on the surface of the bump (210) can be prevented during the process of the semiconductor chip (200) being positioned on the semiconductor substrate (100) and being preheated for bonding with the semiconductor substrate (100).

[0159]

[0160] Step S130

[0161] The above step S130 is a step of bonding the semiconductor substrate (100) and the semiconductor chip (200) so that the metal pad (110) of the semiconductor substrate (100) aligned in the vertical direction through the above step S120 and the bump (210) of the semiconductor chip (200) make electrical contact.

[0162] In the above step S130, when the temperature of the bump (210) heated through the above step S120 reaches a preset target temperature, for example, 250°C to 300°C, the semiconductor chip (200) can be lowered toward the semiconductor substrate (100).

[0163] Through this, in the step S130, a bump (210) provided on the lower surface of the semiconductor chip (200) can be bonded to a metal pad (110) provided on the upper surface of the semiconductor substrate (100).

[0164] According to one embodiment of the present invention, in the step S130, the semiconductor substrate (100) and the semiconductor chip (200) can be bonded under flux-less conditions without using flux.

[0165] Accordingly, in the above step S130, ultraviolet rays can be continuously irradiated to the bonding interface between the metal pad (110) and the bump (210).

[0166] In this way, by irradiating ultraviolet rays to the bonding interface between the metal pad (110) and the bump (210), it is possible to prevent a metal oxide film from being formed at the bonding interface between the metal pad (110) and the bump (210).

[0167] To this end, the irradiation energy of ultraviolet rays irradiated to the bonding interface of the metal pad (110) and the bump (210) may also be relatively greater than the generation energy of the metal oxide film generated at the bonding interface of the metal pad (110) and the bump (210).

[0168] At this time, the bonding interface between the metal pad (110) and the bump (210) may be irradiated with the same ultraviolet ray as the ultraviolet ray irradiated to the bump (210) in the step S120.

[0169] For example, the bonding interface between the metal pad (110) and the bump (210) may be irradiated with either UV-C or UV-C (Ozone).

[0170] These ultraviolet rays can be irradiated to the bonding interface between the metal pad (110) and the bump (210) with a strength of 10 mV to 2000 mV.

[0171] In addition, the irradiation angle of ultraviolet rays irradiated to the bonding interface between the metal pad (110) and the bump (210) can be adjusted within the range of 0° to 90°.

[0172] Through this, the irradiation range and intensity of ultraviolet rays irradiated to the bonding interface between the metal pad (110) and the bump (210) can be controlled, and as a result, the bonding quality between the metal pad (110) and the bump (210) can be improved.

[0173] In this way, according to one embodiment of the present invention, by ultraviolet rays irradiated to the bonding interface between the metal pad (110) and the bump (210), the formation of a metal oxide film that interferes with the bonding between the metal pad (110) and the bump (210) can be prevented.

[0174] Accordingly, in the step S130, interatomic bonding can be formed by diffusion of the metal forming the metal pad (110) and the metal forming the bump (210), and through this interatomic bonding, an IMC (Intermetallic Compound) layer can be created at the bonding interface between the metal pad (110) and the bump (210).

[0175] The formation of an IMC layer at the bonding interface between the metal pad (110) and the bump (210) is evidence of atomic penetration and diffusion, which means that the metal pad (110) and the bump (210) are completely bonded at the atomic level.

[0176] According to one embodiment of the present invention, the metal pad (110) may be formed of a Cu pad, and the bump (210) may be formed of a solder bump.

[0177] In this case, when the Cu pad and the solder bump are bonded through the above S130 step, an IMC layer made of Cu6Sn5 can be created at their interface.

[0178] Referring to FIG. 5, the S130 step can be executed through a semiconductor package bonding device (10), similar to the S120 step.

[0179] That is, in the above step S130, when the semiconductor chip (200) reaches the target temperature through the heater (13), the first ultraviolet irradiation unit (14) installed between the lower chuck (11) and the upper chuck (12) can be removed.

[0180] Next, in the above step S130, the upper chuck (12) on which the semiconductor chip (200) is vacuum-absorbed on the lower surface can be lowered toward the lower chuck (11) on which the semiconductor substrate (100) is vacuum-absorbed on the upper surface.

[0181] When the bump (210) provided on the lower surface of the semiconductor chip (200) comes into contact with the metal pad (110) provided on the upper surface of the semiconductor substrate (100) by lowering the upper chuck (12) and bonding between them is initiated, the second ultraviolet irradiation unit (15) can be operated in step S130. Through this, ultraviolet rays can be irradiated to the bonding interface between the metal pad (110) and the bump (210) in step S130.

[0182] Accordingly, an IMC layer can be created while preventing the formation of a metal oxide film at the bonding interface between the metal pad (110) and the bump (210).

[0183] When the above S130 step is completed, the metal pad (110) and the bump (210) are electrically connected by bonding to form a semiconductor package.

[0184] In a semiconductor package bonding method according to one embodiment of the present invention, a semiconductor package bonding device (10) using a heater (13) as a heat source can be used.

[0185] However, this is only an example, and semiconductor package bonding devices that use various heat sources can be used for semiconductor package bonding.

[0186] For example, as illustrated in FIG. 6, a semiconductor package bonding device using IPL as a heat source may be used in a semiconductor package bonding method according to an embodiment of the present invention.

[0187] In this case, while the bump (210) and the metal pad (110) are being bonded by the IPL irradiated from the IPL irradiation unit (23), ultraviolet rays can be irradiated from the ultraviolet irradiation unit (25) to the bonding interface between the bump (210) and the metal pad (110).

[0188] As another example, as illustrated in FIG. 7, a semiconductor package bonding device using a laser as a heat source may be used in a semiconductor package bonding method according to an embodiment of the present invention.

[0189] In this case, while the bump (210) and the metal pad (110) are joined by the laser irradiated from the laser irradiation unit (33), ultraviolet rays can be irradiated from the ultraviolet irradiation unit (35) to the joining interface between the bump (210) and the metal pad (110).

[0190] Meanwhile, referring to FIG. 8, when the metal pad to be bonded is made of a Cu pad and the bump is made of a solder bump through a semiconductor package bonding method according to an embodiment of the present invention, it was confirmed that when UV-A and UV-B were irradiated as ultraviolet rays during the bonding process, there was a partially unbonded portion at the bonding interface between the metal pad and the bump.

[0191] On the other hand, when UV-C was irradiated with ultraviolet rays and UV-C (Ozone) was irradiated, it was confirmed that the metal pad and the bump were evenly and well bonded without any raised areas.

[0192] FIG. 9 is a graph showing the temperature profile of a semiconductor chip in a semiconductor package bonding method according to an embodiment of the present invention.

[0193] Referring to Fig. 9, it was confirmed that the semiconductor chip must be heated for at least 60 seconds to reach the target temperature, i.e., to completely melt the bump, and accordingly, it was confirmed that the ultraviolet irradiation time must also be set to at least 60 seconds.

[0194] FIG. 10 is a graph showing the relationship between temperature and bump deformation over time in a semiconductor package bonding method according to an embodiment of the present invention.

[0195] Referring to Fig. 10, as confirmed in Fig. 9, when the temperature was raised to the target temperature and ultraviolet rays were simultaneously irradiated for up to 60 seconds and then the ultraviolet rays were removed, it was confirmed that deformation of the bump occurred at the target temperature, which means that the bonding between the bump and the metal pad was well formed.

[0196]

[0197] Example 1

[0198] After preparing a semiconductor substrate with a Cu pad on one side and a semiconductor chip with a solder bump on one side, the semiconductor chip was preheated and the solder bump was irradiated with ultraviolet rays.

[0199] Next, the Cu pad and solder bump were bonded through flip-chip bonding. At this time, under fluxless conditions, the bonding interface between the Cu pad and solder bump was continuously irradiated with ultraviolet light.

[0200]

[0201] Comparative Example 1

[0202] A semiconductor substrate with a Cu pad on one side and a semiconductor chip with a solder bump on one side were prepared, and the semiconductor chip was preheated. Next, the Cu pad and solder bump were bonded using flux through flip-chip bonding.

[0203]

[0204] Figure 11 is an image of a cross-section of a semiconductor package manufactured according to Example 1 and Comparative Example 1, taken using an optical microscope.

[0205] Referring to Fig. 11, in the case of Comparative Example 1 where UV was not used during the bonding process (without UV), it was confirmed that some bonding was only formed in the form of local points even when temperature and pressure were applied, and most of the solder bumps and Cu pads were simply in contact.

[0206] In contrast, in Example 1, where UV was used during the bonding process (UV assist), perfect bonding between the solder bump and the Cu pad was confirmed, and a slight diffusion phenomenon was also observed at the interface between the solder bump and the Cu pad. This diffusion phenomenon may indicate that an IMC layer was formed at the interface between the solder bump and the Cu pad.

[0207] FIGS. 12 and 13 are images of cross-sections of semiconductor packages manufactured according to Comparative Example 1 taken with a scanning electron microscope at different magnifications, and FIGS. 14 to 16 are images of cross-sections of semiconductor packages manufactured according to Example 1 taken with a scanning electron microscope at different magnifications.

[0208] First, referring to FIGS. 12 and 13, as confirmed in the optical microscope image, in the case of Comparative Example 1 (without UV), it was confirmed that the solder bump did not adhere to the Cu pad at the bonding interface between the Cu pad and the solder bump, but was simply in contact with it, or an IMC layer was formed only in some parts.

[0209] On the other hand, referring to FIGS. 14 to 16, in the case of Example 1 (UV assist), although the solder bump was significantly distorted, it was confirmed that the IMC layer was well formed overall at the interface between the Cu pad and the solder bump.

[0210] Accordingly, if the alignment between the Cu pad and the solder bump is accurately achieved, it is expected that good bonding between the Cu pad and the solder bump will be achieved by UV irradiation instead of flux.

[0211] Figures 17 to 19 are EDS analysis results for a semiconductor package manufactured according to Example 1.

[0212] Referring to FIGS. 17 to 19, the EDS (Energy Dispersive Spectroscopy) mapping results for the IMC layer portion formed at the bonding interface between the Cu pad and the solder bump clearly confirm that Cu6Sn5 was formed when looking at the distribution of Cu and Sn at the bonding interface between the Cu pad and the solder bump.

[0213]

[0214] Example 2

[0215] After preparing a semiconductor substrate with a Cu pad on one side and a semiconductor chip with a solder bump on one side, the semiconductor chip was preheated and the solder bump was irradiated with ultraviolet rays.

[0216] At this time, one side of the semiconductor substrate on which the Cu pad was provided was surface-treated using the OSP method.

[0217] Next, the Cu pad and solder bump were bonded through flip-chip bonding. At this time, under fluxless conditions, the bonding interface between the Cu pad and solder bump was continuously irradiated with ultraviolet light.

[0218]

[0219] Comparative Example 2

[0220] After preparing a semiconductor substrate with a Cu pad on one side and a semiconductor chip with a solder bump on one side, the semiconductor chip was preheated.

[0221] At this time, one side of the semiconductor substrate on which the Cu pad was provided was surface-treated using the OSP method.

[0222] Next, the Cu pad and solder bump were bonded using flux through flip chip bonding.

[0223]

[0224] Example 3

[0225] After preparing a semiconductor substrate with a Cu pad on one side and a semiconductor chip with a solder bump on one side, the semiconductor chip was preheated and the solder bump was irradiated with ultraviolet rays.

[0226] At this time, one side of the semiconductor substrate on which the Cu pad was provided was surface-treated using the ENIG method.

[0227] Next, the Cu pad and solder bump were bonded through flip-chip bonding. At this time, under fluxless conditions, the bonding interface between the Cu pad and solder bump was continuously irradiated with ultraviolet light.

[0228]

[0229] Comparative Example 3

[0230] After preparing a semiconductor substrate with a Cu pad on one side and a semiconductor chip with a solder bump on one side, the semiconductor chip was preheated.

[0231] At this time, one side of the semiconductor substrate on which the Cu pad was provided was surface-treated using the ENIG method.

[0232] Next, the Cu pad and solder bump were bonded using flux through flip chip bonding.

[0233]

[0234] Figure 20 is an image of a cross-section of a semiconductor package manufactured according to Examples 2 and 3 and Comparative Examples 2 and 3, taken using an optical microscope and a scanning electron microscope.

[0235] Referring to Fig. 20, the resistance was well measured in the Daisy-chain pattern in both Examples 2 and 3 and Comparative Examples 2 and 3, and it was confirmed that in the case of Examples 2 and 3 using ultraviolet irradiation, a bonding quality similar to that of Comparative Examples 2 and 3 was secured.

[0236] That is, it was confirmed that bonding of the semiconductor substrate and the semiconductor chip is possible under fluxless conditions through ultraviolet irradiation even if the semiconductor substrate is surface treated.

[0237]

[0238] Experimental Example 1

[0239] Referring to Fig. 21, a copper plate (C) was placed on a hot plate (52), and ultraviolet rays were irradiated to the upper surface of the copper plate (C) through a UV lamp (51).

[0240] That is, ultraviolet rays were directly irradiated on the upper surface of the copper plate (C), and heat was applied to the lower surface of the copper plate (C) by a hot plate (52).

[0241]

[0242] Figure 22 is an image of the upper surface of a copper plate directly irradiated with ultraviolet rays, and Figure 23 is an image of the lower surface of a copper plate in contact only with a heat source.

[0243] Referring to Fig. 22, it was confirmed that even when the copper plate (C) was heated by the hot plate (52), the upper surface of the copper plate (C) directly irradiated with ultraviolet rays maintained the original color of copper.

[0244] On the other hand, referring to Fig. 23, the lower surface of the copper plate (C) that was not directly irradiated with ultraviolet rays was confirmed to be discolored.

[0245] Figure 24 shows the results of XPS (X-ray Photoelectron Spectroscopy) analysis of the upper and lower surfaces of the copper plate according to Experimental Example 1.

[0246] Referring to Figure 24, the upper surface of the copper plate (C) directly irradiated with ultraviolet rays has a Cu-like shape, and the oxidation inhibition effect of ultraviolet rays (Cu reduction) was confirmed.

[0247] On the other hand, the lower surface of the copper plate (C) that was not directly irradiated with ultraviolet rays was confirmed to have the same morphology as the oxidized surface of Cu, such as CuO and Cu2O.

[0248] Through this, it was confirmed that when ultraviolet rays are irradiated to the bonding interface between the Cu pad and the solder bump, the formation of a copper oxide film at the bonding interface between the Cu pad and the solder bump is prevented, which means that when ultraviolet rays are irradiated to the bonding interface between the Cu pad and the solder bump, flux does not need to be used (flux-less).

[0249]

[0250] While the present invention has been described in detail using preferred embodiments, the scope of the present invention is not limited to the specific embodiments described above, and should be interpreted in accordance with the appended claims. Furthermore, those skilled in the art will appreciate that numerous modifications and variations are possible without departing from the scope of the present invention.

Claims

1. A step of preparing a semiconductor substrate having a metal pad on one side and a semiconductor chip having a bump on one side and bonded to the semiconductor substrate; A step of positioning the semiconductor chip on the semiconductor substrate such that the metal pads and bumps are aligned in the vertical direction; and A step of bonding the semiconductor substrate and the semiconductor chip under flux-less conditions so that the metal pad and the bump make electrical contact; In the step of bonding the semiconductor chip, ultraviolet rays are irradiated to the bonding interface of the metal pad and the bump. A semiconductor package bonding method wherein the ultraviolet irradiation energy is relatively greater than the metal oxide film formation energy so that the formation of a metal oxide film at the bonding interface between the metal pad and the bump is prevented by the ultraviolet irradiation.

2. In paragraph 1, When heat is used as energy to bond the semiconductor substrate and semiconductor chip, In the step of positioning the semiconductor chip, heat is applied to the semiconductor chip while ultraviolet rays are irradiated to the bump. A semiconductor package bonding method, wherein, in the step of bonding the semiconductor chip, when the temperature of the bump reaches a preset target temperature, the semiconductor chip is lowered onto the semiconductor substrate to bond the bump to the metal pad, and the ultraviolet rays are continuously irradiated to the bonding interface between the metal pad and the bump.

3. In paragraph 1, A semiconductor package bonding method, wherein, in the step of bonding the semiconductor chip, an IMC (Intermetallic Compound) layer is created at the bonding interface between the metal pad and the bump through interatomic bonding by diffusion of the metal forming the metal pad and the metal forming the bump.

4. In paragraph 3, A semiconductor package bonding method, wherein when the metal pad is made of a Cu pad and the bump is made of a solder bump, an IMC layer made of Cu6Sn5 is created at the bonding interface between the Cu pad and the solder bump.

5. In paragraph 1, A semiconductor package bonding method wherein the above ultraviolet rays can be irradiated at an angle adjustable within a range of 0° to 90° to the bonding interface between the metal pad and the bump.

6. In paragraph 1, A semiconductor package bonding method, wherein the above ultraviolet rays are irradiated at a strength of 10 mV to 2000 mV to the bonding interface of the metal pad and the bump.

7. In paragraph 1, A semiconductor package bonding method, wherein the above ultraviolet rays are irradiated to the bump for a time exceeding 0 seconds and less than 70 seconds.

8. In paragraph 1, A semiconductor package bonding method, wherein either UV-C or UV-C (Ozone) is used as the above ultraviolet ray.

9. In paragraph 2, A semiconductor package bonding method, wherein the temperature of heat applied to the semiconductor chip is controlled to 250°C to 300°C.

10. In paragraph 1, The steps for preparing the above semiconductor chip are: A step of moving the semiconductor chip onto the semiconductor substrate is included, During the above moving step, a flipping step of the semiconductor chip is included, A semiconductor package bonding method, wherein the moving step includes a step of applying heat and the ultraviolet rays to the semiconductor chip.

11. In paragraph 1, A semiconductor package bonding method, wherein any one of a wafer chip, a PCB, a glass substrate, an interposer, and a carrier is prepared as the semiconductor substrate.

12. In paragraph 11, A semiconductor package bonding method wherein the semiconductor substrate is surface treated using any one of OSP (Organic Solderability Preservative), ENIG (Electroless Nickel Immersion Gold), and ENEPIG (Electroless Nickel Electroless Palladium Immersion Gold).

13. A lower chuck on which a semiconductor substrate having a metal pad on one side is vacuum-absorbed; An upper chuck which is provided to be liftable on the lower chuck and on which a semiconductor chip having bumps on one surface is vacuum-absorbed so as to be aligned vertically with the semiconductor substrate; A heater that is linked to the lifting and lowering motion of the upper chuck and applies heat to the semiconductor chip; A first ultraviolet irradiation unit that is installed so as to be removable between the lower chuck and the upper chuck, and irradiates ultraviolet rays toward the bump when heat is applied from the heater to the semiconductor chip vacuum-absorbed to the upper chuck; and A semiconductor package bonding device, comprising: a second ultraviolet irradiation unit installed on the lower chuck and irradiating ultraviolet rays toward a bonding interface between the metal pad and the bump when the upper chuck is lowered under flux-less conditions and the bump is bonded to the metal pad.

14. In paragraph 13, A semiconductor package bonding device, wherein when the bump is bonded to the metal pad, an IMC layer is created at the bonding interface between the metal pad and the bump through interatomic bonding by diffusion of the metal forming the metal pad and the metal forming the bump.

Images